Optimizing data transfers between a parallel processing processor and memory

Abstract

A computing system (20) comprising a memory A (30), a memory access control module (50), and a parallel processing processor (40) comprising a plurality of computing units (41) each comprising a memory B shared by one or more elementary processors (43). The computing units are arranged in a column. A partition (31) of the memory A is associated with each column. Connection modules (60) are connected respectively to the partitions of the memory A and to the memories B of the computing units (41). Within a column, the neighboring connection modules are connected to each other by a dedicated interface link (61). The memory access control module (50) is adapted to configure the connection modules (60) to execute data transfers in parallel in several columns, each transfer allowing an exchange of data within a column between a partition of the memory A and a memory B of at least one computing unit.Figure for abstract: Fig. 2.

Description

Title of the invention: Optimization of data transfers between a parallel processing processor and a memory Field of the invention

[0001] The present invention belongs to the field of computing systems comprising a parallel processing processor acting as a hardware accelerator. The invention relates in particular to a particular architecture for such a computing system aimed at optimizing data transfers between the parallel processing processor and a memory external to said processor. State of the art

[0002] In the field of artificial intelligence, and more specifically in the context of deep neural networks, the issue of data movement is of great importance. Deep neural networks are machine learning models that require a considerable volume of data to perform complex tasks such as image recognition, object detection, or anomaly detection.

[0003] Data movement refers to the manipulation and transfer of data from one memory location to another. This poses a number of challenges in the context of deep neural networks. The massive volume of data used by these models requires adequate storage and processing resources to efficiently handle movement operations. Data must be transferred quickly and reliably to minimize latency and optimize neural network performance.

[0004] The problem of data movement in embedded systems presents additional challenges. Indeed, embedded systems, such as loT (Internet of Things) devices, autonomous vehicles or drones, are characterized by their limited resources in terms of computing power, memory and energy. In this context, efficient data movement becomes crucial to ensure optimal performance and efficient use of resources. Another important challenge is energy management in embedded systems. Since energy resources are limited, it is crucial to minimize energy consumption during data movement.

[0005] [Fig.l] schematically represents a conventional computing system 10 for processing a large amount of data in parallel. Such a computing system 10 can in particular be used to implement an algorithm based on a deep neural network.

[0006] As illustrated in [Fig.l], the computing system 10 comprises a host processor 11, a parallel processing processor 15, a memory 12 (memory A, or “Mem A”), an interconnection bus 13, and a memory access control module 14.

[0007] The host processor 11 corresponds to a central processing unit (CPU). The host processor 11 manages the general execution of the system, including communication with the parallel processing processor 15. The parallel processing processor 15 acts as a hardware accelerator; it is a component designed specifically to perform intensive calculation operations for machine learning algorithms. The parallel processing processor 15 comprises a plurality of calculation units 16 (CU). Each calculation unit 16 comprises one or more elementary processors and a memory (memory B or Mem B) shared by the elementary processors.

[0008] In the case of embedded systems, memory A may correspond to the main memory of the system. This memory is generally referred to as level 2 memory (L2 memory). The memories B of the distributed computing units in the parallel processing processor are then generally referred to as level 1 memory (L1 memory).

[0009] The interconnection bus 13 allows data exchanges to take place between the host processor 11, the memory 12 and the parallel processing processor 15, and also possibly with other components of the system.

[0010] The memory access control module 14 (DMA, for “Direct Memory Access”) makes it possible to transfer data between the parallel processing processor 15 (or possibly another component of the system) and the memory 12 without the direct intervention of the host processor 11.

[0011] DMA is a key element because it allows the best use of the interconnect bus throughput. In a conventional system, when an external device wants to transfer data to or from memory A, this generally requires the intervention of the host processor. The host processor must read or write the data sequentially, and this can create a bottleneck and inefficient use of the host processor and the interconnect bus.

[0012] DMA overcomes this limitation by providing a direct path for data transfers between peripherals and memory A without going through the host processor at each step. DMA typically has a dedicated controller that handles the transfer operations.

[0013] When a peripheral wants to transfer data, it sends a request to the DMA. The DMA then accesses memory A via the interconnect bus and performs the requested data transfer between the peripheral and memory A, without requiring an intervention from the host processor. Once the transfer is complete, the DMA can generate an interrupt to inform the host processor that the operation is complete.

[0014] Using DMA has several advantages. First, it reduces the workload on the host processor. This allows the host processor to focus on other critical tasks. In addition, data transfers via DMA are generally faster than those performed by the host processor. This improves overall system performance. Finally, DMA allows for more efficient management of A memory, avoiding deadlocks and optimizing data transfers between peripherals and A memory.

[0015] However, despite all these advantages, the maximum theoretical achievable throughput remains directly linked to the width of the interconnection bus. The maximum throughput is in the best case equal to the width of the interconnection bus multiplied by the operating frequency of the system. Conventionally, memory A of the computing system 10 illustrated in [Fig.l] is a unified memory, with a single access interface connected to the interconnection bus. This creates a bottleneck at the level of access to memory A, and a limitation of the throughput for data transfers between memory A and the memories B distributed within the parallel processing processor 15. In particular, when data must be transferred from several memories B to memory A, the DMA will have to sequentially launch a series of transfers from each memory B, one after the other, to memory A. Statement of the invention

[0016] The present invention aims to remedy all or part of the drawbacks of the prior art.

[0017] To this end, and according to a first aspect, the present invention proposes a calculation system comprising a memory, called "memory A", a memory access control module, and a parallel processing processor comprising a plurality of calculation units. Each calculation unit comprises one or more elementary processors and a memory, called "memory B", shared by said elementary processors. The calculation units of the parallel processing processor are arranged in several columns and, in each column, the calculation units are ordered from a first calculation unit to a last calculation unit, with zero, one or more intermediate calculation units between the first calculation unit and the last calculation unit. The first calculation unit corresponds to the last calculation unit when the column comprises only one calculation unit.

[0018] The memory A is partitioned so as to associate a partition of the memory A with each column of calculation units and, for each column, the calculation system comprises connection modules ordered from a first connection module connected to memory partition A, to a last connection module connected to memory B of the last computing unit, with zero, one or more intermediate connection modules between the first connection module and the last connection module, each intermediate connection module being connected to memory B of a computing unit.

[0019] The first connection module has a dedicated interface link with the following connection module, each intermediate connection module has a dedicated interface link on the one hand with the previous connection module and on the other hand with the following connection module, the last connection module has a dedicated interface link with the previous connection module.

[0020] The memory access control module is adapted to configure the connection modules to make a first data transfer, for a first column, between the partition of memory A associated with said first column and a memory B of at least one calculation unit of said first column and, simultaneously with the first transfer, to make at least a second data transfer, for a second column, between the partition of memory A associated with said second column and a memory B of at least one calculation unit of said second column.

[0021] The invention is thus based on a division of memory A into several partitions having a column arrangement similar to that of the memories B embedded in the parallel processing processor (“column symmetry” between the partitions of memory A and the distributed memories B). Data transfers can take place in parallel in different columns via the connection modules.

[0022] The partitioning of memory A in fact makes it possible to multiply the access interfaces to the different partitions and provides the opportunity for parallel transfers with the distributed memories B. The transfer rate is thus multiplied by the number of columns defined in the chosen arrangement.

[0023] In particular embodiments, the invention may further comprise one or more of the following features, taken individually or in any technically possible combination.

[0024] In particular embodiments, the first data transfer makes it possible to transfer data from the partition of memory A associated with the first column to the memories B of several different calculation units of the first column, passing at most once through the connection module of each calculation unit of the first column.

[0025] Such arrangements make it possible to broadcast data from a partition of memory A to memories B of several computing units of the column associated with the partition, with a single transfer from memory A.

[0026] In particular embodiments, the memory access control module is adapted to configure the connection modules to transfer data, for at least one column, from a memory B of a calculation unit of said column to a memory B of at least one other calculation unit of said column.

[0027] The connection modules can thus also allow a transfer of data between the memories B of different calculation units of the same column (without necessarily involving the memory A).

[0028] In particular embodiments, the memory access control module is adapted to configure the connection modules to make simultaneous data transfers involving several columns with, for each column involved, a transfer of data from a region of the partition located at a local source address identical for all the columns involved, to a region of a memory B of at least one calculation unit, said region being located at a local destination address identical for all the columns involved.

[0029] In particular embodiments, the memory access control module is adapted to configure the connection modules to carry out simultaneous data transfers involving several columns with, for each column involved, a transfer of data from a region of a memory B of a calculation unit, said region being located at a local source address identical for all the columns involved, to a region of the partition located at a local destination address identical for all the columns involved.

[0030] In other words, the connection modules of the same line can be configured identically to parallelize similar data transfers (with the same source local address and the same destination local address) in different columns.

[0031] In particular embodiments, each intermediate connection module comprises an upper routing block and a lower routing block. The upper routing block can be configured in the following modes: - “Read”: to read data in memory B to which the module intermediate connection module is connected and transmit the read data to the previous connection module, or - “Write”: to receive data from the previous connection module and write the received data into memory B to which the intermediate connection module is connected, or - “Default”: to receive data from the previous connection module and transfer the received data to the lower routing block of the intermediate connection module,

[0032] The lower routing block can be configured in the following modes: - “Read”: to read data in memory B to which the module intermediate connection module is connected and transmit the read data to the next connection module, or - “Write”: to receive data from the next connection module and write the received data into memory B to which the intermediate connection module is connected, or - “Default”: to receive data from the next connection module and transfer the received data to the upper routing block of the intermediate connection module.

[0033] In particular embodiments, the first connection module comprises a lower routing block which can be configured in the following modes: - “Read”: to read data in memory A and transmit the data read to the next connection module, - “Write”: to receive data from the next connection module and write received data into memory A;

[0034] The last connection module includes an upper routing block that can be configured in the following modes: - “Read”: to read data in memory B of the last module of connection and transmit the read data to the previous connection module, - “Write”: to receive data from the previous connection module and write the received data into memory B of the last connection module.

[0035] In particular embodiments, the memory access control module comprises at least two control modules, each control module being adapted to configure in an identical manner all the connection modules having the same ordering rank in the different columns.

[0036] In particular embodiments, the connection modules are all implemented identically, and the control modules are all implemented identically.

[0037] In particular embodiments, the computing system comprises a host processor and an interconnect bus, and the memory A comprises program code instructions for configuring the host processor. The partitions of the memory A are defined with contiguous address mapping such that the program code instructions are stored in a region of memory A separate from the partitions.

[0038] By defining a contiguous address mapping at the partition level of memory A, the possibility of global access to memory A via the interconnect bus is retained, as if it were unified.

[0039] In particular embodiments, the computing system comprises a host processor and an interconnection bus. The host processor is adapted to configure the memory access control module to exchange data with the memory A or with a memory B of at least one computing unit of the parallel processing processor, via the interconnection bus, without passing through a dedicated interface link connecting two neighboring connection modules. Each connection module comprises an arbitration module to manage a priority of access to the memory to which the connection module is connected, between: - a “dedicated” transfer involving a neighboring connection module, and - a “bus” transfer involving the interconnection bus.

[0040] Such arrangements make it possible to manage the coexistence of “dedicated” transfers (transfers operated via the connection modules, without involving the interconnection bus) and “bus” transfers (transfers operated via the interconnection bus, without involving the interface links connecting the connection modules to each other). Presentation of figures

[0041] The invention will be better understood on reading the following description, given by way of non-limiting example, and made with reference to Figures 1 to 20 which represent:

[0042] [Fig.l] a schematic representation of a conventional computing system,

[0043] [Fig.2] a schematic representation of a calculation system according to the invention,

[0044] [Fig.3] a schematic representation of a computing unit of the parallel processing processor of the computing system of [Fig.2],

[0045] [Fig.4] an illustration (first part) of a data transfer from the distributed memories of the parallel processing processor to the memory A of the computing system,

[0046] [Fig.5] an illustration (second part) of a data transfer from the distributed memories B of the parallel processing processor to the memory A of the computing system,

[0047] [Fig.6] an example of memory address mapping of memory A of the computing system 20 (example with forty-eight computing units arranged in eight columns and six rows),

[0048] [Fig.7] a schematic representation of a connection module,

[0049] [Fig.8] another schematic representation of a connection module,

[0050] [Fig.9] another schematic representation of a connection module,

[0051] [Fig. 10] a schematic representation of the memory access control module,

[0052] [Fig. 11] an illustration of the configuration of the different connection modules by memory access control module control modules,

[0053] [Fig. 12] a schematic representation of the fields forming a source address or a destination address,

[0054] [Fig. 13] a schematic representation of a control module of the memory access control module,

[0055] [Fig. 14] a schematic representation of a routing module according to a first embodiment,

[0056] [Fig. 15] a schematic representation of an upper or lower routing block according to a second embodiment,

[0057] [Fig. 16] a schematic representation of an intermediate connection module according to the second embodiment,

[0058] [Fig. 17] a schematic representation of a connection module at the head of the column according to the second embodiment,

[0059] [Fig. 18] a schematic representation of a connection module at the foot of the column according to the second embodiment,

[0060] [Fig. 19] a schematic representation of a control module for configuring a connection module at the head or foot of the column according to the second embodiment,

[0061] [Fig.20] an illustration of the configuration of three connection modules of a column according to the second embodiment.

[0062] In these figures, identical references from one figure to another designate identical or similar elements. For reasons of clarity, the elements represented are not necessarily on the same scale, unless otherwise stated. Detailed description of the invention

[0063] [Fig. 2] represents an exemplary embodiment of a calculation system 20 according to the invention. By way of non-limiting example, the case of an embedded calculation system 20 is used for executing artificial intelligence processing (for example a machine learning algorithm) requiring the processing of a large amount of data. This may, for example, be an algorithm based on a deep neural network for performing image processing tasks (image recognition, object detection, anomaly detection, etc.).

[0064] In a similar manner to the conventional computing system 10 described with reference to [Fig.l], the computing system 20 comprises a host processor 21, a parallel processing processor 40, a memory 30, hereinafter “memory A” (Mem A), an interconnection bus 22, and a memory access control module 50 (DMPA for “Direct Memory Parallel Access”).

[0065] As illustrated in [Fig.3], each calculation unit 41 comprises one or more elementary processors 43 (PE) and a memory 42, hereinafter “memory B” (Mem B), shared by these elementary processors 43.

[0066] The calculation units 41 (UC) of the parallel processing processor 40 are arranged in a matrix manner in N columns and M rows (N being an integer greater than or equal to two, and M an integer greater than or equal to one). In each column, the calculation units 41 are ordered from a first calculation unit to a last calculation unit, with zero, one or more intermediate calculation units between the first calculation unit and the last calculation unit. For a column of index i (i being an index varying between 0 and Nl), the calculation units are denoted UCjj (j being an index varying between 0 and Ml); the first calculation unit 41 of the column corresponds to the calculation unit UQo; the last calculation unit 41 of the column corresponds to the calculation unit UCijM_i; the intermediate calculation units correspond to the calculation units UC^ with j varying between 1 and M-2).When the column has only one calculation unit (M=l), then the first calculation unit and the last calculation unit in the column correspond to one and the same calculation unit.

[0067] In the example considered, memory A corresponds to the main memory of the system. This memory is generally referred to as level 2 memory (L2 memory). The memories B of the distributed computing units in the parallel processing processor 40 are generally referred to as level 1 memory (L1 memory).

[0068] The host processor 21 (CPU) manages the general execution of the system, including communication with the parallel processing processor 40. The parallel processing processor 40 acts as a hardware accelerator: it is designed specifically to be able to perform intensive computing operations to execute the machine learning algorithm. In particular, the different computing units UCij can work in parallel to optimize the performance of the system.

[0069] Conventionally, the interconnection bus 22 can allow data exchanges to take place between the host processor 21, the memory 30 and the parallel processing processor 40, and also possibly with other components of the system.

[0070] The invention is based on a division of the memory A into several partitions with a column arrangement similar to that of the memories B embedded in the parallel processing processor 40 (“column symmetry” between the partitions of the memory A and distributed memory B). This partitioning allows for the multiplication of memory access interfaces and provides the opportunity for parallel transfers with distributed memory B.

[0071] To allow these parallel transfers in the different columns, the memory A is partitioned into N partitions (as many partitions as columns of calculation units). In [Fig.2], the partitions are noted Ai5 with i varying between 0 and (Nl). Each partition of the memory A is associated with a column of calculation units 41. For a column of index i, the calculation system 20 comprises connection modules 60 ordered from a first connection module connected to the partition A;, up to a last connection module connected to the memory B of the last calculation unit UCijM_i. Zero, one or more intermediate connection modules can be positioned between the first connection module and the last connection module. Each intermediate connection module is connected to the memory B of a calculation unit UCLJ with j varying between 0 and (M-2).

[0072] The connection modules 60 of a column of index i can therefore be ordered with an index k varying between 0 and M: the first connection module 60, of index 0, is associated with the partition 31 of the memory A; the second connection module 60, of index 1, is associated with the first calculation unit UCij0 of the column; ...; the last connection module 60 of index M is associated with the last calculation unit UCijM_i of the column. For a connection module 60 of index k, with k between 1 and (Ml), the previous connection module corresponds to the connection module of index (k-1), and the following connection module corresponds to the connection module of index (k+1).

[0073] As illustrated in [Fig.2], the first connection module (the one associated with the partition of memory A) has a dedicated interface link 61 with the next connection module (the one associated with the first calculation unit of the column). Each intermediate connection module has a dedicated interface link 61 on the one hand with the previous connection module and on the other hand with the next connection module. The last connection module has a dedicated interface link 61 with the previous connection module.

[0074] The memory access control module 50 is adapted to configure the connection modules 60 to make data transfers in parallel in at least two different columns. The memory access control module 50 can in particular be configured by the host processor 21; in a variant, the memory access control module 50 can be configured by the parallel processing processor 40.

[0075] For example, the memory access control module 50 is adapted to configure the connection modules 60 to make a first data transfer, within of a column of index p, with p between 0 and (Nl), between the partition Ap and a memory B of at least one calculation unit 41 of the column of index p and, simultaneously with the first transfer, making at least a second data transfer, within a column of index q, with q between 0 and (Nl) and different from p, between the partition Aq and a memory B of at least one calculation unit 41 of the column of index q.

[0076] For each data transfer within a column, the data passes through the dedicated interface links 61 connecting the different connection modules 60 to each other, without passing through the interconnection bus 22. The dedicated interface links 61 are bidirectional, they each have an uplink and a downlink.

[0077] According to a first example, a transfer of data within a column may have as its origin (source) the partition of memory A and as its destination the memory B of at least one calculation unit 41 of the column (this is then referred to as a “downward” transfer). According to a second example, a transfer of data within a column may have as its origin the memory B of a calculation unit 41 of the column and as its destination the partition of memory A (this is then referred to as an “upward” transfer). According to a third example, a transfer of data within a column may have as its origin the memory B of a calculation unit 41 and as its destination the memory B of at least one other calculation unit of the column (the transfer may then be upward or downward).According to yet another example, a data transfer within a column may originate from memory B of a computing unit 41 and may be addressed to both the partition of memory A and memory B of at least one other computing unit of the column.

[0078] Advantageously, when a transfer of data within a column originates from the partition of memory A and has the recipients of memories B of several calculation units 41 of the column, the transferred data passes at most once through the connection module 60 of each calculation unit 41 of the column.

[0079] Advantageously, and as illustrated in Figures 4 and 5, the memory access control module 50 can be adapted to configure the connection modules 60 to carry out simultaneous data transfers involving several columns with, for each column involved, a transfer of data from a region of a memory B of a calculation unit 41, said region being located at a local source address identical for all the columns involved, to a region of the partition 31 located at a local destination address identical for all the columns involved.

[0080] In the example illustrated in Figures 4 and 5, the calculation units 41 of the parallel processing processor 40 are used to process the pixels of an image 80. The image 80 is divided in a matrix manner into as many pixel zones 81 as there are calculation units 41 (the image is therefore divided into N columns and M rows). The data associated with each area 81 of pixels of the image 80 are processed by a calculation unit. It is possible to move the data processed 82 by each calculation unit 41 of the same line to the memory A simultaneously, by carrying out parallel transfers in the N columns. All the data processed 82 by the different calculation units 41 of the same line are all stored at the same local address in the different partitions of the memory A. By repeating this operation M times (line by line), all the data processed by the calculation units 41 of the parallel processing processor 40 can then be moved to the memory A, as illustrated in [Fig.5].

[0081] On a neural network type application, and in particular for a residual neural network, the fact of having several branches in the graph modeling the neural network implies the need to save the data at the separation of branches and to reload them later during the merging of branches. The calculation system 20 according to the invention allows the saving of data from memories B to the partitions of memory A (in the upstream direction), this in parallel for the N columns. A partition of memory A is itself divided into several regions, each region being associated with a memory B of the column and identified by an offset.

[0082] Similarly, the loading of the data required at the time of branch merging will be performed in parallel on the different columns (in the downward direction). For this purpose, the memory access control module 50 may be adapted to configure the connection modules 60 to perform simultaneous data transfers involving several columns with, for each column involved, a data transfer from a region of the partition 31 located at a local source address identical for all the columns involved, to a region of a memory B of at least one calculation unit 41, said region being located at a local destination address identical for all the columns involved.

[0083] The transfer rate is thus multiplied by the number of columns in the chosen arrangement. For example, suppose that the dedicated interface links 61 have a data width of sixty-four bits. If we consider a parallel processing processor 40 having twenty-four calculation units 41 arranged in four columns and six rows, then the transfer rate is 256 bits / cycle (4 x 64 = 256). If we consider a parallel processing processor 40 having forty-eight calculation units 41 arranged in eight columns and six rows, then the transfer rate is 512 bits / cycle (8 x 64 = 512). If we consider a parallel processing processor 40 having sixty-four calculation units 41 arranged in sixteen columns and four rows, then the transfer rate is 1024 bits / cycle (16 x 64 = 1024).

[0084] [Fig.6] illustrates an example of memory address mapping A for a computing system 20 with a parallel processing processor 40 comprising forty-eight computing units 41 arranged in eight columns and six rows. For each partition Ao to A7 associated with a column, memory regions are reserved for each of the six computing units 41 of the column (Bo, Bb B6). Memory addresses are represented in hexadecimal. For each address, the field formed by the sixteen least significant bits represents a local address range; the field represented in bold is used to code the column position; the underlined field is used to code the row position.

[0085] The partitions 31 of the memory A are advantageously defined with a contiguous address mapping. This allows in particular a unified access via the interconnection bus 22. Thus, the host processor 21 can use the memory A as a unified memory. This access from the interconnection bus 22 is particularly interesting in the case of embedded systems, for which the memory A can correspond to the main memory of the host processor 21. This main memory can contain the executable code as well as the data necessary for the execution of the host processor 21. A linker script file is generally used by the compiler to organize the different sections of code and data in the memory when creating an executable.Specific sections (distinct from those storing the executable code of the host processor) can then be added to this script file, in particular to define sections dedicated to the exchange of data between memory A and the distributed memories B, or sections dedicated to the parameters of a neural network.

[0086] [Fig.7] schematically represents an exemplary embodiment of a connection module 60. As illustrated in [Fig.7], the connection module 60 comprises a routing module 62 for exchanging data with another connection module 60 of the same column. A configuration link 66 (cfg link) allows the memory access control module 50 (DMPA) to configure the routing module 62 of the connection module 60. The connection module 60 comprises a bidirectional routing link 63 with the previous connection module (data_prev link), a bidirectional routing link 64 with the next connection module (data_nxt link), and a bidirectional routing link 65 with the memory to which it is connected (data_cur link, routing link with the memory of the current connection module). Each bidirectional link comprises an uplink and a downlink.The data_prev link (respectively the data_nxt link) can be connected to a dedicated interface link 61 to exchange data with the previous connection module (respectively with the next connection module).

[0087] In the example illustrated in [Fig.7], the connection module 60 is connected to the memory 42 of a calculation unit 41 (memory B). According to another example (for the first connection module of the column), the connection module 60 could be connected to a partition 31 of memory A; in this case there would be no dedicated interface link 61 connected to the routing link 63 data_prev. If the connection module 60 corresponds to the last connection module in the column, then there is no dedicated interface link 61 connected to the routing link 64 data_nxt.

[0088] To write data from the previous connection module into the memory 42 associated with the current connection module 60, the data passes through the downlink of the routing link 63 data_prev, then through the uplink of the routing link 65 data_cur.

[0089] To write data from the next connection module into the memory 42 associated with the current connection module 60, the data passes through the uplink of the routing link 64 data_nxt, then through the uplink of the routing link 65 data_cur.

[0090] To transmit data read in the memory 42 associated with the current connection module 60 to the previous connection module, the data passes through the downlink of the routing link 65 data_cur, then through the uplink of the routing link 63 data_prev.

[0091] To transmit data read from the memory 42 associated with the current connection module 60 to the next connection module, the data passes through the downlink of the routing link 65 data_cur, then through the downlink of the routing link 64 data_nxt.

[0092] The routing module 62 can also be configured to route data from the previous connection module to the next module without reading or writing to the memory 42 associated with the current connection module 60 (in this case the data passes through the downlink of the routing link 63 data_prev then through the downlink of the routing link 64 data_nxt). Similarly, the routing module 62 can be configured to route data from the next connection module to the previous module without reading or writing to the memory 42 associated with the current connection module 60 (in this case the data passes through the uplink of the routing link 64 data_nxt then through the uplink of the routing link 63 data_prev).

[0093] In particular embodiments, and as illustrated by way of example in [Fig.8], the routing module 62 may comprise an upper routing block 62a and a lower routing block 62b.

[0094] The upper routing block 62a can be configured in the following modes: - “Read”: to read data in memory 42 associated with the module 60 current connection and transmit the read data to the previous connection module, or - “Write”: to receive data from the previous connection module and write the received data into the memory 42 associated with the current connection module 60, or - “Default”: to receive data from the previous connection module and transfer the received data to the lower routing block 62b of the current connection module 60.

[0095] The lower routing block 62b can be configured in the following modes: - “Read”: to read data in memory 42 associated with the module 60 current connection and transmit the read data to the next connection module, or - “Write”: to receive data from the next connection module and write the received data into the memory 42 associated with the current connection module 60, or - “Default”: to receive data from the next connection module and transfer the received data to the upper routing block 62a of the current connection module 60.

[0096] It should be noted that, for reasons of simplification, the control signals with the memory 42 (conventional control signals making it possible, for example, to indicate the type of access (read or write) and the target address) are not shown in FIGS. 7 and 8.

[0097] In particular embodiments, and as illustrated in [Fig.9], the connection module 60 may comprise an arbitration module 70 making it possible to manage a priority of access to the memory 42 associated with the connection module 60. The priority is managed between: - a “dedicated” transfer involving a neighboring connection module 60 (previous or next connection module), - a “bus” transfer involving the interconnection bus 22.

[0098] As illustrated in [Fig.9], the arbitration module 70 can exchange (read or write) data with the interconnection bus 22 via a bidirectional routing link 72 data_bus. The arbitration module 70 can exchange data with the memory associated with the connection module 60 via a bidirectional routing link 73 data_mem.

[0099] The host processor 21 can in fact use the memory access control module 50 to exchange data with the memory B of a calculation unit 41 of the parallel processing processor 40, by passing through the interconnection bus 22, without passing through a dedicated interface link 61 connecting two neighboring connection modules 60; this is what is called a “bus” transfer. In this case the data transits on the interconnection bus 22 and on the routing links 72 data_bus and 73 data_mem.

[0100] The host processor 21 can also use the memory access control module 50 to transfer data between the memory A and a memory B of at least one calculation unit 41 of the parallel processing processor 40, passing through the dedicated interface links 61 connecting the connection modules 60 to each other, without passing through the interconnection bus 22; this is called a “dedicated” transfer. In this case, the data transits on dedicated interface links 61, on routing links 63 data_prev or 64 data_nxt, and on the routing links 65 data_cur and 73 data_mem.

[0101] In the case of concurrent access to the memory, for a “dedicated” transfer on the routing link 65 data_cur and for a “bus” transfer on the routing link 72 data_bus, the arbitration module 70 makes it possible to manage the priority of access to the memory, so as to authorize only one transfer at a time among the two concurrent transfers (or in other words to prohibit simultaneous access to the memory for these two concurrent transfers).

[0102] As illustrated in [Fig.9], a control link 71 ctrl_arb allows the memory access control module 50 to configure the arbitration module 70. Control signals (represented by dotted arrows in [Fig.9]) are associated respectively with the routing link 65 data_cur, the routing link 72 data_bus and the routing link 73 data_mem. These control signals make it possible, in a conventional manner, to indicate the type of access to the memory (read or write) and the target address. Furthermore, a return signal managed by the arbitration module 70 makes it possible to indicate to the routing module 62 (respectively to the interconnection bus 22) whether it is authorized to access the memory associated with the connection module 60.For example, return signals take the value '1' by default; the return signal associated with the data_cur routing link changes to the value '0' when a "bus" transfer is in progress; the return signal associated with the data_bus routing link changes to the value '0' when a "dedicated" transfer is in progress).

[0103] [Fig. 10] schematically represents an exemplary embodiment of the memory access control module 50 (DMPA) of the computing system 20 described with reference to FIGS. 2, 4 and 5.

[0104] The memory access control module 50 comprises a set 51 of configuration registers, with for example: - a “Source Address” register to indicate the source memory address of the transfer, - a “Dest. Address” register to indicate the destination memory address of the transfer, - a “Length” register to indicate the length of the transfer (for example in number of bytes), - a “Broadcast” register to handle the case where data must be transferred to several recipients (“broadcast”), - a “Control” register to initiate the transfer, - a “Status” register to provide information on the transfer in progress, and in particular to indicate the end of the transfer, - a “Priority” register to manage the priority between a “bus” transfer and a “dedicated” transfer.

[0105] The memory access control module 50 also includes an address generation unit 52 (AGU, for “Address Generator Unit”). The AGU allows the calculation of the source and destination addresses throughout the duration of a transfer.

[0106] In the example considered, the memory access control module 50 also comprises a control module 53 (Ctrl Mem) for each line of connection modules 60. Each control module 53 is adapted to configure in an identical manner all the connection modules 60 of the same line (i.e. all the connection modules 60 having the same ordering rank in the different columns).

[0107] It should be noted that, in a variant, it would be possible to envisage configuring the connection modules 60 of the same line differently; however, for this purpose it would be appropriate to implement several control modules for the same line (for example a control module for each connection module 60).

[0108] Each control module 53 takes as input a source address (signal addr_src), a destination address (signal addr_dest) and broadcast options (signal diff), and provides as output a configuration (signal cfg) intended for each connection module 60.

[0109] As seen previously, the control signal ctrl_arb allows the arbitration module 70 to be configured.

[0110] [Fig. 11] schematically illustrates the configuration of the different connection modules 60 by the control modules 53 of the DMPA.

[0111] As illustrated in [Fig.l 1], the signal cfg_0 corresponds to the configuration of the connection modules 60 associated with the partitions 31 of the memory A; the signal cfg_l corresponds to the configuration of the connection modules 60 associated with the memories B of the first calculation units of the different columns; the signal cfg_M corresponds to the configuration of the connection modules 60 associated with the memories B of the last calculation units of the different columns. The propagation of the signal ctrl_arb to the different connection modules 60 is not shown in [Fig. 11], for the sake of clarity.

[0112] Advantageously, in the example considered, the connection modules 60 are all implemented identically; the control modules 53 are also all implemented identically.

[0113] As illustrated in [Fig.l 1], it is possible to envisage using a loopback link 61r to connect the uplink and the downlink of the data_prev routing link of the first connection module 60 of each column, and to connect the downlink and the uplink of the data_nxt routing link of the last connection module 60 of each column. Such arrangements make it possible to manage certain particular scenarios of data broadcasting from the memory B of a computing unit 41 both to the memory B of at least one other computing unit 41 and to the memory A.

[0114] [Fig. 12] schematically represents the fields forming a source address or a destination address at the input of a control module 53 (address provided via the addr_src signal or the addr_dest signal). The address includes in particular a “pos” field indicating the position of the targeted memory, and an “addr” field indicating the local memory address in the targeted memory. In the example considered, the addr field is coded by low-order bits; the pos field is coded by high-order bits. In the example considered, all the connection modules 60 of the same row are configured identically (or in other words all the connection modules 60 positioned at the same position in a column are configured identically); it is therefore sufficient for the pos field to indicate the position in the column.For example, the pos field takes the value '0' to indicate partition 31 of memory A associated with the column; the pos field takes the value '1' to indicate memory B of the first calculation unit 41 of the column; ...; the pos field takes the value 'M' to indicate memory B of the last calculation unit 41 of the column.

[0115] [Fig. 13] schematically represents an exemplary embodiment of a control module 53 of the DMPA. Each control module 53 stores its position via a “loc_pos” register. As illustrated in [Fig. 13], different logic blocks make it possible to determine, from the addr_src and addr_dest signals and from the loc_pos register, whether the memory associated with a connection module 60 configured by the control module 53 is a source or a destination for the transfer, as well as the direction (upward or downward) of the transfer.

[0116] In particular, if addr_src_pos (value of the pos field of addr_src) is equal to loc_pos, then the memory associated with a connection module 60 configured by the control module 53 is a source for the transfer considered (it will be necessary to carry out a reading in this memory); the signal s is then activated (it is set to the value '1') in the logic block 57 (otherwise it is set to the value '0').

[0117] If addr_dest_pos (value of the pos field of addr_dest) is equal to loc_pos, then the memory associated with a connection module 60 configured by the control module 53 is a destination for the transfer in question (a write will have to be performed in this memory); the signal d is then set to the value '1' in logic block 57 (otherwise it is set to the value '0').

[0118] If addr_src_pos is strictly greater than addr_dest_pos, then it is a downward transfer; the signal u is then set to '0' in logic block 57. Otherwise, it is an upward transfer; the signal u is then set to '1' in logic block 57.

[0119] A routing module 62 can then be configured according to the signals s, d and u. More particularly, the upper routing block 62a is configured (signal cfg_a at the output of the multiplexer 54 in [Fig. 13]): - in “Read” mode if the s and u signals are both activated (i.e. if they both take the value '1'), - in “Write” mode if the d signal is activated and the u signal is deactivated, - in “Default” mode otherwise.

[0120] The lower routing block 62b is configured (cfg_b signal at the output of the multiplexer 55 in [Fig. 13]): - in “Read” mode if the s signal is activated and the u signal is deactivated, - in “Write” mode if the d and u signals are both activated, - in “Default” mode otherwise.

[0121] As illustrated in [Fig.13], a configuration of an upper or lower routing block includes a control signal es (“chip select”) and a control signal we (“write enable”). In “Read” mode, the signal es is enabled and the signal we is disabled; in “Write” mode, the signal es and the signal we are both enabled; in “Default” mode, the signal es and the signal we are both disabled. The configuration also includes an addr signal indicating the local address targeted for reading (if the signal s is enabled, then it is the addr field of addr_src) or for writing (if the signal d is enabled, then it is the addr field of addr_dest).

[0122] When a data transfer requires writing data into the memories associated with several connection modules 60 of the same column (broadcasting of data to several recipients within the same column), the diff signal includes information on the connection modules 60 involved in these multiple writes. For example, the diff signal provides coded information in the form of a bit field comprising as many bits as there are connection modules 60 per column. Each bit of the bit field is respectively associated with a position of a connection module 60 in the column (for example the first least significant bit corresponds to the connection module 60 associated with the partition 31 of the memory A, the second least significant bit corresponds to the first connection module 60 of a column, ..., the (M+1)th least significant bit corresponds to the last connection module 60 of a column). The value of a bit of the bit field takes the value '1' if the corresponding connection module 60 is involved in a multiple write (i.e. if it is one of the recipients for the transfer in question). Otherwise, the bit takes the value '0'.

[0123] As illustrated in [Fig.13], a mask loc_diff_msk may be stored in a register of the control module 53 to check whether the connection modules 60 they configure are involved in a multiple write (e.g., by bitwise comparison of diff and loc_diff_msk). If so, then the signal d is activated.

[0124] In addition to the es and we signals, the configuration of an upper 62a or lower 62b routing block includes a control signal br (“broadeast”). This signal is always deactivated (it takes the value '0') in “Read” mode. This signal is activated (it takes the value '1') in “Write” mode or in “Default” mode when the diff signal indicates that the transfer involves several recipients.

[0125] Let us consider a first example of transfer for a case with M = 2, that is to say two computing units 41 per column (that is to say three connection modules 60 per column). For this first example of transfer: - for each column of index i, a parallel transfer of data from the computing unit UC; i to the partition A; must be carried out; - addr_src = h0002_0100 (pos = 2 and addr = hOlOO), this means that for each computing unit UCi,i, the data must be read from a region at the local address hOlOO of the computing unit's memory B; - addr_dest = h0000_0000 (pos = 0 and addr = hOOOO), this means that in each partition, data must be written to a region located at the local address hOOOO of the partition, - diff = bOOO, this means that there is no broadcasting of data to several recipients (in each column partition A; is the only recipient).

[0126] Under these conditions, in each column, the upper routing block of the last connection module (third connection module) is configured in the “Read” mode, the lower and upper routing blocks of the intermediate connection module (second connection module) are configured in the “Default” mode, and the lower routing block of the first connection module is configured in the “Write” mode. The upper routing module of the first connection module and the lower routing module of the last connection module are configured in the “Default” mode.

[0127] Let us consider a second example of transfer for a case with M = 2, for which: - for each column of index i, a parallel transfer of data from the partition Ai to the two calculation units UCi,0 and UCi,i of the column must be carried out, - addr_src = h0000_0100 (pos = 0 and addr = hOlOO), this means that for each partition, the data to be transferred must be read from a region at the local address hOlOO of the partition, - addr_dest = h0001_0050 (pos = 1 and addr = h0050), this means that in each column, the data must be written in a memory region located at the local address h0050 of memory B of the first calculation unit, - diff = bl 10, this means that in each column the data must be broadcast to several recipients, namely the two calculation units UCij0 and UCi,i of the column.

[0128] Under these conditions, in each column, the lower routing block of the first connection module (third connection module) is configured in the “Read” mode, the upper routing block of the second intermediate connection module is configured in the “Write” mode, the lower routing block of the second connection module is configured in the “Default” mode, the upper routing block of the third connection module is configured in the “Write” mode. The upper routing module of the first connection module and the lower routing module of the last connection module are configured in the “Default” mode.

[0129] [Fig. 14] schematically represents an exemplary embodiment of the routing module 62. An upper routing block (upper part of the routing module 62 in the figure) is configured by a control module 53 of the DMPA 50 via the signal cfg_a; a lower routing block (lower part of the routing module 62 in the figure) is configured by the control module 53 via the signal cfg_b. The control signals relating to the upper routing block are named with the suffix “_a” (cs_a, addr_a, we_a and br_a), while the control signals relating to the lower routing block are named with the suffix “_b” (cs_b, addr_b, we_b and br_b). With reference to [Fig.9], the links rdata_prev and wdata_prev correspond respectively to the uplink and the downlink of the routing link 63 data_prev; the links wdata_nxt and rdata_nxt correspond respectively to the uplink and the downlink of the routing link 64 data_nxt; the links wdata_cur and rdata_cur correspond respectively to the uplink and the downlink of the routing link 65 data_cur. .

[0130] When the upper routing block is configured in "Write" mode, data arriving on the wdata_prev link is routed to the wdata_cur link, and the control signals cs_cur, we_cur and addr_cur correspond respectively to the control signals cs_a, we_a and addr_a.

[0131] When the upper routing block is configured in “Read” mode, the control signals cs_cur, we_cur and addr_cur correspond respectively to the signals of controls cs_a, we_a and addr_a, and the data read from the memory associated with the routing module 62 is routed from the rdata_cur link to the rdata_prev link.

[0132] When the upper routing block is configured in "Default" mode, if a data broadcast is to take place (in this case the br_b control signal is activated), then the data arriving on the rdata_fwd link (from the next connection module) is routed to the rdata_prev link.

[0133] A similar operation takes place at the lower routing block. When the lower routing block is configured in "Write" mode, data arriving on the wdata_nxt link is routed to the wdata_cur link, and the control signals cs_cur, we_cur and addr_cur correspond respectively to the control signals cs_b, we_b and addr_b.

[0134] When the lower routing block is configured in “Read” mode, the control signals cs_cur, we_cur and addr_cur correspond respectively to the control signals cs_b, we_b and addr_b, and the data read from the memory associated with the routing module 62 are routed from the rdata_cur link to the rdata_nxt link.

[0135] When the lower routing block is configured in "Default" mode, if a data broadcast is to take place (in this case the control signal br_a is activated), then the data arriving on the wdata_fwd link (coming from the previous connection module) is routed to the rdata_nxt link.

[0136] Figures 15 to 20 correspond to a second embodiment of a routing module 62.

[0137] [Fig. 15] schematically represents an exemplary embodiment of an upper routing block 62a or a lower routing block 62b for this second embodiment (the upper routing block 62a and the lower routing block 62b are both implemented identically). The signals rdata and wdata correspond respectively to the signals rdata_prev and wdata_prev in the case of an upper routing block. The signals rdata and wdata correspond respectively to the signals rdata_nxt and wdata_nxt in the case of a lower routing block.

[0138] [Fig. 16] represents the production of an intermediate connection module for a memory B of a computing unit 41 by connecting an upper routing block 62a and a lower routing block 62b to a memory B of a computing unit 4L. The reference 6lu (respectively 61d) corresponds to an uplink (respectively downlink) of a dedicated interface link 61 with a neighboring connection module.

[0139] [Fig. 17] represents the production of a first connection module (at the top of the column) by connecting a lower routing block 62b to a partition 31 of the memory A.

[0140] [Fig. 18] represents the production of a last connection module (at the bottom of the column) by connecting an upper routing block 62b to the memory B of the last calculation unit 41 of the column.

[0141] In this second embodiment, the connection modules at the head and foot of the column only comprise a single routing block (unlike the intermediate connection modules which comprise two). It is therefore possible to simplify the control module 53' which configures the connection modules at the head or foot of the column, as illustrated in [Fig. 19].

[0142] [Fig.20] illustrates the configuration of three connection modules of a column according to the second embodiment described above.

Claims

1. Claims Calculation system (20) comprising a memory (30), called "memory A", a memory access control module (50), and a parallel processing processor (40) comprising a plurality of calculation units (41), each calculation unit (41) comprising one or more elementary processors (43) and a memory (42), called "memory B", shared by said elementary processors (43), the calculation units (41) of the parallel processing processor (40) are arranged in several columns and, in each column, the calculation units (41) are ordered from a first calculation unit to a last calculation unit, with zero, one or more intermediate calculation units between the first calculation unit and the last calculation unit, the first calculation unit corresponding to the last calculation unit when the column only comprises a single calculation unit; the computing system (20) is characterized in that the memory A is partitioned so as to associate a partition (31) of the memory A with each column of computing units (41) and, for each column: the computing system (20) comprises connection modules (60) ordered from a first connection module connected to the partition (31) of the memory A, to a last connection module connected to the memory B of the last computing unit, with zero, one or more intermediate connection modules between the first connection module and the last connection module, each intermediate connection module being connected to the memory B of a computing unit, the first connection module has a dedicated interface link (61) with the following connection module, each intermediate connection module has a dedicated interface link (61) on the one hand with the previous connection module and on the other hand with the following connection module,the last connection module has a dedicated interface link (61) with the previous connection module;, the memory access control module (50) is adapted to configure the connection modules (60) to make a first data transfer, for a first column, between the partition (31) of the memory A associated with said first column and a memory B of at least one calculation unit (41) of said first column and, simultaneously with the first transfer, make at least a second data transfer, for a second column, between the partition (31) of memory A associated with said second column and a memory B of at least one calculation unit (41) of said second column, said data transfers being carried out by passing through the dedicated interface links (61) connecting the connection modules (60) together.

2. Calculation system (20) according to claim 1, for which the first data transfer makes it possible to transfer data from the partition (31) of the memory A associated with the first column to the memories B of several different calculation units (41) of the first column, passing at most once through the connection module (60) of each calculation unit (41) of the first column.

3. A computing system (20) according to any one of claims 1 to 2, wherein the memory access control module (50) is adapted to configure the connection modules (60) to transfer data, for at least one column, from a memory B of a computing unit (41) of said column to a memory B of at least one other computing unit (41) of said column.

4. A computing system (20) according to any one of claims 1 to 3, wherein the memory access control module (50) is adapted to configure the connection modules (60) to make simultaneous data transfers involving several columns with, for each column involved, a data transfer from a region of the partition (31) located at a local source address identical for all the columns involved, to a region of a memory B of at least one computing unit (41), said region being located at a local destination address identical for all the columns involved.

5. A computing system (20) according to any one of claims 1 to 4, wherein the memory access control module (50) is adapted to configure the connection modules (60) to make simultaneous data transfers involving several columns with, for each column involved, a data transfer from a region of a memory B of a computing unit (41), said region being located at a local source address identical for all the columns. involved, to a region of the partition (31) located at a local destination address identical for all the columns involved.

6. A computing system (20) according to any one of claims 1 to 5, wherein each intermediate connection module (60) comprises an upper routing block (62a) and a lower routing block (62b), the upper routing block (62a) being configurable in the following modes: - "Read": to read data from the memory B to which the intermediate connection module is connected and transmit the read data to the previous connection module, or - "Write": to receive data from the previous connection module and write the received data to the memory B to which the intermediate connection module is connected, or - "Fault": to receive data from the previous connection module and transfer the received data to the lower routing block (62b) of the intermediate connection module,the lower routing block (62b) being configurable in the following modes: - "Read": to read data in the memory B to which the intermediate connection module is connected and transmit the read data to the next connection module, or - "Write": to receive data from the next connection module and write the received data in the memory B to which the intermediate connection module is connected, or - "Fault": to receive data from the next connection module and transfer the received data to the upper routing block (62a) of the intermediate connection module.,

7. A computing system (20) according to any one of claims 1 to 6, wherein: the first connection module (60) comprises a lower routing block (62b) which can be configured in the following modes: - "Read": to read data in the memory A and transmit the read data to the next connection module, - "Write": to receive data from the next connection module and write received data in the memory A; the last connection module (60) comprises an upper routing block (62a) which can be configured in the following modes: - “Read”: to read data in memory B of the last connection module and transmit the read data to the previous connection module, - “Write”: to receive data from the previous connection module and write the received data in memory B of the last connection module.

8. Calculation system (20) according to any one of claims 1 to 7 in which the memory access control module (50) comprises at least two control modules (53), each control module (53) being adapted to configure in an identical manner all the connection modules (60) having the same ordering rank in the different columns.

9. A computing system (20) according to claim 8 wherein the connection modules (60) are all implemented identically, and the control modules (53) are all implemented identically.

10. A computing system (20) according to any one of claims 1 to 9 comprising a host processor (21) and an interconnect bus (22), the partitions (31) of memory A being defined with a contiguous address mapping, the memory A comprising program code instructions for configuring the host processor (21), the program code instructions being stored in a region of memory A separate from the partitions (31).

11. Computing system (20) according to any one of claims 1 to 10 comprising a host processor (21) and an interconnection bus (22), the host processor (21) being adapted to configure the memory access control module (50) to exchange data with the memory A or with a memory B of at least one computing unit (41) of the parallel processing processor (40), via the interconnection bus (22), without passing through a dedicated interface link (61) connecting two neighboring connection modules (60), each connection module (60) comprises an arbitration module (70) to manage a priority of access to the memory to which the connection module (60) is connected, between: - a "dedicated" transfer involving a neighboring connection module (60), - a "bus" transfer involving the interconnection bus (22).

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