Manufacturing process

Abstract

Manufacturing Method This description relates to a manufacturing method for an electronic device (1) comprising a phase-change memory cell, the method comprising: forming a first layer (18) of a resistive material; forming a stack of layers (20, 22, 24) on the first layer (18), the stack comprising at least a second layer (20) of a phase-change material; etching the stack (20, 22, 24), said etching stopping when the first layer (18) is reached around the location of the memory cell; forming a spacer (28) on the lateral walls of the stack; and then etching the first layer (18) such that the stack (20, 22, 24) rests on a central portion of the first layer (18) and the spacer rests on a peripheral portion of the first layer. Figure for the abstract: Fig. 1

Description

Title of the invention: Manufacturing method Technical field

[0001] The present description relates generally to electronic devices and their manufacturing methods and more particularly to phase change memory devices. Prior art

[0002] In a conventional phase change memory, each memory cell comprises, for example, a layer of phase change material which is in contact with a resistive element. Phase change materials are materials which can switch between a crystalline phase and an amorphous phase. This switching is caused by an increase in the temperature of the resistive element through which an electric current is passed. The difference in electrical resistance between the amorphous phase of the material and its crystalline phase is used to define at least two memory states, arbitrarily 0 and 1.

[0003] Memories are generally arranged in the form of matrices, comprising word lines and bit lines, i.e. rows and columns. A memory cell, containing binary information, is located at each intersection of a row and a column.

[0004] The information contained in a cell of a phase change memory is for example accessed, or read, by measuring the resistance between the bit line and the word line of the memory cell.

[0005] The phase change memory cells are for example located in an interconnection network. By interconnection network is meant a stack of insulating layers, formed during the so-called "back end of line" manufacturing steps, in which are located metal tracks connected to each other by conductive vias. Preferably, the levels of the interconnection network, each comprising conductive tracks in an insulating layer and conductive vias in an insulating layer, have a constant height.

[0006] Some methods for manufacturing phase-change memory cells include a step of etching a metal layer. The metal layer is, for example, made of a material that can be etched by the same etching methods as the phase-change material of the memory cell. Thus, such methods risk causing unintentional etching of the phase-change material, which can lead to performance reductions. Summary of the invention

[0007] One embodiment provides a method of manufacturing an electronic device comprising a phase change memory cell, the method comprising: forming a first layer of a resistive material; forming a stack of layers on the first layer, the stack comprising at least a second layer of a phase change material; etching the stack, said etching stopping when the first layer is reached around the location of the memory cell; forming a spacer on the side walls of the stack; then etching the first layer, such that the stack rests on a central portion of the first layer and the spacer rests on a peripheral portion of the first layer.

[0008] Another embodiment provides an electronic device comprising a memory cell, the phase change memory cell comprising: a first layer of a resistive material; a stack of layers resting on a central portion of the first layer, the stack comprising at least a second layer of a phase change material; and a spacer resting on the side walls of the stack and on a peripheral portion of the first layer.

[0009] According to one embodiment, the second layer is in contact with the first layer.

[0010] According to one embodiment, the first layer is entirely covered by the stack and the spacer.

[0011] According to one embodiment, the first layer is made of a material having a resistivity greater than 10 mΩ / cm.

[0012] According to one embodiment, the maximum distance between an inner wall of the spacer and a nearest outer wall of the spacer is less than 5 nm.

[0013] According to one embodiment, the thickness of the first layer is between 2 nm and 3 nm.

[0014] According to one embodiment, the stack comprises at least a third layer of a conductive material covering the second layer.

[0015] According to one embodiment, the stack comprises at least a fourth layer of an insulating material covering the third layer.

[0016] According to one embodiment, the second layer is made of an alloy comprising at least one chalcogen element.

[0017] According to one embodiment, the first layer is in contact with an L-shaped resistive element.

[0018] According to one embodiment, the first layer is made of a refractory metal and / or a refractory metal nitride, for example tantalum, tungsten, TiSiN, TiN or TaN.

[0019] According to one embodiment, the spacer is made of SiC14, SiN or SiC.

[0020] According to one embodiment, the formation of the spacer is carried out in the same enclosure as the step of etching the stack, the device not having been removed from the enclosure between the steps.

[0021] According to one embodiment, the etching of the stack forms a pattern of the stack on the first layer.

[0022] According to one embodiment, the step of etching the stack is preceded by the formation of an etching mask covering the location of the memory cell. Brief description of the drawings

[0023] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0024] [Fig.l] represents an embodiment of a device comprising a memory cell;

[0025] [Fig.2] illustrates a step of a method of manufacturing an electronic device;

[0026] [Fig.3] illustrates another step in a method of manufacturing an electronic device electronics;

[0027] [Fig.4] illustrates another step of a method of manufacturing an electronic device;

[0028] [Fig.5] illustrates another step of a method of manufacturing an electronic device; and

[0029] [Fig.6] illustrates another step in a method of manufacturing an electronic device. Description of the embodiments

[0030] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0031] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed.

[0032] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0033] In the following description, when referring to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., are referred to, unless otherwise specified, the orientation of the figures.

[0034] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0035] [Fig.l] represents an embodiment of a device comprising a memory cell 1.

[0036] The device comprises an insulating layer 10 located, for example, on a substrate not shown. A conductive element 12, for example a via or a wall, is located in the layer 10. The element 12 passes through the layer 10 from an upper face to a lower face, for example so as to reach the substrate in contact with the lower face.

[0037] The device further comprises a resistive element 14, for example having an L shape. More precisely, the device comprises an insulating layer 16 crossed by the resistive element 14 so as to reach the conductive element 12. The element 14 comprises for example a horizontal part resting on the element 12 and a vertical part extending between the lower and upper faces of the layer 16, so as to be in contact with the element 12 and to have one end flush with the upper face of the layer 16.

[0038] The device further comprises a layer 18. The layer 18 partially covers the layer 16. More specifically, the layer 18 covers, and is in contact with, the upper end of the element 14 flush with the upper face of the layer 16, and the upper face of the layer 16 surrounding the upper end of the element 14. The layer 18 is preferably a planar layer.

[0039] Layer 18 preferably has a constant thickness. Layer 18 has, for example, a thickness of between 2 nm and 3 nm.

[0040] The layer 18 is made of a material, preferably a metal, having a high resistivity. In other words, the layer 18 has a resistivity at least equal to 10 mΩ / cm. The layer 18 is preferably made of the same material as the material of the resistive element 14. The layer 18 is for example made of a refractory metal and / or a refractory metal nitride. The layer 18 is for example made of tantalum, tungsten, TiSiN, TiN or TaN.

[0041] The device further comprises a stack of layers comprising at least one layer 20 made of a phase change material. In the example of [Fig. 1], said stack further comprises a layer 22 and a layer 24.

[0042] The layers 20, 22, 24 preferably have substantially identical lateral dimensions. The side walls of the layers 20, 22, 24 are preferably coplanar.

[0043] Layer 18 covers a central portion of layer 14. Thus, a central portion of the upper face of layer 18 is covered by, and in contact with, layer 20. A peripheral portion of the upper face of layer 18 is not covered by layer 20. The peripheral part is not covered by layers 22 or 24. The peripheral part completely surrounds the central part.

[0044] The layer 20 is made of a phase-change material, that is to say a material that changes phase when the layer 20 is subjected to a programming current having a value greater than a threshold. The layer 20 is for example made of a homogeneous material, that is to say each portion of the layer 20 is made of the same material, preferably in the same proportions. The layer 20 preferably comprises a chemical element from the chalcogen family. The chalcogen family more precisely comprises oxygen, sulfur, selenium, tellurium and polonium. The layer 20 is for example a chalcogen element alone or, preferably, an alloy comprising a chalcogen element. The layer 20 is for example made of an alloy of germanium, antimony and tellurium. The layer 20 is for example made of an alloy of germanium and tellurium.More generally, layer 20 is for example made of an alloy of germanium and at least one other chemical element from at least one of columns 13, 14, 15, and 16 of the periodic table of elements. The elements in column 13 are considered to be boron, aluminum, gallium, indium, thallium, and nihonium. The elements in column 14 are considered to be carbon, silicon, germanium, tin, lead, and flerovium. The elements in column 15 are considered to be nitrogen, phosphorus, arsenic, antimony, bismuth, and moscovium. The elements in column 16 are considered to be oxygen, sulfur, selenium, tellurium, polonium, and livermorium.

[0045] The layer 20 preferably has a constant thickness. The layer 20 has, for example, a thickness of between 40 nm and 60 nm.

[0046] Layer 22 preferably completely covers layer 20. Layer 22 is preferably completely in contact with layer 20. Layer 22 is a conductive layer, for example made of metal, for example titanium nitride.

[0047] Layer 24 preferably completely covers layer 22. Layer 24 is preferably completely in contact with layer 22. Layer 24 is an insulating layer, for example made of silicon nitride.

[0048] The device comprises spacers 28 extending over the side walls of the layers 20, 22, 24. The spacers 28 are made of an insulating material, for example SiCl4, SiN, or SiC. The spacers 28 extend at least over the side walls of the layer 20. The spacers 28 extend from the upper face of the layer 18. The spacers 28 extend at least to the level of the upper face of the layer 20. In the example of [Fig. 4], the spacers 28 extend to the level of the upper face of the layer 24.

[0049] The maximum thickness of the spacers 28, i.e. the maximum distance between an internal wall of a spacer and the nearest external wall, is preferably in less than 5 nm, preferably between 2 nm and 3 nm. By inner wall is meant the wall in contact with the layers 20, 22, 24. By outer wall is meant the wall opposite the inner wall, i.e. the wall not in contact with either the layer 18 or the layers 20, 22, 24.

[0050] The spacers 28 completely cover the peripheral part of the upper face of the layer 18. The upper face of the layer 18 is thus completely covered by the layer 20 and the spacers 28.

[0051] The device further comprises a passivation layer 30 on the memory cell. The layer 30 is made of an insulating material, for example silicon nitride or silicon carbide. The layer 30 preferably conformally covers the upper face of the layer 16, the side walls of the layer 18, the spacers 28 and the upper face of the layer 24.

[0052] Figures 2 to 6 illustrate steps, preferably successive, of a method of manufacturing an electronic device comprising a memory. More specifically, Figures 1 to 6 illustrate an embodiment of a method of manufacturing a memory cell of the device. The method described can of course be used to manufacture a plurality of memory cells.

[0053] [Fig.2] illustrates a step in a method of manufacturing an electronic device.

[0054] During this step, an insulating layer 10 is formed, for example on a substrate not shown. A conductive element 12, for example a via or a wall, is formed in the layer 10. The element 12 passes through the layer 10 from an upper face to a lower face, for example so as to reach the substrate in contact with the lower face.

[0055] The step of [Fig.2] further comprises the formation of a resistive element 14, for example having an L shape. More precisely, the step of [Fig.2] comprises the formation of an insulating layer 16 and the formation of the resistive element 14 passing through the layer 16 and reaching the conductive element 12. The element 14 comprises for example a horizontal part resting on the element 12 and a vertical part extending between the lower and upper faces of the layer 16, so as to be in contact with the element 12 and to have one end flush with the upper face of the layer 16.

[0056] The step of [Fig.2] further comprises the formation of a stack 17 of layers on the layer 16 and on the upper end of the element 14. The stack 17 is for example formed on the entire structure resulting from the formation of the layer 16 and the element 14. The stack 17 covers at least the locations of the memory cells.

[0057] The stack 17 comprises a lower layer 18. The layer 18 is thus the layer of the stack 17 closest to the layer 16. More precisely, the layer 18 covers the layer 16 and the upper end of the element 14. The layer 18 preferably completely covers the upper face of layer 16, i.e. the face of layer 16 furthest from layer 10. Layer 18 covers, and is in contact with, the end of the vertical part of element 14 flush with the upper face of layer 16. Layer 18 is preferably a flat layer.

[0058] Layer 18 preferably has a constant thickness. Layer 18 has, for example, a thickness of between 2 nm and 3 nm.

[0059] The layer 18 is made of a material, preferably a metal, having a high resistivity. In other words, the layer 18 has a resistivity at least equal to 10 mΩ / cm. The layer 18 is preferably made of the same material as the material of the resistive element 14. The layer 18 is for example made of a refractory metal and / or a refractory metal nitride. The layer 18 is for example made of tantalum, tungsten, TiSiN, TiN or TaN.

[0060] The stack 17 comprises a layer 20. The layer 20 is made of a phase change material, i.e. a material that changes phase when the layer 20 is subjected to a programming current having a value greater than a threshold. The layer 20 preferably completely covers the layer 18. The layer 20 is preferably completely in contact with the layer 18.

[0061] The layer 20 is for example made of a homogeneous material, that is to say each portion of the layer 20 is made of the same material, preferably in the same proportions. The layer 20 preferably comprises a chemical element from the chalcogen family. The chalcogen family more specifically comprises oxygen, sulfur, selenium, tellurium and polonium. The layer 20 is for example a chalcogen element alone or, preferably, an alloy comprising a chalcogen element. The layer 20 is for example made of an alloy of germanium, antimony and tellurium. The layer 20 is for example made of an alloy of germanium and tellurium. More generally, the layer 20 is for example made of an alloy comprising at least germanium and a chalcogen element. The layer 20 is for example made of an alloy comprising germanium, a chalcogen element and at least one element from columns 13, 14, 15, 16 of the periodic table of elements.

[0062] The layer 20 preferably has a constant thickness. The layer 20 has, for example, a thickness of between 40 nm and 60 nm.

[0063] The stack 17 may comprise a layer 22. The layer 22 preferably completely covers the layer 20. The layer 22 is preferably completely in contact with the layer 20. The layer 20 is a conductive layer, for example made of metal, for example titanium nitride.

[0064] The stack 17 may comprise a layer 24. The layer 24 preferably completely covers the layer 22. The layer 24 is preferably completely in contact with the layer 22. The layer 24 is an insulating layer, for example made of silicon nitride.

[0065] [Fig.3] illustrates another step in a method of manufacturing an electronic device.

[0066] During this step, the stack 17, with the exception of the layer 18, is etched outside the locations of the memory cells. In other words, in the example of [Fig. 3], the layers 20, 22, 24 are etched around the location of the memory cell. Thus, the step of [Fig. 3] comprises for example a step of etching, up to the upper face of the layer 18, of the stack 17 in which the portions of the stack 17 located between the columns of memory cells are etched and a step of etching, up to the upper face of the layer 18, of the stack 17 in which the portions of the stack 17 located between the rows of memory cells are etched.

[0067] The etching performed in the step of [Fig.3] is configured to reach the upper face of layer 18. Layer 18 is not etched during the step of [Fig.3]

[0068] [Fig.4] illustrates another step in a method of manufacturing an electronic device.

[0069] During this step, a layer 26 is formed conformally on the structure resulting from the step of [Fig. 3]. The layer 26 preferably covers the entire structure resulting from the step of [Fig. 3]. The layer 26 covers in particular the upper face of the layer 18, the side walls of the layers of the stack 17 having been etched during the step of [Fig. 3], the upper face of the upper layer of the stack 17, that is to say the layer 24 in the example of [Fig. 4].

[0070] The layer 26 is made of an insulating material. The layer 26 is for example made of silicon nitride. The layer 26 corresponds for example to a stack of one or more layers of silicon nitride and one or more layers of silicon carbide. The layer 26 preferably has a thickness of less than 5 nm, for example between 2 nm and 3 nm.

[0071] According to a first embodiment, the layer 26 is formed ex situ, that is to say outside the enclosure in which the etching step of [Fig. 3] is carried out. The layer is then formed by depositing a layer of silicon nitride or layers of silicon nitride and silicon carbide.

[0072] According to a second embodiment, the layer 26 is formed in situ, that is to say in the enclosure in which the etching step of [Fig. 3] is carried out. Preferably, the structure resulting from the step of [Fig. 3] is not removed from said enclosure between the step of [Fig. 3] and the formation of the layer 26. The formation of the layer 26, comprising for example silicon, nitrogen and chlorine, comprises for example the formation of a plasma and the application of SiCl4 and N2 gases.

[0073] [Fig.5] illustrates another step in a method of manufacturing an electronic device. electronics.

[0074] The step of [Fig. 5] comprises a step of anisotropic etching of the layer 26. More precisely, the step of [Fig. 5] comprises the formation of spacers 28 extending for example on the side walls of the layers 20, 22, 24. The spacers 28 extend at least on the side walls of the layer 20. The spacers 28 extend from the upper face of the layer 18. The spacers 28 extend at least up to the level of the upper face of the layer 20. In the example of [Fig. 5], the spacers 28 extend up to the level of the upper face of the layer 24.

[0075] The maximum thickness of the spacers 28, i.e. the maximum distance between an inner wall of a spacer and the nearest outer wall, is preferably less than 5 nm, preferably between 2 nm and 3 nm. By inner wall is meant the wall in contact with the layers 20, 22, 24. By outer wall is meant the wall opposite the inner wall, i.e. the wall not in contact with either the layer 18 or the layers 20, 22, 24.

[0076] [Fig.6] illustrates another step in a method of manufacturing an electronic device.

[0077] The step of [Fig.6] comprises a partial etching of the layer 18. More precisely, the portions of the layer 18 surrounding the cells are etched. In other words, the portions of the layer 18 not being protected by the spacers 28 and the layers 20, 22, 24 are etched.

[0078] The etching method of layer 18 is for example a chemical etching, for example based on chlorine. The etching of layer 18 is preferably carried out by the same etching method as that used to etch layers 20, 22, 24. The etching is preferably a selective etching of the material of layer 18 relative to the material of layer 24 and to the material of spacers 28. By selective, it is meant that the etching etches the material of layer 18 at least twice as fast as the materials of layer 24 and spacers 28.

[0079] Layer 18 comprises side walls coplanar with the outer walls of the lower parts of the spacers. Layer 18 is thus entirely covered by the spacers and layer 20.

[0080] The method further comprises a step subsequent to the step of [Fig. 6]. During this step, a passivation layer, not shown, is formed on the memory cell. More precisely, a layer of an insulating material, for example silicon nitride or silicon carbide, is formed, preferably conformally, on the structure resulting from the step of [Fig. 5]. The layer thus covers the upper face of layer 16, the side walls of layer 18, the spacers 28 and the upper face of layer 24.

[0081] We could have chosen not to form the spacers 28 and to etch the layer 18 in same time as the rest of the stack 17. However, the material of layers 20, 22, 24 is etched faster than the material of layer 18. Thus, during the etching of layer 18, layer 20 located in the location of the memory cell would be etched from the side walls. The profile of the cell and its critical dimensions would then not correspond to the target values. In addition, there could be a variation in the critical dimensions and profile between the cells of the same device.

[0082] An advantage of the described embodiments is that it is possible to etch the stack comprising the highly resistive layer and the phase change material without causing damage to the phase change material layer.

[0083] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art.

[0084] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims

Claims

1. A method of manufacturing an electronic device (1) comprising a phase change memory cell, the method comprising: forming a first layer (18) of a resistive material; forming a stack of layers (20, 22, 24) on the first layer (18), the stack comprising at least one second layer (20) of a phase change material; etching the stack (20, 22, 24), said etching stopping when the first layer (18) is reached around the location of the memory cell; forming a spacer (28) on the side walls of the stack (20, 22, 24); then etching the first layer (18), such that the stack (20, 22, 24) rests on a central part of the first layer (18) and the spacer (28) rests on a peripheral part of the first layer (18).

2. An electronic device (1) comprising a memory cell, the phase change memory cell comprising: a first layer (18) of a resistive material; a stack of layers (20, 22, 24) resting on a central portion of the first layer (18), the stack comprising at least one second layer (20) of a phase change material; and a spacer (28) resting on the side walls of the stack and on a peripheral portion of the first layer (18).

3. A method according to claim 1 or a device according to claim 2, wherein the second layer (20) is in contact with the first layer (18).

4. A method according to claim 1 or 3 or a device according to claim 2 or 3, wherein the first layer (18) is entirely covered by the stack (20, 22, 24) and the spacer (28).

5. A method according to any one of claims 1, 3 or 4 or a device according to any one of claims 2 to 4, wherein the first layer (18) is made of a material having a resistivity greater than 10 mΩ / cm.

6. A method according to any one of claims 1, 3 to 5 or a device according to any one of claims 2 to 5, wherein the maximum distance between an inner wall of the spacer (28) and an outer wall of the nearest spacer (28) is less than 5 nm.

7. A method according to any one of claims 1, 3 to 6 or a device according to any one of claims 2 to 6, wherein the thickness of the first layer (18) is between 2 nm and 3 nm.

8. Method according to any one of claims 1, 3 to 7 or device according to any one of claims 2 to 7, in which the stack (20, 22, 24) comprises at least a third layer (22) of a conductive material covering the second layer (20).

9. A method or device according to claim 8, wherein the stack (20, 22, 24) comprises at least a fourth layer (24) of an insulating material covering the third layer (22).

10. Method according to any one of claims 1, 3 to 9 or device according to any one of claims 2 to 9, in which the second layer (20) is made of an alloy comprising at least one chalcogen element.

11. A method according to any one of claims 1, 3 to 10 or a device according to any one of claims 2 to 10, wherein the first layer (18) is in contact with an L-shaped resistive element (14).

12. A method according to any one of claims 1, 3 to 11 or a device according to any one of claims 2 to 11, wherein the first layer (18) is made of a refractory metal and / or a refractory metal nitride, for example tantalum, tungsten, TiSiN, TiN or TaN.

13. A method according to any one of claims 1, 3 to 12 or a device according to any one of claims 2 to 12, wherein the spacer is (28) made of SiCl4, SiN or SiC.

14. A method according to any one of claims 1, 3 to 13, wherein the formation of the spacer (28) is carried out in the same enclosure as the step of etching the stack (20, 22, 24), the device not having been removed from the enclosure between the steps.

15. A method according to any one of claims 1, 3 to 14, wherein the etching of the stack (20, 22, 24) forms a pattern of the stack on the first layer (18).

16. Method according to any one of claims 1, 3 to 15, in which the step of etching the stack is preceded by the formation of an etching mask covering the location of the memory cell.

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