Phase change memory
By introducing a spacer layer structure of an oxide interlayer and a nitride layer into the phase change memory unit, the problem of thermal crosstalk in the phase change memory is solved, and higher read and write reliability and performance are achieved.
Patent Information
- Application Number
- CN202510360837.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-25
- Publication Date
- 2025-06-13
AI Technical Summary
In a phase change memory, thermal crosstalk between phase change memory cells leads to misreading during read operations.
A phase change storage unit is designed, including a phase change storage material and a spacer layer, which consists of an oxide interlayer and a nitride layer to form an N-O-N structure to increase thermal boundary resistance and reduce heat transfer efficiency.
It effectively improves thermal crosstalk between each phase change memory cell in the phase change memory, reduces the misread rate during read operation, and improves the reliability and performance of the memory.
Smart Images
Figure CN120152299A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and particularly to a phase change memory. Background Art
[0002] Compared with dynamic random access memory, phase change memory (PCM) has a higher capacity. Compared with flash memory, it has a lower latency and byte-level addressing ability, making it one of the most promising technologies in the field of non-volatile memory.
[0003] In a phase change memory, a phase change storage material can be crystallized or amorphized based on the heat generated by an electric current to achieve the writing of "1" or "0". Among them, during the RESET operation on a selected phase change storage cell, that is, the process of writing "0", compared with the SET operation on the selected phase change storage cell, that is, the process of writing "1", a higher temperature needs to be provided for the phase change storage material to make it amorphous, that is, a higher electric current needs to be applied to the phase change storage material.
[0004] However, with the increase in the storage density of phase change memory, the distance between phase change storage cells becomes smaller and smaller. When performing a RESET operation on a selected phase change storage cell, if an adjacent phase change storage cell is in the RESET state, the phase change storage material in it will be partially crystallized under the continuous heat effect, resulting in misreading when reading the adjacent phase change storage cell.
[0005] Therefore, how to improve the thermal crosstalk between phase change storage cells in a phase change memory has become a problem to be solved. Summary of the Invention
[0006] Based on the above problems, the present application provides a phase change memory, which can improve the thermal crosstalk between phase change storage cells in the phase change memory.
[0007] The embodiments of the present application disclose the following technical solutions:
[0008] In a first aspect, an embodiment of the present application provides a phase change storage cell, including a phase change storage material and a spacer layer;
[0009] The spacer layer covers the sidewall of the phase change storage material;
[0010] The spacer layer includes a first spacer layer and a second spacer layer; the phase change storage material, the first spacer layer, and the second spacer layer are arranged in sequence from the inside to the outside. The first spacer layer includes an oxide interlayer and a nitride layer, and the second spacer layer is an oxide layer;
[0011] The thickness of the oxide interlayer in the first spacer layer is less than the thickness of the second spacer layer.
[0012] Optionally, the spacer layer further includes a third spacer layer and a fourth spacer layer;
[0013] The first spacer layer, the second spacer layer, the third spacer layer, and the fourth spacer layer are arranged in sequence from inside to outside;
[0014] The third spacer layer is a nitride layer, and the fourth spacer layer is an oxide layer.
[0015] Optionally, the spacer layer further includes a fifth spacer layer and a sixth spacer layer;
[0016] The first spacer layer, the second spacer layer, the fifth spacer layer, and the sixth spacer layer are arranged in sequence from inside to outside;
[0017] The fifth spacer layer includes an oxide interlayer and a nitride layer, and the sixth spacer layer is an oxide layer.
[0018] Optionally, the spacer layer further includes a seventh spacer layer and an eighth spacer layer;
[0019] The seventh spacer layer, the eighth spacer layer, the first spacer layer, and the second spacer layer are arranged in sequence from inside to outside;
[0020] The seventh spacer layer is a nitride layer, and the eighth spacer layer is an oxide layer.
[0021] Optionally, the oxide interlayer is formed by low-temperature atomic layer deposition technology.
[0022] Optionally, the preparation temperature of the oxide interlayer is 50 °C.
[0023] Optionally, the thickness of the oxide interlayer is
[0024] Optionally, in the first spacer layer, the nitride layers on both sides of the oxide interlayer have equal thicknesses.
[0025] Optionally, the nitride layer is obtained by performing an even number of deposition cycles.
[0026] Optionally, the number of deposition cycles of the nitride layer is at least 4 times.
[0027] Compared with the prior art, the present application has the following beneficial effects:
[0028] An embodiment of the present application provides a phase change memory, which includes phase change memory cells arranged in an array. Among them, the phase change memory cell includes a phase change memory material and a spacer layer; the spacer layer covers the side wall of the phase change memory material; the spacer layer includes a first spacer layer and a second spacer layer; the phase change memory material, the first spacer layer, and the second spacer layer are arranged in sequence from the inside to the outside. The first spacer layer includes an oxide interlayer and a nitride layer, and the second spacer layer is an oxide layer; the thickness of the oxide interlayer in the first spacer layer is less than the thickness of the second spacer layer. Thus, by adding an oxide interlayer to the first spacer layer and jointly forming a sandwich-like N-O-N structure with the nitride layer, using the nitride layer as the contact layer in contact with the phase change memory material and increasing the oxide interlayer as a thermal barrier layer, the thermal boundary resistance can be effectively increased, and the efficiency of the heat generated by the phase change memory material along the signal line of the phase change memory can be weakened, thereby improving the thermal crosstalk between the phase change memory cells in the phase change memory. Description of the Drawings
[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.
[0030] Figure 1 It is a structural diagram of a phase change memory cell provided by an embodiment of the present application;
[0031] Figure 2 It is another structural diagram of a phase change memory cell provided by an embodiment of the present application;
[0032] Figure 3 It is another structural diagram of a phase change memory cell provided by an embodiment of the present application;
[0033] Figure 4 It is another structural diagram of a phase change memory cell provided by an embodiment of the present application;
[0034] Figure 5 It is a simulated thermal distribution curve diagram of a phase change memory cell provided by an embodiment of the present application;
[0035] Figure 6 It is a comparison diagram of thermal crosstalk data provided by an embodiment of the present application. Detailed Embodiments
[0036] A phase change memory provided by the present application can be used in the semiconductor field. The above is only an example and does not limit the application field of the phase change memory provided by the present application.
[0037] The terms "first", "second", "third", "fourth", etc. in the description, claims and drawings of this application are used to distinguish different objects, rather than to limit a specific order.
[0038] In the embodiments of this application, words such as "as an example" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "as an example" or "for example" in the embodiments of this application should not be construed as more preferred or more advantageous than other embodiments or designs. Rather, the use of words such as "as an example" or "for example" is intended to present relevant concepts in a specific manner.
[0039] The terms used in the embodiments section of this application are only used to explain the specific embodiments of this application, rather than to limit this application.
[0040] As described above, during the RESET operation on the selected phase change memory cell, that is, when writing "0", a high and short current pulse needs to be provided to the phase change storage material. The joule heat generated by the action of the current on the phase change storage material raises the temperature of the phase change storage material above the melting temperature and then rapidly cools to form a high-resistance amorphous state. During the SET operation on the selected phase change memory cell, that is, when writing "1", a current pulse with medium amplitude and long duration needs to be provided to the phase change storage material. The joule heat generated by the action of the current on the phase change storage material raises the temperature of the phase change storage material above the crystallization temperature and below the melting temperature, and maintains for a period of time to form a low-resistance polycrystalline state.
[0041] When performing the RESET operation on the selected phase change memory cell, if the adjacent phase change memory cell is in the RESET state, partial crystallization of the phase change storage material therein will occur under the continuous heat action, resulting in misreading when reading the adjacent phase change memory cell.
[0042] In view of this, the embodiments of this application provide a phase change memory, including phase change memory cells arranged in an array. Among them, the phase change memory cell includes a phase change storage material and a spacer layer; the spacer layer covers the sidewall of the phase change storage material; the spacer layer includes a first spacer layer and a second spacer layer; the phase change storage material, the first spacer layer and the second spacer layer are arranged in sequence from the inside to the outside. The first spacer layer includes an oxide interlayer and a nitride layer, and the second spacer layer is an oxide layer; the thickness of the oxide interlayer in the first spacer layer is less than the thickness of the second spacer layer.
[0043] Accordingly, an oxide interlayer is added to the first spacer layer to jointly form a sandwich-like N-O-N structure with the nitride layer. Taking the nitride layer as the contact layer in contact with the phase change memory material and adding the oxide interlayer as a thermal barrier layer can effectively increase the thermal boundary resistance and weaken the efficiency of heat generated by the phase change memory material from transferring along the signal line of the phase change memory, thereby improving the thermal crosstalk between the phase change memory cells in the phase change memory.
[0044] To enable those skilled in the art to better understand the solution of this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are only a part of the embodiments of this application, rather than all the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of this application.
[0045] The embodiment of this application provides a phase change memory, which includes phase change memory cells arranged in an array.
[0046] See Figure 1 , which is a structural diagram of a phase change memory cell provided by the embodiment of this application. Among them, the cross-sectional view is the cross-sectional view corresponding to AA marked in the top view.
[0047] The phase change memory cell includes a phase change memory material 110 and a spacer layer 120. The phase change memory material 110 can be selected from materials such as germanium-antimony-tellurium alloy that can quickly and reversibly convert between the amorphous state and the crystalline state. For example, Ge 2 Sb 2 Te 5 material is selected as the phase change memory material.
[0048] The spacer layer 120 covers the sidewalls of the phase change memory material 110.
[0049] The spacer layer 120 includes a first spacer layer 121 and a second spacer layer 122; the phase change memory material 110, the first spacer layer 121, and the second spacer layer 122 are arranged in sequence from the inside to the outside. The first spacer layer 121 includes an oxide interlayer 01 and a nitride layer 02, and the second spacer layer 122 is an oxide layer.
[0050] The thickness of the oxide interlayer 01 in the first spacer layer 121 is less than the thickness of the second spacer layer 122.
[0051] Among them, multiple phase change memory cells can be arranged at equal intervals on the signal line of the phase change memory, and the signal line of the phase change memory can be a word line.
[0052] As an example, the nitride layer 02 in the first spacer layer 121 is obtained by performing a plurality of deposition cycles. For example, it is obtained by performing 4 deposition cycles. Among them, chemical vapor deposition or physical vapor deposition can be performed in the deposition cycle.
[0053] Thus, adding one layer of nitride in each deposition cycle can enable the nitride to form a more complete coverage in a structure with a high aspect ratio, obtain a better step coverage, ensure that a thin film with a uniform thickness can be formed on the surface of the three-dimensional phase change memory material 110, reduce the defect density inside the nitride layer 02 and between it and the phase change memory material 110, improve the interface quality, and further improve the long-term reliability of the phase change memory.
[0054] In addition, by adjusting the number of deposition cycles and the parameters of each deposition cycle, the total thickness of the nitride layer 02 can be precisely controlled, its thermal conductivity can be effectively adjusted, and thermal crosstalk can be reduced.
[0055] The oxide interlayer 01 in the first spacer layer 121 can be formed by low-temperature atomic layer deposition (ALD, Atomic Layer Deposition) technology. For example, low-temperature atomic layer deposition can be performed at a temperature of 50 °C, so as to reduce the thermal impact on the phase change memory material during the formation of the oxide interlayer 01, and form an oxide interlayer 01 that is much thinner than the second spacer layer 122.
[0056] In a phase change memory, to ensure the performance of the memory, enhance the electrical isolation effect between adjacent phase change memory cells, and facilitate the implementation of a three-dimensional stacked structure, while increasing the storage density without affecting the function of the underlying phase change memory cells, a certain distance usually needs to be left between each phase change memory cell. To ensure the density of the phase change memory material that actually plays a storage role in the phase change memory, and thus ensure the capacity of the phase change memory, the thickness of the spacer layer needs to be as thin as possible while meeting the heat insulation requirements.
[0057] Low-temperature atomic layer deposition technology is a deposition technology based on surface self-limiting reactions. By alternately introducing a variety of precursor substances and depositing only one layer of atoms each time, the thickness of the formed film layer can be precisely controlled, the impurity content is low, and the formed film layer has extremely high uniformity and conformality. An extremely thin but efficient thermal insulation layer, that is, the oxide interlayer 01, can be introduced without significantly increasing the thickness of the first spacer layer 121, so that both the device miniaturization can be maintained and the thermal boundary resistance (TBR) can be increased.
[0058] Optionally, the thickness of the oxide interlayer 01 can be Thus, without significantly increasing the thickness of the spacer layer 120, an oxide interlayer 01 can be added as a thermal barrier layer to effectively increase the thermal boundary resistance in the extending direction of the phase change memory signal line, weaken the efficiency of heat generated by the phase change memory material from being transmitted along the signal line, and thus improve the thermal crosstalk between the phase change memory cells in the phase change memory.
[0059] In one embodiment, in the first spacer layer 121, the nitride layers 02 on both sides of the oxide interlayer 01 have equal thickness.
[0060] For example, the nitride layer 02 is obtained by performing an even number of deposition cycles. If it is obtained by performing 2X deposition cycles, X deposition cycles can be performed first to obtain a partial nitride layer; then atomic layer deposition at a low temperature is performed to obtain the oxide interlayer 01; finally, X deposition cycles are performed again to obtain another partial nitride layer, forming the first spacer layer 121. Exemplarily, in order to enable the nitride to form a more complete coverage in a structure with a high aspect ratio and obtain a better step coverage, X can be at least 2, that is, the number of deposition cycles of the nitride layer 02 is at least 4 times. Among them, 2 deposition cycles of the nitride layer 02 are performed before depositing the oxide interlayer 01, and 2 deposition cycles of the nitride layer 02 are performed after depositing the oxide interlayer 01.
[0061] Thus, by making the parameters in each deposition process consistent, the nitride layers 02 on both sides of the oxide interlayer 01 in the first spacer layer 121 can have equal thickness. During the preparation process, it is not necessary to adjust the deposition parameters of the nitride, reducing the process complexity, and making the first spacer layer 121 more symmetric in terms of thermal conduction characteristics and providing a uniform thermal isolation effect.
[0062] In addition, making the nitride layers 02 on both sides of the oxide interlayer 01 in the first spacer layer 121 have equal thickness can also maintain the overall stability of the structure and reduce the stress concentration phenomenon caused by the difference in thermal expansion coefficients between different materials.
[0063] Similar to the formation method of the nitride layer 02 in the first spacer layer 121, the second spacer layer 122 can also be formed by performing multiple deposition cycles to obtain a better step coverage and uniformly cover the surface of the first spacer layer 121.
[0064] The second spacer layer 122 can be an oxide layer. The oxide has a high resistivity. Using an oxide layer on the outer layer of the phase change memory cell can effectively prevent current leakage, ensure that the charge only flows through the expected path, and thus improve the reliability of the device. On the other hand, the oxide has a low thermal conductivity and can more effectively serve as a thermal barrier to reduce the diffusion of heat to the surrounding environment or adjacent phase change memory cells, facilitating the control of the temperature distribution inside the phase change memory.
[0065] Exemplarily, the temperature of the deposition cycle can be 250 °C. Growing the nitride layer 02 in the first spacer layer 121 and the second spacer layer 122 at a relatively low temperature such as 250 °C can prevent unnecessary phase transitions or other thermal effects from occurring in the phase change storage material 110, while protecting the existing structure and supporting the effective deposition of the spacer layer 120.
[0066] Optionally, in the embodiments of the present application, the nitride is silicon nitride and the oxide is silicon oxide.
[0067] In addition, it should be noted that in the phase change storage unit provided by the embodiments of the present application, the top view of the phase change storage material can be rectangular, or can be other shapes such as square, circular or oval, and the embodiments of the present application do not limit this. Figure 1 The phase change storage material with a rectangular shape in the top view is only one of the examples.
[0068] Therefore, an oxide interlayer 01 is added to the first spacer layer 121 to jointly form a sandwich-like N-O-N structure with the nitride layer 02. Using the nitride layer as the contact layer in contact with the phase change storage material and the oxide interlayer as the thermal barrier layer to construct a multi-level thermal resistance system can effectively increase the thermal boundary resistance and weaken the efficiency of the heat generated by the phase change storage material from being transmitted along the signal line of the phase change memory, thereby improving the thermal crosstalk between the phase change storage units in the phase change memory. In addition, adding the oxide interlayer 01 to the first spacer layer 121 can also better disperse stress, which is beneficial to improving the long-term stability of the phase change storage unit.
[0069] See Figure 2 , which is another structural diagram of the phase change storage unit provided by the embodiments of the present application. Among them, the cross-sectional view is the cross-sectional view corresponding to BB marked in the top view.
[0070] This phase change storage unit includes a phase change storage material 110 and a spacer layer 120. The spacer layer 120 covers the side walls of the phase change storage material 110.
[0071] The spacer layer 120 includes a first spacer layer 121, a second spacer layer 122, a third spacer layer 123 and a fourth spacer layer 124; the phase change storage material 110, the first spacer layer 121, the second spacer layer 122, the third spacer layer 123 and the fourth spacer layer 124 are arranged in sequence from the inside to the outside.
[0072] Among them, the first spacer layer 121 includes an oxide interlayer 01 and a nitride layer 02; the second spacer layer 122 is an oxide layer; the third spacer layer 123 is a nitride layer; the fourth spacer layer 124 is an oxide layer.
[0073] As an example, the thickness of the nitride layer 02 in the first spacer layer 121 and the third spacer layer 123 can be different. For example, the nitride layer 02 in the first spacer layer 121 can be thinner than the third spacer layer 123. For instance, the nitride layer 02 in the first spacer layer 121 can be formed through 4 deposition cycles, and the third spacer layer 123 can be formed through 12 deposition cycles. Thus, the third spacer layer 123 can provide stronger mechanical protection for the phase change memory cell, improving the structural stability of the phase change memory cell throughout its entire life cycle.
[0074] In addition, in the embodiments of the present application, two oxide layers, namely the second spacer layer 122 and the fourth spacer layer 124, are provided, which can achieve a stronger thermal isolation effect and better electrical insulation. The thicknesses of the second spacer layer 122 and the fourth spacer layer 124 can be the same.
[0075] See Figure 3 , which is another structural diagram of the phase change memory cell provided by the embodiments of the present application. Among them, the cross-sectional view is the cross-sectional view corresponding to CC marked in the top view.
[0076] This phase change memory cell includes a phase change memory material 110 and a spacer layer 120. The spacer layer 120 covers the sidewalls of the phase change memory material 110.
[0077] The spacer layer 120 includes a first spacer layer 121, a second spacer layer 122, a fifth spacer layer 125, and a sixth spacer layer 126; the phase change memory material 110, the first spacer layer 121, the second spacer layer 122, the fifth spacer layer 125, and the sixth spacer layer 126 are arranged in sequence from the inside to the outside.
[0078] Among them, the first spacer layer 121 includes an oxide interlayer 01 and a nitride layer 02; the second spacer layer 122 is an oxide layer; the fifth spacer layer 125 includes an oxide interlayer 03 and a nitride layer 04; the sixth spacer layer 126 is an oxide layer.
[0079] As an example, the thickness of the nitride layer 02 in the first spacer layer 121 and the nitride layer 04 in the fifth spacer layer 125 can be different. For example, the nitride layer 02 in the first spacer layer 121 can be thinner than the nitride layer 04 in the fifth spacer layer 125. For instance, the nitride layer 02 in the first spacer layer 121 can be formed through 4 deposition cycles, and the nitride layer 04 in the fifth spacer layer 125 can be formed through 12 deposition cycles. Thus, the nitride layer 04 in the fifth spacer layer 125 can provide stronger mechanical protection for the phase change memory cell, improving the structural stability of the phase change memory cell throughout its entire life cycle.
[0080] The oxide interlayer 01 in the first spacer layer 121 and the oxide interlayer 03 in the fifth spacer layer 125 are both formed by low-temperature atomic layer deposition technology. For example, low-temperature atomic layer deposition can be carried out at a temperature of 50 °C, so as to reduce the thermal impact on the phase change memory material during the formation of the oxide interlayer 01.
[0081] Exemplarily, the oxide interlayer 01 in the first spacer layer 121 and the oxide interlayer 03 in the fifth spacer layer 125 have the same thickness. For example, both are Thus, without significantly increasing the thickness of the spacer layer 120, the oxide interlayer 01 and the oxide layer interlayer 03 can be added as thermal barrier layers, more effectively increasing the thermal boundary resistance in the extending direction of the phase change memory signal line, weakening the efficiency of heat generated by the phase change memory material from being transmitted along the signal line, and improving the thermal crosstalk between the phase change memory cells in the phase change memory.
[0082] Optionally, in the fifth spacer layer 125, the nitride layers 04 on both sides of the oxide interlayer 03 have equal thickness.
[0083] In addition, in the embodiments of the present application, two oxide layers, namely the second spacer layer 122 and the fourth spacer layer 124, are provided, which can achieve a stronger thermal isolation effect and better electrical insulation. The second spacer layer 122 and the fourth spacer layer 124 may have the same thickness.
[0084] See Figure 4 , which is another structural diagram of a phase change memory cell provided by the embodiments of the present application. Among them, the cross-sectional view is the cross-sectional view corresponding to DD marked in the top view.
[0085] The phase change memory cell includes a phase change memory material 110 and a spacer layer 120. The spacer layer 120 covers the sidewall of the phase change memory material 110.
[0086] The spacer layer 120 includes a first spacer layer 121, a second spacer layer 122, a sixth spacer layer 126, and a seventh spacer layer 127; the phase change memory material 110, the seventh spacer layer 127, the eighth spacer layer 128, the first spacer layer 121, and the second spacer layer 122 are arranged in sequence from the inside to the outside.
[0087] Among them, the seventh spacer layer 127 is a nitride layer; the eighth spacer layer 128 is an oxide layer; the first spacer layer 121 includes an oxide interlayer 01 and a nitride layer 02; the second spacer layer 122 is an oxide layer.
[0088] As an example, the thickness of the nitride layer 02 in the first spacer layer 121 and the eighth spacer layer 128 can be different. For example, the nitride layer 02 in the first spacer layer 121 can be thicker than the eighth spacer layer 128. For instance, the nitride layer 02 in the first spacer layer 121 can be formed through 12 deposition cycles, and the eighth spacer layer 128 can be formed through 4 deposition cycles. In this case, after forming a partial nitride layer through 6 deposition cycles, an oxide interlayer 01 can be formed by low-temperature atomic layer deposition technology, and then another partial nitride layer can be formed through 6 deposition cycles to obtain the first spacer layer 121.
[0089] Thus, the nitride layer 02 in the first spacer layer 121 can provide stronger mechanical protection for the phase change memory cell, improving the structural stability of the phase change memory cell throughout its life cycle; through the thinner eighth spacer layer 128, heat can be transferred to the phase change memory material 110 faster, improving the speed and efficiency of the phase change memory material in switching between the crystalline state and the amorphous state, reducing the contact resistance between the spacer layer 120 and the phase change memory material 110, and enhancing the read / write speed and reliability of the phase change memory.
[0090] In the embodiments of the present application, two oxide layers, namely the eighth spacer layer 128 and the second spacer layer 122, are provided, which can achieve a stronger thermal isolation effect and better electrical insulation. The thicknesses of the second spacer layer 122 and the eighth spacer layer 128 can be the same.
[0091] See Figure 5 , which is a simulated thermal distribution curve of a phase change memory cell provided by the embodiments of the present application. Here, the horizontal axis represents time, and the vertical axis represents temperature.
[0092] Among them, Add Liner X is the simulated thermal distribution curve of the phase change memory cell in any embodiment of the present application where the spacer layer includes an oxide interlayer, and No Liner X is the simulated thermal distribution curve of the phase change memory cell where the spacer layer does not include an oxide interlayer. The phase change memory cell corresponding to No Liner X and the phase change memory cell corresponding to Add Liner X are completely the same in structure and size except for whether they include an oxide interlayer.
[0093] It can be seen that, compared with No Liner X, the thermal distribution curve of Add Liner X is more convergent, indicating that the heat conduction along the signal line direction of the phase change memory cell corresponding to Add Liner X is suppressed, and the oxide interlayer in the spacer layer significantly helps to improve the thermal crosstalk between the phase change memory cells in the phase change memory.
[0094] See Figure 6, this figure is a thermal crosstalk data comparison diagram provided by an embodiment of the present application. Among them, the horizontal axis represents the number of usage cycles (cycle) experienced by the phase change memory cells, and the vertical axis represents the average uncorrected raw bit error rate (Average RBER (PPM)); a and b are phase change memories using the phase change memory cells with an oxide interlayer in the spacer layer according to any embodiment of the present application, and c and d are phase change memories using the phase change memory cells without an oxide interlayer in the spacer layer. a, b, c, and d are completely the same in structure and size except for whether they contain an oxide interlayer; FF, MM, and NN respectively represent different positions of the phase change memory cells in the phase change memory.
[0095] It can be seen that as the cycle increases, the RBER of the phase change memories a, b, c, and d all increases, which indicates that thermal crosstalk has a significant impact on the performance of the phase change memory cells; however, the RBER increase rate of a and b is significantly slower than that of c and d. For example, for the phase change memory cells in the NN region, compared with c and d, the number of cycles experienced by a and b when the RBER reaches 200, that is, the average uncorrected raw bit error rate reaches two hundred parts per million, is about 30 more cycles. Thus, it can be seen that adding an oxide interlayer to the spacer layer significantly improves the thermal crosstalk between the phase change memory cells.
[0096] It should be noted that the various embodiments in this specification are described in a progressive manner. The same or similar parts between the various embodiments can be referred to each other, and the key points of each embodiment are the differences from other embodiments. In particular, for the phase change memory embodiment, since it is basically similar to the phase change memory cell embodiment, the description is relatively simple, and the relevant parts can be referred to the description of the method embodiment. The parts or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. A person of ordinary skill in the art can understand and implement it without creative work.
[0097] The above is only a specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present application should be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.
Claims
1. A phase change memory, characterized in that: A phase change memory unit comprising an array arrangement, wherein the phase change memory unit comprises a phase change memory material and a spacer layer; The spacer layer covers the sidewall of the phase change memory material; The spacer layer includes a first spacer layer and a second spacer layer; the phase change memory material, the first spacer layer and the second spacer layer are arranged in sequence from inside to outside, the first spacer layer includes an oxide interlayer and a nitride layer, and the second spacer layer is an oxide layer; The thickness of the oxide interlayer in the first spacer layer is smaller than the thickness of the second spacer layer.
2. The phase change memory according to claim 1, characterized in that: The spacer layer further includes a third spacer layer and a fourth spacer layer; The first spacer layer, the second spacer layer, the third spacer layer and the fourth spacer layer are arranged in sequence from inside to outside; The third spacer layer is a nitride layer, and the fourth spacer layer is an oxide layer.
3. The phase change memory according to claim 1, characterized in that: The spacer layer further includes a fifth spacer layer and a sixth spacer layer; The first spacer layer, the second spacer layer, the fifth spacer layer and the sixth spacer layer are arranged in sequence from inside to outside; The fifth spacer layer includes an oxide interlayer and a nitride layer, and the sixth spacer layer is an oxide layer.
4. The phase change memory according to claim 1, characterized in that: The spacer layer further includes a seventh spacer layer and an eighth spacer layer; The seventh spacer layer, the eighth spacer layer, the first spacer layer and the second spacer layer are arranged in sequence from inside to outside; The seventh spacer layer is a nitride layer, and the eighth spacer layer is an oxide layer.
5. The phase change memory according to any one of claims 1 to 4, characterized in that: The oxide interlayer is formed by low temperature atomic layer deposition technology.
6. The phase change memory according to claim 5, characterized in that: The preparation temperature of the oxide interlayer is 50°C.
7. The phase change memory according to any one of claims 1 to 4, characterized in that: The thickness of the oxide interlayer is 8. The phase change memory according to any one of claims 1 to 4, characterized in that: In the first spacer layer, the thickness of the nitride layer on both sides of the oxide interlayer is equal.
9. The phase change memory according to claim 8, characterized in that: The nitride layer is obtained by performing an even number of deposition cycles.
10. The phase change memory according to any one of claims 9, characterized in that: The deposition cycle number of the nitride layer is at least 4 times.