COULOMB BLOCK DETECTION STRUCTURE SUPERIMPOSED ON A QUANTUM BOX

Abstract

A quantum device formed from a substrate (5), the substrate being coated with: - at least one semiconductor region (12a, 120a) forming a quantum dot (QD), - a Coulomb block detection structure for detecting a charge state of the quantum dot, said Coulomb block detection structure comprising a detection island (ID) disposed above and opposite the quantum dot (QD) and capable of being coupled to the quantum dot by electrostatic coupling, said detection structure further comprising at least one first tunnel junction (TJ1) between said detection island (ID) and a first gate block (22), the first gate block (22) being juxtaposed to said detection island (ID). Figure for the abbreviation: Figure 1.

Description

Title of the invention: DEVICE WITH A COULOMB BLOCK DETECTION STRUCTURE SUPERIMPOSED ON A QUANTUM BOX

[0001] TECHNICAL FIELD AND PRIOR TECHNOLOGY

[0002] The present application relates to the field of quantum devices in which at least one bit of quantum information based on a given quantum state among at least two measurable levels is used as an information vector. This quantum state is called a qubit or quantum bit.

[0003] A particular type of qubit is the spin qubit when the intrinsic degree of freedom of the spin of individual electrons is used to encode quantum information.

[0004] Qubits can be formed in a semiconductor material within confinement structures of nanometric size and defined electrostatically. These confinement structures are typically called "quantum dots".

[0005] A quantum dot behaves like a potential well confining one or more elementary charges (electrons or holes) in a region of semiconductor.

[0006] To measure the state of a qubit, it is known to perform a spin-to-charge conversion that converts the spin state of charged particles into a charge state of the quantum dots containing said particles. It is then necessary to measure this charge state in order to deduce the spin state of the charged particles before conversion. For this purpose, a means of measuring the charge state is generally placed opposite each quantum dot.

[0007] Reading a qubit can in particular be achieved using another quantum dot called a "reading island" or "detection island" coupled to that of the qubit to be read. These two elements form two potential wells separated by a potential barrier.

[0008] Devices in which the detection islands and quantum dots are arranged opposite each other and in the same plane parallel to the principal plane of a substrate on which the detection islands and quantum dots are formed are known.

[0009] They pose space problems. Furthermore, due to manufacturing constraints of such devices, the possibilities of bringing the detection structure and quantum dot closer together are limited, which can impair detection sensitivity.

[0010] Document FR 3066297, issued by the applicant, describes a quantum device in which, according to one embodiment, the detection structure can be located in a separate plane from that of the quantum dots. Electrostatic control grids are planned between a level in which the quantum dots are formed and a level in which charge detectors are planned. Such a device poses a problem in terms of the complexity of implementing its fabrication process.

[0011] The problem arises of realizing an improved quantum device with respect to at least one of the disadvantages mentioned above. Description of the invention

[0012] According to one aspect, the present invention relates to a quantum device formed from a coated substrate:

[0013] - of at least one semiconductor region in which a quantum dot is suitable to be trained,

[0014] - at least a first grid block for modulating the potential of the quantum dot and forming a reservoir of charges,

[0015] - a detection structure for detecting a charge state of said quantum dot, said detection structure comprising a detection island disposed above and opposite the quantum dot and capable of being coupled to the quantum dot by electrostatic coupling, said detection structure further comprising at least a first tunnel junction between said detection island and the first grid block, the first grid block being juxtaposed to said detection island.

[0016] The semiconductor region is typically located at a first level of the device, in other words in a first plane parallel to a principal plane of the substrate, while the first gate block and the detection structure are arranged in a second level, in other words in a second plane parallel to a principal plane of the substrate.

[0017] Such an arrangement of superimposed quantum dots and detection islands allows for a reduced footprint in the plane and enables a close arrangement of the detection island relative to the quantum dot. This allows for good capacitive coupling between the detection island and the quantum dot, thereby improving detection sensitivity. This arrangement of the aforementioned elements also facilitates integration into a matrix with one or more rows of quantum dots and associated detection structures.

[0018] According to a first embodiment of the quantum device and the detection structure, a second grid block distinct from the first grid block and located in the same first plane as the first grid block and the detection island, the first plane being parallel to a principal plane of the substrate, the second grid block being arranged so that the detection island is disposed between the first grid block and the second grid block, the charge detection structure being provided with a second tunnel junction formed between the detection island and the second grid block.

[0019] With such an arrangement, it is possible to detect the charge state of the quantum dot by appropriately biasing the first and second gate blocks so as to cause a current to flow through the tunnel junctions. The current level then provides information on the charge state of the quantum dot.

[0020] To make contact on the first grid block, a first contact pad can be provided on this first grid block.

[0021] Similarly, to make contact on the second grid block, a second contact pad can also be provided on this second grid block.

[0022] According to one possible implementation, the detection pilot can be based on the same conductive or doped semiconductor material as the gate block(s).

[0023] Advantageously, the first contact pad and the second contact pad are provided, respectively, for:

[0024] - during an operating phase known as "detection" apply respectively a first potential at the first gate block and a second potential at the second gate block, different from the first potential, so as to allow the passage of a current through said first and second junctions, and

[0025] - during at least one other operating phase distinct from said phase of detection operation: apply the same given potential to the first grid block and the second grid block.

[0026] Applying the same given potential prevents the flow of current, which can be troublesome during qubit operation, and helps to overcome local heating problems of the device and charge noise generated near the quantum dot that could disturb the state of the qubit during operations.

[0027] Advantageously, the device can further be provided with a current measurement stage through said first junction and second junction coupled to the first contact pad and the second contact pad.

[0028] According to a second embodiment of the quantum device, the device may further comprise a first contact pad on the first gate block, the first contact pad being coupled to a circuit of a reflectometry measurement device, said circuit being in particular configured to:

[0029] - emit an RF signal on the first contact pad towards said island of detection;

[0030] - detect a variation in the phase and / or amplitude of an RF signal reflected by said islet following said emission.

[0031] Advantageously, whether for the first or second embodiment, the device can be equipped with a conductive pad for electrostatic control of said detection island, said conductive pad being disposed above and in view of said detection island and separated from said detection island by means of at least one dielectric region so as to permit electrostatic coupling between said conductive pad and said detection island.

[0032] According to a particular embodiment of the device, the conductive pad can be arranged in contact with a region of conductive or semiconducting material separated from the detection island by means of the dielectric region, said detection island being based on the same material as said region of conductive or semiconducting material.

[0033] Advantageously, the conductive pad is arranged in contact with a region of doped conductive or semiconducting material separated from the detection island by means of a dielectric region, said region of doped conductive or semiconducting material, said dielectric region, said detection island having the same footprint and forming the same pattern.

[0034] According to another aspect, the present invention relates to a method for manufacturing a quantum device as defined above.

[0035] According to another aspect, the present invention relates to a method for manufacturing a quantum device comprising the following steps:

[0036] - provide a substrate coated with at least one semiconductor layer, at least one region of said semiconductor layer being capable of forming a quantum dot,

[0037] - form a bar based on at least one conductive or semiconductor material in which at least one detection island opposite said quantum dot is provided,

[0038] - form at least one tunnel dielectric region on at least one lateral flank said bar association,

[0039] - to form one or more grid blocks juxtaposed to said bar and extending principally palement in a direction orthogonal to a principal direction in which said bar extends, at least one first grid block among said grid blocks being disposed against the tunnel dielectric region arranged on said detection island, so as to form a tunnel junction between the first grid block and the detection island.

[0040] Advantageously, said one or more grid blocks may be formed by:

[0041] - deposition of at least one grid material, then:

[0042] - engraving of said grid material, said engraving being carried out concurrently with an engraving of the bar to form the detection island.

[0043] According to a particular embodiment, said bar may be based on said grid material.

[0044] Advantageously, the tunnel dielectric region can be formed by depositing a tunnel dielectric layer on the bar and then etching the tunnel dielectric layer, the etching of the tunnel dielectric layer and the etching of said bar to form the detection island and the etching of said grid material being carried out in using the same masking.

[0045] Alternatively, the tunnel dielectric region can be formed by oxidation of said bar.

[0046] According to one possible embodiment, the bar is called the “upper bar” and is formed by depositing a conductive material and then etching the conductive material using a masking, said etching of the conductive material being extended into the semiconducting layer and so as to form another bar called the “lower” bar and advantageously reproducing the shape of the upper bar.

[0047] Advantageously, following said engraving to form the lower bar, lateral flanks of the lower bar are exposed. The process may then further comprise: after formation of said lower bar and prior to the formation of said tunnel dielectric region, the steps of:

[0048] - deposition of one or more insulating layers,

[0049] - engraving said one or more insulating layers so as to form blocks of insulating protection on both sides of the lateral faces of the semiconductor region,

[0050] - formation of a tunnel dielectric region by deposition of a layer of di electrical tunnel on the upper bar while the lateral sides of the lower bar are protected. Brief description of the drawings

[0051] The present invention will be better understood upon reading the description of exemplary embodiments given by way of illustration only and in no way limiting, with reference to the accompanying drawings in which:

[0052] [Fig.l] schematically represents an example of a quantum device according to a first embodiment in which each quantum dot is associated with a coulomb blocking detection structure arranged above and opposite this quantum dot.

[0053] [Fig.2] schematically represents a variant embodiment of the quantum device for which each quantum dot is formed in a semiconductor block of width on the order of that of a detection island of said detection structure placed opposite the dot.

[0054] [Fig.3] schematically represents a variant implementation of the device quantum for which the detection structure is associated with a reflectometry measurement device.

[0055] [Fig.4] illustrates an example of a possible starting substrate for implementing a quantum device according to the invention.

[0056] [Fig.5]

[0057] [Fig.6A]

[0058] [Fig.6B] illustrate an embodiment of a conducting or semiconducting bar in which one or more quantum dots are intended to be formed.

[0059] [Fig.7]

[0060] [Fig. 8]

[0061] [Fig.9A]

[0062] [Fig.9B] illustrate an implementation of a plurality of electrostatic control grids of a quantum island and definition by concomitant etching to realize this quantum island and these grids.

[0063] [Fig. 10]

[0064] [Fig. 11]

[0065] [Fig.12A]

[0066] [Fig. 12B], illustrate the optional realization of a silicification of the top of the gate blocks when these are semiconductors.

[0067] [Fig. 13]

[0068] [Fig.l4A]

[0069] [Fig.l4B]

[0070] [Fig. 15 A]

[0071] [Fig.15B]

[0072] [Fig.10A]

[0073] [Fig.16B]

[0074] [Fig. 17]

[0075] [Fig. 18]

[0076] [Fig.19A]

[0077] [Fig.l9B]

[0078] [Fig.20]

[0079] [Fig.21]

[0080] [Fig.22] illustrate another example of a method for manufacturing a device quantum as implemented according to the present invention.

[0081] [Fig.23] illustrates an alternative embodiment in which a lower end a pad for the control by electrostatic coupling of a detection island is arranged in contact with a conductive or semiconductive layer provided above the detection island and separated from the island by a dielectric region.

[0082] Identical, similar or equivalent parts of the different figures described below bear the same numerical references so as to facilitate the transition from one figure to another.

[0083] Furthermore, in the description below, terms that depend on the orientation of the structure, such as "above," "below," "back," "front," "upper," "lower," apply considering that the structure is oriented in the way illustrated in the figures.

[0084] The different parts represented in the figures are not necessarily shown on a uniform scale, in order to make the figures more legible.

[0085] The different possibilities (variants and embodiments) should be understood as not being mutually exclusive and can be combined with each other.

[0086] DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS

[0087] We refer first of all to [Fig.1] which gives an example of the realization of a quantum device according to a first embodiment.

[0088] In the particular embodiment given in this figure, a quantum dot BQ is formed in a region of a semiconductor layer 12. This semiconductor layer 12 can be the surface layer of a substrate or a layer transferred or deposited on a substrate and formed of a semiconductor material or of several stacked semiconductor materials.

[0089] According to one particular embodiment, the semiconductor layer 12 is the surface layer of a semiconductor-on-insulator substrate, in particular a silicon layer of an SOI substrate (SOI for "Silicon On Insulator"), for example 28Si. According to another embodiment, the semiconductor layer 12 may be formed of a heterostructure, for example SiGe / Si.

[0090] The BQ quantum dot ensures the confinement of at least one elementary charge (electrons or holes). Preferably, the BQ quantum dot here contains a single elementary charge. The spin of this charge, in particular an electron, can be used to encode quantum information. In this case, the qubit associated with the BQ quantum dot is a spin qubit.

[0091] To enable the detection of the quantum dot BQ, a charge-sensing structure is provided in close proximity to, and in this case above, the quantum dot BQ. The operation of this charge-sensing structure relies on capacitive coupling, also called "electrostatic coupling," between the quantum dot BQ and a detection island ID arranged above and opposite the quantum dot BQ. The detection island ID is made of a block, typically conductive or semiconductive, and separated from the quantum dot BQ by means of an insulating region 13a. This insulating region 13a can be an area of ​​an insulating layer covering the surface semiconductor layer 12. The composition of the insulating region 13a, for example silicon oxide, and the thickness of this insulating layer, for example between 2 nm and 20 nm, advantageously between 5 nm and 10 nm, are provided to enable coupling between the quantum dot BQ and a detection island ID.Such coupling depends on the capacitance between the detection island ID and the quantum dot BQ in terms of their respective surfaces facing each other, and the thickness of the layer. the insulating material separating them and the dielectric constant of the insulator separating them. Such an arrangement of a superimposed quantum dot (QD) and detection island (ID) minimizes the distance between the quantum dot and the detector, ensuring good detector sensitivity.

[0092] The device here comprises a first gate block 22 and a second gate block 24 located above the semiconductor layer 12 and on either side of the island ID. These gate blocks 22 and 24 serve as charge reservoirs and also to adjust the potential of the quantum dot BQ. They are designed to be good conductors – including at the cryogenic temperatures at which the device operates.

[0093] The first gate block 22 and the second gate block 24 are typically made of a doped semiconductor material such as, for example, polysilicon, or of a conductive material such as, for example, TiN. The first gate block 22 is located in the same plane P parallel to a principal plane of the substrate as the detection island ID, this plane P being arranged above the semiconductor layer 12 in which the quantum dot is arranged. By principal plane of the substrate, we mean a plane passing through the substrate and parallel to the plane [O; x; y ] of the orthogonal coordinate system [O; x; y; z ] given in [Fig. 1].

[0094] The first gate block 22 and the second gate block 24 are separated from the semiconductor region 12a in which the quantum dot BQ is realized by at least one insulating layer.

[0095] The charge detection structure is a Coulomb blocking type structure here based on the passage of a current through the island ID opposite the quantum dot BQ. Detection of this current provides information on the charge state of this BQ box.

[0096] The Coulomb block structure has a first tunnel junction JT1 between the detection island ID arranged above and opposite the quantum dot BQ and a portion of the first gate block 22 juxtaposed to the detection island ID. The first gate block 22 and the detection island ID are separated by a tunnel dielectric region DTI.

[0097] In this particular embodiment, the second gate block 24 is juxtaposed with the detection island ID and located in the same plane P as the detection island ID and the first gate block 22, such that the detection island ID is positioned between the first gate block 22 and the second gate block 24. A second tunnel junction JT2 is provided between the detection island ID and the second gate block 24. The second gate block 24 and the detection island ID are separated by a tunnel dielectric region DT2. The Coulomb block structure thus operates, in this particular embodiment, similarly to a single-electron transistor (SET). The gate blocks 22 and 24 can be considered here as a source region and a drain region, respectively. of the transistor. We thus control the passage of a current through this SET transistor as a function of respective potentials applied to the gate blocks 22, 24.

[0098] Conductive contact pads 72, 74 connected to the gate blocks 22, 24 are preferably provided to allow the application of respective biasing potentials. Depending on the biasing potentials applied to pads 72 and 74 respectively, a current (schematically represented by arrows) can be made to flow through the junctions JT1, JT2 and the detection island ID.

[0099] Apart from using the coulomb-blocking structure as a charge detector, in particular when initializing, checking, or holding the qubit stored in the quantum dot at rest without reading the charge state, the contact pads 72, 74, and consequently the gate blocks 22, 24, can be set to the same first potential VG1. The SET transistor is then in a blocked operating mode so that current flow through the JT1, JT2 junctions is prevented.

[0100] This potential VGi is adjustable and can be set when the quantum dot BQ is initialized, so as to allow a given charge state to be imposed on this quantum dot. The initialization of the quantum dot BQ can then be implemented via the gate blocks 22, 24. The gate blocks on either side of the detection island ID are maintained at the VGi potential. The tunnel junctions allow the passage of charge and the filling of the island ID until the potentials between the gate blocks 22, 24 and the quantum island are balanced to a resolution on the order of a few mV or less, which does not affect the adjustment of the quantum dot's potential.

[0101] The grid blocks themselves have an influence and contribute to this adjustment to possibly fall short of the resolution imposed by the coulomb block.

[0102] During a phase of use of the coulomb blocking structure as a charge detector, a potential difference AVSDSET is applied between the contact pads 72, 74. The contact pads 72, 74 are then brought to respective distinct potentials VG2 and VG3 such that VG3 - VG2 = AVSDSET with AVSDSET 0, so as to allow a passage of current (represented by two arrows on [Fig.1]) through the coulomb blocking structure.

[0103] According to a particular embodiment, the respective potentials VG2 and VG3 applied to the grid blocks 22, 24 can be such that VG2 = VGi and VG3 = VGi + AVSdset

[0104] The value of the current resulting from this particular biasing depends on, and therefore provides information about, the state of charge of the quantum dot BQ located opposite and below the detection island ID. Detection of this current can be achieved by means of a current detection circuit which is connected to the contact pads 72, 74.

[0105] An arbitrary voltage VG can be applied to the first contact pad 72 by example via a stage equipped with a digital-to-analog converter (DAC).

[0106] The current reading at the second contact pin 74 can be performed using a TIA (Trans-Impedance Amplifier) ​​circuit. To ensure that this pin 74 is also biased to a controllable voltage, an additional digital-to-analog converter (DAC) can, for example, be used to adjust the reference voltage of the TIA circuit to this value.

[0107] Optionally and advantageously, the detection island ID can itself be controlled and coupled by electrostatic coupling to an additional pad 71 to provide an additional electrostatic control means. This conductive pad 71 is arranged above and opposite said detection island ID without being in contact with it. The conductive pad 71 is separated from said detection island ID by means of at least one dielectric region RDI provided, in particular in terms of composition and thickness, so as to allow electrostatic coupling between said conductive pad 71 and said detection island ID. For example, the dielectric region RDI is formed of a dielectric material such as a silicon oxide with a thickness that may be, for example, between 5 and 15 nm.

[0108] Depending on a potential applied to the conductive pad 71, the chemical potential, in other words the Fermi level of the coulomb-blocking structure, can be adjusted. The conductive pad 71 thus provides an additional degree of adjustment for the sensing structure. The voltage applied to this conductive pad 71 serves to control the chemical potential of the sensing island. In other words, it allows the discrete energy levels of the sensing island ID to be adjusted with respect to the potential of the grid blocks 22, 24, and therefore allows it to be switched from a coulomb-blocking regime to an unblocking regime without having to modify the voltages applied to the grid blocks 22, 24. Furthermore, modulating this voltage offers a way to finely control the potential of the quantum dot.

[0109] A variant (not shown) without this conductive pad 71 can nevertheless be provided. The electrostatic control of the detection island ID can then be carried out via the grid blocks 22, 24, which however removes one degree of freedom in the control of the detection structure and makes the polarization of the different elements more complex.

[0110] A variant embodiment of a quantum device as described above is illustrated in [Fig. 2]. It differs from the embodiment described above, in particular, in the configuration of the semiconductor region in which the quantum dot BQ is located. In the specific embodiment shown in this figure, the quantum dot BQ is formed in a semiconductor region that does not extend over the entire surface of the substrate but only over a portion of it. This semiconductor region can, in particular, be a region of an etched or transferred semiconductor block.

[0111] The semiconductor block 120 can be designed with a width (dimension measured parallel to the y-axis of the orthogonal coordinate system [O; x; y; z] shown in [Fig. 2]) that is on the order of that of the detection island, preferably equal to or less than that W of the detection island ID. The width of the block 120 housing the quantum dot BQ can be, for example, between 20 nm and 100 nm, advantageously between 20 nm and 40 nm. With such an arrangement, and by positioning the quantum dot BQ exactly above the detection island ID, the detection sensitivity can be maximized.

[0112] Advantageously, for this variant of the structure, a dielectric region 202 is provided against the lateral sides of the semiconductor region 12a which is of different composition and / or dimensions than that of the DTI, DT2 areas of tunnel dielectric against the detection island ID and is preferably provided to prevent current passage between the gate blocks and the quantum dot via the lateral sides.

[0113] A variant of the embodiment described above is illustrated in [Fig. 3]. The coulomb-blocking structure differs from those described above, notably in that it has a single tunnel JT1 junction formed between the detection island ID and a first grid block 22 juxtaposed to the detection island ID. A single grid block 22 is then provided opposite a first lateral flank 301 of the detection island ID. Instead of a second grid block, an insulating region 305 is here arranged against a second lateral flank 302 of the island ID.

[0114] The detection of the charge state of the quantum dot BQ can be implemented here by reflectometry. A conductive pad 72 intended to apply a biasing potential to the first gate block 22 is coupled to a circuit 350 of a reflectometry device configured to emit an SE RF signal on the contact pad 72 and receive a reflected SR RF signal following the emission of the SE RF signal.

[0115] The SE RF signal is typically a high-frequency signal (for example, between 100 MHz and 1 GHz) sent to the detection island ID. The RF signal reflected by this island ID is then demodulated by the circuit 350. An inductor 352 is used to create an LC resonator composed of this inductor 352 and which depends on a quantum capacitance Cq formed by the quantum dot BQ and the detection island ID. When the value of Cq varies, the phase and amplitude of the reflected signal vary, which can be detected by measurement means. It is thus possible to know the relative charge state of the quantum dot BQ of the qubit intended to be read.

[0116] A circuit of a type such as described for example in the document by RJ Schoelkopf et al., Science, 280, 5367, pp. 1238-1242, 1998 may be used as an alternative.

[0117] Optionally, and again advantageously, a conductive pad 71 can be provided above and at a distance from the detection island ID. This conductive pad 71 is separated from the detection island ID by means of at least one dielectric region, and allows the chemical potential of the coulomb-blocking structure to be adjusted by electrical coupling. retrostatic with the ID detection island.

[0118] Apart from using the coulomb blocking structure as a charge detector, the contact pad 72 and consequently the grid block 22, can be maintained at a given, adjustable potential.

[0119] During a phase of use of the coulomb blocking structure as a charge detector, an RF signal is applied to contact pad 72. The amplitude of the RF signal reflected and taken from the contact pad 72 provides information on the charge configuration of the island ID, and therefore on its electrostatic environment.

[0120] In the example of [Fig. 3], the quantum dot BQ is provided in a semiconductor layer that can extend across the entire plate on the substrate. Alternatively, this quantum dot can be made in an etched or transferred semiconductor block whose dimensions, particularly in terms of width, are substantially equal to or less than those of the island ID.

[0121] Either of the quantum devices introduced above may comprise more than one quantum dot (QD). In fact, a quantum device according to the invention typically comprises several qubits, each formed of at least one quantum dot for storing quantum information associated with a Coulomb blocking detection structure arranged above it. The quantum dots can thus be arranged in at least one row or even in several rows and according to a matrix arrangement of quantum dots with a corresponding matrix arrangement of Coulomb blocking detection structures.

[0122] An example of a method for realizing a quantum device of a type such as described above, in particular in relation to [Fig.1] will now be given in relation to Figures 4 to 12A-12B.

[0123] A possible starting material ([Fig. 4]) for the fabrication of the device is a semiconductor-on-insulator substrate 5. The substrate 5 comprises a support layer 10 made of semiconductor material, an insulating layer 11 placed on the support layer 11, and a semiconductor surface layer 12 placed on the insulating layer. The substrate 5 is, for example, an SOI substrate with a silicon surface layer 12. The semiconductor surface layer 12 is intended to accommodate the quantum dot(s). The semiconductor-on-insulator substrate can, in particular, be an SOI (Silicon On Insulator) substrate with a silicon surface layer 12, especially 28Si, when this layer is intended to accommodate electron spin qubits.The insulating layer 11 and the support layer 10 of the substrate are typically, respectively, a silicon oxide layer commonly called a "BOX" layer (for "Buried Oxide") and a semiconductor layer, for example silicon-based. The thickness of the super layer. For example, ficielle 12 is between 5 nm and 25 nm, typically on the order of 10 nm.

[0124] Next, one or more detection islands are created.

[0125] To achieve this, a stack is formed covering the surface semiconductor layer 12. This stack comprises at least one insulating layer 13, advantageously based on a gate dielectric such as, for example, silicon oxide. An insulating layer 13 with a thickness, for example, between 5 nm and 15 nm can be formed.

[0126] A so-called “high-k” dielectric, in other words, one with a high dielectric constant k, such as HfO2, can also be used to form this insulating layer 13.

[0127] The insulating layer 13 is surmounted by at least one layer 14 of semiconductor or conductive material, typically a gate material such as, for example, polysilicon, with a thickness that may be, for example, between 20 nm and 50 nm. The layer 14 of semiconductor or conductive material is coated with at least one dielectric layer 15. A gate dielectric made of silicon oxide or a high-k dielectric such as, for example, HfO2 may also be used. The resulting stack is then covered with at least one masking layer 17, in particular a hard mask. Such a masking layer may be formed of at least one layer of insulating material, for example, SiN and / or SiO2. In the illustrated embodiment, the masking layer is formed of a bilayer of SiN and SiO2.

[0128] One or more patterns, and in particular at least one pattern, in the illustrated parallelepiped example, are then defined by etching into the masking layer 17 to form a masking block. This allows this pattern to then be transferred to the stack of underlying layers 14, 15. Anisotropic etching, particularly using a plasma, is thus performed to create the masking block, and then a corresponding block reproducing that of the masking block in the second dielectric layer 15 and the grid material layer 14.

[0129] A structure that can be obtained at the end of this step is illustrated in Figures 6A and 6B, respectively showing a perspective view and a cross-sectional view along a cutting plane parallel to a plane [O; y; z] of an orthogonal coordinate system [O; x; y; z] given in these figures. After etching, layer 14 forms a block in the form of a bar 14a in which one or more detection islands ID are provided. In the particular embodiment illustrated, the etching to form block 14a is stopped at the first insulating layer 13. In this case, the insulating layer 13 can be retained so as to cover the entire surface layer 12.

[0130] A thin layer of tunnel dielectric 19, the thickness of which, for example, is The dielectric 19, between 1 nm and 5 nm thick, depends on the material chosen and is then deposited, particularly on the lateral sides of bar 14a ([Fig. 7]). The dielectric 19 used can be, for example, SiO2 or HfO2 formed by deposition. Alternatively, bar 14a can be oxidized to allow the formation of a tunnel dielectric 19 on its lateral sides.

[0131] Grid blocks are then formed on either side of the detection island(s).

[0132] To do this, a layer of at least one conductive material is first deposited. or semiconductor, advantageously a grid material identical to that of bar 14a, for example polysilicon, which may optionally be doped. The creation of patterns in this layer may be preceded by a CMP (Chemical Mechanical Planarization) step to then form a second mask on a layer preferably without relief. This second mask may consist of one, or as in the embodiment illustrated in [Fig. 8], several layers 21, 23 of hard mask in which one or more patterns are then defined by etching, in particular orthogonal to bar 14a.

[0133] Anisotropic etching of the layer of at least one conductive or semiconducting material 20 is then carried out, typically using a plasma. In the particular example illustrated in Figures 9A-9B, the anisotropic etching of the layer of conductive or semiconducting material 20 protected by the masking 25 is continued until the dielectric layer 19 or the insulating layer 13 is reached. Blocks 22, 24 of grid are thus formed on either side of a detection island ID.

[0134] These grid blocks 22, 24 extend mainly in a direction orthogonal to that of the bar 14a before it is etched. A first grid block 22 is disposed against a region of the tunnel dielectric layer 19 arranged on a lateral flank of the detection island ID, so as to form a tunnel junction between the first grid block 22 and the detection island ID. A second grid block 24 is disposed against a region of the tunnel dielectric layer 19 arranged on an opposite lateral flank of said detection island, so as to form a tunnel junction between the second grid block 24 and the detection island.

[0135] To form the contact pads 72, 74 on the grid blocks 22, 24, one or more insulating layers can then be formed in which holes are made whose bottom reaches the grid blocks. Then, these holes are filled with a conductive material, in particular a metallic material such as, for example, W.

[0136] In the optional case where an additional conductive pad 71 is provided, coupled to the detection island ID, an additional hole is formed, but its bottom is positioned at a distance from the block 14a that receives the detection island ID. This additional hole can be formed concurrently with the receiving holes for the contact pads 72, 74. This additional hole is then subsequently filled with conductive material typically made of the same material. time as the aforementioned reception holes.

[0137] To facilitate contact between the grid blocks and the contact pads, it is possible to optionally provide for regions of metal and semiconductor alloy on the grid blocks 22, 24.

[0138] An example of the realization of these metal and semiconductor alloy regions is given in connection with Figures 10, 11, 12A-12B.

[0139] In order to form the alloy regions only on the upper faces of the gate blocks, the exposed lateral faces of these gate blocks 22, 24 can be encapsulated beforehand. Such encapsulation is illustrated, for example, in [Fig. 10], where insulating spacers 47 are produced, for example, by deposition and then etching of a dielectric material such as silicon nitride.

[0140] We can then, as in [Fig.1 1], remove the masking 25 possibly preserved on the grid blocks 22, 24 to reveal their upper faces 233. In the illustrated case where a nitride layer is to be removed from the top of the grid blocks, selectively with respect to a lateral encapsulation in SiO2, a chemical etching based on H3PO4 can be used.

[0141] Then, as shown in Figures 12A-12B, the metal-semiconductor alloy regions 51 are formed on the upper faces 233 of the gate blocks 22, 24 to create ohmic contacts on them. A deposition step of at least one layer of metal, for example Ni, Pt, W, Co, or Ti, can be carried out first. A heat treatment is then performed to achieve silicification. Such a treatment can be carried out at a temperature, for example, between 400°C and 500°C, and for a duration adapted according to the treatment temperature. The temperature range depends strongly on the materials used and the desired alloy phase.

[0142] A variant of a manufacturing process for the implementation of a quantum device of the type illustrated for example in [Fig.2] will now be given in connection with Figures 13 to 22.

[0143] Here we manufacture a device in which the quantum dot(s) is or are confined in a block also called a semiconductor bar which does not extend over the entire surface of the substrate.

[0144] The starting material can be the same substrate 5 as in the previously described embodiment example.

[0145] This substrate 5 can then be coated ([Fig.13]) with a stack comprising the first insulating layer 13, the layer 14 of semiconductor or conductive material, and the masking layer 17.

[0146] A masking block 17a is then defined in the masking layer 17, and the pattern of this masking is transferred to the stack of sub-layers 12, 13, 14. underlying. At least one anisotropic etching using a plasma is then performed to reproduce the pattern of the masking block in the grid material layer 14. In this embodiment, the insulating layer 13 and the surface semiconducting layer 12 of the substrate are also etched to reproduce this same pattern in the insulating layer 13 and the semiconducting layer 12.

[0147] A structure that can be obtained at the end of this step is shown in Figures 14A and 14B (giving, respectively, a perspective view and a cross-sectional view along axis A'A). A bar 140a, referred to as the "upper" bar, is formed after the etching of layer 14. Several detection islands are provided in this bar 140a. A bar 120a, referred to as the "lower" bar, is located below the upper bar 140a and is formed by etching the surface semiconductor layer 12. In the particular embodiment illustrated, the etching to form the upper bar 140a and the lower bar 120a is stopped on the insulating layer 11 of the substrate 5.

[0148] Lateral flanks 121 of the semiconductor bar 120a are exposed after this etching. To prevent the possibility of current flow between the future grid blocks and the bar 120a, insulating protective blocks are then formed on either side of the lateral flanks 121 of the lower semiconductor bar 120a. A high-temperature deposited oxide (HTO "High Thermal Oxide") can be used.

[0149] The fabrication of these insulating protective blocks can, as in the embodiment illustrated in Figures 15A-15B, comprise the deposition of a first thin insulating layer 151, for example, a thermal silicon oxide, with a thickness that can be, for example, between 5 nm and 20 nm. This deposition can be followed by the deposition of a thicker insulating layer 153, for example, between 50 nm and 200 nm and based on SiO2. The cumulative thickness of the insulating layers 151, 153 can then be made greater than the height of the stack covered by the masking layer 17. In this case, planarization (CMP) is then typically carried out, stopping at the level of the masking layer 17.

[0150] A partial removal of the insulating layers 151, 153 is then carried out (Figures 16A-16B) so as to remove these insulating layers 151, 153 around the upper bar 140a and expose at least part of the lateral faces of this upper bar 140a, while preserving these insulating layers 151, 153 against the lateral sides 121 of the lower bar 120a. The partial removal of the insulating layers 151, 153 can be carried out by wet etching, for example using HF.

[0151] A thin layer of tunnel dielectric 159, for example with a thickness between 1 nm and 5 nm, is then formed by deposition on the lateral faces 141 of the upper bar 140a or by oxidation of the upper bar 14a. In the particular embodiment illustrated in [Fig. 17], the thin layer of tunnel dielectric 159 also covers the masking layer 17 located at the top of the stacking of bars 120a, 140a. The thin dielectric layer 159 tunnel layer can be for example based on silicon oxide and for example of thickness between 1 and 2 nm.

[0152] The grid blocks are then formed on either side of the stack of the lower 120a and upper 140a bars. To do this, a layer of conductive or semiconducting material 162 is first deposited ([Fig. 18]), preferably a grid material identical to that of the upper 140a bar, such as polysilicon. CMP planarization is then performed to align the level reached by the conductive or semiconducting material 162 with the top of the central stack in which the 120a and 140 bars are arranged.

[0153] Then, a second masking 165 is formed. In a case where the aim is to make several detection islands and several pairs of grid blocks, the second masking 165 is formed of several distinct blocks 165a, 165b, 165c, 165d parallel to each other and which extend here orthogonally to the main direction of the superimposed bars 120a, 140a (said main direction being a direction parallel to the x-axis of the frame [O;x;y;z] given in the figures).

[0154] Next, an engraving is carried out on the layer 162 of grid material and the bar 140a in order to remove areas of the layer of grid material 162 and the bar 140a not protected by these masking blocks 165a, 165b, 165c, 165d 165.

[0155] Following such an engraving, pairs of grid blocks 172, 174 are obtained as illustrated in figures 19A-19B. Each pair of grid blocks is associated and arranged on either side of an island ID1, ID2, ID3, ID4 formed by an engraved portion of the upper bar 140a.

[0156] As with the example of process described above, here again optional steps of forming an encapsulation or insulating spacers 177 on the lateral sides of the grid blocks ([Fig.20]), of removing the second masking 165 on the upper face 173 of these grid blocks ([Fig.21]), then of making regions 185 of metal and semiconductor alloy, in particular si-liciated regions ([Fig.22]) of the grid blocks in order to make ohmic contacts can be carried out.

[0157] Contact pads can then be formed to make contact with the grid blocks. Conductive pads opposite and at a distance from the detection islands can be provided to create an electrostatic control method for the islands above them.

[0158] To implement a structure such as described above in connection with [Fig. 3] where each detection island can be associated with only one grid block, one or the other of the methods described above is adapted by forming a masking 25 or 165 which extends only on one first side of the island so that the can then be removed material from the grid block(s) on a second side of the island opposite the first side. The process steps described previously can then be followed.

[0159] In another embodiment, illustrated in [Fig. 23], the masking layer 17 formed in [Fig. 5], typically made of at least one insulating material and / or a material commonly used for making a hard mask, is replaced by a region 232 of conductive or semiconducting material. Advantageously, the material used to form the region 232 is a grid material, which can be the same material as that used to form the detection island ID, for example, polysilicon. This can provide improved contact with a conductive pad 71, which can be provided above the island ID and is intended to control it by electrostatic coupling. This can allow for an insulating region 234 with better-controlled dielectric properties and thus enable improved electrostatic coupling between the conductive pad 71 associated with the region 232 of conductive or semiconducting material and the detection island ID.

[0160] Advantageously, the region 232 of conductive or semiconducting material, insulating region 234 and the detection island can be formed concurrently through the same etching step and / or through the same masking in order to have substantially the same imprint and reproduce the same pattern.

[0161] To achieve a similar type of contact with a conductive pad 71 above and opposite the island ID, another method involves replacing the layer of material used to form the island ID with a stack of several layers comprising a first conductive or semiconducting layer, for example, made of polysilicon, an insulating layer on top of this first conductive or semiconducting layer, and a second conductive or semiconducting layer, preferably made of the same material as the first conductive or semiconducting layer, for example, polysilicon. A hard mask used to etch this stack can then be removed after the etching is complete and before forming the conductive pad 71. This conductive pad 71 is then typically formed by filling a hole made in an insulating layer that opens onto the second conductive or semiconducting layer.

Claims

Demands

1. A quantum device formed on a substrate (5) and comprising: - a first level in which at least one semiconductor region (12a, 120a) is arranged, - a second level in which at least one first gate block (22) is arranged and intended to modulate the potential of a quantum dot (QD) formed in the at least one semiconductor region (12a, 120a), the second level also comprising a charge state detection structure of the quantum dot, said detection structure comprising a detection island (ID) disposed above and opposite the quantum dot (QD) and capable of being coupled to the quantum dot, said detection structure further comprising at least one first tunnel junction (TJ1) between said detection island (ID) and the first gate block (22),the first grid block (22) being juxtaposed to said detection island (ID) and the first grid block (22) forming a charge reservoir for the detection island (ID).

2. Quantum device according to claim 1, comprising at least a second gate block (24) distinct from the first gate block (22) and located in the same first plane (P) as the first gate block (22) and the detection island (ID), the first plane being parallel to a principal plane of the substrate (5), the second gate block (24) being arranged so that the detection island (ID) is disposed between the first gate block (22) and the second gate block (24), the charge detection structure being provided with a second tunnel junction (TJ2) formed between the detection island (ID) and the second gate block (24).

3. Quantum device according to claim 2, further comprising a first contact pad (72) on the first grid block (22) and a second contact pad (74) on the second grid block (24).

4. A quantum device according to claim 3, wherein the first contact pad (72) and the second contact pad (74) are provided to: - during a so-called "detection" operating phase, apply respectively a first potential to the first gate block (22) and a second potential to the second gate block (24), different from the first potential, so as to allow the passage of a current through said first and second junctions (JT1, JT2), and - during at least one other operating phase distinct from said detection operating phase: apply the same potential given to the first grid block (22) and the second grid block (24).

5. Quantum device according to claim 4, wherein the first contact pad (72) and the second contact pad (74) are coupled to a current measurement stage through said first junction (JT1) and second junction (JT2).

6. Quantum device according to any one of claims 1 to 3, further comprising a first contact pad (72) on the first grid block (22), the first contact pad (72) being coupled to a circuit (350) of a reflectometry measurement device, said circuit (350) being in particular configured to: - emit an RF signal on the first contact pad to said island; - detect an impedance variation by means of a change in amplitude or phase of the RF signal reflected by said island.

7. Quantum device according to any one of claims 1 to 6, wherein the detection structure is provided with a conductive pad (71) for electrostatic control of said detection island (ID), said conductive pad (71) being disposed above and opposite said detection island (ID) and separated from said detection island by means of at least one dielectric region (RD, 234) so ​​as to permit electrostatic coupling between said conductive pad (71) and said detection island (ID).

8. Quantum device according to claim 7, wherein the conductive pad (71) is disposed in contact with a region of conductive or doped semiconductor material (232) separated from the detection island (ID) by means of a dielectric region (234), said region of conductive or doped semiconductor material (232), said dielectric region (234), said detection island (ID) having the same footprint and forming the same pattern.

9. Quantum device according to any one of claims 1 to 8, wherein the detection island (ID) is based on the same doped conductive or semiconductor material as the gate block(s) (22, 24).

10. A method for manufacturing a quantum device comprising the following steps: - providing a substrate (5) coated with at least one semiconductor layer (12) having at least one region (12a, 120a) in which a quantum dot is suitable for formation, - forming a bar (14a, 140a) based on at least one conductive or doped semiconductor material in which at least one island of detection opposite said quantum dot is provided, - forming at least one tunnel dielectric region (19, 159) on at least one lateral flank of said bar (14a, 140a), - forming one or more grid blocks (22, 24, 172, 174) juxtaposed to said bar (14a, 140a) and extending principally in a direction orthogonal to a principal direction in which said bar (14a, 140a) extends, at least one first grid block among said grid blocks being arranged against the tunnel dielectric region arranged on said detection island, so as to form a tunnel junction between the first grid block and the detection island.

11. Method according to claim 10, wherein said one or more grid blocks (22, 24, 172, 174) are formed by: - ​​deposition of at least one grid material, then: - engraving said grid material, said engraving being carried out concurrently with an engraving of the bar (14a, 140a) to form the detection island.

12. Method according to claim 10, said bar (14a, 140a) being based on said grid material.

13. A method according to any one of claims 11 or 12, wherein the tunnel dielectric region is formed by depositing a tunnel dielectric layer (19, 159) on the bar (14a, 140a) and then by etching the tunnel dielectric layer (19, 159), the etching of the tunnel dielectric layer and the etching of said bar (14a, 140a) to form the detection island and the etching of said grid material being carried out using the same masking.

14. A method according to any one of claims 10 to 13, wherein the tunnel dielectric region is formed by oxidation of said bar.

15. A method according to any one of claims 10 to 14, wherein said bar is said to be "upper" and formed by depositing a conductive material and then etching the conductive material using a masking, said etching of the conductive material being extended into the semiconducting layer (12) and so as to form another bar (120a) said to be "lower".

16. A method according to claim 15, wherein, after said engraving to form said other lower bar (120a), lateral flanks (121) of the lower bar (120a) are exposed, the method further comprising: after formation of said lower bar (120a) and prior to the formation of said tunnel dielectric region, steps of: - deposition of one or more insulating layers (151, 153), - etching said one or more insulating layers (151, 153) so as to form insulating protective blocks on either side of the lateral faces of the semiconductor region, - formation of a tunnel dielectric region by deposition of a tunnel dielectric layer (159) on the upper bar (140a) while the lateral flanks of the lower bar (120a) are protected.

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