Electronic component comprising a grid structure

Abstract

Electronic Device Comprising a Gate Structure The present disclosure relates to an electronic component (200) comprising a gate structure (230) on a semiconductor layer (110), the gate structure including a magnetic material. Figure for abstract: Fig. 2A

Description

Title of the invention: Electronic component comprising a grid structure Technical field

[0001] The present description relates generally to electronic components, and more particularly to electronic components comprising a gate structure, for example MOS (Metal Oxide Semiconductor) type electronic components comprising a gate structure on a semiconductor.

[0002] For example, the electronic components concerned may be FET transistors (Field Effect Transistor), MOSFET transistors (Metal Oxide Field Effect Transistor), SET transistors (Single Electron Transistor), gated diodes, MOS structures, and / or gated quantum dots. Prior art

[0003] Among the electronic components comprising a gate structure, MOSFET transistors are known, which are field effect transistors (FET), and whose gate structure comprises a layer of insulation called a gate insulator which makes it possible to isolate the rest of the gate structure from a layer of semiconductor in which drain, source and channel regions of the MOSFET transistor are formed.

[0004] Various embodiments of MOSFET transistors, and in particular several gate structures, have already been proposed.

[0005] It would be desirable to at least partially overcome certain drawbacks of known embodiments of MOSFET transistors, more generally of electronic components with a gate structure. In particular, in certain applications, it may be advantageous to give the gate structure other functions. Summary of the invention

[0006] One embodiment overcomes all or part of the drawbacks of known grid structure electronic components.

[0007] One embodiment provides an electronic component comprising a gate structure on a semiconductor layer, the gate structure including a magnetic material.

[0008] According to one embodiment, the grid structure comprises a first layer of the magnetic material.

[0009] According to one embodiment, the grid structure comprises a second layer in polycrystalline silicon, for example in contact with the first layer.

[0010] According to one embodiment, the grid structure comprises a third metal layer, for example titanium nitride.

[0011] According to one embodiment, the gate structure comprises a gate insulator layer configured to insulate said gate structure from the semiconductor layer, for example in contact with said semiconductor layer.

[0012] According to one embodiment, the third layer is between the gate insulator layer and the first layer.

[0013] According to one embodiment, the gate insulator layer is at a first face of the gate structure in contact with the semiconductor layer, and the gate structure comprises an electrical contact layer, for example made of silicide, at a second face opposite the first face.

[0014] According to one embodiment, the magnetic material comprises at least one of: cobalt, a cobalt-based material, nickel, or a nickel-based material.

[0015] According to one embodiment, the electronic component is a FET transistor, a MOSFET transistor, a SET transistor, a gate diode, a gate MOS structure, or a gate quantum dot.

[0016] One embodiment provides an electronic device comprising a semiconductor layer and at least one electronic component as described above, the at least one electronic component being in and on the semiconductor layer.

[0017] According to one embodiment, the at least one electronic component is a MOS structure, the electronic device comprising an inductor integrated on the MOS structure.

[0018] According to one embodiment, the gate structure of the MOS structure comprises a plurality of combs connected to a central rod, each comb and the rod including the magnetic material.

[0019] According to one embodiment, the electronic device is a quantum device comprising a first electronic component among the at least one electronic component, said first electronic component being a quantum dot forming a confinement region of a spin qubit.

[0020] According to one embodiment, the electronic device comprises a second electronic component among the at least one electronic component, said second electronic component being of the MOSFET transistor type forming a charge carrier injector towards the quantum box.

[0021] According to one embodiment, the electronic device further comprises an external magnetic field generator.

[0022] According to one embodiment, the semiconductor layer is a layer of silicon, for example a surface silicon layer of an SOI type substrate. Brief description of the drawings

[0023] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0024] [Fig.l] represents, by a sectional view, an example of an electronic component being a MOS transistor;

[0025] [Fig.2A] represents, by a sectional view, an electronic component according to one embodiment;

[0026] [Fig.2B] represents, by a sectional view, a variant of the electronic component of [Fig.2A];

[0027] [Fig.3A] represents, by a sectional view, an electronic component according to another embodiment;

[0028] [Fig.3B] represents, by a sectional view, a variant of the electronic component of [Fig.3A];

[0029] [Fig.4A] represents, in a top view, an electronic device comprising an electronic component according to another embodiment;

[0030] [Fig.4B] represents, by a sectional view, the electronic device of [Fig.4A]

[0031] [Fig.5A] represents, in a top view, an electronic device comprising an electronic component according to another embodiment;

[0032] [Fig.5B] represents, by a sectional view, a detail of the electronic device of [Fig.5A];

[0033] [Fig.6A] represents curves giving the inductance L of different inductors on MOS structure as a function of the frequency; and

[0034] [Fig.6B] represents curves giving the quality factor Q of different inductors on MOS structure as a function of the frequency;

[0035] [Fig.7] represents, by a 3D view, a variant of the electronic device of [Fig.5A];

[0036] [Fig.8A], [Fig.8B], and [Fig.8C] represent curves giving respectively the inductance, the resistance and the quality factor of the inductor in the electronic device of [Fig.7] as a function of the frequency. Description of the embodiments

[0037] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0038] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular, the steps of the method for manufacturing the electronic components and devices have not been described, being achievable with the usual microelectronics methods. Similarly, not all the details of the electronic components and devices have been described. Furthermore, not all the applications that the described electronic components and devices may have have been detailed.

[0039] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0040] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0041] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0042] In the following description, a length corresponds to a dimension in a first lateral direction of the electronic component, which corresponds to the X direction identified in the figures, a width corresponds to a dimension in a second lateral direction of the electronic component, orthogonal to the first direction, which corresponds to the Y direction identified in the figures, and a thickness or a depth corresponds to a dimension in a direction perpendicular to the first and second directions, which corresponds to the vertical Z direction identified in the figures. In certain electronic components, the length may correspond to a channel length between a drain region and a source region of a MOSFET transistor.

[0043] In the following description, to simplify it, a MOSFET transistor may be designated a MOS transistor, or even a transistor.

[0044] [Fig.l] represents, by a sectional view, an example of electronic component 100 being a MOS transistor.

[0045] The MOS transistor 100 is formed in and on a semiconductor layer 110. The semiconductor layer 110 is positioned above, preferably in contact with, a buried insulating layer 102 ("BOX", from the English "Buried Oxide", buried oxide), this buried insulating layer itself being above, preferably in contact with, a substrate 101. The layers 101, 102, 110 correspond for example to an SOI type substrate (from the English "Silicon On Insulator").

[0046] The semiconductor layer 110 is for example made of silicon, for example monocrystalline silicon. The buried insulating layer 102 is for example made of silicon dioxide (SiO2). The substrate 101 is for example made of silicon.

[0047] The transistor 100 comprises a drain region 121 and a source region 122 at least partially located in the semiconductor layer 110, and very heavily doped N (for an NMOS) or P (for a PMOS), a channel region 123 being formed between the drain region and the source region.

[0048] The drain and source regions may comprise raised drain 121S and source 122S portions, generally formed by epitaxial growth, as shown in the example of [Fig.l]. This makes it possible to increase the thickness of the drain and source regions relative to the thickness of the silicon layer 110 which may be very thin. This may be the case, for example, in a transistor technology of the FD-SOI type, from the English "fully-depleted Silicon on insulator", that is to say a technology making it possible to operate in fully depleted mode. In an FD-SOI type transistor, the silicon layer 110 typically has a thickness of between a few nanometers and around fifteen nanometers, for example between 5 and 15 nm, and the buried insulating layer 102 typically has a thickness of between a few nanometers and a few tens of nanometers, for example between 10 and 50 nm.

[0049] Extension regions, having an N doping (for an NMOS) or P doping (for a PMOS) a little weaker than the doping of the drain and source regions (LDD doping), are generally formed at each junction between the channel region and the source and drain regions, for example to limit the lateral electric field in the MOS transistor.

[0050] The MOS transistor 100 further comprises a gate structure 130 located above the channel region 123.

[0051] The gate structure 130 comprises an insulating layer 131, called the gate insulator, which insulates it from the channel region 123, for example a layer of silicon dioxide (SiO2), and on the gate insulator: - a layer of metal 133 (optional), for example titanium nitride (TiN), TiN being a so-called "mid-gap" type material allowing for example to have balanced threshold voltages between an NMOS and a PMOS; - a layer 134 of polycrystalline silicon, also called polysilicon, on layer 133; and, generally, - a conductive contact layer 135, typically a silicide layer, on the layer 134, making it possible to reduce the access resistance.

[0052] An insulating film 132 made of a material with a high dielectric constant k (high k in English) compared to that of silicon dioxide, for example an oxide film of hafnium (HfO2), can be positioned on the insulating layer 131.

[0053] Other gate structures and / or other layer stacks are possible, depending on the application and / or the targeted performances for example. Thus, another possible gate structure comprises a polysilicon layer on a gate insulator, generally with a contact layer, for example made of silicide, on the polysilicon layer.

[0054] Insulating spacers 137 are formed on either side of the gate structure 130, on portions of the semiconductor layer 110 not covered by this gate structure, and on the side walls (flanks) of the gate structure 130. The insulating spacers 137 are, for example, made of a silicon nitride (SiN). An insulating spacer may comprise several lateral insulating portions, as in the example shown which shows a first lateral insulating portion 137A (spacer 0) covered by a second lateral insulating portion 137B (spacer 1), the number of lateral insulating portions being able to be defined by the manufacturing method of the MOS transistor.

[0055] One function of the insulating spacers 137 may be to limit the extension of the LDD extension regions under the gate structure 130. The insulating spacers 137 may have other functions, which may be made necessary by the manufacturing process of the MOS transistor. The insulating spacers 137 may be used to reduce a parasitic capacitance of the transistor.

[0056] A conductive contact layer 124, typically made of silicide, may be positioned on each of the drain 121 and source 122 regions, for example on the raised portions 121S, 122S of the drain and source regions.

[0057] A etch stop layer, for example made of TiN, covered by a so-called "PMD" (from the English "Pre-Metal Dielectric") region made of a dielectric material which can be silicon dioxide (SiO2) can be located on the transistor 100, and contacts can pass through the etch stop layer and the PMD region up to the contact conductive layers of the transistor 100.

[0058] Some integrated electronic devices on a silicon layer can make it possible to create, in the silicon layer, one or more quantum boxes ("quantum dots" in English), with a view to using them as a confinement region for one or more quantum bits (qubit, from the English "quantum bit"), or spin qubit. The structure of a quantum box is not detailed, being known to those skilled in the art.

[0059] Such a quantum dot may be made using a technology derived from that of MOS components, for example a technology derived from that of MOS transistors such as the MOS transistor 100 of [Fig.l]. The silicon layer in which the quantum dots are formed may correspond to the super layer ficial, or active, of an FD-SOI type substrate in and on which the MOS component is formed.

[0060] The structure of the MOS transistor 100 of [Fig. 1] may for example be adapted to form all or part of a quantum dot of a quantum device intended to confine and control a spin qubit. A confinement region of the qubit may be formed in a portion of the silicon layer 110, for example corresponding to the channel region 123. The drain and source regions 121, 122 may be displaced away from the channel region 123 and replaced by charge carrier reservoirs (charge reservoirs) and / or by injection regions interposed between the confinement region and the charge reservoirs, and the gate structure 130 may form a control gate, or front gate, intended to receive an electrical potential in order to control the qubit. Other gate structures may be provided in the quantum device. For example, the qubit may also be controlled by a back gate.

[0061] During operation of the quantum device, the number of charge carriers confined in the quantum dot can be controlled by the Coulomb blockade phenomenon obtained by applying an electric potential to the control gate. For example, the electric potential applied to the control gate can have the effect of lowering the chemical potential of the quantum dot defined in the confinement region, and can thus make tunneling of a charge carrier from the charge reservoirs possible. The term "charge carrier" generally refers to an electron for an N-doped qubit, but it can be a hole for a P-doped qubit.

[0062] Furthermore, the application of a magnetic field makes it possible to separate the spin states of the qubit confined in the confinement region in energy. For example, it is possible to move from the low energy state to the higher energy state using resonant electromagnetic excitation. When the energy of the electromagnetic excitation is equal to the separation of the spin states, the transitions are then possible. For this, the quantum dot can be coupled with an ESR (Electron Spin Resonance) device which generates a magnetic field oscillating at the resonant frequency, or an EDSR (Electrical Dipole Spin Resonance) device.

[0063] One solution for coupling the quantum dot with the ESR or EDSR device may be to position the magnetic field generating element, for example a current-powered coil, or a magnetic bar, above and / or around the confinement region of the spin qubit. However, due to this configuration, the field generating element is at a minimal distance from the confinement region, typically a few micrometers, which causes the magnetic field to be attenuated at the qubit.

[0064] The inventors propose an electronic component with a grid structure making it possible to meet the improvement needs described above, and to overcome all or part of the drawbacks of the electronic components described above. In particular, the inventors propose an electronic component with a grid structure which makes it possible to integrate a magnetic function, in particular without complicating the manufacturing process of this electronic component.

[0065] Embodiments of electronic components with a grid structure will be described below. The embodiments described are non-limiting and various variants will become apparent to those skilled in the art from the indications of the present description.

[0066] [Fig.2A] represents, by a sectional view, an electronic component 200 according to one embodiment. [Fig.2B] represents, by a sectional view, a variant of the electronic component 200 of [Fig.2A].

[0067] [Fig. 3A] represents, by a sectional view, an electronic component 300 according to another embodiment. [Fig. 3B] represents, by a sectional view, a variant of the electronic component 300 of [Fig. 3A].

[0068] The electronic component shown in Figures 2A, 2B, 3A, 3B is a MOS transistor of the SOI type which includes characteristics in common with the MOS transistor 100 of [Fig.l], but which differs therefrom in that the gate structure comprises a magnetic material. This magnetic material is preferably in the form of a layer of magnetic material. The layer of magnetic material can replace all or part of the polysilicon layer 134 of [Fig.l].

[0069] The magnetic material is for example cobalt or a cobalt-based material, for example an iron cobalt alloy (FeCo), nickel or a nickel-based material.

[0070] An advantage of cobalt, or even nickel, is that this material follows a hysteresis cycle by application of an external magnetic field. An application of this is that it is possible to modify the orientation and / or the amplitude of the magnetic field generated by the magnetic material (internal magnetic field) by applying to this material an external magnetic field, for example defined by its hysteresis cycle. As shown in [Fig.2A], depending on the external magnetic field applied, in a first configuration, the magnetic field B1 generated by the magnetic material (vertical arrow in solid line) can be oriented in the Z direction, and in a second configuration the magnetic field B2 generated by the magnetic material (horizontal arrow in dotted line) can be oriented in the X direction.

[0071] More broadly, an external magnetic field can be applied in addition to the magnetic field generated by the magnetic material in the grid structure (internal magnetic field). For example, the external magnetic field, typically a constant field, can be used for a Zeeman effect, and the internal magnetic field, ty- staking a magnetic gradient, can be used for EDSR control.

[0072] Another advantage of cobalt is that it is compatible with MOS technologies, being for example already implemented in certain processes for forming silicide contact layers.

[0073] In the example of [Fig.2A], the gate structure 230 comprises an insulating layer 231, called the gate insulator, which isolates it from the channel region 123, for example a layer of silicon dioxide (SiO2), and it further comprises: - a layer of magnetic material 236 (first layer) on the gate insulator 231; and, generally, - a contact layer 235 (electrical contact layer) on the magnetic material layer 236: the contact layer is an electrically conductive layer, for example made of tungsten (W) or titanium silicide (TiSi), making it possible for example to reduce the access resistance.

[0074] The insulating layer 231 is located at a lower face 230A (first face) of the gate structure 230, in contact with the semiconductor layer 110, while the contact layer 235 is located at an upper face 230B (second face) of the gate structure opposite the first face 230A.

[0075] One or more contacts may be provided on the contact layer 235, or even directly on the layer of magnetic material 236, for example a contact made of tungsten (W) or a titanium and silicon alloy (TiSi).

[0076] The other characteristics of the transistor 200 of [Fig.2A] may be similar to those of the transistor 100 of [Fig.l], the variants described in relation to the transistor 100 of [Fig.l] may also apply to the transistor 200 of [Fig.2A].

[0077] For example, in the variant of [Fig.2B], the gate structure 230 comprises a metal layer 233 (third layer) between the gate insulator 231 and the magnetic material layer 236. The metal layer 233 may be designated by the term "metal gate" in English, metal gate. The metal layer 233 may be made of TiN, TiN being a so-called "mid-gap" type material allowing for example to have balanced threshold voltages between an NMOS and a PMOS.

[0078] An insulating film 232 of the high k type, for example a hafnium oxide (HfO2) film, may be positioned between the gate insulator 231 and the magnetic material layer 236 or the metal layer 233.

[0079] In the example of [Fig.3A], the gate structure 330 comprises an insulating layer 331, called the gate insulator, which isolates it from the channel region 123, for example a layer of silicon dioxide (SiO2), and it further comprises: - a layer of polysilicon 334 (second layer) on the gate insulator 331; - a layer of magnetic material 336 (first layer) on the polysilicon layer 334; and, generally, - a contact layer 335 (electrical contact layer) on the magnetic material layer 336: the contact layer is an electrically conductive layer, for example made of tungsten (W) or titanium silicide (TiSi), making it possible for example to reduce the access resistance.

[0080] An advantage of having the polysilicon 334 and magnetic material 336 layers is that it enables electrical control of charges in the qubit quantum box application, as well as qubit operations through magnetic control, and allows adjustment of the magnitude, location, and gradient of the magnetic field in the channel 123 region.

[0081] The insulating layer 331 is located on a lower face 330A (first face) of the grid structure 330, in contact with the semiconductor layer 110, while the contact layer 335 is located on an upper face 330B (second face) of the grid structure opposite the first face 330A.

[0082] One or more contacts can be provided on the contact layer 335, or even directly on the magnetic material layer 336, for example a tungsten (W) contact or a titanium and silicon alloy (TiSi) contact.

[0083] The other characteristics of the transistor 300 of [Fig.3A] may be similar to those of the transistor 100 of [Fig.l], the variants described in relation to the transistor 100 of [Fig.l] may also apply to the transistor 300 of [Fig.3A].

[0084] For example, in the variant of [Fig.3B], the gate structure 330 comprises a metal layer 333 (third layer), or gated metal, between the gate insulator 331 and the magnetic material layer 336. The metal layer 333 may be made of TiN.

[0085] An insulating film 332 of the high k type, for example a hafnium oxide (HfO2) film, may be positioned between the gate insulator 331 and the polysilicon layer 334 or the metal layer 333.

[0086] Other gate structures and / or other layer stacks are possible, depending on the application and / or the targeted performances, for example, to the extent that these structures comprise a magnetic material, for example a layer of magnetic material. For example, in the example of Figures 3A, 3B, the order of the layers of polysilicon 334 and magnetic material 336 can be reversed, i.e. the layer of magnetic material 336 can be on the gate insulator 331 and the layer of polysilicon 334 on the layer of magnetic material 336.

[0087] The MOS transistors shown in the description of FIGS. 2A, 2B, 3A, 3B may be N-channel MOS transistors (NMOS), i.e. transistors whose source and drain regions are N-type doped, for example doped with arsenic or phosphorus atoms, or P-channel MOS transistors (PMOS), i.e. transistors whose source and drain regions are P-type doped, for example doped with boron atoms.

[0088] Each of the electronic components 200, 300 shown in Figures 2A, 2B, 3A, 3B may be included in an electronic device. The electronic device may include one or more other electronic components formed in and on the same semiconductor layer 110. The electronic components 200, 300 of Figures 2A, 2B, 3A, 3B may be combined with each other in and on the same semiconductor layer 110.

[0089] According to an exemplary embodiment, the MOS transistors of FIGS. 2A, 2B, 3A, 3B are FD-SOI type transistors, for example with a gate dimension of 28 nm (28 nm node), the different layers then having dimensions linked to the 28 nm node. For illustration, the Si semiconductor layer 110 has a thickness of about 7 nm, the drain and source regions 121, 122 with the raised portions 121S, 122S have a thickness of about 13 nm, the buried insulating layer 102 of SiO2 has a thickness of about 25 nm, the Si substrate layer 101 has a thickness of about 100 nm, the magnetic material layer 236 has a thickness of about 24 nm in the example of [Fig. 2A], or the magnetic material layers 336 and polysilicon 334 each have a thickness of about 12 nm in the example of [Fig. 3A], and the metal layer 233, 333 has a thickness of about 6.5 nm in the examples of FIGS. 2B and 3B.

[0090] An advantage of having a magnetic material in the gate structure of the electronic component is that this makes it possible to generate a magnetic field from the electronic component, as close as possible to the semiconductor layer, for example as close as possible to the channel region 123 in the example shown in FIGS. 2A, 2B, 3A, 3B.

[0091] The inventors determined by simulations, based on a 28 nm node FD-SOI model with the example thicknesses indicated above, that the presence of the magnetic material in the gate structure allowed for a larger magnetic field gradient under, and around, the gate structure, and less spreading when moving away from the gate structure. In particular, the inventors determined, by simulations at different levels in the Z direction, that the magnetic field could be particularly large at the channel region.

[0092] The inventors also determined by simulations that, in the first configuration where the magnetic field B1 is oriented in the Z direction, the gradient of the magnetic field was more elongated in the Z direction than in the X direction, whereas in the second configuration where the magnetic field B2 is oriented in the X direction, the gradient of the magnetic field was more elongated in the X direction than in the Z direction.

[0093] The inventors also determined that the presence of the magnetic material did not disturb the characteristics of the MOS transistor, for example that the voltage of transistor threshold was very little impacted. In the application to a qubit quantum dot, the qubit can also be controlled by a back gate (not shown in Figures 2A, 2B, 3A, 3B). More generally, the threshold voltage can be adjusted via a voltage on a back gate.

[0094] The transistors represented in the description of figures 2A, 2B, 3A, 3B are MOSFET transistors, but the description can extend to other transistors with a gate structure, for example to SET transistors, and more broadly to any other electronic component comprising a gate structure.

[0095] Thus, an electronic component according to one embodiment may be, for example, a FET transistor, a MOSFET transistor, a SET transistor, a gate diode, a MOS type structure (MOS structure) with a gate, or a quantum dot with a gate.

[0096] The MOS transistors according to the embodiments can be manufactured according to known techniques of microelectronics, in particular known techniques for manufacturing MOS transistors, for example using the same manufacturing lines. More broadly, the electronic components according to the embodiments can be manufactured according to known techniques of microelectronics, in particular known techniques for manufacturing these electronic components, by adapting the steps of forming the gate structure.

[0097] [Fig.4A] represents, by a top view, an electronic device 400 comprising an electronic component according to another embodiment. [Fig.4B] represents, by a sectional view (section AA), the electronic device of [Fig.4A].

[0098] The electronic device 400 is for example suitable for the formation of at least one quantum dot, and may be designated as a quantum device. For example, when a quantum dot is formed, the electronic device 400 may make it possible to produce a spin qubit.

[0099] The electronic device 400 comprises a silicon strip 410 which rests on, and preferably in contact with, a buried insulating layer 402, for example made of silicon oxide. The buried insulating layer 402 rests on, and preferably in contact with, a semiconductor substrate 401, for example made of silicon. The vertical stacking of the strip 410, the layer 402 and the substrate 401 can form an SOI structure, the strip 410 then corresponding to a portion of the silicon-on-insulator layer.

[0100] The strip 410 is delimited laterally by insulating trenches 403, i.e. trenches filled with an insulating material such as silicon dioxide, for example STI type trenches (from the English "Shallow Trench Insulation"). The insulating trenches 403 penetrate vertically from an upper face of the device 400 coplanar with the upper face of the strip 410 to the lower face of the buried insulating layer 402, or even partially penetrate in the substrate 401. Thus, the strip 410 is delimited by the insulating trenches 403 in a first direction X parallel to the length of the strip 410 and in a second direction Y perpendicular to the length of the strip 410. The first and second directions X, Y are orthogonal to each other and to the vertical direction of the stack.

[0101] For example, when the strip 410 corresponds to a portion of a silicon-on-insulator layer, the strip 410 is defined in this silicon-on-insulator layer by the insulating trenches 403.

[0102] The electronic device 400 further comprises a first grid structure 430 resting on a central portion of the strip 410. The first grid structure 430 may have, in top view, a substantially square shape, although, in other examples, the grid structure 430 may have a substantially circular shape and / or be stretched in the longitudinal direction X of the strip 410 (first direction). An electrical contact 435 with the grid structure 430 may be provided, so as to allow the application of a voltage to the first grid structure 430.

[0103] The first gate structure 430 comprises a gate insulator 431 between the strip 410 and the remainder of the first gate structure 430.

[0104] As an example, the portion of the strip 410 located under the first gate structure 430 corresponds to an electronic component which is a quantum dot 403 functioning as a confinement region of a spin qubit, and the first gate structure 430 forms a control gate, or front gate, intended to receive an electrical potential in order to control the qubit.

[0105] Preferably, the first grid structure 430 comprises a magnetic material, for example cobalt or a cobalt-based material, nickel or a nickel-based material. The magnetic material may be in the form of a layer of the magnetic material.

[0106] In the application where the quantum box 403 forms a confinement region of a spin qubit, a magnetic field can thus be applied as close as possible to the qubit in order to act on the spin, for example to separate in energy the spin states of the qubit confined in the confinement region. The distance between the magnetic field generating element and the qubit is thereby reduced compared to the solutions described previously in which the magnetic field generating element is arranged above and / or around the confinement region of the spin qubit. According to the embodiments, this distance can thus be a few nanometers instead of a few micrometers.

[0107] For example, one can use the ESR technique by applying a radio frequency (RF) signal to the front gate 430 to generate an electromagnetic field to couple onto the charge carrier (hole or electron), or the EDSR technique in ap folding a DC signal onto the front gate 430 and / or onto a back gate to move the charge carrier in a magnetic gradient.

[0108] The first gate structure 430 may be similar to any of the gate structures 230, 330 described in relation to FIGS. 2A, 2B, 3A, 3B, for example without the insulating spacers and / or without the silicide regions.

[0109] The electronic device 400 further comprises two second grid structures 440 which extend longitudinally in the first direction X on either side of the first grid structure 430 in this first direction X.

[0110] Each second gate structure 440 rests on the strip 410, being insulated therefrom by a gate insulator 441, and may also include one end resting on the trenches 403 as shown in [Fig.4B].

[0111] Every second grid structure 440 is separated from the first grid structure 430 by a space el. One or more electrical contacts 445 with every second grid structure 440 may be provided, so as to allow the application of a voltage to the second grid structure 440.

[0112] The electronic device 400 further comprises, below each second gate structure 440, a semiconductor region 451, 452, for example made of silicon, on the buried insulating layer 402. Each semiconductor region 451, 452 is for example doped with a first conductivity type, for example the N type. By way of example, each semiconductor region 451, 452 corresponds to a portion of a silicon-on-insulator layer, for example the silicon-on-insulator layer in which the strip 410 is defined. As illustrated by [Fig.4A], the first gate structure 430 is between a first semiconductor region 451 and a second semiconductor region 452 in the first direction X.For example, the first semiconductor region 451 forms a drain region, the second semiconductor region 452 forms a source region, the assembly of the two second gate structures 440 and the first and second semiconductor regions 451, 452 forming an electronic component which is a MOS transistor 450.

[0113] The first and second semiconductor regions 451, 452 are exposed. One or more electrical contacts 455, 456 with each of the first and second semiconductor regions 451, 452 are provided. These electrical contacts 455, 456 allow a voltage to be applied to each of the first and second semiconductor regions 451, 452.

[0114] For example, the first semiconductor region 451 is biased, for example to a positive voltage, via the electrical contact 455, and the second gate structure 440 which surmounts the first semiconductor region 451 is also biased via the electrical contact 445 to extract a charge carrier potentially generated in the first semiconductor region 451 and allow its circulation to space. el, in the portion of the strip 410 arranged under this second grid structure 440. To cross the space el to the quantum dot 403, it is possible to act on the first grid structure 430, and possibly on one or more third grid structures 460 described later. It is also possible to act on a rear grid (not shown in FIGS. 4A and 4B). Each second grid structure 440 can be designated as being a charge carrier injector, or "injector", or an accumulation grid.

[0115] The first and second semiconductor regions 451, 452 are advantageously positioned at a distance from the quantum box 403, for example to avoid noise between these regions and this quantum box.

[0116] For example, each second gate structure 440 comprises a magnetic material, for example cobalt or a cobalt-based material, nickel or a nickel-based material. The magnetic material may be in the form of a layer of magnetic material. This may allow, for example, to precondition the spin of a charge carrier before it is injected into the quantum dot 403. Each second gate structure 440 may be similar to any of the gate structures 230, 330 described in connection with FIGS. 2A, 2B, 3A, 3B.

[0117] The electronic device 400 further comprises third grid structures 460 arranged opposite the space el in the second direction Y, and devoid of a portion resting on the strip 410. In other words, all or part of the third grid structures 460 rests on the insulating trenches 403, at least the portions of the third grid structures 460 positioned above the space el.

[0118] There may be two third grid structures 460 on either side of each el space in the second Y direction, preferably aligned with each other in the second Y direction, as shown in [Fig.4A], or a single third grid structure on one side of each el space in the second Y direction.

[0119] The third gate structures 460 are, for example, configured to allow control of the electrostatic potential in the portion of the strip 410 arranged in the el space between the first gate structure 430 and each second gate structure 440. For example, when a tunnel barrier is present in the el space, the third gate structures 460 allow control of this tunnel barrier, a tunnel barrier being, for example, an electrostatic potential barrier that can be tunneled through. The potential barriers in the el spaces correspond to the potential barriers of the quantum dot 403 under the first gate structure 430.

[0120] One or more electrical contacts 465 with each third gate structure 460 may be provided, so as to allow the application of a voltage to each third gate structure 460.

[0121] In the example of [Fig.4A], the third grid structures 460 each have, in top view, a substantially rectangular shape, and extend longitudinally in the second direction Y. In another example not illustrated, each third grid structure may have, in top view, a substantially square shape.

[0122] For example, a space e2 separates the portion of the strip 410 which is arranged in the space el from each third grid structure 460.

[0123] According to one example, each third gate structure 460 comprises a magnetic material, for example cobalt or a cobalt-based material, nickel or a nickel-based material. The magnetic material may be in the form of a layer of the magnetic material. Each third gate structure 460 may then be similar to any of the gate structures 230, 330 described in relation to FIGS. 2A, 2B, 3A, 3B, for example without the insulating spacers.

[0124] In the embodiment of Figures 4A and 4B, the electronic device 400 comprises a single first gate structure 430, and therefore a single quantum dot 403. In alternative embodiments, the electronic device 400 may comprise at least two first gate structures 430 and therefore at least two quantum dots 403, for example one next to the other in the first direction X, separated by a non-zero space, for example el.

[0125] [Fig.5A] represents, by a top view, an electronic device 500 comprising an electronic component according to another embodiment. [Fig.5B] represents, by a sectional view (section BB), a detail of the electronic device of [Fig.5A].

[0126] The electronic device 500 shown in FIGS. 5A and 5B illustrates an application to the production of an integrated inductor on a MOS structure forming the electronic component with a gate structure, which may be a structure of the SOI type, for example FD-SOI.

[0127] The electronic device 500 thus comprises an inductor 540, represented in the form of a single-loop induction coil, positioned above, for example on, a MOS structure 550. The induction coil 540 comprises for example a layer of copper 541 covered by a layer of aluminum 542.

[0128] The MOS structure 550 comprises a silicon layer 510, which may be a surface silicon layer of an SOI type substrate, for example FD-SOI. The MOS structure 550 comprises, on the semiconductor layer 510, a gate structure 530 which is in the form of a central rod 531 connected to a plurality of combs 532 substantially perpendicular to the central rod, forming a screen as explained later. This gate structure geometry is given for illustrative purposes and other geometries may be envisaged by those skilled in the art. Between the gate structure 530 and the inductor 540, the MOS structure 550 comprises a layer of dielectric 520, which may be a PMD region of silicon dioxide (SiO2). The dielectric layer 520 may comprise, or correspond to, an interconnection region (known by those skilled in the art by the acronym "BEOL", Back End Of Line), and this interconnection region may comprise a first metallization level, which is the metallization level closest to the substrate, known by the name "Ml", to which electronic components may be connected via contacts passing through the dielectric layer 520.

[0129] Preferably, the gate structure 530 comprises a magnetic material, for example cobalt or a cobalt-based material, nickel or a nickel-based material. The magnetic material may be in the form of a layer of the magnetic material. The gate structure 530 may be similar to any of the gate structures 230, 330 described in connection with FIGS. 2A, 2B, 3A, 3B, for example without the insulating spacers and / or without the silicide regions.

[0130] The grid structure 530 including the magnetic material makes it possible to form a protective screen to reduce the interactions between the inductor and the substrate. This protective screen can be grounded.

[0131] The inventors have determined that the integration of a magnetic material into the grid structure 530 makes it possible to improve certain characteristics of the inductor 540, as explained in the description which follows.

[0132] [Fig.6A] represents curves giving the inductance L of different inductors on MOS structure as a function of the frequency.

[0133] Curve 610 corresponds to a metal screen (without magnetic material) which, in a known manner, is integrated into the first metallization level ML. Curve 620 corresponds to a metal screen (without magnetic material) which would be integrated at the level of the silicon layer 510 of FIGS. 5A and 5B. Curve 630 corresponds to the grid structure 530 of FIGS. 5A and 5B, with magnetic material at 1 Tesla (T), forming a metal screen integrated at the level of the silicon layer 510.

[0134] [Fig.6A] shows that the integration of a magnetic material in the grid structure 530 under the inductor 540 makes it possible to increase the inductance of this inductor. In addition, this makes it possible to have a more stable inductance in a wider range of frequencies.

[0135] [Fig.6B] represents curves giving the quality factor Q of different inductors on MOS structure as a function of frequency.

[0136] Curve 640 corresponds to a metal screen (without magnetic material) which, in a known manner, is integrated into the first metallization level ML. Curve 650 corresponds to a metal screen (without magnetic material) which would be integrated at the level of the silicon layer 510 of Figures 5A and 5B. Curve 660 corresponds to the gate structure 530 of Figures 5A and 5B, with magnetic material at 1T, forming metal screen integrated at the 510 silicon layer.

[0137] [Fig.6B] shows that the integration of a magnetic material in the gate structure 530 under the inductor 540 makes it possible to increase the quality factor of this inductor up to a frequency of approximately 15 GHz. This may be of interest in certain applications, for example in a low-noise amplifier (LNA) of a qubit readout circuit, which generally operates at 7 GHz.

[0138] A single-loop induction coil is shown in Figures 5A and 5B, but this embodiment can be extended to a multi-loop induction coil such as that described above, or even to any other type of inductor integrated on a MOS structure.

[0139] [Fig.7] represents, by a 3D view, a variant of the electronic device of [Fig.5A].

[0140] In the example shown in [Fig.7], the electronic device 700 comprises an induction coil 740 with two concentric loops 741, 742 on a MOS structure 550 such as that described in connection with FIGS. 5A and 5B.

[0141] [Fig.8A], [Fig.8B] and [Fig.8C] represent curves giving respectively the inductance L, the resistance R and the quality factor Q of the inductor in the electronic device 700 of [Fig.7] as a function of the frequency.

[0142] These curves show that the presence of the magnetic material in the grid structure makes it possible to induce on the double-loop inductor a singularity point between approximately 7 and 10 GHz (circled in dotted lines). One application of this is to form a band-feed filter, or a band-stop filter.

[0143] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art.

[0144] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims

Claims

1. An electronic component (200; 300; 403; 450; 550) comprising a gate structure (230; 330; 430; 440; 460; 530) on a semiconductor layer (110; 410; 510), the gate structure including a magnetic material.

2. An electronic component (200; 300) according to claim 1, wherein the gate structure (230; 330) comprises a first layer (236; 336) of the magnetic material.

3. Electronic component (300) according to claim 2, wherein the gate structure (330) comprises a second layer (334) of polycrystalline silicon, for example in contact with the first layer (336).

4. Electronic device (200; 300) according to claim 2 or 3, wherein the gate structure (230; 330) comprises a third layer (233; 333) of metal, for example titanium nitride.

5. Electronic component (200; 300; 403; 450) according to any one of claims 1 to 4, wherein the gate structure (230; 330; 430; 440) comprises a gate insulator layer (231; 331; 431; 441) configured to insulate said gate structure from the semiconductor layer (110; 410; 510), for example in contact with said semiconductor layer.

6. An electronic component (200; 300) according to claim 5 in its dependency with claim 4, wherein the third layer (233; 333) is between the gate insulator layer (231; 331) and the first layer (236; 336).

7. Electronic component (200; 300) according to claim 5 or 6, wherein the gate insulator layer (231; 331) is located at a first face (230A; 330A) of the gate structure in contact with the semiconductor layer (110), and the gate structure comprises an electrical contact layer (235; 335), for example made of silicide, at a second face (230B; 330B) opposite the first face.

8. An electronic component according to any one of claims 1 to 7, wherein the magnetic material comprises at least one of: cobalt, a cobalt-based material, nickel, or a nickel-based material.

9. An electronic component according to any one of claims 1 to 8, the electronic component being an FET transistor, a transistor MOSFET, SET transistor, gate diode, gate MOS structure, or gate quantum dot.

10. An electronic device (400; 500; 700) comprising a semiconductor layer (110; 410; 510) and at least one electronic component (200; 300; 403; 450; 550) according to any one of claims 1 to 9, the at least one electronic component being in and on the semiconductor layer.

11. An electronic device (500; 700) according to claim 10, wherein the at least one electronic component is a MOS structure (550), the electronic device comprising an inductor (540; 740) integrated on the MOS structure.

12. The electronic device (500; 700) of claim 11, wherein the gate structure (530) of the MOS structure (550) comprises a plurality of combs (532) connected to a central rod (531), each comb and the rod including the magnetic material.

13. An electronic device (400) according to claim 10, the electronic device being a quantum device comprising a first electronic component (403) among the at least one electronic component, said first electronic component being a quantum dot forming a confinement region of a spin qubit.

14. Electronic device (400) according to claim 13, comprising a second electronic component (450) among the at least one electronic component, said second electronic component being of the MOSFET transistor type forming a charge carrier injector towards the quantum dot (403).

15. An electronic device (400) according to any one of claims 10 to 14, further comprising an external magnetic field generator.

16. Electronic component according to any one of claims 1 to 9, in which the semiconductor layer (110; 410; 510) is a silicon layer, for example a surface silicon layer of an SOI type substrate.

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