SUPERNETWORK OBTAINED BY LAYER TRANSFER, STRUCTURE AND MANUFACTURING METHOD

Abstract

A method (600) of manufacturing a structure comprising a stack of superlattices, comprising the steps of forming (610Car) two superlattices (Stck1, Stck2) on respective substrates, each formed from a stack of channel layers alternating with sacrificial layers; forming (620Car, 620Don) respective cover layers (Cap1, Cap2) on the two superlattices (Stck1, Stck2); and assembling (660) the two superlattices (Stck1, Stck2) by contacting their respective cover layers (Cap1, Cap2) which together form a bonding layer, the first cover layer (Cap1) and the second cover layer (Cap2) each having a thickness of less than 2 nm. Figure to be published with the abstract: Fig. 6

Description

Title of the invention: SUPERNETWORK OBTAINED BY LAYER TRANSFER, STRUCTURE AND MANUFACTURING METHOD TECHNICAL FIELD OF THE INVENTION

[0001] The invention relates generally to superlattices, which are made up of at least one periodic stack of thin layers. The invention relates more particularly to superlattices including layers of semiconductor materials. TECHNOLOGICAL BACKGROUND

[0002] Superlattices have attracted attention for their mechanical and semiconducting properties, or even for the possibility they offer of forming quantum dots.

[0003] They are also used for the development of transistors called nanosheet transistors, also called Nanosheet transistors or GAAFET for Gate-all-around Field-Effect Transistors in English terminology, whose conduction channels are formed from a stack of layers of nanometric thickness each surrounded by a gate metal, as described in patents US 10,249,739 B2 and US 11,018,222 Bl. These are semiconductor structures with an enveloping gate, or GAA for Gate-All-Around in English terminology.

[0004] This principle has been adopted to form so-called CFET transistors, for Complementary Field Effect Transistor in English terminology, having a three-dimensional structure formed using a pair of stacked superlattices: a first superlattice formed on a substrate is used to form a p-type transistor while a second superlattice formed on the first superlattice is used to form an n-type transistor, or vice versa. This three-dimensional structure is advantageous in terms of integration compared to conventional approaches used to implement CMOS technology, which usually uses p-type transistors and n-type transistors manufactured side-by-side in the same plane.In particular, the CFET approach makes it possible in principle to halve the size of a pair of p- and n-type transistors, or to shorten the connections between the two transistors and therefore to reduce the electrical resistance of the corresponding connections. This approach is described for example in documents US 2019 / 0319095 Al, US 2021 / 0104523 Al, and US 2023 / 0326925 AL.

[0005] Whether it is Nanosheet transistors or CFET transistors, the manufacturing processes considered involve the manufacturing of super networks comprising stacks of two alternating types of materials: one is intended to form the channel regions of the transistors, the other to form sacrificial layers intended to be removed to be replaced by a gate dielectric and gate metal structure during the fabrication of the transistors.

[0006] The manufacture of CFET transistors requires stacking transistors of two types, n-type and p-type, one on top of the other. Two approaches are possible.

[0007] The first approach is called "sequential", in the sense that the transistors of the two types are formed sequentially, during distinct steps. In this approach, a semiconductor structure made of silicon or other semiconductor material, or a superlattice intended to form second Nanosheet transistors, is transferred onto a semiconductor substrate already carrying, for example, first Nanosheet transistors. In a first step, the first transistors are formed on the substrate, then the semiconductor structure is transferred onto it, in which the second transistors are then formed. The thermal budget for the process of transferring the semiconductor structure and for forming the second transistors is limited by the need not to degrade the first transistors.Furthermore, the alignment control of the second transistors with the first transistors must be extremely strict and specific electrical contact structures between the two stages must be provided.

[0008] The second approach is called "monolithic", in the sense that the first and second transistors are formed on the same substrate, at least part of the manufacturing steps being applied simultaneously to all of the layers in which the first and second transistors are formed. Reference may be made to document US 2019 / 0319095 AL One of the main advantages of this approach is the self-alignment of the second transistors on the first transistors, which allows a higher density of transistors on the substrate, and reduces the parasitic capacitances and resistances between the first and second transistors.

[0009] The monolithic approach requires thicker superlattices as a starting structure than the sequential approach, since these superlattices form the basic structure of two stacked transistors manufactured simultaneously. Superlattices are generally manufactured by epitaxy. However, the number of stackable layers for the formation of these superlattices is limited by the critical epitaxy thickness, thickness beyond which the quality of the deposited layers degrades due to elastic relaxation and / or plastic relaxation phenomena. The monolithic approach is close to and could require exceeding the critical epitaxy thickness.

[0010] Thus, there is a need for super network structures comprising layers in sufficient number and quality to guarantee homogeneity and performance. of transistors formed from these layers. In addition, the manufacturing processes for CFET transistors require basic structures that facilitate and make their manufacture more reliable, and, if possible, improve the characteristics of the devices obtained, in particular miniaturization, parasitic capacitances, or even the electrical resistances of the connections. Statement of the invention

[0011] The applicant's objective is to provide a method for manufacturing a structure capable of facilitating the integration and production of Nanosheet transistors, and optionally CFET transistors, i.e. p-type transistors and superimposed n-type transistors. More generally, the method according to the invention aims to form superlattices of arbitrary thickness or number of layers.

[0012] To achieve this aim, one aspect of the invention is a method of manufacturing a structure comprising a stack of superlattices, comprising the steps of: forming a first superlattice on a first substrate, by stacking a plurality of first channel layers alternating with a plurality of first sacrificial layers; forming a first covering layer on the first superlattice; forming at least one second sacrificial layer on a second substrate; forming a second covering layer on the at least one second sacrificial layer;and assembling the at least one sacrificial layer to the first superlattice by contacting the second capping layer with the first capping layer which together form a bonding layer, the first superlattice, the bonding layer and the at least one sacrificial layer being stacked in this order, wherein the first capping layer and the second capping layer each have a thickness of less than 2 nm.;

[0013] A first advantage of the method is to provide a stack of superlattices which can be either identical or distinct in composition and / or orientation.

[0014] A second advantage of the method is the possibility of exceeding the critical epitaxy thickness for the structures obtained, which limits the number and thickness of layers that can be epitaxied on top of each other without losing quality in the crystalline structures of these layers.

[0015] A third advantage of the method lies in the provision within the stack of a bonding layer between two superlattices, this layer being able to be eliminated during the same process as that of the elimination of sacrificial layers included in the superlattices.

[0016] Thus, the manufacturing method according to the invention is suitable for the production of structures which can serve as the basis for a monolithic method for producing an electronic circuit integrating Nanosheet transistors or CFET transistors.

[0017] According to additional non-limiting characteristics of the method according to the invention, considered individually or according to any technically feasible combination:

[0018] - the step of forming at least one second sacrificial layer on the second substrate may comprise forming a second superlattice by stacking a plurality of second channel layers alternating with a plurality of second sacrificial layers;

[0019] - the step of forming at least one second sacrificial layer on the second substrate may comprise forming a seed layer, the method may further comprise a step of forming a second superlattice on the seed layer after the assembly step, by stacking a plurality of second channel layers alternating with a plurality of second sacrificial layers;

[0020] - the bonding layer may be continuously formed in a plane parallel to a surface of the first substrate on which the first superlattice is formed;

[0021] - the first channel layers and the second channel layers may each be formed of a semiconductor material, and the first sacrificial layers and the second sacrificial layers may each be formed of a material capable of exhibiting a faster etch rate than the first channel layers and the second channel layers, respectively;

[0022] - the sacrificial layers in direct contact with the bonding layer may each having a thickness equal to or less than half the thicknesses of the other sacrificial layers;

[0023] - the method may further comprise a step of eliminating at least a part of the second substrate after the assembly step;

[0024] - the method may further comprise a step of forming a plan of embrittlement of the carrier substrate by implantation of ions of a light species into the donor substrate; and a step of fracturing the donor substrate and removing a portion of the donor substrate after the assembly step;

[0025] - the method may further comprise a step of releasing a layer of channel of the second superlattice after the step of removing the second substrate;

[0026] - the first covering layer and the second covering layer may each be formed of silicon;

[0027] - one of the first covering layer and the second covering layer one covering may be formed from amorphous silicon and the other may be formed from crystalline silicon;

[0028] - the method may further comprise a step of forming at least one layer stopping etching on the second substrate before the formation of the primer layer;

[0029] - the at least one etch stop layer may comprise a layer of the same material as the primer layer.

[0030] The invention extends to a structure of a superlattice stack, comprising: a carrier substrate; a first superlattice on the carrier substrate; a bonding layer on the first superlattice, formed of a first covering layer and a second covering layer; and a second superlattice on the bonding layer, wherein the first covering layer and the second covering layer each have a thickness of less than 2 nm.

[0031] According to additional non-limiting characteristics of the structure according to the invention, considered individually or according to any technically feasible combination:

[0032] - the bonding layer may be continuously formed in a plane parallel to a surface of the carrier substrate supporting the first superlattice;

[0033] - the first superlattice may be formed from a stack of a plurality of first channel layers alternating with a plurality of first sacrificial layers; the second superlattice may be formed from a stack of a plurality of second channel layers alternating with a plurality of second sacrificial layers; the first channel layers and the second channel layers may each be formed of a semiconductor material, and the first sacrificial layers and the second sacrificial layers may each be formed of a material capable of exhibiting a faster etch rate than the first channel layers and the second channel layers, respectively;

[0034] - one of the first covering layer and the second covering layer covering may be formed from crystalline silicon and the other of the first covering layer and the second covering layer may be formed from amorphous silicon; and

[0035] - the sacrificial layers in direct contact with the bonding layer may each having a thickness equal to or less than half the thicknesses of the other sacrificial layers. BRIEF DESCRIPTION OF THE FIGURES

[0036] Other characteristics and advantages of the invention will emerge from the detailed description of the invention which follows with reference to the appended figures in which:

[0037] [Fig.l] [Fig.l] illustrates a first manufacturing method according to the invention;

[0038] [Fig.2] [Fig.2] illustrates a continuation of the method of [Fig.l];

[0039] [Fig.3] [Fig.3] illustrates variants of structures that can be obtained by the method of figures 1 and 2;

[0040] [Fig.4] [Fig.4] illustrates a detail of one of the variants of the bonding layers of the [Fig.3] ;

[0041] [Fig.5] [Fig.5] illustrates an interest of the structures of [Fig.3] in the manufacture of Nanosheet or CFET transistors;

[0042] [Fig.6] [Fig.6] is a diagram summarizing the manufacturing process of Figures 1 and 2;

[0043] [Fig.7] [Fig.7] illustrates a second manufacturing method according to the invention;

[0044] [Fig.8] [Fig.8] illustrates a continuation of the method of [Fig.7]; and

[0045] [Fig.9] [Fig.9] is a diagram summarizing the manufacturing process of Figures 7 and 8. DETAILED DESCRIPTION OF THE INVENTION

[0046] First embodiment

[0047] A first embodiment of the present invention is described by means of Figures 1 to 6 and the associated description below.

[0048] [Fig.3] illustrates in (A) a Strc structure formed from a carrier substrate Car, a first superlattice Stckl, a bonding layer Bnd, and a second superlattice Stck2, stacked in this order. The first superlattice Stckl comprises a plurality of first Chl layers stacked alternately with a plurality of first Sacl layers, preferably such that each first Chl layer is interposed between and in direct contact with two of the first Sacl layers. The second superlattice Stck2 comprises a plurality of second Ch2 layers stacked alternately with a plurality of second Sac2 layers, preferably such that each second Ch2 layer is interposed between and in direct contact with two of the second Sac2 layers.

[0049] The first Chl layers and the second Ch2 layers are layers formed of at least one semiconductor material for forming channel regions of transistors and may be referred to as the first channel Chl layers and the second channel Ch2 layers, respectively. These channel layers may be formed of the same material, or of different materials.

[0050] The first Sacl layers and the second Sac2 layers are layers formed from at least one material capable of exhibiting faster etching rates than the first Chl layers and the second Ch2 layers, and may be referred to as the first sacrificial Sacl layers and the second sacrificial Sac2 layers, respectively. These sacrificial layers may be formed from the same material, or from different materials. In particular, the Sacl layers may have a composition SiiXGex and the Sac2 layers may have a composition Si i yGey where x and y represent the proportions of germanium in the Sacl layers and Sac2, respectively, with x being different from or equal to y. These Sacl and Sac2 layers of SiGe alloy can be associated with Chl and Ch2 layers of silicon, thanks to the epitaxial growth compatibility of these two materials which have a fairly close lattice parameter. The proportions x and y are preferably less than 40%, for example between 15% and 35%.

[0051] The second layers Sacl and Sac2 are intended to serve as sacrificial layers in a procedure for forming Nanosheet transistors, during which the layers Sacl and Sac2 are removed by etching, which may be chemical, so as to obtain a structure of floating ribbons formed from the layers Chl and Ch2. These floating ribbons will subsequently be surrounded by a gate dielectric layer and a gate metal so as to form Nanosheet transistors.

[0052] Figures 1, 2 and 6 illustrate a method for manufacturing the Strc structure, which is advantageously based on the separate manufacturing of the two superlattices Stckl and Stck2 on two respective substrates, then the transfer of the second superlattice Stck2 onto the first superlattice Stckl. The first and second superlattices each comprise at least two channel layers Chl and Ch2, respectively. [Fig.6] represents a diagram schematizing the steps of the manufacturing method 600.

[0053] [Fig.l] illustrates in (A) the formation of the first Stckl superlattice on a carrier substrate Car, during a step 610Car- In the context of this example, the carrier substrate Car is made of a monocrystalline silicon wafer. On a surface SCar of the substrate Car, Chl layers of silicon Si of 5 to 15 nm thickness, preferably 7 to 10 nm thickness, are grown by epitaxy, alternating with Sacl layers of a first alloy of silicon and germanium of formula Sii xGex of 5 to 10 nm thickness, preferably 6 to 9 nm thickness, and where x represents the percentage of germanium in the alloy, preferably starting and ending with a Sacl layer.

[0054] On the last Sacl layer, a covering layer Capl is formed during a step 620Car, here formed from silicon Si of crystalline or amorphous structure and having the function of preventing the oxidation of the last Sacl layer. The Capl layer may have a thickness of less than 2 nm or 3 nm, for example between 0.5 and 2 nm, preferably between 1 and 2 nm, for reasons which will be explained below, by means of [Fig.5].

[0055] [Fig.l] illustrates in (B) the formation of the second superlattice Stck2 on a donor substrate Don, during a step 620Don. In the context of this example, the donor substrate Don consists of a monocrystalline silicon wafer.

[0056] On an SDon surface of the Don substrate, Ch2 layers of silicon Si with a thickness of 5 to 15 nm, preferably 7 to 10 nm, are grown by epitaxy, in alternating with Sac2 layers of the first silicon and germanium alloy of formula SU xGex 5 to 10 nm thick, preferably 6 to 9 nm thick. Preferably, the growth is implemented so that one begins and ends with a Sac2 sacrificial layer. On the last Sac2 layer, a covering Cap2 layer is formed, made of silicon of amorphous or crystalline structure, during a step 630Don- Preferably, one of the silicon layers Capl and Cap2 has an amorphous structure while the other has a crystalline structure in order to facilitate their subsequent assembly by direct contact. The Cap2 layer has the function of preventing the oxidation of the last Sac2 layer. This Cap2 layer is however optional, its interest depending on the ease of oxidizing the material constituting the last layer of the second Stck2 superlattice.The Cap2 layer may have a thickness less than 2 nm or 3 nm, for example between 0.5 and 2 nm, preferably between 1 nm and 2 nm, for reasons which will be explained below, by means of [Fig.5].

[0057] Optionally, before the formation of the second superlattice Stck2, it is possible to form on the donor substrate Don a layer Stp formed for example from the first alloy of silicon and germanium of formula Sii xGex with a thickness of between 5 and 10 nm, during a step 610Don- This layer is an etch stop layer and is intended to protect the integrity of the layers of the second superlattice Stck2 during the manufacturing steps following the fracture of the donor substrate described later and illustrated by (B) and (C) of [Fig.2].

[0058] [Fig.l] illustrates in (C) an implantation of light species such as hydrogen, helium, or a combination of such species in the donor substrate Don through the second superlattice Stck2 and the covering layer Cap2, so as to form an embrittlement plane lmp in the donor substrate Don, during a step 640Don.

[0059] Following the formation of the weakening plane lmp, the donor substrate Don is turned over and the covering layer Cap2 is brought into intimate contact with the silicon layer Capl and is assembled there, for example by molecular bonding or any other assembly technique by bringing into direct contact surfaces of elements to be assembled, so as to obtain the structure illustrated in (A) of [Fig.2], during an assembly step 660. The bonding layer Bnd is formed at this step by bonding the last layers formed respectively on the carrier substrate Car and on the donor substrate Don, and corresponds to the assembly formed by the layers Capl and Cap2 separating the first superlattice Stckl and the second superlattice Stck2, as illustrated by [Fig.3]. This bonding layer Bnd preferably completely overlaps the donor substrate Don. In addition, the bonding layer Bnd is continuously formed in a plane parallel to the surface SCar of the carrier substrate Car supporting the first superlattice Stckl. Even if the bonding layer does not strictly overlap the entire carrier substrate Car, it is at least formed continuously over an area intended to form an assembly of semiconductor components such as transistors, possibly an assembly of Nanosheet transistors or CFET transistors.

[0060] Preferably, the support and donor substrates respectively comprising the first and second superlattices are substantially identical. This advantageously makes it possible to easily produce them on a large scale, thus facilitating their industrialization. Furthermore, substantially identical support and donor substrates advantageously make it possible to have a symmetrical assembled structure having similar thermal expansion coefficients, which advantageously avoids problems of mechanical deformation following the bonding steps and subsequent heat treatments.

[0061] At this stage of the manufacturing, the superlattices Stckl and Stck2 are sandwiched between the carrier substrate Car and the donor substrate Don. These superlattices must be released in order to make them accessible. This release operation 670 is carried out in two successive steps 670A and 670B which will allow direct access to the second superlattice Stck2. Step 670A here consists of removing the majority of the donor substrate while step 670B consists of eliminating the remainder of the donor substrate and exposing the upper part of the second superlattice Stck2.

[0062] [Fig.2] illustrates in (B) the fracture of the donor substrate Don at the level of the weakening plane lmp obtained by ion implantation, so that a part Donb is removed from the structure illustrated in (A) while a part Dona remains fixed there, during the fracture and removal step 670A. This fracture can be obtained by heat treatment, possibly assisted by a mechanical stress to initiate the fracture, according to conventional layer transfer techniques well known in the field of microelectronics.

[0063] Following assembly and fracture of the donor substrate, a heat treatment may be applied to consolidate the assembly and cure the assembled layers. The temperature and duration of the heat treatment are limited to avoid exceeding the authorized thermal budget to avoid or at least limit the diffusion of germanium from one layer to another of the superlattices, and in particular the contamination of the channel layers by germanium over their entire thicknesses. The heat treatment may typically consist of an annealing of 2 hours or less at a maximum temperature of 750°C and preferably less than 700°C.

[0064] An alternative to forming a weakening plane and fracturing the donor substrate Don at that plane may be thinning the donor substrate Don after assembly, for example by etching, grinding and / or polishing. chemical mechanical polishing (CMP). This thinning can be used to completely remove the second substrate Don if it is pushed, for example, to the stop layer Stp.

[0065] [Fig.2] illustrates in (C) the structure illustrated in (B) after it has been subjected to mechanical and / or chemical attacks to remove the Dona part of the donor substrate Don, and the etch stop layer Stp, during step 670B. Thus, the Ch2 layer of the second superlattice furthest from the carrier substrate Car is released during this step.

[0066] The structure at (C) of [Fig.2] represents the structure Strc formed of the carrier substrate Car, the first superlattice Stckl, the capping layer Capl formed of silicon, the capping layer Cap2 formed of silicon, and the second superlattice Stck2, stacked in this order. The capping layer Capl and the capping layer Cap2 form a bonding layer Bnd between the first superlattice Stckl and the second superlattice Stck2, as indicated by [Fig.3] at (A). This structure is ready to be subjected to a monolithic process for forming CFET transistors.

[0067] The figures bear the indications "Si" or "SiGe" at the locations of certain layers, and in particular those forming the Stckl and Stck2 superlattices, in order to increase their readability by indicating their compositions for a given example. These indications are not, however, to be interpreted as limiting the nature of the layers thus annotated. Other materials, and in particular those cited in this description, may be used to form these layers.

[0068] [Fig.3] illustrates in (A') a Strc' structure with a possible particularity of the layers surrounding and in direct contact with the bonding layer Bnd.

[0069] In (A) and (A'), the bonding layer Bnd is formed by bonding the covering layer Capl to the covering layer Cap2, constituting respectively the last layers formed on the carrier substrate Car and on the donor substrate Don, in direct contact with, respectively, the last sacrificial layer Sacl or Saclo formed on the carrier substrate Car and the last sacrificial layer Sac2 or Sac20 formed on the donor substrate Don. The thicknesses of these last sacrificial layers Sacl (annotated Sacl0 for Strc') and Sac2 (annotated Sac20 for Strc') may for example be of the same thickness as the other layers Sacl and Sac2, respectively.

[0070] In the example shown in (A), all the Sacl and Sac2 layers are of the same thickness. In this configuration, the distance separating the Chl and Ch2 layers closest to each other and separated by the Bnd layer is greater than the distances separating two consecutive Chl layers or two consecutive Ch2 layers. in the stack, since this distance corresponds to the sum of the thicknesses of a Sacl layer, a Sac2 layer and the Bnd layer.

[0071] In A', the sacrificial layers in direct contact with the bonding layer Bnd, identified as Sacl0 and Sac20, are respectively of thicknesses ts aci0 and ts ac20 smaller than the thicknesses of the other sacrificial layers Sacl and Sac2 of respective thicknesses ts aci and ts ac2. The layers Sacl0 and Sac20 may thus each have a thickness equal to or less than half the thicknesses of the other sacrificial layers Sacl and Sac2, respectively. In this way, the total thickness ttot separating the Chl and Ch2 layers closest to each other and separated by the Bnd layer of thickness tB nd can approach or even be equal to the thicknesses ts ad and ts ac2, as illustrated by [Fig.4] (ttot=tSacio+tB nd+tsac2o)- An interest of this geometry is explained in relation to [Fig.5].

[0072] As explained above, a method for manufacturing Nanosheet or CFET transistors employs a superlattice of semiconductor material with sacrificial layers interposed between layers of a semiconductor material intended to form the transistor channel regions.

[0073] According to the invention, in the present embodiment, the silicon layers Capl and Cap2 are sufficiently thin so that germanium from the layers Sacl0 and Sac20 has diffused over the entire thickness of the layers Capl and Cap2 during the manufacturing process. This diffusion can be ensured by a dedicated heat treatment, by choosing the parameters of a bonding heat treatment during the assembly of the two stacks Stckl and Stck2, by choosing the parameters of a fracture heat treatment of the donor substrate Don, the heat treatment parameters for consolidating the assembly and repairing the assembled layers, or even by parameterizing these different operations so as to ensure the diffusion of the germanium in the layers Capl and Cap2. It is of course advisable not to go beyond the necessary thermal budget so as to avoid the germanium diffusing throughout the entire thickness of the channel layers.Also, the thickness of the channel layers can be designed to take this diffusion into account. Thus, the Capl and Cap2 layers of the structures illustrated in [Fig.3] are in fact made of an alloy of silicon and germanium, and can therefore be considered as sacrificial layers with respect to the Chl and Ch2 channel layers, just like the sacrificial layers Sacl, Sacl0, Sac2 and Sac20.

[0074] [Fig.5] illustrates the Strc' structure of [Fig.3] having been subjected to an attack of the sacrificial layers Sacl, Sacl0, Sac2 and Sac20 having left the channel layers Chl and Ch2 suspended. In view of the comments in the previous paragraph, it is understood that the layers Capl and Cap2 forming the bonding layer have also been attacked. In the general case of the Strct structure, it is possible to obtain a structure of suspended Chl and Ch2 channel layers, of good crystalline quality over a thickness and / or a number of layers exceeding what is possible to achieve from a structure obtained by a conventional epitaxy process, a process limited by the critical epitaxy thickness.

[0075] Furthermore, in the particular case of the Strc' structure, the environment of each of the channel layers Chl and Ch2 can be arranged as substantially identical to that of the other channel layers, including with regard to the distances separating them: the distance ttot separating the two channel layers closest to each other and previously separated by the bonding layer Bnd can be brought closer to tSaci and tSaC2 or arranged equal to these distances separating the other channel layers from each other, as illustrated by [Fig.5]. An advantage is the uniformity of the environment of the channel layers of the transistors formed on this basis.

[0076] The bonding layer Bnd, which is the layer bonding the two superlattices to each other, is not in principle limited to being formed of crystalline silicon and amorphous silicon. The layer Bnd may be formed exclusively of crystalline silicon, exclusively of amorphous silicon, or of any other material compatible with the manufacturing methods disclosed in the present document, and possibly with the manufacturing methods envisaged using as a basis the assembly of the two superlattices Stckl and Stck2.

[0077] The manufacturing method illustrated by Figures 1 and 2 makes it possible to obtain a superposition of two superlattices. In addition, the method can be repeated to stack an arbitrary number of superlattices. Thus, the critical epitaxy thickness can be exceeded: each of the superlattices taken individually can respect this thickness so as to be formed of layers of high quality, and their stacking allows an assembly of superlattices exceeding the critical thickness while maintaining the quality of the layers composing them. When the stacked superlattices have similar characteristics as to the layers (nature, dimension) forming them, it can be considered that a single superlattice is formed, possibly exceeding the critical epitaxy thickness.

[0078] The formation by epitaxy of the layers constituting the superlattices involves the reproduction of the crystalline structure from one layer to another, so that the Chl (or Ch2) and Sacl (or Sac2) layers, for example respectively in Si and SiGe, have the same crystalline structure. Ordinarily, it is not possible to epitaxy a layer of semiconductors with acceptable characteristics in order to form transistors on an amorphous layer. Indeed, the latter does not constitute an adequate basis for the epitaxy of a quality crystalline semiconductor layer. The bonding layer obtained by the layer transfer of the method according to the invention makes it possible to assemble two superlattices formed from semiconductor layers of sufficient quality to produce transistors for commercial applications.

[0079] Furthermore, the bonding layer can be adapted (composition, thickness of the layer(s) forming it) to the intended use of the stacked superlattices. In particular, it is possible to ensure elimination of the bonding layer during a subsequent operation of eliminating the sacrificial layers by means of an appropriate choice of the nature and thickness of the layers composing it.

[0080] The bonding layer between the two superlattices is formed continuously in a plane parallel to the upper surface of the substrate supporting it, covering substantially the entire surface of the substrate.

[0081] The carrier substrate Car and the donor substrate Don may comprise any semiconductor material. In addition to silicon, the semiconductor material may be germanium (Ge), a silicon-germanium alloy (SiGe), silicon carbide (SiC), silicon-germanium carbide (SiGeC), IILV compound semiconductors or ILVI compound semiconductors, or SOI type substrates for Silicon-On-Insulator in English terminology, and more generally any type of semiconductor substrate comprising a buried or surface layer of dielectric material. Such a dielectric layer may serve as an etch stop layer for the formation of structures on the rear face (on the side of the carrier substrate Car) of the structure obtained by the method described in FIGS. 1 and 2, or, for the case where it is located on the surface, as insulation in order to prevent the so-called "latch-up" phenomenon of an integrated circuit manufactured on the basis of this structure.

[0082] The Chl and Ch2 layers may be formed, for example, from silicon or a type IILV semiconductor compound. The Sacl and Sac2 layers may be formed, for example, from silicon and germanium alloys generically designated by SiGe. The Chl and Ch2 layers may be of the same composition in both Stckl and Stck2 superlattices, and similarly, the Sacl and Sac2 layers may be of the same composition Six xGex in both Stckl and Stck2 superlattices. This latter point makes it possible to eliminate the Sacl and Sac2 sacrificial layers during the same step.

[0083] Alternatively, the superlattices Stckl and Stck2 may be of different natures and / or orientations. The orientation of the second superlattice relative to the first superlattice is defined during the assembly step. The layers Sacl and Saclo (and Chl) on the one hand, and the layers Sac2 and Sac20 (and Ch2) on the other hand, may for example have different orientations, for example with crystallographic axes offset by 45°. It is also possible to consider the use of strained silicon, silicon and germanium alloys SiGe or germanium for the channel layers of one or other of the two superlattices or for the two. When both superlattices comprise alloys of silicon and germanium, the proportions of germanium in the alloy may be the same or different for the two superlattices. It is of course appropriate to adapt the nature and characteristics of the sacrificial layers Sacl and Sac2 to those of the layers Chl and Ch2.

[0084] Similarly, the numbers of channel layers and sacrificial layers in the two superlattices may be the same, respectively, or may be different.

[0085] Second embodiment

[0086] A second embodiment of the present invention is described by means of Figures 3, 7, 8 and 9 and the associated description below.

[0087] In the first embodiment, the two superlattices Stckl and Stck2 illustrated by [Fig. 3] are formed separately on two respective substrates, then the second superlattice Stck2 is transferred onto the first superlattice Stckl. The second embodiment differs from this first embodiment in that instead of transferring a second superlattice onto the first superlattice Stckl, a seed layer Init is transferred onto the first superlattice Stckl, then the second superlattice Stck2 is formed on this seed layer Init by epitaxy. The seed layer Init is then integrated into the second superlattice Stck2. Apart from this aspect, reference may be made to the description of the first embodiment, the same elements and the same steps being identified by the same references. In particular, the structures obtained by the manufacturing methods of the two embodiments are illustrated in common by [Fig. 3].

[0088] Figures 7, 8 and 9 illustrate a manufacturing method 900 of the structures Strc and Strc' of [Fig.3], this method being based on the sequential manufacturing of the two superlattices Stckl, the second superlattice Stack2 being formed directly on the first superlattice Stckl. [Fig.9] represents a diagram schematizing the steps of the manufacturing method 900.

[0089] Subsequently, only the steps distinct from the corresponding steps of the first embodiment are commented on. Steps 610Car, 620Car, 640Don, 660, and 670A and their sequences remain unchanged in this second embodiment.

[0090] A step 910Don replaces step 610Don: before the formation of the primer layer Init formed during the following step 920Don, the layer Stp of the first silicon and germanium alloy of formula Sii xGex with a thickness of between 5 and 10 nm can be formed on the donor substrate Don, then a protective layer Cap2' in silicon with a thickness of between 1 and 5 nm. These two layers are etch stop layers and are intended to protect the integrity of the layer Init during the steps manufacturing following the fracture of the donor substrate described later and illustrated in (B) and (C) of [Fig.8],

[0091] A step 920Don replaces step 620Don: instead of forming a superlattice on the donor substrate, a seed layer Init is formed. This may be a layer of the same nature and characteristics as one of the sacrificial layers Sac2. [Fig.7] illustrates in (A), (B) and (C) the progress of the manufacturing process after steps 620Car, 930Don and 640Don, respectively.

[0092] A step 930Don is substantially identical to step 630Don. Simply, instead of forming the Cap2 layer on a second superlattice, this Cap2 layer is formed on the Init seed layer.

[0093] The following steps do not change up to step 970 which replaces step 670 of the first embodiment. This is substantially identical to step 670, except that step 670B is replaced by a step 970B during which it is the primer layer Init which is cleared and exposed. [Fig.8] illustrates in (C) the structure illustrated in (B) after it has been subjected to mechanical and / or chemical attacks to eliminate the Dona part of the donor substrate Don, the etch stop layer Stp, and the protective layer Cap2' during step 970B. Thus, the primer layer Init is cleared during this step, and accessible for the rest of the manufacturing process.

[0094] The manufacturing method ends with the implementation of a step 980 of forming the second superlattice Stck2 by epitaxy. A preliminary step is to eliminate, within a thin-film deposition frame, any native oxide from the surface of the Init layer, using the “in-situ” etching function available in a large number of epitaxy frames. This operation makes it possible to clean the Init layer and to guarantee the quality of its surface in order to ensure the quality of the growth of the layers deposited there. The second superlattice Stck2 is then formed directly on the seed layer Init, during a step 980, according to methods described for step 620Don, considering the seed layer Init as one of the sacrificial layers Sac2 of the second superlattice Stck2 and as the starting layer for growth by epitaxy. Ch2 layers are thus formed in succession alternating with Sac2 layers.

[0095] The operation of cleaning the Init layer prior to the layer depositions is conventional and is considered as part of the step of forming the Ch2 and Sac2 layers by epitaxy. Alternatively, other known methods of cleaning the surface of the Init layer could be envisaged, such as the complete oxidation of the Cap2' layer and its removal by HF directly in the frame. The essential thing is to obtain a clean, non-oxidized surface before proceeding to the deposition of thin layers on this surface, whether the deposition sequence begins with a Sac2 layer or a Ch2 layer. Following this step, one or other of the structures illustrated in [Fig.3] are obtained.

[0096] The embodiments described above relate to an association of superlattices intended to form transistors, and more specifically Nanosheet or CFET transistors. The scope of the invention, however, extends beyond this field, and includes the combination of superlattices in general, not only in the field of semiconductors.

[0097] The invention is not limited to the embodiments described above and variations may be made thereto without departing from the scope of the invention as defined by the claims.

Claims

Claims

1. Method (600; 900) for manufacturing a structure (Strc, Strc') comprising a stack of superlattices, comprising the steps of: - forming (610Car) a first superlattice (Stckl) on a first substrate (Car), by stacking a plurality of first channel layers (Chl) alternating with a plurality of first sacrificial layers (Sacl); - forming (620Car) a first covering layer (Capl) on the first superlattice (stckl); - forming (620Don; 920Don) at least one second sacrificial layer (Stck2; Init) on a second substrate (Don); - forming (630Don; 930Don) a second covering layer (Cap2) on the at least one second sacrificial layer (Stck2; Init); and - assembling (660) the at least one sacrificial layer (Stck2;Init) to the first superlattice (Stckl) by contacting the second covering layer (Cap2) with the first covering layer (Capl) which together form a bonding layer (Bnd), the first superlattice (Stckl), the bonding layer (Bnd) and the at least one sacrificial layer (Stck2; Init) being stacked in this order, wherein the first covering layer (Capl) and the second covering layer (Cap2) each have a thickness of less than 2 nm.;

2. The method (600) of claim 1, wherein the step of forming at least one second sacrificial layer on the second substrate (Don) comprises forming (620Don) a second superlattice (Stck2) by stacking a plurality of second channel layers (Ch2) alternating with a plurality of second sacrificial layers (Sac2).

3. The method (900) according to claim 1, wherein the step of forming at least one second sacrificial layer (Stck2) on the second substrate (Don) comprises forming (920Don) a primer layer (Init), the method further comprising a step (980) of forming a second superlattice (Stck2) on the primer layer (Init) after the step (660) of assembling, by stacking a plurality of second channel layers (Ch2) alternating with a plurality of second sacrificial layers (Sac2).

4. The method according to any one of claims 1 to 3, wherein the bonding layer (Bnd) is continuously formed in a plane parallel to a surface (SCar) of the first substrate (Car) on which the first superlattice (Stckl) is formed.

5. The method according to any one of claims 2 to 4, wherein: - the first channel layers (Chl) and the second channel layers (Ch2) are each formed of a semiconductor material, and - the first sacrificial layers (Sacl) and the second sacrificial layers (Sac2) are each formed of a material capable of exhibiting a faster etching rate than the first channel layers (Chl) and the second channel layers (Ch2), respectively.

6. The method according to claim 5, wherein the sacrificial layers (Sacl0, Sac20) in direct contact with the bonding layer (Bnd) each have a thickness (tSacio, tSac2o) equal to or less than half the thicknesses (tSac, tSac) of the other sacrificial layers (Sacl, Sac2).

7. The method according to any one of claims 1 to 6, further comprising a step of removing (670A) at least a portion (Donb) of the second substrate (Don) after the assembling step (660).

8. The method according to any one of claims 1 to 6, further comprising: - a step (640Don) of forming a weakening plane of the carrier substrate by implanting ions of a light species into the donor substrate (Don); and - a step (670A) of fracturing the donor substrate (Don) and removing a portion (Donb) of the donor substrate (Don) after the assembly step (660).

9. The method according to claim 7 or 8, further comprising a step of releasing (670B) a channel layer (Ch2) from the second superlattice (Stck2) after the step of removing (670A) the second substrate (Don).

10. The method of any one of claims 1 to 9, wherein the first covering layer (Capl) and the second covering layer (Cap2) are each formed of silicon.

11. The method of claim 10, wherein one of the first covering layer and the second covering layer is formed of amorphous silicon and the other is formed of crystalline silicon.

12. The method of claim 3, further comprising a step of forming (610Don) at least one etch stop layer (Stp) on the second substrate (Don) before forming the primer layer (Init).

13. The method of claim 12, wherein the at least one etch stop layer comprises a layer (Stp) of the same material as the primer layer (Init).

14. Structure (Strc, Strc') of a superlattice stack, comprising: - a carrier substrate (Car); - a first superlattice (Stckl) on the carrier substrate; - a bonding layer (Bnd) on the first superlattice (Stckl), formed of a first covering layer (Capl) and a second covering layer (Cap2); and - a second superlattice (Stck2) on the bonding layer (Bnd), wherein: - the first superlattice is formed of a stack of a plurality of first channel layers (Chl) alternating with a plurality of first sacrificial layers (Sacl); - the second superlattice is formed of a stack of a plurality of second channel layers (Ch2) alternating with a plurality of second sacrificial layers (Sac2); - the first covering layer (Capl) and the second covering layer (Cap2) each have a thickness of less than 2 nm.

15. The structure of a superlattice stack according to claim 14, wherein the bonding layer (Bnd) is continuously formed in a plane parallel to a surface (SCar) of the carrier substrate (Car) supporting the first superlattice (Stckl).

16. The structure of a superlattice stack according to claim 14 or 15 wherein: - the first channel layers (Chl) and the second channel layers (Ch2) are each formed of a semiconductor material, and - the first sacrificial layers (Sacl) and the second sacrificial layers (Sac2) are each formed of a material capable of exhibiting a faster etching rate than the first channel layers (Chl) and the second channel layers (Ch2), respectively.

17. The superlattice stack structure according to any one of claims 14 to 16, wherein one of the first capping layer (Capl) and the second capping layer (Cap2) is formed of crystalline silicon and the other of the first capping layer (Capl) and the second capping layer (Cap2) is formed of amorphous silicon.

18. The structure according to any one of claims 14 to 17, wherein the sacrificial layers (Sacl0, Sac20) in direct contact with the bonding layer (Bnd) each have a thickness (t sacio, tsac2o) equal to or less than half the thicknesses (tsac, tsac) of the other sacrificial layers (Sacl, Sac2).

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