Communication hub

Abstract

Communication Hub This description relates to a communication hub circuit comprising: two ports (P1) for exchanging data with another communication hub circuit (102); one port (P2) for exchanging data with a computing microchip (106); one port (P3) for exchanging data with an accelerator microchip (108); one interface (ITm) for exchanging data with a memory circuit (110); one interface (ITs, ITe) for exchanging data with a sensor (104); a data processing circuit (PUs); and a network-on-chip (NOC) for transferring data between elements of the communication hub circuit. Figure for the abstract: Fig. 2

Description

Title of the invention: Communication concentrator technical field

[0001] The present description relates generally to electronic circuits. Previous technique

[0002] In the automotive field, a single manufacturer generally has a wide range of vehicles.

[0003] In addition, the electronic / electrical architecture of vehicles is moving towards a centralization, in each vehicle, of calculations and data processing on a single platform, system or computer, capable of addressing the multimedia application needs and assisted or autonomous driving of the vehicle.

[0004] However, in a range of vehicles, each vehicle has different computing and data processing needs depending on the multimedia devices it includes, i.e. the multimedia experience offered by this vehicle, and, on the other hand, the level of its advanced driver assistance system (ADAS), i.e., for example, the L2, L2+, L3 or L4 level of the driving assistance system with which the vehicle benefits.

[0005] To meet the computing and data processing needs of a whole range of vehicles, one solution is to integrate a single, very high-performance processor into each vehicle and program this processor using software according to the specific needs of the vehicle. However, since such a processor must be able to address the computing and data processing needs of the highest-end vehicle, it will be oversized when installed in a lower-end vehicle, which is undesirable.

[0006] A second solution consists of developing, in the form of a system-on-a-chip, a specific, dedicated, and different computer for each set of vehicles with similar computing and processing needs. However, developing several different systems-on-a-chip is complex and undesirable, and, moreover, lacks scalability. This complexity generates significant costs and technical development difficulties. Summary of the invention

[0007] There is a need to overcome all or part of the disadvantages of known computers addressing different computing and data processing needs between products in the same product range, for example between vehicles in the same vehicle range.

[0008] One embodiment overcomes all or part of the drawbacks of computers known to address different computing and data processing needs between products in the same product range, for example between vehicles in the same vehicle range.

[0009] One embodiment provides a communication concentrator circuit comprising: at least two initial physical ports configured each to exchange data with another communication hub circuit that is part of the same cache-coherent memory area as said hub circuit, when said first port is connected via a high-speed link to that other communication hub circuit; at least one second physical port configured to exchange data with a computing microchip that is part of said same cache-coherent memory area when said at least one second physical port is connected via a high-speed link to that computing microchip; at least one third physical port configured to exchange data with an accelerator microchip that is part of an input / output coherent memory area with said same cache coherent memory area, when said at least one third physical port is connected via a high-speed link to this accelerator microchip; at least one first interface configured to exchange data with a memory circuit that is part of said same cache-coherent memory area when said at least one first interface is connected to that memory circuit; at least one second interface configured to exchange data with a sensor; at least one processing circuit configured to implement data processing; at least one network-on-chip configured to transfer data between elements of the communication hub circuit, said elements comprising said at least two first ports, said at least one second port, said at least one third port, said at least one processing circuit and said at least one first interface.

[0010] According to one embodiment: said at least two first physical ports are each configured to implement a CXL.mem and CXL.cache or AXI stream protocol when exchanging data with the other communication hub circuit; said at least a second physical port is configured to implement a CXL.cache and CXL.mem protocol during data exchange with the computing microchip; and said at least a third physical port is configured to implement a CXL.mem, CXL.io or PCIe protocol when exchanging data with the accelerator microchip.

[0011] According to one embodiment, the concentrator circuit is configured to merge several data streams that it receives without implementing any processing on said several streams.

[0012] According to one embodiment, the concentrator circuit is configured to perform processing on separate data streams that it receives and then to merge the results of these processing.

[0013] According to one embodiment, the hub circuit is configured to implement cache coherence in said same cache coherence memory area.

[0014] According to one embodiment, the hub circuit is configured to implement input / output coherence between said same cache coherency memory area and another memory area to which an accelerator microchip belongs.

[0015] According to one embodiment, said at least a first interface comprises an interface for DDR type memory and / or an interface for FLASH type memory.

[0016] According to one embodiment, the concentrator circuit further includes a direct memory access circuit.

[0017] According to one embodiment, said at least a second interface comprises at least one CSI type interface and / or at least one Ethernet type interface.

[0018] According to one embodiment, the concentrator circuit further includes at least one third interface configured to exchange data with a screen.

[0019] Another embodiment provides a system comprising: exactly a concentrator circuit as described above; and a memory connected to said at least one first interface, no computing microchip and accelerating microchip being connected to the concentrator circuit.

[0020] Another embodiment provides a system comprising: exactly a concentrator circuit as described above; and a computing microchip connected to at least a second port of the hub circuit by a high-speed link, with no other computing microchips and no accelerator microchips connected to the hub circuit.

[0021] Another embodiment provides a system comprising: exactly a first concentrator circuit as described above and a second concentrator circuit as described above, one of the first ports of the first concentrator circuit being connected to one of the first ports of the second concentrator circuit by a first high-speed link; a first computing microchip connected to at least a second port of the first concentrator circuit via a second high-speed link, with no other computing microchip and no accelerator microchip being connected to the first concentrator circuit; and a second computing microchip connected to at least a second port of the second concentrator circuit by a third high-speed link, with no other computing microchip and no accelerator microchip being connected to the second concentrator circuit.

[0022] Another embodiment provides a system comprising: exactly a first concentrator circuit as described above and a second concentrator circuit as described above, one of the first ports of the first concentrator circuit being connected to one of the first ports of the second concentrator circuit by a first high-speed link; a first computing microchip connected to at least a second port of the first concentrator circuit by a second high-speed link, with no other computing microchips and no accelerator microchips connected to the first concentrator circuit; and a first accelerator microchip connected to at least a third port of the second concentrator circuit by a third high-speed link, with no other accelerator microchip and no computing microchip being connected to the second concentrator circuit.

[0023] Another embodiment provides a system comprising: exactly a first concentrator circuit as described above, a second concentrator circuit as described above, a third concentrator circuit as described above, a fourth concentrator circuit as described above, one of the first ports of the first circuit being connected to one of the first ports of the second circuit by a first high-speed link, another of the first ports of the second circuit being connected to one of the first ports of the third circuit by a second high-speed link, another of the first ports of the third circuit being connected to one of the first ports of the fourth circuit by a third high-speed link, another of the first ports of the fourth circuit being connected to another of the first ports of the first circuit by a fourth high-speed link; a first computing microchip connected to at least a second port of the first concentrator circuit by a fifth high-speed link, with no other computing microchip and no accelerator microchip being connected to the first concentrator circuit; a second computing microchip connected to at least one second port of the second hub circuit by a sixth high-speed link, with no other computing microchips and no accelerator microchips being connected to the second concentrator circuit; a first accelerator microchip connected to at least a third port of the third concentrator circuit by a seventh high-speed link, with no other accelerator microchip and no computing microchip being connected to the third concentrator circuit; a second accelerator microchip connected to at least a third port of the fourth concentrator circuit by an eighth high-speed link, with no other accelerator microchip and no computing microchip being connected to the fourth concentrator circuit.

[0024] According to one embodiment, each accelerator microchip is configured to implement data processing for advanced pilot assistance systems at level L2+, L3 or L4. Brief description of the drawings

[0025] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0026] [Fig.1] represents, schematically and in block form, an example of an embodiment of a data processing and calculation system;

[0027] [Fig.2] represents, in more detail, an example of an embodiment of a basic component of the system of [Fig.1];

[0028] [Fig.3] represents, in more detail, an example of an embodiment of another component of the system of [Fig.1];

[0029] [Fig.4] represents, in more detail, an example of an embodiment of yet another component of the system of [Fig.1];

[0030] [Fig.5] represents, schematically and in block form, an example of an embodiment of a first data calculation and processing system;

[0031] [Fig.6] represents, schematically and in block form, an example of an embodiment of a second data processing and calculation system;

[0032] [Fig.7] represents, schematically and in block form, an example of an embodiment of a third data processing and calculation system;

[0033] [Fig.8] represents, schematically and in block form, an example of an embodiment of a fourth data processing and calculation system;

[0034] Figure 9 schematically represents, in block form, an example of an embodiment of a fifth data processing and computing system; and

[0035] Figure 10 represents a match between the first, second, third, fourth and fifth systems and the calculation and data processing requirements of a range of motor vehicles. Description of the implementation methods

[0036] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0037] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been represented and are detailed.

[0038] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements coupled together, this means that these two elements can be connected or linked through one or more other elements.

[0039] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0040] Unless otherwise specified, the expressions "approximately", "roughly", and "in the order of" mean within 10%, preferably within 5%.

[0041] To address the different computing and data processing needs of vehicles within the same vehicle range, a solution based on the hardware disaggregation of a range of computing and data processing systems is proposed here. Hardware disaggregation consists of dividing the hardware architecture of a circuit into several distinct functional elements manufactured separately as integrated circuits called microchips (or "chiplets"), and then rearranging and reassembling these microchips in a single package to form a component. US patent 11756150 presents the principle of hardware disaggregation into microchips.

[0042] However, in the patent mentioned above, the disaggregation is based on computing functionalities, and therefore does not address the needs of products, for example motor vehicles, related to the management of the many data streams, for example from many sensors, which serve as input data to the computing algorithms executed by the microchips.

[0043] US patent 11100028 describes a programmable component for data routing and data stream protocol transposition between microchips. However, this solution requires that the programmable component be associated with at least one microchip, which may not be desirable to address the needs in calculation and data processing for the lowest-end products in a product line, for example, the lowest-end vehicles in a vehicle line. Furthermore, even when this component is associated with one or more microchips, its limitation to data routing and data stream protocol transposition may not be sufficient to address the specific needs of products within a product line, for example, vehicles in a vehicle line.

[0044] Herein, for the design of computers based on disaggregation into microchips, a component, hereinafter called a communication hub, is proposed to overcome the disadvantages described above.

[0045] Fig. 1 represents schematically and in block form an example of an embodiment of a data processing and computing system based on disaggregation into microchips and at least one data concentrator.

[0046] The system 100 includes at least one communication hub 102 (block "COM HUB" in [Fig. 1]). In this example, the system 100 includes two hubs 102.

[0047] Each hub 102 is configured to be connected, in a modular manner, to several other integrated circuits of the system 100. Each hub 102 is further configured to exchange data streams, or, more simply put, data, with other integrated circuits, or elements, of the system 100.

[0048] The hub(s) 102 of system 100 are configured to direct data flows into system 100.

[0049] For example, each concentrator 102 is configured to acquire data or data streams from one or more sensors 104 (block "SENSOR" in [Fig.1]) of the system 100. In the example of [Fig.1], the system 100 includes only one sensor 104, although in practice a system 100 may include more.

[0050] For example, each concentrator 102 is configured to redirect received data or data streams to a microchip in the system 100 so that the data can be processed by the microchip. For example, a concentrator receiving data from a sensor can send it back, after simple encapsulation and without any calculations on the data, to another microchip or another concentrator in the system 100 so that the data can be processed, that is, so that calculations and processing can be performed on the data.

[0051] The system 100 can comprise two types of microchips, namely, computing microchips 106 (block "CHIPLET C" in [Fig. 1]), and accelerator microchips 108 (block "CHIPLET A" in [Fig. 1]). The microchips 106 are generic processing and computing circuits. Thus, each microchip 106 can address a wide variety of processing and computing tasks, relatively simple compared to those addressed by the microchips 108. For example, each microchip 106 is software programmable. By For example, each 10⁶ microchip is a generic processor. Conversely, 10⁸ microchips are integrated circuits specifically designed to address specific processing and computational needs, which are relatively complex compared to those addressed by 10⁶ microchips. In other words, unlike 10⁶ microchips, which implement generic computational and processing functions, 10⁸ microchips implement specific computational and processing functions that accelerate the implementation of certain specific system functionalities; 10⁸ chips are then, for example, called 10⁸ accelerator microchips.

[0052] By way of example, when the system 100 implements a computer for a motor vehicle, the microchips 108 of the system 100 can implement accelerating functions specific to the needs of autonomous driving, for example AD AS levels 3 and 4.

[0053] In the example of [Fig. 1], the system 100 comprises exactly two microchips 108 and exactly one microchip 106, although, in other examples, the system 100 may: - include any non-zero number of 10⁶ microchips and no 10⁸ microchips, - include any non-zero number of 10⁸ microchips and no 10⁶ microchips, - include any non-zero number of 10⁸ microchips and any non-zero number of 10⁶ microchips, or - do not understand any 106 and 108 microchips.

[0054] By way of further example, each concentrator 102 is further configured to ensure the collection of data or data streams into memory, for example for subsequent use of this data by the system 100. By way of example, each concentrator 102 is configured to control the recording of data or data streams, for example: - in a memory circuit or memory 110 (block "MEM" in [Fig.1]) associated, that is to say connected, to this hub 102, - in a memory 110 associated with another hub 102 to which this hub 102 is connected or coupled, - in a memory 110 associated, that is to say connected, to a microchip 106 or 108, whether this microchip 106 or 108 is associated, that is to say connected, to this concentrator 102 or simply coupled to this concentrator 102 via another concentrator 102.

[0055] For example, each hub 102 is associated with at least one memory 110. For example, each microchip 106 is associated with at least one memory 110, of preference to exactly one memory 110. For example, each microchip 108 is associated with at least one memory 110, preferably with exactly one memory 110.

[0056] By way of example, each memory 110 associated (i.e. connected) to a microchip 108 or 106 is of the Dual Data Rate (DDR) type, although each memory associated with a microchip 106 or 108 may also be of another type, for example a FLASH memory.

[0057] By way of example, each memory 110 associated (i.e. connected) to a circuit 102 is of the Dual Data Rate (DDR) or FLASH type, although other types of memory may be considered.

[0058] Thus, in system 100, there is a functional partitioning with, on the one hand, the management of communications by the concentrator(s) 102 of system 100, and, on the other hand, the management of calculations and processing by the microchips 106 and 108.

[0059] This partitioning in which the microchips 106 and 108 are not in charge of the redistribution of communications, or data, within the system 100 promotes the grouping of analog functions in the communication hub(s) 102 of the system 100. For example, the physical layers of the communication interfaces are grouped in the circuit(s) 102 of the system 100, so that the microchips 106 and 108 can be devoid of these physical layers in their communication interfaces.

[0060] To ensure the function of redistribution of data flows within the system 100, each hub 102 includes a network on chip (NoC) configured to redistribute, internally within the circuit 102, the data between the different constituent elements of the circuit 102, for example, in particular between the input / output ports and the interfaces of the hub.

[0061] In addition to managing the redistribution of communications or data transmissions within the system 100, between the different circuits that compose it, each hub 102 is preferably configured to implement protocol transpositions between data that it receives and corresponding data that it re-transmits to another element of the system.

[0062] Furthermore, in addition to managing the redistribution of data streams in system 100, with or without protocol transposition, preferably each concentrator 102 is configured to perform fusions of separate received data streams, without preprocessing the received data streams, and then to provide the resulting fused data stream to another element of system 100. In other words, each concentrator 102 is configured to implement early fusions of the separate data streams it receives. Each concentrator 102 is preferably further configured to perform processing, going beyond simple protocol transposition, on the separate data streams it receives, and then to merge the results of these preprocessing steps to provide a corresponding merged data stream. In other words, each 102 hub is configured to perform late fusion of the separate data streams it receives. The fact that each 102 hub is configured to perform both late and early fusion enables multimodal fusion of separate data streams, with multimodal fusion strategies being particularly advantageous for applications such as artificial intelligence.

[0063] By way of example, to implement the fusions described above, each circuit 102 includes at least one data processing circuit configured to implement calculations and processing on the data going beyond simple protocol transposition.

[0064] According to one embodiment, each concentrator 102 is configured to perform processing or calculations on data, for example, relatively simple processing or calculations compared to those performed by the accelerator microchips 108. Thus, a system 100 comprising only a single concentrator 102 and lacking microchips 106 and 108 can address relatively low computing and processing needs, for example, the computing and processing needs of the lowest-end vehicles in a vehicle range. In other words, a system 100 comprising only a single concentrator 102 and lacking microchips 106 and 108 exhibits a relatively low operational intensity, that is to say, the maximum number of operations per second that the system can process is relatively low compared to a system comprising microchips 106, 108, and / or other concentrators.As an example, the concentrator 102 has an operative current at least twice as low as that of each microchip 106, 108 that can be connected to this concentrator.

[0065] For example, to implement the data processing described above, each hub 102 includes at least one processing circuit chosen from the group comprising central processing units (CPU), graphics processing units (GPU), digital signal processors (DSP), and neural processing units (NPU).

[0066] In order to be able to be connected to one or more memory circuits 110, each hub 102 includes at least one memory interface ITm configured to exchange data with a memory circuit 110 when such a memory 110 is connected to this ITm interface.

[0067] By way of example, each ITm interface can be configured to be connected to DDR type memory. In this case, the interface is said to be of the DDR type. For example, a A DDR-type ITm interface is implemented by a memory controller for DDR memory. Alternatively, each ITm interface can be configured to connect to FLASH memory. In this case, the ITm interface is said to be of the FLASH type. For example, a FLASH-type ITm interface is implemented by a Low-Voltage Differential Signaling (LVDS) interface adapted to communicate with a FLASH memory circuit. As an example, when the concentrator includes several ITm interfaces, these interfaces can be of different types; for example, one ITm interface might be DDR while another is FLASH.

[0068] Each ITm interface of each hub 102 can be either connected to a memory circuit 110 or not connected to anything. However, it is preferable that at least one ITm interface of each hub 102 be connected to a memory 110.

[0069] Similarly, in order to be able to be connected to a memory circuit 110, each microchip 106 includes an ITmc memory interface configured to be connected to this memory 110. In the same way as the ITm interfaces, each ITmc interface can be of a given type, for example DDR or FLASH, for example different from that of another ITmc interface.

[0070] Each ITmc interface of each microchip 106 can either be connected to a memory circuit 110, or not be connected to anything.

[0071] In addition, in order to be able to be connected to a memory circuit 110, each microchip 108 includes an ITma memory interface configured to be connected to this memory 110. In the same way as the ITm and ITmc interfaces, each ITma interface can be of a given type, for example DDR or FLASH, for example different from that of another ITma interface.

[0072] Each ITma interface of each microchip 108 can either be connected to a memory circuit 110, or be not connected to anything.

[0073] In addition, each memory circuit 110 is preferably connected to only one element among a hub 102, a microchip 106 and a microchip 108, the memory 110 then being said to be associated with this element.

[0074] Although this is not the case in the example of [Fig.1], a microchip 108 may not be connected to any memory 110, and / or a microchip 106 may not be connected to any memory 110, and / or a hub may not be connected to any memory 110. However, a hub 102 will preferably be associated with a memory 110, for example a memory containing code executable by the hub 102, for example so as to program the hub 102.

[0075] The memories 110 of system 100 implement shared memory or distributed from system 100.

[0076] Furthermore, each 102 hub includes at least two physical PI ports. Each PI port is configured to exchange data with another 102 hub when the 102 hub containing that PI port is connected. In other words, each PI port is configured to exchange data with another 102 hub to which that PI port is connected. The connection of two 102 hubs via their respective PI ports is implemented by a high-speed link (HSL). By way of example, a high-speed link is configured to transfer at least 4 gigabytes per second, preferably at least 8 gigabytes per second, regardless of whether this HSL is a serial or parallel link. In [Fig.1], the high-speed links between two circuits 102 are referenced 112, the system 100 of the example in [Fig.1] comprising only one link 112.

[0077] Each hub 102, and, more particularly, each PI port of that hub 102, is configured, when connected to the PI port of another hub 102 by a link 112, for example another hub 102 belonging to the same system as that hub 102, so that the two hubs 102 and the memory or memories 110 to which these hubs are connected, are part of the same cache coherency memory area 116 (delimited by dashed lines in [Fig. 1]). This cache coherency memory area 116 is attached, or associated, with these two hubs 102. Preferably, all the hubs 102 of a system 100 are part of the same cache coherency memory area. The cache coherency memory area 116 is, for example, a memory distributed among several memories 110 that are part of the memory area 116.

[0078] Thus, each PI port of each hub 102 can be connected either to the PI port of another hub 102 via a link 112, or be connected to nothing.

[0079] Each hub 102 further includes at least one interface, for example an ITs interface, configured to exchange data with a sensor 104 when connected to that sensor 104. The connection of the ITs interface to a sensor is made, for example, via a link 118 that is not a high-speed link. By way of example, each hub 102 may include at least one ITs interface of the Camera Serial Interface (CSI) type. Of course, each ITs interface of each hub 102 may be of a type other than the CSL type.

[0080] Each hub 102 includes at least one physical port P2. Each port P2 is configured to exchange data with a computing microchip 106 when that port P2 is connected to that microchip 106. The connection of a microchip 106 to the port P2 of a hub 102 is implemented by a high-speed link (HSL). [Fig.1], the high-speed links between two circuits 102 and 106 are referenced 120, the system 100 of the example in [Fig.1] comprising only one link 120. As an example, each microchip 106 includes a physical port P2c similar to the port P2 of the hub 102 to which this microchip 106 is connected by a corresponding link 120 linking these ports P2 and P2c together.

[0081] Each hub 102, and more particularly each hub 102 port P2, is configured, when connected to a microchip 106 by a link 120, so that the microchip 106 and any memory 110 to which the microchip 106 is connected are part of the same cache-coherent memory area 116 as the hub 102 to which the microchip 106 is connected. By way of example, this cache coherence within the shared memory area 116 is implemented by each of the hubs 102 to which this area 116 is attached.

[0082] Each P2 port of each hub 102 can either be connected to a computing microchip 106 via a link 120, or be connected to nothing.

[0083] Each hub 102 includes at least one physical port P3. Each port P3 is configured to exchange data with an accelerator microchip 108 when that port P3 is connected to that microchip 108. The connection of a microchip 108 to the port P3 of a hub 102 is implemented by a high-speed link (HSL). In [Fig. 1], the high-speed links between two circuits 102 and 108 are referenced as 122, the system 100 of the example in [Fig. 1] comprising only two links 122. By way of example, each microchip 108 includes a physical port P3a similar to the port P3 of the hub 102 to which that microchip 108 is connected by a corresponding link 122 connecting these ports P3 and P3a together.

[0084] Each hub 102, and, more particularly, each hub 102 port P3, is configured, when connected to a microchip 108 by a link 122, so that the microchip 108 and any memory 110 to which the microchip 108 is connected are part of an input / output coherent memory area 124 with respect to the cache coherent memory area 116 to which the hub 102 connected to that microchip 108 belongs. In [Fig. 1], in the example system 100 shown, two microchips 108 are connected to two respective hubs 102, the two hubs 102 being part of the cache coherent area 116, and the two microchips 108 each being part of a respective memory area 124 (delimited by dashed lines in [Fig. 1]) with I / O coherence input / output relative to memory area 116.

[0085] By way of example, this input / output coherence between a memory area 124 to which a microchip 108 belongs and the cache coherence memory area 116 to which the hub 102 connected to this microchip 108 belongs is implemented by the hub(s) 102 of the system 100.

[0086] Each P3 port of each hub 102 can either be connected to an accelerator microchip 108 via a link 122, or be connected to nothing.

[0087] Although not illustrated in the example system 100 of [Fig. 1], in addition to the physical ports PI, P2 and P3 and the interfaces ITm and ITs, each hub may also include: - at least one Ethernet-type ITe interface, for example intended to be connected to a modem, i.e., a modulator / demodulator circuit, or for example intended to be connected to a LiDAR (Light Detection and Ranging) sensor. An ITe interface can therefore, like ITs interfaces, be used to connect a sensor 104 to a concentrator 102; and / or - at least one ITd interface intended to be connected to a screen, for example a low-voltage differential signaling (LVDS) type interface.

[0088] Furthermore, although not illustrated in the example system 100 of [Fig. 1], in addition to the physical ports, interfaces, its processing circuit(s), and its network-on-chip, each circuit 102 may include a Direct Memory Access (DMA) circuit. This circuit is, for example, configured to handle data transfers, for example, primarily data from a sensor 104 connected to an ITs or ITe interface of the hub 102.

[0089] Preferably, when a system 100 includes several networked concentrators 102, these concentrators are identical to each other.

[0090] By way of example, ports P3 and P3a are each configured to implement a "CXL.mem", "CXL.io" or "PCIe" protocol when a P3 port is connected to a P3c port via a link 122, i.e. during a data exchange between a hub 102 and an accelerator microchip 108.

[0091] By way of example, ports P2 and P2c are each configured to implement a "CXL.cache" and "CXL.mem" protocol when a port P2 is connected to a port P2c via a link 120, i.e. during a data exchange between a hub 102 and a computing microchip 106.

[0092] As an example, each PI port is configured to implement a "CXL.mem" and "CXL.cache" or "AXI stream" protocol when connected, via a 112 link, to the PI port of another 102 hub, i.e. during a data exchange with that other hub.

[0093] Figure [Fig.2] represents, in more detail, an example of an embodiment of a circuit 102 of the system of [Fig.1].

[0094] Circuit 102 (block "COM HUB in [Fig.2]) comprises, as indicated above- above in relation to [Fig. 1]: - at least two PI ports, for example exactly two PI ports in the example of [Fig.2]; - at least one P2 port, for example exactly one P2 port in the example of [Fig.2] - at least one P3 port, for example exactly one P3 port in the example of [Fig.2] - at least one IT interface, for example exactly five IT interfaces in the example of [Fig.2], for example all of type CSI; - at least one ITm interface, for example exactly two ITm interfaces in the example of [Fig.2], for example one ITm interface of type FLASH and one ITm interface of type DDR; - at least one processing unit, represented as a PU block in [Fig.2]; and - a network-on-a-chip (NOC).

[0095] In the example of [Fig.2], the circuit 102 further includes a direct memory access circuit (block "DMA" in [Fig.2]).

[0096] Still in the example of [Fig.2], the circuit 102 includes at least one ITe interface of type Ethernet, for example exactly three ITe interfaces in the example of [Fig.2].

[0097] Still in this example, the circuit 102 includes at least one ITd interface, for example exactly one ITd interface in the example of [Fig.2], for example of the low-voltage differential transmission type (LVDS from the English "Low-Voltage Dif-ferential Signaling").

[0098] Figure 3 represents, in more detail, an example of an embodiment of a computing microchip 106 of system 100 of Figure 1.

[0099] The microchip 106 (block "CHIPLET C" in [Fig. 3]) includes at least one ITmc memory interface, preferably a single ITmc memory interface. For example, this ITmc interface is of the DDR type, and is then configured to be connected to a DDR type memory 110.

[0100] The microchip 106 further includes a physical port P2c for connection, via a link 120, to the port P2 of a hub 102.

[0101] Finally, the microchip 106 comprises one or more processing units, represented by a single PU block in [Fig. 3]. For example, the processing unit(s) of a microchip 106 are chosen from the group comprising CPUs, GPUs, and NPUs. For example, since the microchip 106 is intended to implement generic functionalities as opposed to the specific functionalities of the microchips 108, the microchip 106 does not include a DSP.

[0102] Preferably, all microchips 106 of a system 100 have an architecture similar or identical to that of the microchip 106 described in relation to [Fig.3].

[0103] Figure 4 represents, in more detail, an example of an embodiment of an accelerator microchip 108 of system 100 of Figure 1.

[0104] The microchip 108 (block "CHIPLET A" in [Fig. 4]) includes at least one ITma memory interface, preferably a single ITma memory interface. For example, this ITma interface is of the DDR type, and is then configured to be connected to a DDR type memory 110.

[0105] The microchip 108 further includes a physical port P3a for connection, via a link 122, to the port P3 of a hub 102.

[0106] Finally, the microchip 108 comprises one or more processing units, represented by a single ACC block in [Fig. 4]. For example, the processing unit(s) of a microchip 108 are chosen from the group comprising CPUs, GPUs, DSPs, and NPUs. For example, since the microchip 108 is intended to implement specific functionalities compared to the generic functionalities of microchips 106, the microchip 108 comprises a DSP and / or a GPU.

[0107] Preferably, all microchips 108 of a system 100 have an architecture similar or identical to that of the microchip 108 described in relation to [Fig.4].

[0108] According to one embodiment, the processing unit(s) PUs of a microchip 108 are configured to implement assisted or autonomous driving functionalities.

[0109] Various examples of embodiments of systems built from at least one concentrator 102, and, when application requirements so require, from at least one microchip 106 and / or at least one microchip 108, will now be described.

[0110] Of course, these examples of systems are not limiting, and a person skilled in the art will be able to foresee many other examples of systems or computers obtained by assembling, that is to say by re-aggregating, one or more concentrators 102 with one or more microchips 106 and / or 108.

[0111] Fig. 5 represents schematically and in block form an example of an embodiment of a 500 data processing and calculation system.

[0112] Compared to system 100, system 500 comprises only one circuit 102, and is devoid of microchip 106 and microchip 108.

[0113] Put another way, the system 500 comprises exactly one circuit 102, and no microchip 106 or 108 is connected to this circuit 102.

[0114] A memory circuit 110 is connected to the ITm interface of the circuit 102.

[0115] Circuit 102, and the memory 110 associated with it, belong to an area cache coherence memory 116.

[0116] Because circuit 102 includes at least one processing unit, system 500 can address processing and computing needs even when no microchip 106, 108 is connected to circuit 102.

[0117] Fig. 6 represents schematically and in block form an example of an embodiment of a 600 data processing and calculation system.

[0118] The 600 system includes, like the 500 system, exactly one circuit 102 and a memory circuit 110 associated with this circuit 102.

[0119] However, compared to system 500, a microchip 106 is connected, via a link 120, to port P2 of circuit 102. For example, link 120 connects port P2 of circuit 102 to port P2c of microchip 106.

[0120] In this example, a memory circuit 110 is connected to the ITmc interface of the microchip 106, this memory being associated with the microchip 106.

[0121] The hub 102 and its associated memory 110 as well as the microchip 106 and its associated memory 110 are part of the same cache-coherent memory area 116.

[0122] Fig. 7 represents schematically and in block form an example of an embodiment of a 700 data processing and calculation system.

[0123] Compared to systems 500 and 600, system 700 comprises exactly two concentrator circuits 102, exactly one microchip 106 and exactly one microchip 108.

[0124] The two circuits 102 are connected to each other. For example, a PI port of one of the circuits 102 is connected to a PI port of the other circuit 102, via a link 112.

[0125] By way of example, each circuit 102 is associated with a corresponding memory circuit 110. For example, each circuit 102 has an ITm interface connected to the memory circuit 110 to which that circuit 102 is associated.

[0126] A microchip 106 is connected, via a link 120, to port P2 of one of the first two circuits 102, the one on the left in [Fig.7]. For example, link 120 connects port P2 of the first circuit 102 to port P2c of the microchip 106.

[0127] In this example, a memory circuit 110 is connected to the ITmc interface of the microchip 106, this memory being associated with the microchip 106.

[0128] In addition, a microchip 108 is connected, via a link 122, to port P3 of the second of the two circuits 102, the one on the right in [Fig.7]. For example, link 122 connects port P3 of the second circuit 102 to port P3a of the microchip 108.

[0129] In this example, a memory circuit 110 is connected to the ITma interface of the microchip 108, this memory being associated with the microchip 108.

[0130] The two hubs 102 and their associated memories 110 as well as the microchip 106 and its associated memory 110 are part of the same cache coherency memory area 116.

[0131] On the other hand, the microchip 108 and its associated memory 110 are part of another memory area 124, this other memory area 124 being input / output coherent by report to memory area 116.

[0132] Fig. 8 represents schematically and in block form an example of an embodiment of a 800 data processing and calculation system.

[0133] Like system 700, system 800 comprises exactly two concentrator circuits 102. On the other hand, unlike system 700, system 800 comprises exactly two microchips 106 and is devoid of microchip 108.

[0134] The two circuits 102 are connected to each other. For example, a PI port of one of the circuits 102 is connected to a PI port of the other circuit 102, via a link 112.

[0135] By way of example, each circuit 102 is associated with a corresponding memory circuit 110. For example, each circuit 102 has an ITm interface connected to the memory circuit 110 to which that circuit 102 is associated.

[0136] A first microchip 106 is connected, via a link 120, to the port P2 of a first of the two circuits 102. For example, the link 120 connects the port P2 of the first circuit 102 to the port P2c of the first microchip 106.

[0137] In this example, a memory circuit 110 is connected to the ITmc interface of the first microchip 106, this memory being associated with the microchip 106.

[0138] In addition, a second microchip 106 is connected, via a link 120, to the port P2 of the second of the two circuits 102. For example, the link 120 connects the port P2 of the second circuit 102 to the port P2c of the second microchip 106.

[0139] In this example, a memory circuit 110 is connected to the ITmc interface of the second microchip 106, this memory being associated with the microchip 106.

[0140] The two hubs 102 and their associated memories 110 as well as the two microchips 106 and their associated memories 110 are part of the same cache coherency memory area 116.

[0141] Fig. 9 represents schematically and in block form an example of an embodiment of a 900 data processing and calculation system.

[0142] The system 900 comprises exactly four circuits 102, namely a first concentrator 102 (top left in [Fig.9]), a second concentrator 102 (top right in [Fig.9]), a third concentrator 102 (bottom right in [Fig.9]) and a fourth concentrator 102 (bottom left in [Fig.9]).

[0143] In this example, each of the concentrators 102 is associated with a corresponding memory circuit 110, the memory circuit 110 associated with a concentrator 102 being connected to an ITm interface of that concentrator 102.

[0144] The circuits 102 are coupled to each other. For example, the circuits 102 form a two-dimensional network. For example, a PI port of the first circuit 102 is connected to a PI port of the second circuit 102 by a first link 112, another PI port of the second circuit 102 is connected to a PI port of the third circuit 102 by a second link 112, another PI port of the third circuit 102 is connected to a port PI of the fourth circuit by a third link 112, and another PI port of the fourth circuit is connected to another PI port of the first circuit 102 by a fourth link 112.

[0145] Furthermore, the system 900 comprises exactly two microchips 106. A first microchip 106 is connected, via a link 120, to port P2 of the third circuit 102. For example, link 120 connects port P2 of the third circuit 102 to port P2c of the first microchip 106. In this example, a memory circuit 110 is connected to the ITmc interface of the first microchip 106, this memory being associated with the microchip 106. The second microchip 106 is connected, via another link 120, to port P2 of the fourth circuit 102. For example, this other link 120 connects port P2 of the fourth circuit 102 to port P2c of the second microchip 106. In this example, a memory circuit 110 is connected to the ITmc interface of the second microchip 106, this memory being associated to the 106 microchip.

[0146] Furthermore, the system 900 comprises exactly two microchips 108. A first microchip 108 is connected, via a link 122, to port P3 of the first circuit 102. For example, link 122 connects port P3 of the first circuit 102 to port P3a of the first microchip 108. In this example, a memory circuit 110 is connected to the ITma interface of the first microchip 108, this memory being associated with the microchip 108. The second microchip 108 is connected, via another link 122, to port P3 of the second circuit 102. For example, this other link 122 connects port P3 of the second circuit 102 to port P3a of the second microchip 108. In this example, a memory circuit 110 is connected to the ITma interface of the second microchip 108, this memory being associated to the microchip 108.

[0147] The two hubs 102 and their associated memories 110 as well as the two microchips 106 and their associated memories 110 are part of the same cache-coherent memory area 116.

[0148] On the other hand, the two microchips 108 and their associated memories 110 are each part of another memory area 124, this other memory area 124 being input / output coherent with respect to the memory area 116.

[0149] Fig. 10 illustrates, in tabular form, the suitability of the systems in Figures 5 to 9 for the computing and data processing needs of a range of motor vehicles.

[0150] More specifically, the x-axis of the table, labeled MEDIA in [Fig. 10], represents the calculation and data processing requirements as a function of the multimedia experience offered by a vehicle. These requirements are lowest when the vehicle offers a basic multimedia experience ("BASIC, MID" in [Fig. 10]), highest when the vehicle offers a medium multimedia experience ("HIGH" in [Fig. 10]), and highest when the vehicle offers a high-quality multimedia experience. high multimedia ("PREMIUM" in [Fig. 10]).

[0151] In addition, the ordinate axis of the table, referenced AD AS in [Fig.10], represents the level of the pilot assistance system, AD AS, with only levels L2, L2+, L3 and L4 being represented in [Fig. 10], with levels L3 and L4 being grouped into a single group L3, L4.

[0152] For a motor vehicle offering a BASIC, MID multimedia experience with an AD AS L2 level, i.e. a low-end vehicle, a single 102 circuit can meet the computing and data processing needs of the vehicle, and a 500 system can be used as a computer for this vehicle.

[0153] For a motor vehicle with the same BASIC, MID infotainment system but with ADAS L2+ capability, the computing and data processing requirements increase due to the higher ADAS level, and a microchip 106 is added to meet this increased demand. System 600 thus addresses the application requirements of this vehicle. For example, System 600's microchip 106 is configured to handle calculations related to ADAS L2+ capability.

[0154] In addition, the 106 microchip of the 600 system is sufficiently generic to allow addressing the computing and data processing needs of a vehicle having a HIGH level of infotainment and an ADAS L2, or even L2+ level.

[0155] On the other hand, for a vehicle with a BASIC, MID or HIGH infotainment level, with an ADAS L3 or L4 level, the computing and processing requirements specific to ADAS L3 and L4 levels require the addition of a microchip 108 and a concentrator 102. Thus, the 700 system makes it possible to address the computing and data processing requirements of vehicles with an ADAS L3 or L4 level, and a BASIC, MID or HIGH infotainment level.

[0156] For a vehicle with a PREMIUM infotainment system, the computing and data processing requirements increase compared to HIGH and BASIC, MID infotainment systems, particularly due to screen management and the increased number of infotainment devices. However, the computing and data processing requirements remain relatively generic as long as the vehicle has an ADAS L2+ or L2 level. These computing and data processing requirements are then addressed by a system 800 with two concentrators 102 to provide a sufficient number of interfaces for the infotainment devices, each associated with a microchip 106 to perform the computing and data processing related to this infotainment system level and the ADAS L2 or L2+ level.

[0157] Finally, for a vehicle with ADAS L3 or L4 level and a PREMIUM infotainment system, the use of four 102 circuits allows for the management of the large amount of data to be processed and redistributed within the system; the use of two mi The 106 microchip addresses the generic computing and data processing needs associated with the PREMIUM infotainment level, while the use of two 108 microchips addresses the specific computing and data processing needs associated with AD AS L3 or L4. The 900 system therefore meets the needs of a vehicle in this range.

[0158] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to those skilled in the art. In particular, although the advantages of the 102 circuit, and more generally of computing and data processing systems, have been presented in relation to the automotive field, the 102 circuit and computing and data processing systems obtained by modular construction from at least one 102 circuit can be used, with the same advantages, in other fields such as avionics, drones, robotics, etc.Furthermore, although the case described above describes where, when two 102 hubs belonging to the same system or computer are connected to each other via their PI ports and a 112 link, the two hubs then belong to the same cache-coherent memory area, it is also possible, as an example, to connect two systems or computers together via a 112 link between the PI port of a hub in the first system and the PI port of a hub in the second system. In this latter case, the two hubs preferably belong to two different cache-coherent memory areas, and, for example, input / output coherence is implemented between the two hubs, i.e., between the two systems. In other words, a PI port configured to implement cache coherence is preferably also configured to allow the implementation of input / output coherence, although the reverse is not true.Connecting several systems together allows, for example, the implementation of a redundant system.

[0159] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.

Claims

Demands

1. Communication hub circuit (102) comprising: at least two first physical ports (PI) each configured to exchange data with another communication hub circuit (102) that is part of the same cache-coherent memory area (116) as said hub circuit (102), when said first port is connected via a high-speed link (112) to that other communication hub circuit; at least one second physical port (P2) configured to exchange data with a computing microchip (106) forming part of said same cache-coherent memory area (116) when said at least one second physical port is connected via a high-speed link (120) to this computing microchip; at least one third physical port (P3) configured to exchange data with an accelerator microchip (108) forming part of an input / output coherent memory area (124) with said same cache coherent memory area (116), when said at least one third physical port is connected via a high-speed link (122) to this accelerator microchip; at least one first interface (ITm) configured to exchange data with a memory circuit (110) forming part of said same cache-coherent memory area (116) when said at least one first interface is connected to this memory circuit; at least one second interface (ITs, ITe) configured to exchange data with a sensor (104); at least one processing unit (PU) configured to implement data processing; at least one network-on-chip (NOC) configured to transfer data between elements of the communication hub circuit (102), said elements comprising said at least two first ports (PI), said at least one second port (P2), said at least one third port (P3), said at least one processing circuit (PUs) and said at least one first interface (ITm).

2. Hub circuit according to claim 1, wherein: said at least two first physical ports (PIs) are each configured to implement a CXL.mem and CXL.cache or AXI stream protocol when exchanging data with the other circuit communication hub (102); said at least a second physical port (P2) is configured to implement a CXL.cache and CXL.mem protocol when exchanging data with the computing microchip (106); and said at least a third physical port (P3) is configured to implement a CXL.mem, CXL.io or PCIe protocol when exchanging data with the accelerator microchip (108).

3. Hub circuit according to claim 1 or 2, wherein the hub circuit (102) is configured to merge several data streams that it receives without performing any processing on said several streams.

4. Hub circuit according to any one of claims 1 to 3, wherein the hub circuit (102) is configured to perform processing on separate data streams it receives and then to merge the results of this processing.

5. Hub circuit according to any one of claims 1 to 4, wherein the hub circuit (102) is configured to implement cache coherency in said same cache-coherent memory area (116).

6. Hub circuit according to any one of claims 1 to 5, wherein the hub circuit (102) is configured to implement input / output coherence between said same cache-coherent memory area (116) and another memory area (124) to which an accelerator microchip (108) belongs.

7. Hub circuit according to any one of claims 1 to 6, wherein said at least one first interface (ITm) comprises an interface for DDR type memory and / or an interface for FLASH type memory.

8. Hub circuit according to any one of claims 1 to 7, wherein the hub circuit (102) further comprises a direct memory access (DMA) circuit.

9. Hub circuit according to any one of claims 1 to 8, wherein said at least a second interface comprises at least one CSI-type interface and / or at least one Ethernet-type interface.

10. Hub circuit according to any one of claims 1 to 9, wherein the hub circuit (102) further comprises at least one third interface (ITd) configured to exchange data with a screen.

11. System (500) comprising: exactly a concentrator circuit (102) according to any one of claims 1 to 10; and a memory (110) connected to said at least one first interface (ITm), no computing microchip (106) and accelerator microchip (108) being connected to the concentrator circuit.

12. System (600) comprising: exactly one concentrator circuit (102) according to any one of claims 1 to 10; and a computing microchip (106) connected to said at least one second port (P2) of the concentrator circuit by a high-speed link (120), no other computing microchip (106) and no accelerator microchip (108) being connected to the concentrator circuit.

13. System (800) comprising: exactly a first concentrator circuit (102) according to any one of claims 1 to 10 and a second concentrator circuit (102) according to any one of claims 1 to 10, one of the first ports (P1) of the first concentrator circuit being connected to one of the first ports (P1) of the second concentrator circuit by a first high-speed link (112); a first computing microchip (106) connected to said at least one second port (P2) of the first concentrator circuit by a second high-speed link (120), no other computing microchip (106) and no accelerator microchip (108) being connected to the first concentrator circuit;and a second computing microchip (106) connected to said at least a second port (P2) of the second concentrator circuit by a third high-speed link (120), no other computing microchip (106) and no accelerator microchip (108) being connected to the second concentrator circuit.;

14. System (700) comprising: exactly a first concentrator circuit (102) according to any one of claims 1 to 10 and a second concentrator circuit (102) according to any one of claims 1 to 10, one of the first ports (PI) of the first concentrator circuit being connected to one of the first ports (PI) of the second concentrator circuit by a first high-speed link (112); a first computing microchip (106) connected to said at least one second port (P2) of the first concentrator circuit (120) by a second high-speed link (120), no other computing microchip (106) and no accelerator microchip (108) being connected to the first concentrator circuit; and a first accelerator microchip (108) connected to at least a third port (P3) of the second concentrator circuit (102) by a third high-speed link (122), no other accelerator microchip (108) and no computing microchip (106) being connected to the second concentrator circuit.

15. System (900) comprising: exactly a first concentrator circuit (102) according to any one of claims 1 to 10, a second concentrator circuit (102) according to any one of claims 1 to 10, a third concentrator circuit (102) according to any one of claims 1 to 10, a fourth concentrator circuit (102) according to any one of claims 1 to 10, one of the first ports (PI) of the first circuit being connected to one of the first ports (PI) of the second circuit by a first high-speed link (112), another of the first ports (PI) of the second circuit being connected to one of the first ports (PI) of the third circuit by a second high-speed link (112), another of the first ports (PI) of the third circuit being connected to one of the first ports (PI) of the fourth circuit by a third high-speed link (112),another of the first ports (PI) of the fourth circuit being connected to another of the first ports (PI) of the first circuit by a fourth high-speed link (112); a first computing microchip (106) connected to at least a second port (P2) of the first concentrator circuit by a fifth high-speed link (120), no other computing microchip (106) and no accelerator microchip (108) being connected to the first concentrator circuit; a second computing microchip (106) connected to at least a second port (P2) of the second concentrator circuit by a sixth high-speed link (120), no other computing microchip (106) and no accelerator microchip (108) being connected to the second concentrator circuit; a first accelerator microchip (108) connected to at least one third port (P3) of the third hub circuit by a seventh high-speed link (122), no other accelerator microchip (108) and no computing microchip (106) being connected to the third concentrator circuit; a second accelerator microchip (108) connected to at least a third port (P3) of the fourth concentrator circuit by an eighth high-speed link (122), no other accelerator microchip (108) and no computing microchip (106) being connected to the fourth concentrator circuit.

16. System according to claim 14 or 15, wherein each accelerator microchip (108) is configured to implement data processing for advanced L2+, L3 or L4 level pilot assistance systems.

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