Memristor matrix display device and methods of implementing the device

Abstract

A memristor matrix display device and methods for implementing the device are provided. The device comprises a plurality of pixels (P) each comprising a memory (MEM) for storing a binary word, the memory (MEM) comprising a plurality of memristors (RMx) each for storing a bit of the binary word. Figure for abstract: Fig. 1

Description

Title of the invention: Membrane matrix display device and methods of implementing the device

[0001] The invention relates to a matrix display device on an active matrix screen and methods for implementing the device. This type of screen has been widely developed in recent years, particularly for liquid crystal type screens known by their English abbreviation: LCD. More recently, other types of screens using light-emitting diodes have been developed, particularly using organic diodes or micro-diodes, known by their English abbreviation: OLED, respectively pLED.

[0002] In the case of a light-emitting diode screen, each pixel of the matrix contains a storage component and a transistor which makes it possible to control the power supply of the light-emitting diode as a function of the useful signal stored in the storage component.

[0003] It is known to drive the display in an analog manner. More precisely, once per frame, each pixel receives a voltage representative of the brightness that the pixel must display. This voltage is stored in the storage component, for example a capacitor. For a light-emitting diode pixel, the voltage is applied to the transistor configured as a follower to power the light-emitting diode proportionally to the stored voltage.

[0004] To store the information in the storage components, the display device comprises a vertical register which selects, one line after the other, the different lines of the matrix and a horizontal register where digital / analog converters are located, one per column, which generate the analog values ​​to be stored in each storage component.

[0005] This storage operation is performed sequentially, where each line is addressed and the corresponding pixels are refreshed once per frame.

[0006] The main advantage is the low number of components per pixel, which allows for a smaller size. Power consumption is also reduced. Power consumption is essentially the current consumed by the light-emitting diode of the pixel in question.

[0007] This architecture has certain drawbacks, such as leaks on the capacitors which generate attenuation and flickering phenomena of the image. Other defects to be mentioned are the capacitive couplings in the pixel, as well as the non-linearities and the need to compensate for the non-uniformities due to the shift of the threshold voltage of the transistor.

[0008] To overcome certain defects, it is possible to control the light-emitting diodes using pulse width modulation, known by its English abbreviation: PWM for "Pulse Width Modulation". The light-emitting diode is switched on or off for a predetermined duration. The inertia of the eye allows the user to see an average brightness equal to the ratio between the duration of lighting of the light-emitting diode and the duration of a frame. This control mode makes it possible to overcome the offset of the threshold voltage of the transistor and the non-linearity of response of the light-emitting diode.

[0009] Driving light-emitting diodes using pulse width modulation also makes it possible to do without a storage component in each of the pixels, but this requires very high frequency switching, resulting in an increase in power consumption. Patent EP3079142 B1 filed in the name of the applicant makes it possible to reduce the frequency by proposing a pulse width proportional to the weight of the bit addressed to each pixel. This technique is known as "Binary Coded Modulation" or BCM in the English literature for "Binary Coded Modulation". In the cited patent, the addressing is unconventional. However, the refresh frequency still remains very high.

[0010] Another solution for maintaining slower addressing of the various pixels consists of implementing pixels each having a digital storage component and a pulse width modulation controller. The storage component may comprise flip-flops connected in series or a static random access memory known by its English abbreviation: SRAM for: "Static Random Access Memory". The main drawback of this type of solution is the complexity of each of the pixels in which the storage component must have a capacity of the order of 10 bits, complexity to which are added the gates of the pulse width modulation controller.

[0011] The invention aims to overcome all or part of the problems cited above by proposing a display device controlled by pulse width modulation and each pixel of which comprises a memory making it possible to store a binary word representative of the brightness to be displayed, the memory being produced from simple components such as memristors.

[0012] To this end, the invention relates to a matrix display device comprising a matrix of pixels organized in rows and columns, each pixel comprising: - an elementary display component, a first electronic switch making it possible to control the elementary display component between two states called: on and off, - a memory for storing a binary word for controlling the elementary display component to display a brightness corresponding to the binary word, the memory comprising several memristors each intended to store a bit of the binary word and connected to a node of the pixel common to all memristors, the node of the pixel forming a control of the first electronic switch, - a resistor connected between the pixel node and a reference voltage, - a second electronic switch connected in parallel with the resistor and allowing, in an on state, to modify the resistance values ​​of the memristors while keeping the elementary display component off and in a blocked state to turn on the elementary component according to the binary word.

[0013] Advantageously, the resistance is a second memristor.

[0014] Advantageously, the device further comprises means for applying to the node of the pixel a voltage configured to initialize the first memristors.

[0015] In a variant of the invention, the memristors are each connected between a column conductor and the node of the pixel common to all memristors.

[0016] In another variant of the invention, the device further comprises a third electronic switch connected in series with each of the memristors, for each row of pixels the third electronic switches are each controlled by a column conductor.

[0017] In another variant compatible with the first two variants, each pixel comprises a memory element arranged at the node, the memristors being connected to the node via a latch making it possible to load the memory element with the value of the bit to be displayed and to maintain this value for a duration depending on the weight of the bit.

[0018] The device may further comprise: - a circuit for reading the bits of a current binary word stored in each memory, - a circuit for comparing the bits of the current binary word with the bits of a new binary word to replace the current binary word, - a circuit for writing the new binary word configured to be deactivated if for a given bit its value in the new binary word is equal to its value in the current binary word and to be activated if for a given bit its value in the new binary word is different from its value in the current binary word.

[0019] The invention also relates to a method for implementing a matrix display device as summarized above, in which, during an operation of storing a binary word in the memory, a voltage is applied to the elementary display component keeping it in its off state for the two states of the first electronic switch.

[0020] The invention also relates to another method for implementing a matrix display device as summarized above in which, from an operation of storing a binary word in the memory to the following storage operation, only the memristors whose associated bits have changed value receive a voltage making it possible to modify their resistance value, the memristors whose associated bits have not changed value receive a voltage not making it possible to modify their resistance value.

[0021] The invention also relates to a method for implementing a matrix display device according to the invention and in which the memristors are each connected between a column conductor and the node of the pixel common to all memristors, in this method, to store a binary word in the memory, the following steps are successively carried out, for each of the lines of pixels: - closing of the second electronic switches, - application to each column conductor of a voltage corresponding to the value of the bit to be stored in the memristor connected to the corresponding column conductor, - opening of the second electronic switches, these steps are repeated for each line.

[0022] The invention also relates to a method for implementing a matrix display device according to the invention and further comprising a third electronic switch connected in series with each of the memristors, in this method, to store a binary word in the memory, the following steps are successively carried out for each of the lines of pixels: - closing of the second electronic switches, - selective closing of the third electronic switches and application of the value of the bit to be stored to the different memristors, - opening of the second electronic switches, these steps are repeated for each line.

[0023] Advantageously, for the last method cited, all the third electronic switches associated with memristors which are to store the same bit value are simultaneously closed.

[0024] The invention also relates to a method for implementing a matrix display device according to the invention, in this method, to display on the elementary display component a brightness corresponding to the binary word stored in the memory, the following steps are successively carried out simultaneously for all the lines of pixels: - opening of electronic switches, - application of voltage pulses successively to each memristor, - closing of electronic switches.

[0025] In this latter method applied to a matrix display device according to the invention and comprising the memory element, the slots are pulses whose duration is independent of the weight of the bit concerned and the pulses are separated by a duration which is a function of the weight of the bit stored in the corresponding memristor.

[0026] Advantageously, in this latter method, the storage of a binary word in the memory occurs between the pulses.

[0027] Advantageously, in this latter method applied to the display device not comprising a memory element, the voltage pulses have a duration which is a function of the weight of the bit stored in the corresponding memristor.

[0028] The invention will be better understood and other advantages will appear on reading the detailed description of an embodiment given as an example, a description illustrated by the attached drawing in which:

[0029] [Fig.l] represents an example of a matrix display device according to the invention whose pixels comprise a memristor-based memory;

[0030] [Fig.2] represents a variant of the display device integrating means allowing a memory initialization cycle;

[0031] Figures 3 and 4 illustrate respectively for the display device, writing in the memory and displaying from a binary word stored in the memory;

[0032] [Fig.5] represents a variant of the display device making it possible to reduce the electrical consumption of the memristors by placing an electronic switch in series with each of them;

[0033] [Fig.6] represents a variant of the display device making it possible to further reduce the electrical consumption of the memristors by reducing the reading time of the state of each memristor;

[0034] [Fig.7] represents a variant of the display device of [Fig.6] making it possible to stabilize the voltage levels applied to an electronic switch allowing the switching on and off of the elementary display component of each pixel of the device;

[0035] [Fig.8] represents a variant of the device making it possible to limit the number of writings in the memory of each pixel.

[0036] For the sake of clarity, the same elements will bear the same references in the different figures.

[0037] The invention implements memristors, which it is interesting to introduce. A memristor is a passive component whose electrical resistance value changes permanently when an adequate electrical current passes through it. The memristor makes it possible to permanently store a resistance value. Among the memristors, we can cite resistive random access memories known by their acronym RRAM for "Resistive Random Access Memory". An article by Zahoor et al. published in 2020 in the journal Nanoscale Research Letters allows you to familiarize yourself with this type of component. The title of the article is: "Resistive Random Access Memory (RRAM): an Overview of Materials, Switching Mechanism, Performance, Multilevel Cell (mlc) Storage, Modeling, and Applications".

[0038] Other types of memristors have also been developed, such as magnetoresistive or phase-change memories. These different types of memristors have very promising characteristics, particularly in terms of speed and energy consumption. All of these memristor technologies can be implemented within the framework of the invention.

[0039] The applicant has developed an oxide-based memristor technology in which it is possible to switch the resistance between two values ​​having a difference of more than two decades. This technology is also known by the English acronym: OxRAM for "Oxide-based Resistive Random Access Memory". In practice, an OxRAM type memristor is a two-terminal component. After applying a positive voltage between its terminals of the order of +1.5V, the memristor has a resistance of the order of 3kΩ considered to be a low impedance and subsequently called LORES and after applying a negative voltage of the order of -2.5V, the memristor has a resistance of the order of 600kΩ considered to be a high impedance and subsequently called HIRES.

[0040] [Fig. 1] represents an example of a matrix display device 10 according to the invention. The device 10 comprises several pixels P organized in rows and columns. In [Fig. 1], a single pixel P is represented. It is understood that conventional devices generally comprise a large number of pixels. The number of rows and the number of columns can exceed a thousand. Furthermore, the designations row and columns are purely conventional and can be reversed.

[0041] Each of the pixels P comprises an elementary LED display component and a first electronic switch N1 arranged in series with the elementary LED display component. For convenience, a single elementary display component is shown here. It is also possible for each pixel to comprise several elementary display components connected in parallel in order to achieve the maximum brightness desired for the display device 10. The electronic switch NI makes it possible to turn the elementary LED display component on and off. Any type of elementary display component making it possible to emit or reflect light radiation can be implemented, in particular a conventional light-emitting diode, an organic light-emitting diode, a micro light-emitting diode, a micro-mirror implemented in a projector forming the device 10... The electronic switch NI can be a transistor or any other type of controlled switch. The electronic switch NI makes it possible to control the LED elementary component between two states. For an LED elementary component of the light-emitting diode type, the component emits light in a first state and does not emit light in a second state. For an LED elementary component of the micro-mirror type, the component reflects light emitted by a permanent light source of the device 10 in a first state and does not reflect light emitted by the source in a second state. For convenience, the two states will be respectively called: on and off. In practice, these are two binary states of the LED display elementary component.

[0042] Each of the pixels P comprises a memory MEM for storing a binary word for controlling the elementary LED display component between its two states. The binary word is representative of the average brightness that the pixel must display. According to the invention, the memory MEM comprises several memristors RMx for each storing a bit of the binary word. For each memristor, a first state of the corresponding bit is formed by the high impedance state HIRES of the memristor and a second state of the corresponding bit is formed by the low impedance state LORES of the memristor. The memristors have a first terminal RMxa common to all the memristors RMx and connected to a control terminal of the electronic switch NI for modifying its state: the gate G in the case of a transistor. The common terminals RMxa connected to the gate G form a node ngl of the pixel P.The channel of the electronic switch NI, between its drain D and its source S, still in the case of the transistor, is connected in series with the elementary LED display component. The second terminal of each of the memristors RMx, respectively RMxb, is connected to a column conductor Bx.

[0043] In [Fig. 1], the memristors RMx and the conductors Bx are referenced with an index x varying from 0 to N-1. The memristors make it possible to store N bits of a binary word representing the average light intensity displayed by the elementary LED display component.

[0044] Each of the pixels P further comprises a resistor RB and a second electronic switch N0. The resistor RB is connected at a first of its terminals to the node ngl and at a second of its terminals to a reference voltage, for example an electrical ground of the device 10. The electronic switch N0 is connected between the terminals RMxa common to all the memristors RMx and a reference voltage which can also be the electrical ground of the device 10. The switch electronic NO is controlled by means of a row conductor Lli. The index i represents the row rank in the pixel matrix.

[0045] The electronic switch NO makes it possible to switch from a write mode in the MEM memory while keeping the elementary LED display component off to a read mode of the MEM memory while authorizing the lit state for the elementary LED display component. Specifically to keep the elementary LED display component off, the electronic switch NO is in the on state to keep the electronic switch NI blocked by lowering the source gate voltage difference. To authorize the lighting of the elementary LED display component, the electronic switch NO is in a blocked state. The source gate voltage difference is then given by the voltage across the resistor RB.Furthermore, in its on state, the electronic switch NO allows the passage of sufficient current in the different memristors to make them change state and therefore memorize the different bits of the binary word according to information passing on the column bus formed by the column conductors Bx. On the contrary, when the electronic switch NO is in its off state, the memristors RMx and the resistor RB form a voltage divider bridge allowing the lighting of the elementary LED display component. In other words, in the off state, the electronic switch NO allows the reading of the memory MEM for display by the elementary LED display component through the electronic switch NI.

[0046] The resistor RB can be a conventional resistor. However, to ensure better stability of the divider bridge and to harmonize the manufacture of the device 10, it is advantageous for the resistor RB to also be a memristor. As mentioned above, the writing of the binary word representing the brightness to be displayed is done by choosing the resistance value of each of the memristors RMx: HIRES or LORES. On the other hand, the resistance value of the memristor RB remains fixed during the writing and reading operations of the memory MEM. In practice, it is possible to retain for the memristor RB, a resistance value equal to HIRES.

[0047] Such a pixel is suitable for a monochrome display. It is possible to implement the invention for a color display device having pixels of different colors, for example red, green and blue. Each type of pixel comprises one or more elementary display components suitable for emitting the desired color.

[0048] Certain types of memristors may require an initialization cycle performed only once in the life of the memristor. More specifically for OxRAM type memristors, an initialization cycle allows the creation of filaments in the memristor. This cycle can be performed outside the device 10 during the manufacture of each of the memristors. But advantageously, it is possible to provide, in the device 10, means adapted to this cycle. [Fig.2] represents an example of integration in the device 10 of means allowing the initialization cycle.

[0049] In [Fig.2], we find the pixel P, the column conductors Bx and the row conductor Lli. For the switch NO, the reference voltage to which it is connected can take two values, one for writing in the memory MEM and the other for initializing the memristances RMx. To do this, the device comprises for each row i of pixels, a second row conductor L2i and a switch SWPRi. The switches NO of the row i of pixels are connected between the node ngl of their respective pixel and the row conductor L2i. The switch SWPRi makes it possible to apply to the different row conductors L2i either the voltage of the electrical ground of the device 10 to allow writing in the memory MEM of the binary word representing the brightness to be displayed or a specific voltage Vprog-init making it possible to carry out an initialization cycle which can be carried out simultaneously for all the memristances RMx of all the pixels P of the device 10.

[0050] Alternatively, it is possible to provide means distinct from the switch N0 to apply the specific voltage directly to the node of each pixel, for example by means of another switch distinct from N0. However, the use of the switch N0 makes it possible to simplify the pixel P.

[0051] In [Fig.2], the voltage applied to the line conductor L2i appears in the form of a timing diagram when the switch SWPRi applies the specific voltage Vprog-init to it. In a first part of the timing diagram, the voltage Vprog-init takes a value -Vform allowing the creation of filaments for the different RMx memristances then possibly a value Vreset allowing the HIRES value to be established on all the RMx memristances. It is possible to do without the application of the Vreset and define the HIRES and LORES values ​​of the different RMx memristances during a subsequent write operation in the MEM memory.

[0052] When the resistor RB is a memristor, the application of the voltage -Vform to the node ngl of the pixel P also allows it to be initialized. In this case, the application of a programming voltage to the memristor RB is mandatory to freeze its value; in the example illustrated, the voltage Vrst is applied to give the memristor RB the value HIRES.

[0053] [Fig.3] illustrates the writing of the binary word in the memory MEM. [Fig.3] reproduces the structure of device 10 illustrated in [Fig.2], that is to say integrating the line conductor L2i and the switch SWPRi applying the voltage of the electrical ground to the line conductor L2i. It is entirely possible to implement the writing of the memory MEM in the simplified structure shown in [Fig.l], that is to say without means of choosing different voltages applied to the node ngl through the electronic switch N0 when it is conducting.

[0054] Each column bus is associated with two series of switches: SWDIS and SWPRO. Each series comprises as many switches as column conductors Bx. Each column conductor Bx of one of the column buses is connected to a switch of the series SWDIS which makes it possible to apply to the column in question either a reference voltage VREF or an output of one of the switches SWPRO which makes it possible to apply to the column in question either a voltage making it possible to modify the resistance value of the memristor RMx connected to the column in question or the voltage of the electrical ground making it possible not to modify the resistance value of the memristor RMx. Two voltage levels denoted Vset and Vrst make it possible to modify the resistance value of the memristor RMx in question, respectively towards the values ​​LORES and HIRES. It is possible to do without the third voltage level corresponding to the electrical ground.However, this voltage level allows, between two displays, to modify only the bits of the binary word having changed state. The different voltage levels can be generated by a column control module located in the device 10 at the bottom of the column.

[0055] During the programming operation of the MEM memory, the electronic switch N0, controlled by the row conductor Lli in the high state, is on, noted ON in [Fig. 3] and the switch SWPRi applies the voltage of the electrical ground to the row conductor L2i. Thus, the voltage of the node ngl is sufficiently low both for the elementary LED display component to remain off and to allow the programming of the MEM memory. The programming operation of the MEM memory is carried out line by line by sequentially applying to each row conductor Lli, a signal making it possible to make the switches N0 of the same row of pixels on. More precisely, in the embodiment shown in [Fig. 3], the signal PROGi in a high state (HIGH in [Fig. 4]) is sent sequentially to each row conductor Lli.When the different switches N0 of the same row i are on, the voltages corresponding to the values ​​of the corresponding bits are applied to the different column conductors Bx.

[0056] In the example shown in [Fig.3], the memristor RM0 takes the value HIRES, RMI the value LORES and RMN-1 remains unchanged. In [Fig.3], appear in the form of a timing diagram: - the PROGi voltage applied to the line conductor L2i, - the PROG-BN command of the SWPRO switch series, - the voltage applied to the column Bl, - the voltage applied to the column B0. To ensure that the voltages corresponding to the bit values ​​are applied when the elementary display component is switched off, it is advantageous to successively carry out the following steps for each of the pixel lines: - closing of the NO electronic switches, - application to each column conductor Bx of a voltage corresponding to the value of the bit to be stored in the RMx memristor connected to the corresponding column conductor Bx, - opening of the NO electronic switches, these three steps are repeated for each row of the matrix.

[0057] We have seen previously that the programming operation is carried out one line after the other. The selection of a line to be programmed is carried out by closing the electronic switches NO of the line considered, the electronic switches NO of the other non-selected lines remaining open. For the non-selected lines, the voltage divider bridge formed by the memristors RMx and the resistor RB is then active and each memristor RMx of a column receives the programming voltage even if this voltage is not intended for it. These programming voltages could make the electronic switch NI conductive, in particular in an unfavorable case where all the memristors RMx receive a positive voltage Vset. It is possible to provide a positive voltage value Vset compatible with maintaining the electronic switch NI in its closed state.Alternatively, it is possible to temporarily modify the voltage Va applied to the elementary LED display component, for example by setting the voltage Va to the voltage present at the other end of the conduction channel of the NI electronic switch, in this case: VDD / 2. This modification of the voltage Va during the programming operation can be carried out line by line or globally for all the lines of the matrix, including for the lines selected for programming. The voltage VDD / 2 is already available in the device and therefore easily accessible. More generally, other voltage values ​​are possible if this voltage applied to the elementary LED display component allows it to be kept in its off state for both states of the NI electronic switch.

[0058] The duration of the programming operation of the MEM memory is of the order of 100ns for a line of pixels. For a high-definition device 10 comprising 1080 lines of 1920 pixels P, the total duration for the entire device is of the order of 1000s. This duration corresponds to a monochrome screen. For a color screen, each line of pixels can comprise elementary pixels of different colors. In this case, the total duration of the programming operation remains unchanged. It is also possible to produce a color display device in which each line can display only a single color. For example, for a device where three elementary colors are implemented, the duration of the programming operation is then of the order of 300s.

[0059] After the programming operation of all the lines of the matrix, a display operation can begin. Each pixel P having received the binary word representative of the brightness that the elementary display component considered must display, the display operation can be global, that is to say that all the pixels P of the device 10 display simultaneously according to the stored binary word. For a global control, all the pixels P of the device 10 receive the same signals simultaneously.

[0060] [Fig.4] illustrates the display operation. As for the operation of programming, it is possible to implement the display operation with a simplified device as shown in [Fig.l].

[0061] During the programming operation, the switch N0 of each pixel P is on and during the display operation, the switch N0 is off. This is illustrated in [Fig.4] for the display operation where the signal PROGi, in a low state noted LOW in [Fig.4], is sent simultaneously to all the row conductors Lli of the device 10. The series of switches SWPRO is controlled to apply a voltage VDD to the different conductors Bx of all the column buses of the device 10.

[0062] During the display operation, a voltage pulse VDD is applied successively to each memristor RMx. The duration of the pulse depends on the weight of the bit that it stores. The pulse is applied to each memristor RMx through the associated column conductor Bx. In the example shown in [Fig.4], the voltage pulses are controlled by the series of switches SWDIS, each switch of which allows either the voltage VDD or the voltage VREF to be applied to the column conductor Bx with which it is associated. A voltage pulse VDD is applied successively to each column conductor Bx of the same column bus. As mentioned previously, the different column buses of the matrix can be controlled simultaneously to apply the voltage pulses to them.

[0063] More precisely, the slot whose duration t0 is the shortest is applied to the memristor RM0 storing the least significant bit of the binary word. Then, to the memristor RMI is applied a slot of duration tl double that applied to memristor RM0 and so on by doubling the duration of the slots up to the memristor RMN-1 storing the most significant bit of the binary word. The slot applied to the memristor RMN-1 has a duration 2N '.t0.

[0064] In [Fig.4] appears, in the form of a timing diagram, the voltage applied to the row conductor Lli allowing the transistor N0 to be blocked, the different pulses noted DISP BX applied successively to the different memristors RMx and the lit state noted ON and extinguished state noted OFF of the elementary LED display component. The timing diagram also appears the programming operation where the voltage applied to the row conductor Lli allows the transistor N0 to be turned on. On the timing diagram, the application of the voltage pulses is done in the order of the bits of the binary word. It is possible not to respect this order. Indeed, the apparent brightness for a user is an average of the durations during which the elementary LED display component is lit on a display frame. The order in which the bits are displayed does not modify this average.

[0065] The refresh frequency of the device, i.e. the inverse of the duration of a sequence comprising a programming operation and a display operation, has no influence on the average brightness displayed by the elementary LED display components. On the other hand, the electrical consumption of the device increases with this frequency due to the number of switching operations. It is therefore advantageous to choose the lowest possible refresh frequency based on physiological parameters usually retained for a user of the device.

[0066] The values ​​of the voltages VDD and VREF are chosen as a function of the ratio of the resistance values ​​HIRES and LORES of the RMx memristors, of the value of the resistance RB which, as seen previously, can be equal to HIRES and of the number of RMx memristors so that, during the display operation, the elementary LED display component can be in its on state when only one of the RMx memristors has a resistance value LORES and the other RMx memristors have a resistance value HIRES and can be in its off state when the voltage VDD is applied to an RMx memristor having a resistance value HIRES while the other memristors have a resistance value LORES.

[0067] In practice, if the resistor RB is a memristor whose resistance value is HIRES, the voltage VDD can be substantially double that present at the source S of the switch NI. If a voltage pulse VDD is applied to a memristor RMx, whose resistance value is HIRES, the voltage present at the node ngl of the pixel P is approximately VDD / 2 and the transistor NI is blocked because the gate-source potential difference is zero. On the other hand, with a resistance value ratio between HIRES and LORES of the order of two decades, if a voltage pulse VDD is applied to a memristor RMx, whose resistance value is LORES, the voltage present at the node ngl of the pixel P is approximately VDD, the gate-source potential difference increases and the transistor NI is conducting.

[0068] More precisely, when a memristor RMx has a high resistance value (HIRES), the bit it stores is 0 and during the display operation when it receives a VDD voltage slot, the voltage value of the node ngl is:

[0069] V(ngl_low) = VDD RB / (RB+RMx) = VDD (HIRES / (HIRES+HIRES)) = VDD / 2

[0070] By choosing VREF=VDD / 2, the influence on the Vngl_low voltage of the node of pixel P of the other RMx memristors is not significant. As the source of the NI switch is at voltage VDD / 2, the NI transistor is blocked (VGS=0) and the LED display element is in its off state.

[0071] On the other hand, if an RMx memristor has a low resistance value (LORES, bit = 0) and the other RMx memristors have high resistance values ​​(HIRES, bit = 1), the voltage on the ngl node is higher:

[0072] V_(ngl_high) “VDD * (RB / (RB+RMx)) = VDD * (HIRES / (LORES+HIRES)).

[0073] With, for example, a ratio between the LORES and HIRES values ​​of 0.5%, the voltage value Vngl_high is practically equal to VDD. This generates the conduction of the NI transistor and the elementary LED display component is in its on state.

[0074] The elementary LED display component is therefore lit only during the periods when a memristor RMx having a resistance value LORES (bit=1) is addressed by its voltage slot VDD.

[0075] Given the proportionality of the different durations of the slots with respect to the weight of the bit, the average light intensity will correspond to the digital value stored in the pixel P.

[0076] The duration of the programming operation during which the elementary LED display component is in its off state must be taken into account in the average light intensity perceived by a user. The duration of the programming operation being very short (of the order of 100ps for a high definition device (1080 lines) it is possible to choose a much longer duration of the display operation while maintaining a high display rate. The duration of the programming operation has very little influence on the average light intensity.

[0077] In the extreme case where one wishes to display a maximum light intensity, in other words when all the RMx memristors have a resistance value equal to LORES, when applying the different voltage slots, the voltage of the ngl node may not be sufficient to turn on the NI transistor due to the presence of Nl memristors to which the VREF voltage tends to lower the voltage of the ngl node. The voltage level of the ngl node depends on the number of bits N and the LORES resistance value. It is possible to overcome this drawback by increasing the VDD voltage but this has two drawbacks: - Risk of increasing the voltage of the ngl node when the elementary display component must remain in the off state, - Increase in the power consumption in the RMx memristors and in the RB resistor.

[0078] Concerning the power consumption, even if the current flowing in the RMx memristors is low during the display operation compared to that necessary for the programming operation, for large device formats, the power consumption of the RMx memristors is not negligible.

[0079] It is possible to completely overcome the first drawback and to significantly reduce the electrical consumption by interrupting the passage of current in the memristors not receiving a voltage pulse for the display of the corresponding bit.

[0080] [Fig.5] illustrates a variant of the device providing an electronic switch NBx connected in series with each memristor RMx and controlled by the column conductor Bx associated with the memristor RMx considered. During the display operation, the voltage pulse is applied sequentially to control each electronic switch NBx and turn it on. Among the different memristors RMx, at a given instant of the display operation, only one is subjected to the voltage pulse. The memristors RMx whose corresponding electronic switch NBx is blocked therefore do not consume any current. The timing diagram of the display operation is similar to that of [Fig.4].

[0081] To carry out the programming and display operations, an additional column conductor NCOM is necessary to apply to the memristors RMx the voltage level either for their programming or for the display. More precisely, unlike in Figures 1 to 4, where the terminals RMxb are connected respectively to the different column conductors Bx, in the variant of [Fig.5], the terminals RMxb are all connected to the column conductor NCOM.

[0082] During the programming operation, the programming voltage is selectively applied to each memristor RMx by the additional column conductor NCOM. The memristor RMx to be programmed is selected by closing one of the switches NBx selected by the voltage of one of the switches of the series SWDIS.

[0083] During the display operation a voltage equal to that of the slot is applied to the additional column conductor NCOM. The selection of the memristor RMx to apply the information that it stores to be displayed is carried out by closing one of the switches NBx as during the programming operation.

[0084] A SWMOD switch allows either the VDD voltage during the display operation, the programming voltage Vset, Vrst or a zero voltage to be applied to the NCOM column conductor. The SWPRO switch series is no longer useful.

[0085] This variant, however, has a drawback because it does not allow all the RMx memristors to be programmed simultaneously. During the programming operation, the elementary LED display components must be switched off, which increases the risk of the appearance of blinking phenomena of the device, known in English literature as "blinking".

[0086] The variant illustrated in [Fig.5] allows better control of the voltage of the ngl node as a function of the value of the memorized bits.

[0087] For each of the pixels, without counting the electrical consumption of the elementary LED display component, the electrical consumption of the memristors is much reduced compared to that of the pixels illustrated in [Fig.l]. Indeed, only one memristor RMx is selected at a time by making the corresponding switch NBx conductive. No current flows in the other memristors RMx whose corresponding switches NBx are blocked. However, the electrical consumption can still be significant, in particular when the stored brightness is maximum or close to the maximum brightness. For example, in the extreme case where for a high-definition display device, all the binary words only comprise bits in the high state, the electrical consumption excluding the elementary LED display component is of the order of 4A for OxRAM type memristors.

[0088] The programming operation can be done sequentially for each of the RMx memristors by closing the corresponding NBx electronic switch and applying to the column conductor NCOM the programming voltage Vset, Vrst or a zero voltage if the previously stored resistance value does not change. Alternatively, it is also possible to simultaneously program all the RMx memristors to receive the same voltage Vset or Vrst and then to simultaneously program all the RMx memristors to receive the other of the voltages Vset or Vrst. This alternative appears on the timing diagram appearing in [Fig.5]. The control of the NBx electronic switches is done by means of the series of SWDIS switches. For the RMX memristors not to change resistance value, their switch NB1 will not switch to the on state during the successive application of the two voltages Vset and Vrst.This timing diagram also shows the application of the VDD / 2 voltage to the elementary LED display component to prevent it from lighting up during the programming operation, even if the NI electronic switch were to close due to the voltages applied to the RMx memristors.

[0089] The display operation for the variant illustrated in [Fig.5] is carried out in a similar manner to that of the variant illustrated in [Fig.4] by applying during this operation a voltage VDD to the column conductor NCOM. The reading of each memristor RMx is carried out by successively applying to each electronic switch NBx a voltage pulse allowing it to be closed, the duration of the pulse being proportional to the weight of the bit represented by the associated memristor RMx. The application of the voltage pulse is carried out by means of the corresponding column conductor Bx.

[0090] [Fig.6] illustrates another variant of the device making it possible to further reduce the electrical consumption of the memristors. In the previous variants, a current flows in the memristors in series, RMx and RB, which operate as a voltage divider bridge. For a given memristor, this current flows for the duration of the pulse applied to it. This duration is all the greater as the weight of the corresponding bit is large. The variant of [Fig.6] makes it possible to limit the duration of the electrical consumption of each memristor to the duration of a pulse independently of the weight of the corresponding bit. For this purpose, each pixel P comprises a memory element CO arranged at the node ngl and a latch PO making it possible to load the memory element with the value of the bit to be displayed and to maintain this value for a duration that is a function of the weight of the bit. The latch PO is arranged between the node ngl and the common point of the memristors RMx.

[0091] In the example shown where the electronic switch NI is a transistor, the memory element is for example a capacitor C0 making it possible to store a voltage making it possible either to open or to close the channel of the transistor NI depending on the resistance value ratio between the memristor RMx and the resistor Rb. The latch is for example a transistor PO whose channel connects the node ngl and the common point nrb of the memristors RMx, a common point also connected to the resistor RB. The latch PO is controlled by a row conductor L3i.

[0092] In [Fig.6] appears a timing diagram describing the application of a pulse to each of the different columns Bx and of as many simultaneous pulses (LATCH signal) on the column conductor L3i to make the transistor PO conductive. The pulses are separated by a duration depending on the weight of the bit stored in the corresponding memristor RMx. The duration separating the pulses is equal to the duration of the slots described using [Fig.4].

[0093] Between two pulses, the memristors RMx and the resistor RB do not consume any current and it is entirely possible to insert the programming operation between two pulses, i.e. during the display operation. In [Fig.6], the programming operation occurs during the display of the most significant bit. It is possible to have the programming operation occur during the display of another bit. It is even possible to split the programming operation during the display of several bits.

[0094] The variant of [Fig.6] makes it possible both to reduce the electrical consumption of the memristors RMx and the resistor RB, and also to reduce the inactive duration of the display for the programming operation. This second advantage is of particular interest in the variant of [Fig.5] where the programming of the different memristors cannot be done simultaneously. It is of course possible to put implement the memory element CO and the lock PO in the variant shown in [Fig.l].

[0095] The presence of a PO lock and a CO memory element can also be implemented in the variant of [Fig.l].

[0096] [Fig.7] illustrates different structures for producing the lock and the element memory, in particular to stabilize the high and low voltage levels present on the ngl node in order to limit the effects of possible leakage currents on the CO capacitor. More precisely, it is possible to place between the PO latch and the memory element an inverter made for example using three transistors N2, N3 and P2. The memory element can be made using a double inverter made for example using four transistors P4, N4, P5 and N5.

[0097] We mentioned above the fact of not modifying the resistance value of an RMx memristor when the corresponding bit has not been modified, from one programming operation to the next, by applying to a given RMx memristor the voltage level of the electrical ground of the device, see in particular the voltage applied to the RMN-1 memristor in [Fig. 3] during the programming operation. This makes it possible to use the RMx memristors less to make them change state and therefore to increase their lifetime.

[0098] The choice of applying a zero voltage to a given memristor or of applying a voltage to it allowing it to change its resistance value can be made by means of a computer comparing bit by bit the successive binary words to be stored in the MEM memories in different pixels. The comparison is made in the computer by storing there the current binary word previously stored in each of the MEM memories in order to compare it with a new binary word to replace it. If one or more bits of the current binary word have a level identical to that of the new binary word, then the computer applies a zero voltage to the memristor or memristors corresponding to the bits considered through the column conductor Bx.On the contrary, if one or more bits of the current binary word have a different level from that of the new binary word, then the computer applies the voltage either Vset or Vrst to the memristor(s) corresponding to the bits considered through the column conductor Bx. The computer can then address only the pixels whose binary word has been modified in order to reprogram them.

[0099] In such an operating mode, the rewriting of the MEM memories, and therefore the refreshing of the video image, is only done in the case of changes only on the pixels concerned. The concept of fixed video rate is therefore not applicable and the image becomes free of any flickering phenomenon or other artifacts linked to the continuous updating conventionally implemented in existing systems.

[0100] Alternatively, before a programming operation, instead of storing the current binary word in the computer for each of the pixels P, it is possible to read the current binary word stored in the memory MEM and compare this reading with the new binary word to be stored. As previously, a voltage is applied to the different memristors depending on the result of the comparison. The comparison can be made in the computer or by means of a dedicated circuit, for example arranged at the bottom of each column.

[0101] [Fig.8] illustrates an example of a reading circuit R, a comparison circuit C, and a writing circuit W arranged at the bottom of each column and allowing respectively, the reading of the memory MEM of each pixel P, the comparison of the current and new binary words as well as the writing in the memories MEM. In order not to overload [Fig.8], for two pixels of two distinct lines: i and i+1, only one of the memristors is represented, in this case the one having to store the bit of rank k of the binary word, the transistor NBk and the transistor N0. Also appearing in [Fig.8], the column conductors NCOM and Bk as well as the row conductors L2i and L2i+1.

[0102] The row i whose memory MEM is to be read is selected by means of the row conductor L2i. The switch SWMOD is in position to apply the programming voltage to the column conductor NCOM. It is noted that this position of the switch SWMOD here makes it possible either to read the memory MEM or to write the bits of the new binary word there. The choice between the reading circuit R and the writing circuit W is made by means of a switch SWRW. The reading circuit R is connected to the column conductor NCOM through the switches SWMOD, SWPRO and SWRW. The comparison is made for example by means of an operational amplifier OP connected on its inverting input to the column NCOM on which the resistor RMk of the row i is connected to ground through the switch NO in the on state. The operational amplifier OP has a resistor RS in its feedback to the inverting input.The resistance value ratio of the memristor RMk and the resistor RS makes it possible to deliver at the output of the operational amplifier OP a binary information relating to the HIRES or LORES resistance value of the memristor RMk. This binary information is delivered to the comparison circuit C, for example formed by a logic cell, to be compared with the new value, called "new Bk", of the bit concerned. Then after reading and comparing a bit, the switch SWRW changes position to connect the write circuit W to the column conductor NCOM. The result of the comparison makes it possible to apply by means of the write circuit W either a zero voltage if the value of the current bit is equal to that of the new bit, the write circuit W is then considered deactivated, or the value of the new bit, Vset or Vrst. if the value of the current bit is different from that of the new bit, the write circuit W is then considered activated. In other words, the write circuit W is configured to be deactivated if for a given bit its value in the new binary word is equal to its value in the current binary word. Conversely, the write circuit W is configured to be activated if for a given bit its value in the new binary word is different from its value in the current binary word.

[0103] In [Fig.8] appears a truth table indicating the operation of the comparison and writing circuits C and W. It is understood that the circuits R, C and W represented in [Fig.8] are only examples and can be adapted according to specific needs.

Claims

Claims

1. Matrix display device comprising a matrix of pixels (P) organized in rows and columns, each pixel (P) comprising: - an elementary display component (LED), - a first electronic switch (NI) for controlling the elementary display component (LED) between two states called: on and off, - a memory (MEM) for storing a binary word for controlling the elementary display component (LED) to display a brightness corresponding to the binary word, the memory (MEM) comprising several memristors (RMx) each intended to store a bit of the binary word and connected to a node (ngl) of the pixel (P) common to all memristors (RMx), the node (ngl) of the pixel (P) forming a control (G) of the first electronic switch (NI), - a resistor (RB) connected between the node (ngl) of the pixel (P) and a reference voltage (GND),- a second electronic switch (NO) connected in parallel with the resistor (RB) and allowing, in an on state, to modify the resistance values ​​of the memristors (RMx) while keeping the elementary display component (LED) off and in a blocked state to turn on the elementary component (LED) according to the binary word.,

2. A matrix display device according to claim 1, wherein the resistor (RB) is a second memristor.

3. Device according to one of the preceding claims, further comprising means for applying to the node (ngl) of the pixel (P) a voltage configured to initialize the first memristors (RMx).

4. Device according to one of the preceding claims, in which the memristors (RMx) are each connected between a column conductor (Bx) and the node (ngl) of the pixel (P) common to all memristors (RMx).

5. Device according to one of claims 1 to 3, further comprising a third electronic switch (NBx) connected in series with each of the memristors (RMx), for each row of pixels (P), the third electronic switches each being controlled by a column conductor (Bx).

6. Device according to one of the preceding claims, in which each pixel (P) comprises a memory element (CO) arranged at the node (ngl), the memristors (RMx) being connected to the node (ngl) via a latch (PO) making it possible to load the memory element (CO) with the value of the bit to be displayed and to maintain this value for a duration depending on the weight of the bit.

7. Device according to one of the preceding claims, further comprising: - a circuit (R) for reading the bits of a current binary word stored in each memory (MEM), - a circuit (C) for comparing the bits of the current binary word with the bits of a new binary word to replace the current binary word, - a circuit (W) for writing the new binary word configured to be deactivated if for a given bit its value in the new binary word is equal to its value in the current binary word and to be activated if for a given bit its value in the new binary word is different from its value in the current binary word.

8. Method for implementing a matrix display device according to one of claims 1 to 7 in which, during an operation of storing a binary word in the memory (MEM), a voltage (va) is applied to the elementary display component (LED) keeping it in its off state for the two states of the first electronic switch (NI).

9. Method for implementing a matrix display device according to one of claims 1 to 7 in which, from an operation of storing a binary word in the memory (MEM) to the following storage operation, only the memristors (RMx) whose associated bits have changed value receive a voltage making it possible to modify their resistance value, the memristors (RMx) whose associated bits have not changed value receive a voltage not making it possible to modify their resistance value.

10. Method for implementing a matrix display device according to claim 4, in which, to store a binary word in the memory (MEM), the following steps are successively carried out for each of the lines (i) of pixels (P): - closing of the second electronic switches (NO), - applying to each column conductor (Bx) a voltage corresponding to the value of the bit to be stored in the memristor (RMx) connected to the corresponding column conductor (Bx), - opening of the second electronic switches (NO), these steps are repeated for each row (i).

11. Method for implementing a matrix display device according to claim 5, in which, to store a binary word in the memory (MEM), the following steps are successively carried out for each of the lines (i) of pixels (P): - closing of the second electronic switches (NO), - selective closing of the third electronic switches (NBx) and application of the value of the bit to be stored to the different memristors, - opening of the second electronic switches (NO), these steps are repeated for each line (i).

12. Method according to claim 11, in which all the third electronic switches (NBx) associated with memristors (RMx) which are to store the same bit value are simultaneously closed.

13. Method for implementing a matrix display device according to one of claims 1 to 7, in which, to display on the elementary display component (LED) a brightness corresponding to the binary word stored in the memory (MEM), the following steps are successively carried out simultaneously for all the lines (i) of pixels (P): - opening of the electronic switches (NO), - application of voltage pulses successively to each memristor (RMx), - closing of the electronic switches (NO).

14. Method according to the preceding claim for implementing a matrix display device according to claim 6, in which the slots are pulses whose duration is independent of the weight of the bit concerned and in which the pulses are separated by a duration which is a function of the weight of the bit stored in the corresponding memristor (RMx).

15. A method according to the preceding claim for implementing a matrix display device according to claim 6, wherein,

16. the storage of a binary word in memory (MEM), occurs between the pulses. Method according to claim 13 for implementing a matrix display device according to one of claims 1 to 5, in which the voltage slots have a duration which is a function of the weight of the bit stored in the corresponding memristor (RMx).

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