Device comprising several integrated circuits and method of assembling and encapsulating integrated circuits

Abstract

Device comprising several integrated circuits and method for assembling and encapsulating integrated circuits The present description relates to a method comprising: forming on a substrate (104) a first layer of a resin compatible with direct laser structuring, LDS, a first integrated circuit (101) mounted on the substrate being embedded in the first layer, the substrate comprising a first (123) and a second (125) connection terminal covered by the first layer; forming a first via (112) by LDS, the first via passing through the first layer of resin and forming an electrical contact with the second connection terminal; mounting a second integrated circuit (102) on the first integrated circuit; forming on the substrate a second layer of the resin, the second integrated circuit being embedded in the second layer;and the formation of a second via (118) by LDS crossing the second layer and forming an electrical contact with the first via. Figure for abstract: Fig. 1;

Description

Title of the invention: Device comprising several integrated circuits and method for assembling and encapsulating integrated circuits Technical field

[0001] The present disclosure relates generally to devices comprising a plurality of integrated circuits and methods of manufacturing such devices. Prior Art

[0002] In microelectronics, the trend is towards miniaturization to consume less raw materials and reduce production costs or to be able to add new functionalities to a product without increasing its size. With this in mind, it is interesting to superimpose integrated circuits on the same substrate so that they take up less space. Electrical connections between a first integrated circuit mounted on a substrate can be ensured by direct connections between metal pads, and wire bonding presents a solution for making electrical connections between a second integrated circuit mounted on the first integrated circuit. However, the use of wires requires a large amount of space around the integrated circuits to be connected.

[0003] There is therefore a need for a method of assembling several circuits superimposed on each other on the same substrate making it possible to reduce the dimensions of the final device. Summary of the invention

[0004] One embodiment provides a method comprising: - forming on a substrate a first layer of a resin compatible with direct laser structuring, LDS, a first integrated circuit mounted on the substrate being incorporated in the first layer, the substrate comprising a first connection terminal connected to the first integrated circuit and a second connection terminal connected to the first connection terminal and covered by the first layer; - the formation of a first via by LDS, the first via crossing the first layer of resin and forming an electrical contact with the second connection terminal; - mounting a second integrated circuit on the first integrated circuit; - forming on the substrate a second layer of the resin compatible with the LDS, the second integrated circuit being incorporated in the second layer; and - the formation of a second via by LDS crossing the second layer and forming an electrical contact with the first via.

[0005] According to one embodiment, the formation of the first resin layer comprises the deposition of an initial resin layer and a step of thinning the initial layer to obtain the first resin layer.

[0006] According to one embodiment, the formation of the second layer of resin comprises the deposition of an initial layer of resin and a step of thinning the initial layer to obtain the second layer of resin.

[0007] According to one embodiment, the method further comprises adding a device on the second resin layer, the device being connected to the second via.

[0008] According to one embodiment, the method further comprises a step of depositing a third layer of resin on the second layer.

[0009] According to one embodiment, the first integrated circuit and the second integrated circuit each have a first face comprising metallizations comprising one or more connection terminals and a second face opposite the first face, the first and second integrated circuits being mounted with their second faces oriented towards each other.

[0010] According to one embodiment, the vias are formed by autocatalytic growth or non-electrolytic growth.

[0011] According to one embodiment, the second via is laterally offset relative to the first via.

[0012] According to one embodiment, the height of the first resin layer is at least equal to the distance separating the second connection terminal from the upper face of the first integrated circuit.

[0013] According to one embodiment, the height of the second resin layer is at least equal to the distance separating the first via from the upper face of the second integrated circuit.

[0014] Another embodiment provides a microelectronic device comprising: - a substrate; - a first integrated circuit mounted on the substrate; - a first layer of a resin, compatible with structuring by direct laser structuring, LDS, deposited on the substrate and in which the first integrated circuit is incorporated; - in the substrate, a first connection terminal connected to the first integrated circuit and a second connection terminal connected to the first connection terminal and covered by the first layer; - a first via formed by LDS, the first via passing through the first layer of resin and forming an electrical contact with the second connection terminal; - a second integrated circuit mounted on the first integrated circuit; - a second layer of resin compatible with the LDS, the second circuit integrated being incorporated into the second layer; and - a second via formed by LDS crossing the second layer and forming an electrical contact with the first via. Brief description of the drawings

[0015] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0016] [Fig.l] is a sectional view of a device comprising two integrated circuits connected to each other and to the same substrate according to an embodiment of the present description;

[0017] [Fig.2A], [Fig.2B], [Fig.2C], [Fig.2D], [Fig.2E], [Fig.2F], [Fig.2G], [Fig.2H] and Figure 2I are sectional views of successive steps of a method of manufacturing the device of [Fig.1] according to an embodiment of the present description;

[0018] [Fig.3A] and [Fig.3B] are sectional views of successive steps of a manufacturing method that can be applied to the device of [Fig.1]; and

[0019] [Fig.4A] and [Fig.4B] represent partial sectional views of the successive steps of a panel-embedded packaging (PEP) process for an integrated circuit. Description of the embodiments

[0020] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0021] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular, the steps for manufacturing a laminated substrate and integrated circuits are standard and are not detailed.

[0022] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0023] In the following description, when referring to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., it is made reference unless otherwise specified to the orientation of the figures.

[0024] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0025] [Fig.l] is a sectional view of a device 100 comprising two integrated circuits 101, 102 connected to each other and to the same substrate 104 according to an embodiment of the present description.

[0026] In the example of [Fig.l], the two integrated circuits 101 and 102 are mounted on top of each other via a fixing layer 126 and encapsulated in a resin 106. The integrated circuit 101 is for example mounted on the substrate 104 via a dielectric layer 105. The integrated circuits 101 and 102 are electrically connected to each other and to the substrate 104 by a set of vias 112, 117, 118, 112', 117', 118' and metal tracks 114, 119, 124, 114', 119', 124' formed in the resin 106, in the substrate 104 and / or in the dielectric layer 105.

[0027] The substrate 104 and the dielectric layer 105 are for example made of ABF film (from the English “Ajinomoto Build-up Film”) or for example made of polymer. The substrate 104 has a thickness for example at least equal to 50 μm. The dielectric layer 105 has a thickness for example at least equal to 10 μm.

[0028] The integrated circuits 101 and 102 each have metallizations comprising one or more connection terminals 123, 130, 123', 130' on a first face of each of the integrated circuits 101, 102, and have for example no metallization or connection terminal on a second face opposite the first face. The second integrated circuit 102 is mounted on the first integrated circuit 101 so that their second faces are opposite each other and the connection terminals present on their first faces remain accessible.

[0029] The connection terminal 123 of the integrated circuit 101 is for example on its lower face, and is for example connected by one or more metal tracks 124 to a connection terminal 125 on the upper face of the substrate 104. The metal tracks 124 are for example made of copper, gold, tin, silver or an alloy of several of these materials.

[0030] In certain embodiments, the connection terminals 123 and 125 are also connected via the metal tracks 124 to a connection terminal 128 making it possible to connect the device 100 to an external electronic device not shown. The connection terminal 128 is for example present on the lower face of the substrate 104.

[0031] The connection terminal 130 of the integrated circuit 102 is for example on its upper face. The connection terminals 125 and 130 are connected to each other by means of the via 112 and the via 118. In the example of [Fig.l], the via 112 has a height at least equal to the sum of the height of the first integrated circuit 101 and the height of the dielectric layer 105. In the general case, the via 112 has a height at least equal to the distance separating the connection terminal 125 from the upper face of the integrated circuit 101. In the example of [Fig.l], the via 118 has a height at least equal to the sum of the height of the second integrated circuit 102 and the height of the fixing layer 126. In the general case, the via 118 has a height at least equal to the distance separating the via 112 from the upper face of the integrated circuit 102.

[0032] According to one embodiment, the vias 112 and 118 are laterally offset, i.e. offset in a direction parallel to the plane of the substrate 104, from each other by a distance δ. The vias 112 and 118 are for example connected to each other via the metal track 114.

[0033] A via 117 is connected on the one hand to the connection terminal 130 of the integrated circuit 102 and is connected on the other hand to the via 118 by means of one or more metal tracks 119.

[0034] The resin 106 used to encapsulate the integrated circuit 101 is for example a specific resin compatible with direct laser structuring, LDS. The thickness of the resin layer 106 is for example at least equal to the sum of the heights of the vias 112 and 118. In the example of [Fig.l], the thickness of the resin layer 106 is sufficient to cover the metal tracks 119.

[0035] In the example of [Fig.l], a second set of connection terminals 123', 125', 128' and 130' as well as vias 112', 117', 118' and metal tracks 114', 119', 124' are shown and are similar to those described above and will not be described in detail. In other embodiments, it would be possible to provide a single set, or more than two sets, of connection terminals, vias and metal tracks.

[0036] Figures 2A to 21 are sectional views of successive steps of a method of manufacturing the device 100 of [Fig.l] according to an embodiment of the present description.

[0037] Certain elements of Figures 2A to 21 are identical to elements of [Fig.l], and these elements are designated by the same references and are not described again in detail.

[0038] In the following description of Figures 2A to 21, only the formation of the metal tracks 114 and 119 and the vias 112, 117 and 118 is described, the same steps are for example used for the formation of the metal tracks 114' and 119' and the vias 112', 117' and 118'.

[0039] [Fig.2A] shows an example of a device 200 having a starting point for the manufacturing process of the device 100 of [Fig.l]. In comparison with the device 100 of [Fig.l], the device 200 does not yet include the second integrated circuit 102 or the vias 112, 118 for connecting the circuits 101 and 102 between them and to the substrate 104.

[0040] The device 200 of [Fig.2A] is for example obtained according to manufacturing steps of a panel-embedded packaging (PEP) process detailed in FIGS. 4A and 4B.

[0041] The device 200, in the example of [Fig.2A], comprises the first integrated circuit 101 connected to the substrate 104 and encapsulated in a resin layer 106A. The height hl of the resin layer 106A is for example sufficient to cover the integrated circuit 101 and the connection terminal 125.

[0042] [Fig.2B] shows the device of [Fig.2A] after an optional step of thinning the resin layer 106A. According to one embodiment, the thickness of the resin layer is reduced to make the integrated circuit 101 visible. This step is useful, for example, in anticipation of fixing a second integrated circuit 102 on the first 101.

[0043] The final height hl' of the resin layer 106A' is, in the example of [Fig.2B], at least equal to the sum of the height dl of the first integrated circuit 101 and the height d5 of the dielectric layer 105. In the general case, the height hl' is for example at least equal to the distance separating the connection terminal 125 from the upper face of the integrated circuit 101.

[0044] In the following description of Figures 2C to 2K, the steps are considered to be applied to the device obtained in the step of [Fig. 2B]. However, in the case where the step of [Fig. 2B] is omitted, it would be clear to the person skilled in the art how the steps of Figures 2C to 2K would be adapted.

[0045] [Fig.2C] shows the device of [Fig.2B] following a laser ablation step. The resin layer 106A' is perforated by a laser beam to partially expose the connection terminals 125 present on the surface of the substrate 104. The perforations 110 produced correspond to the locations of future metal vias.

[0046] During the laser ablation step, the laser beam used to perforate the resin 106A' interacts with additives present in the resin 106A' and locally activates the periphery of the perforations 110.

[0047] Furthermore, the locations of future formations of the metal tracks 114, on the upper surface of the resin 106A', i.e. the surface furthest from the substrate 104, are for example illuminated by the laser beam during this step to activate them locally.

[0048] [Fig.2D] illustrates the device of [Fig.2C] for example following an autocatalytic growth step or non-electrolytic growth (in English "electroless plating"). During this process, a metal is deposited, without using an electric current, on the surfaces of the resin 106A' previously activated by a laser beam. The activation of the resin by the laser beam creates a primer on the surface of the resin, at the locations where it has been illuminated. For example, vias 112 are created in the perforations 110 of [Fig.2C] starting from the exposed connection terminals 125 and the periphery of the perforations 110 previously activated. Metal tracks 114 are for example created on the surface of the resin 106A', on the previously activated portions.

[0049] Although [Fig.2D] shows an example of non-electrolytic growth to form the metal tracks 114 and the vias 112, it would also be possible to use an electrolytic growth method. In this case, temporary metal tracks (not shown) are for example created on the surface of the resin layer 106A' to circulate an electric current used to obtain this electrolytic growth.

[0050] The vias 112 are for example made of copper, gold, tin, silver or an alloy of several of these materials.

[0051] The steps described above in relation to Figures 2C and 2D correspond to an implementation of an LDS method.

[0052] [Fig.2E] illustrates the device of [Fig.2D] following the fixing of the second integrated circuit 102 on the first integrated circuit 101. As described in relation to [Fig.1], the integrated circuits 101 and 102 each comprise a first face comprising metallizations comprising one or more connection terminals and a second face, opposite the first face, which is for example without metallization or connection terminal. The second integrated circuit 102 is for example fixed so that the second faces of the two integrated circuits 101 and 102 are in contact and its connection terminals are located on its upper face so that they remain accessible after fixing. The two integrated circuits are for example fixed using an epoxy-based glue which polymerizes during a heating step.

[0053] According to one embodiment, in the case where the thinning step of [Fig.2B] is omitted or partial thinning is carried out, a layer of resin is present between the integrated circuits 101 and 102.

[0054] [Fig.2F] shows the device of [Fig.2E] following the deposition of a second layer of resin 106B compatible with the LDS.

[0055] The deposition of the resin layer 106B is, for example, carried out by compression molding, the resin being for example deposited on the surface of the device of [Fig.2E] and pressed into a mold.

[0056] The thickness h2 of the layer 106B is for example at least equal to the height of the future vias 118, i.e. for example at least sufficient to cover the integrated circuit 102.

[0057] [Fig.2G] shows the device of [Fig.2F] after an optional step of thinning the resin layer 106B.

[0058] As for the height h2, the final height h2' of the resin layer 106B' is, in the example of [Fig.2G], at least equal to the sum of the height d2 of the second integrated circuit 102 and the height d26 of the fixing layer 126. In the general case, the height h2' is for example greater than the distance separating the via 112 from the upper face of the integrated circuit 102 to cover the integrated circuit 102.

[0059] In the following description of Figures 2H to 2K, the steps are considered to be applied to the device obtained in the step of [Fig. 2G]. However, in the case where the step of [Fig. 2G] is omitted, it would be clear to the person skilled in the art how the steps of Figures 2H to 2K would be adapted.

[0060] [Fig.2H] shows the device of [Fig.2G] following a laser ablation step. The resin layer 106B is perforated by a laser beam to form perforations 116 and for example perforations 115 which correspond to the locations of future vias. The perforations 116 expose at least a portion of the metal tracks 114 which are connected to the at least one connection terminal 123 of the integrated circuit 101 and to the at least one connection terminal 128 of the substrate 104. The perforations 115 expose for example connection terminals 130 of the integrated circuit 102.

[0061] Following the laser ablation step, the periphery of the perforations 115, 116 is activated.

[0062] Furthermore, the locations of future formations of the metal tracks 119, on the upper surface of the resin 106B', are for example illuminated by the laser beam during this step to activate them locally.

[0063] [Fig. 21] shows the device of [Fig. 2H] for example following an autocatalytic growth step. During this process, vias 118 are created in the perforations 116 of [Fig. 2H] starting from the exposed portions of metal tracks 114 and the periphery of the perforations 116 previously activated. Vias 117 are for example created in the perforations 115 of [Fig. 2H] starting from the exposed connection terminals of the integrated circuit 102 and the periphery of the perforations 115 previously activated. Metal tracks 119 are for example created on the surface of the resin 106B, on the previously activated portions. The vias 118, 117 and the tracks 119 are for example made of copper, gold, tin, silver or an alloy of several of these materials.

[0064] The steps described above in relation to Figures 2H and 21 correspond to an implementation of an LDS process. The LDS process is only possible on compatible resin layers.

[0065] According to one embodiment, the vias formed by autocatalytic growth in steps 2C and 2H are created by forming a metal layer on the walls of the perforations 110, 116, 115. The vias 112, 118, 117 thus created form, for example, cones partially filled in their center. The vias 112 and 118 are, for example, offset from each other by a distance δ and connected by metal tracks. 114 metals to ensure a good connection.

[0066] Although [Fig.2I] represents an example of non-electrolytic growth to form the metal tracks 119 and the vias 114, it would also be possible to use an electrolytic growth method. In this case, temporary metal tracks (not shown) are for example created on the surface of the resin layer 106B' to circulate an electric current used to obtain this electrolytic growth.

[0067] Following a step of depositing a third layer of resin on the surface of the device of [Fig.2I], not shown, we find the device 100 of [Fig.l]. The assembly formed by the resin layers 106A', 106B' and the third layer of resin corresponds to the resin layer 106 of [Fig.l].

[0068] [Fig.3A] and [Fig.3B] are sectional views of successive steps of a manufacturing method that can be applied to the device of [Fig.1].

[0069] Certain elements of Figures 3A and 3B are identical to elements of [Fig.l] and / or Figures 2A to 21, and these elements are designated by the same references and are not described again in detail.

[0070] [Fig.3A] shows the device of [Fig.2I] following an optional step of connecting a surface-mounted component 120 (SMD) to the metal tracks 119 and 119'. According to one embodiment, the surface-mounted component 120 is for example added relative to the device 100 of [Fig.1] and is integrated during the encapsulation process. The component 120 is for example soldered or glued with a conductive adhesive between the tracks 119 and 119'.

[0071] [Fig.3B] shows the device of [Fig.3A] following an optional step of depositing a layer of resin 106C to encapsulate the component 120. A resin not compatible with the LDS is for example used for this layer. The height of the layer of resin 106C is for example at least as high as the component 120 and for example higher than the component 120 to cover it to protect and insulate it.

[0072] According to an alternative embodiment to that represented by [Fig.3B], a succession of layers, for example comprising layers of nickel and / or gold, is for example deposited by electrolytic growth on the surface of the metal tracks 119 to make them stainless and no layer of resin 106C is deposited.

[0073] In the example of [Fig.l], Figures 2A to 21 and Figures 3A and 3B, a dielectric layer 105 is present between the substrate 104 and the chip 101. However, in other embodiments, the layer 105 is omitted, and the integrated circuit 101 is directly mounted on the substrate 104. It would be clear to those skilled in the art how the methods would be adapted.

[0074] During the process thus described, two series of vias 112 and 118 are successively created. An advantage of creating these two sets of vias instead of a single via is that the height of each via is reduced, making the final device more compact. This is because the aspect ratio of a via is generally limited. For example, in the case of a via formed by LDS, the aspect ratio is limited to 1:1, meaning that the height cannot exceed the diameter of the via. Creating two successive vias therefore takes up less surface area than creating a single, taller and therefore wider via. For example, when you want to form a 300pm high via, you can create two 150pm high and 150pm maximum diameter vias one above the other for a total height of 300pm and a maximum diameter of 150pm in the case where the aspect ratio is limited to 1. In comparison, a single 300pm high via would require a maximum diameter of 300pm. The surface area required for the vias is therefore effectively reduced.

[0075] [Fig.4A] and [Fig.4B] represent partial sectional views of the successive steps of a panel-embedded packaging (PEP) process for an integrated circuit 101.

[0076] Elements of figures 4A and 4B are identical to elements of figures 1 and / or 2A to 21 and / or 3A to 3B, they are designated by the same references and are not detailed again.

[0077] The PEP encapsulation method is for example used to obtain the device 200 of [Fig.2A].

[0078] During a step A, a substrate, for example a plate 301 (in English, “Wafer”) of a semiconductor material for example silicon, comprising integrated circuits (not illustrated in step A) is covered with the dielectric layer 105. The dielectric layer 105 is for example an ABF or polymer film.

[0079] During a step B, following the deposition of the dielectric layer 105, the layer 105 is for example locally opened by laser and / or etched with plasma to create perforations for example at the location of the connection terminal 123 of the integrated circuit 101 of FIGS. 1, 2A to 21 and 3A to 3B present on the plate 301. The perforations will be used to form conductive vias.

[0080] During a step C, the plate 301 from step B is then, for example, ground to remove a thickness of substrate that is unnecessary for the operation of the integrated circuits and cut to separate the integrated circuits 101 into individual electronic chips.

[0081] During a step D, following step C, the electronic chips are turned over and repositioned on a support board, for example made of stainless steel, so that the dielectric layer 105 is fixed to the board by a temporary fixing film 302.

[0082] During a step E, following step D, the chips are then for example spaced apart, the spacing between the chips is for example sufficient for the creation of future vias. 112 of [Fig.2D]. The carrier board is for example rectangular and is for example larger than a silicon wafer, for example 700mm by 700mm. The resin layer 106A is deposited to encapsulate the electronic chips.

[0083] During a step F, following the deposition of the resin layer 106A, it is for example thinned by abrasive polishing.

[0084] During a step G, following step F, the chips encapsulated in the resin 106A are detached from the support board, turned over to expose the dielectric layer 105 and their opposite face is fixed to the support board by a temporary fixing film 304. An automated optical inspection (AGI, from the English “Automatic Optical Inspection”) is for example carried out to detect defects on the chips.

[0085] During a step H, following step G, metal particles 306, for example copper and titanium, are deposited on the surface of the encapsulated chips. These particles will serve as a primer for a subsequent autocatalytic or electrocatalytic growth step.

[0086] During a step I, following the deposition of metal particles 306, a layer of photosensitive resin 308 (in English, “photoresist”) is for example deposited.

[0087] In a step J, following the deposition of layer 308, it is exposed by laser direct imaging (LDI) and developed to create openings in the dielectric layer. The use of a laser rather than a mask for this photolithography step allows adjustment of the illumination pattern of the dielectric layer. The position of the electronic chips on the support board can vary from one board to another and LDI imaging makes it possible to adapt to the variations.

[0088] During a step K, after the formation of openings, vias and metal tracks 124 are formed for example by electrolytic growth.

[0089] During a step L, after the formation of metal tracks 124, a layer of photosensitive resin 310 is for example deposited.

[0090] In a step M, the layer 310 is exposed by LDI and developed to create openings in the photoresist layer 310.

[0091] During a step N, following step M, metal tracks 128, for example made of copper, are created on the metal tracks deposited in step K, for example by electrolytic growth according to the openings in the layer 310. The tracks 128 form, for example, connection terminals.

[0092] During a step O, following step N, the layers 308 and 310 as well as the precursor particles 306 remaining under the layers 308 and 310 are removed, for example by etching.

[0093] During a step P, after the etching step, a dielectric layer 104 is deposited to encapsulate the metal tracks and vias.

[0094] During a step Q, following the deposition of the dielectric layer 104, it is for example thinned until the metal tracks 328 are visible and a succession of layers, for example comprising layers of nickel and / or gold, is for example deposited by electrolytic growth on the surface of the metal tracks 328 to make them stainless. The structure comprising two integrated circuits 101 is detached from the support board.

[0095] The method described by steps A to Q detailed in relation to Figures 4A and 4B is for example used to encapsulate the integrated circuit 101 and obtain the device 200 of [Fig.2A]. The resin used to cover the integrated circuits is then, for example, a specific resin compatible with LDS. In the example of Figures 4A and 4B, a structure comprising two integrated circuits 101 is produced. In other embodiments, a structure comprising one or more than two integrated circuits 101 side by side can be produced by the same method. The method described in relation to Figures 2A to 21 is for example applied to all of the integrated circuits 101 simultaneously, and a plurality of individual devices 100 are obtained by separating the structure, for example by laser cutting or mechanical sawing.

[0096] Alternatively, after step Q, during a step R, the electronic chips are for example separated into individual electronic chips, for example by laser cutting or mechanical sawing. In this case, the method described in relation to FIGS. 2A to 21 is applied to each electronic chip individually.

[0097] Various embodiments and variants have been described. Those skilled in the art will understand that certain features of these various embodiments and variants could be combined, and other variants will occur to those skilled in the art. In particular, the method described in Figures 2A to 21 is illustrated for a single device 100 but it could be carried out for several devices simultaneously, fixed on a common substrate and separated at the end of the method. The method is detailed for two integrated circuits 101 and 102 but can be extended to a stack of at least three integrated circuits, and in this case, a set of vias is for example produced for each integrated circuit. In addition, although an example of the formation of the device 200 of [Fig. 2A] has been detailed in relation to the methods of Figures 4A and 4B, other methods could be used to obtain this device.

Claims

Claims

1. A method comprising: - forming on a substrate (104) a first layer of a resin (106A') compatible with direct laser structuring, LDS, a first integrated circuit (101) mounted on the substrate being embedded in the first layer, the substrate comprising a first connection terminal (123) connected to the first integrated circuit and a second connection terminal (125) connected to the first connection terminal and covered by the first layer; - forming a first via (112) by LDS, the first via passing through the first layer of resin and forming an electrical contact with the second connection terminal; - mounting a second integrated circuit (102) on the first integrated circuit; - forming on the substrate a second layer (106B') of the LDS-compatible resin, the second integrated circuit being embedded in the second layer;and - the formation of a second via (118) by LDS crossing the second layer and forming an electrical contact with the first via.;

2. The method of claim 1, wherein forming the first resin layer comprises depositing an initial resin layer (106A) and a step of thinning the initial layer to obtain the first resin layer (106A').

3. A method according to any one of claims 1 to 2, wherein forming the second resin layer comprises depositing an initial resin layer (106B) and a step of thinning the initial layer to obtain the second resin layer (106B').

4. The method of any one of claims 1 to 3, further comprising adding a device (120) onto the second resin layer (106B'), the device being connected to the second via (118).

5. A method according to any one of claims 1 to 4, further comprising a step of depositing a third layer of resin on the second layer (106B').

6. A method according to any one of claims 1 to 5, wherein the first integrated circuit (101) and the second integrated circuit (102) each have a first face comprising metallizations comprising one or more connection terminals and a second face opposite the first face, the first and second integrated circuits being mounted with their second faces oriented towards each other.

7. A method according to any one of claims 1 to 6, wherein the vias (112, 117, 118) are formed by autocatalytic growth or non-electrolytic growth.

8. A method according to any one of claims 1 to 7, wherein the second via (118) is laterally offset from the first via (112).

9. A method according to any one of claims 1 to 8, wherein the height of the first resin layer (106A') is at least equal to the distance separating the second connection terminal (125) from the upper face of the first integrated circuit (101).

10. A method according to any one of claims 1 to 9, wherein the height of the second resin layer (106B') is at least equal to the distance separating the first via (112) from the upper face of the second integrated circuit (102).

11. A microelectronic device comprising: - a substrate (104); - a first integrated circuit (101) mounted on the substrate; - a first layer of a resin (106A'), compatible with structuring by direct laser structuring, LDS, deposited on the substrate and in which the first integrated circuit is incorporated; - in the substrate, a first connection terminal (123) connected to the first integrated circuit and a second connection terminal (125) connected to the first connection terminal and covered by the first layer; - a first via (112) formed by LDS, the first via passing through the first layer of resin and forming an electrical contact with the second connection terminal; - a second integrated circuit (102) mounted on the first integrated circuit; - a second layer (106B') of the resin compatible with LDS, the second integrated circuit being incorporated in the second layer;and - a second via (118) formed by LDS crossing the second layer and forming an electrical contact with the first via.;

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