Multiplier-accumulator (MAC) electronic circuit

Abstract

Title: Multiplier-accumulator type electronic circuit (MAC) Depthwise convolution electronic circuit (10), integrated on a neural network acceleration chip, and configured to perform a sequential convolution and comprising a first input (101) configured to receive an input data item (40) comprising three values, a second input (102) configured to receive a weight data item (50) comprising three times three values, a first (11), a second (12) and a third (13) sequential processing stage each comprising three multipliers configured to multiply, respectively during a first, a second and a third execution cycle, the values of an input data item respectively by the values of a weight data item, to respectively give the product values, an accumulator (103) configured to perform the addition of the product values to obtain an accumulation value Vacc,an output (106) configured to deliver the accumulation value Vacc. Figure for the abstract: Fig.2.,

Description

Title of the invention: Multiplier-accumulator (MAC) type electronic circuit Technical field

[0001] The present invention relates to the fields of neural network circuits and digital signal processing. More specifically, it relates to the architecture of a deep learning accelerator of the NVDLA type (acronym for “NVIDIA® Deep Learning Accelerator”). The invention can advantageously be implemented in neural network architectures for deep convolution or Depthwise calculations, for example for image processing (image classification, object detection, shape recognition, deep learning). STATE OF THE ART

[0002] In the field of neural network computing architectures, data convolution is a fundamental operation. It is generally performed by an accelerator. One challenge for such an accelerator is to quickly process convolution operations, while limiting the required memory size. Such an accelerator is also versatile and can support different sizes of convolution matrices or kernels.

[0003] In order to improve the performance of these accelerators, for example in image processing, convolution calculations are generally carried out using parallel processing units, generally based on multiplier-accumulator circuits (MACs). These “MAC” circuits allow convolutions to be carried out on several channels and several filter weights simultaneously via multiplier-accumulators. Each MAC circuit is typically configured to carry out an operation allowing the product of two numbers to be calculated and then the result to be aggregated with the contents of an accumulator. The operation carried out is thus typically called "multiplication-addition" or "multiplication-accumulation" or simply "MAC operation". These MAC operations are usually organized into data streams, or pipelines, where the data passes through different computational stages, such as loading the input data, performing convolutions, and storing the results. These pipelines are optimized for throughput and latency.

[0004] The NVDLA-Type Artificial Intelligence Accelerator (NVDLA Accelerator) is an open standard neural network acceleration chip written in Verilog format. The NVDLA Accelerator is based on a CK-type architecture. It is typically composed of Atomic-K multiplier-accumulator (MAC-cell) circuits in parallel, each performing atomic_C MAC operations. The NVDLA Accelerator is particularly suitable for performing convolutions in three dimensions (3D).

[0005] As illustrated in [Fig.lA], the 3D convolution is here performed between an input data of dimension H*W*C and K weight data (kernel) of dimension R*S*C each. The 3D convolution produces a data cube of dimension H'*W'*C'. The K*H*W*R*S*C MAC operations are performed in (K / atomic_K)*H*W*R*S*(C / atomic_C) iterations. Each of these iterations executes on the atomic_K x atomic_C multiplier-accumulators, in order to obtain the output data of dimension H'*W'*C' with C'= K, H' = H-(Sl) / 2 and W'=W-(Rl) / 2. This allows to reduce the necessary memory read bandwidth.

[0006] The NVDLA type artificial intelligence accelerator also allows the realization of depthwise convolution. The convolution is no longer carried out in 3D but in two dimensions (2D). This convolution method makes it possible to reduce the total quantity of operations to be carried out. The 2D convolution between C input data of dimension H*W and K weight data of dimension R*S produces a data cube H'*W'*C', with C' = C = K. The K*H*W*R*S MAC operations are carried out in (K / atomic_K)*H*W*R*S iterations, each of these iterations being executed on the Atomic-K x 1 multiplier-accumulators. This produces output data of dimensions C'*H'*W' with C'= K = C, H' = H-(Sl) / 2 and W' = W-(Rl) / 2 (illustrated in [Fig.lB]).

[0007] However, implementing this depthwise convolution on the existing NVDLA standard atomic_K*atomic_C multiplier-accumulator (MAC) results in an underutilization of a factor l / atomic_C of these. This limits the performance of an accelerator based on depthwise convolutions.

[0008] A solution to transform the dimensions of the input data in order to use the atomic_C depth of addition of multiplier-accumulator (MAC) in the NVDLA standard has been studied. However, this solution leads to the oversizing of the number of operations performed in a circuit for an execution sequence. The bandwidth is thus increased, which leads to an additional cost in terms of memory access.

[0009] An object of the present invention is therefore to propose a solution in order to improve the processing performance of depthwise convolutions in the NVDLA accelerator without changing the incoming data stream.

[0010] Other objects, features and advantages of the present invention will become apparent from the following description and accompanying drawings. It is understood that other advantages may be incorporated. SUMMARY

[0011] To achieve this objective, according to a first aspect, an electronic circuit is provided depthwise convolution circuit, hereinafter referred to as depthwise circuit, intended to be integrated on a neural network acceleration chip, and configured to sequentially convolve at least one input data by at least one weight data, said depthwise circuit comprising: - a first input configured to receive at least one input data item comprising three values ​​respectively denoted VI, V2, V3, - a second input configured to receive at least one weight data item comprising three times three values ​​respectively noted W1, W2, W3, W4, W5, W6, W7, W8, W9, - a first sequential processing stage comprising three multipliers respectively denoted M1, M2, M3, said multipliers being configured to multiply, during a first execution cycle, the values ​​VI, V2, V3 of the at least one input data item respectively by the values ​​W1, W2, W3 of the at least one weight data item, to give respectively the product values ​​A1 = V1*W1, A2 = V2*W2, A3 = V3*W3, - a second sequential processing stage comprising three multipliers respectively denoted M4, M5, M6, said multipliers being configured to multiply, during a second execution cycle, the values ​​VI, V2, V3 of the at least one input data item respectively by the values ​​W4, W5, W6 of the at least one weight data item, to give respectively the product values ​​A4 = VI* W4, A5 = V2*W5, A6 = V3*W6, - a third sequential processing stage comprising three multipliers respectively denoted M7, M8, M9, said multipliers being configured to multiply, during a third execution cycle, the values ​​VI, V2, V3 of the at least one input data item respectively by the values ​​W7, W8, W9 of the at least one weight data item, to give respectively the product values ​​A7 = V1*W7, A8 = V2*W8, A9 = V3*W9, - an accumulator comprising at least one adder, the accumulator being configured to add the product values ​​of the three stages to obtain an accumulation value, - a first pair of synchronous flip-flops between the first stage and the second stage, said synchronous flip-flops being configured to transmit respectively the at least one input data item and / or the at least one weight data item to the multipliers M4, M5, M6 of the second stage, after the second execution cycle, - a second pair of synchronous flip-flops between the second stage and the third stage, said synchronous flip-flops being configured to transmit respectively the at least one input data and / or the at least a weight data to the multipliers M7, M8, M9 of the third stage, after the third execution cycle, - an output configured to deliver the accumulation value.

[0012] The integration of such a circuit specialized in the calculation of depthwise convolution in the NVDLA accelerator allows an optimization of the memory bandwidth. This circuit also makes it possible to limit the loss of performance compared to a classic 2D or depthwise convolution. Indeed, the depthwise circuit according to the invention advantageously makes it possible to carry out 9 multiplications and additions, or MAC operations, per cycle on each depthwise circuit, while only one MAC operation per cycle is carried out by a classic depthwise convolution circuit. This increases the computing capacity compared to known depthwise convolution solutions.

[0013] Thus, the use of a depthwise circuit according to the invention in an accelerator to the NVDLA standard makes it possible to improve depthwise type convolutions. The memory bandwidth is improved.

[0014] Another aspect relates to a system comprising Atomic-K depthwise circuits according to the invention, dedicated to the calculation of depthwise or 2D convolution. The integration of Atomic-K depthwise circuits makes it possible to have a total calculation capacity of Atomic-K*9 MAC operations per cycle. These operations being carried out in parallel, this also makes it possible to optimize the throughput and reduce the latency during depthwise convolution carried out in the NVDLA accelerator.

[0015] According to one possibility, the system further comprises Atomic-K * 9 multiplier-accumulator (MAC), preferably to the NVDLA standard, dedicated to 3D convolution calculation. The input data for this system can thus be processed either by a 3D convolution calculation or by a depthwise convolution calculation.

[0016] The addition of depthwise circuits according to the invention can be carried out by retaining the MAC circuits already present in the NVDLA type deep learning accelerator, without modifying them. Such a system integrated into the NVDLA accelerator is more versatile. This makes it possible to optimize the convolution calculation, either by depthwise convolution or by 3D convolution, depending on the needs.

[0017] Another aspect relates to a digital signal processing method implemented by the depthwise circuit according to the invention, comprising: - At least one weight data initialization phase including: • During a first execution cycle: • provide three values ​​W7, W8, W9 of the weight data to the multipliers M1, M2, M3 of the first stage and to one of the synchronous flip-flops of the first pair, called the first weight flip-flop, During a second execution cycle: • Supply, via said first weight scale, the three values ​​W7, W8, W9 of the weight data to the multipliers M4, M5, M6 of the second stage and to one of the synchronous flip-flops of the second pair, called the second weight scale, • provide three values ​​W4, W5, W6 of the weight data to the multipliers M1, M2, M3 of the first stage and to the first weight scale, • During a third execution cycle: • Supply, via said second weight scale, the three values ​​W7, W8, W9 of the weight data to the multipliers M7, M8, M9 of the third stage, • Supply, via the first weight scale, the three values ​​W4, W5, W6 of the weight data to the multipliers M4, M5, M6 of the second stage and to the second weight scale, • provide three values ​​Wl, W2, W3 of the weight data to the multipliers Ml, M2, M3 of the first stage and to the first weight scale, At least one input data processing phase including: • During a first execution cycle: • provide three values ​​VI, V2, V3 of a first input data to the multipliers M1, M2, M3 of the first stage and to the other of the synchronous flip-flops of the first pair, called the first data flip-flop, • During a second execution cycle: • Supply, via said first data flip-flop, the three values ​​VI, V2, V3 of the first input data to the multipliers M4, M5, M6 of the second stage and to the other of the synchronous flip-flops of the second pair, called the second data flip-flop, • provide three values ​​VI', V2', V3' of a second input data to the multipliers Ml, M2, M3 of the first stage and to the first data flip-flop, • During a third execution cycle: • Supply, via said second data flip-flop, the three values ​​VI, V2, V3 of the first input data to the multipliers M7, M8, M9 of the third stage, • Supply, via the first data flip-flop, the three values ​​VI', V2', V3' of the second input data to the multipliers M4, M5, M6 of the second stage and to the second data flip-flop, • provide three values ​​VI”, V2”, V3” of a third input data to the multipliers Ml, M2, M3 of the first stage and to the first data flip-flop, • calculate, via the multipliers M1-M9, the product values ​​Al” =V1”*W1, A2” = V2”*W2, A3” = V3”*W3, A4' = V1'*W4, A5' = V2'*W5, A6' = V3'*W6, A7 = V1*W7, A8 = V2*W8, A9 = V3*W9, • calculate, via the accumulator, an accumulation value from the sum of the product values ​​A1”, A2”, A3”, A4', A5', A6', A7, A8, A9, • During an i-th following execution cycle (i=4 to N): • Supply, via the second data flip-flop, the three values ​​of the (i-2)-th input data to the multipliers M7, M8, M9 of the third stage, • Supply, via the first data flip-flop, the three values ​​of the (i-1)-th input data to the multipliers M4, M5, M6 of the second stage and to the second data flip-flop, • provide three values ​​of an i-th input data to the multipliers M1, M2, M3 of the first stage and to the first data flip-flop, • calculate, via the multipliers M1-M9, the corresponding product values, • calculate, via the accumulator, an (i-2)-th accumulation value from the sum of said corresponding product values. BRIEF DESCRIPTION OF THE FIGURES

[0018] The aims, objects, as well as the characteristics and advantages of the invention will emerge more clearly from the detailed description of an embodiment thereof which is illustrated by the following accompanying drawings in which:

[0019] [Fig.lA] Figures 1A and 1B respectively represent the 3D convolution and the 2D convolution of input data by K weight data.

[0020] [Fig.lB]

[0021] [Fig.2] [Fig.2] represents the electronic circuit of convolution in depth or depthwise according to an exemplary embodiment of the invention.

[0022] [Fig.3] [Fig.3] represents the system according to an exemplary embodiment of the invention.

[0023] [Fig.4] [Fig.4] represents the digital signal processing method implemented implemented by the circuit according to an exemplary embodiment of the invention.

[0024] [Fig.5] [Fig.5] represents a filtering carried out on a weight data according to an exemplary embodiment of the invention.

[0025] The drawings are given as examples and are not limiting of the invention. They constitute schematic representations of principle intended to facilitate the understanding of the invention and are not necessarily on the scale of practical applications. DETAILED DESCRIPTION

[0026] Before beginning a detailed review of embodiments of the invention, optional features which may possibly be used in combination or alternatively are set out below.

[0027] According to one example, the first and second pairs of synchronous flip-flops are configured to assign the different values ​​of the at least one input data item and the at least one weight data item to the different multipliers of each stage. The input and weight data can thus pass from one stage to the other according to the configured pipeline. The memory resources are directly managed within the circuit, without impact on other components of the NVDLA IP.

[0028] According to one example, the different values ​​of the at least one input data item and the at least one weight data item are all coded in n bits (n = 8, 16, 32), and in which the accumulation value Vacc is coded in 3*n bits. This coding makes it possible to use the same data stream as for the 3D convolution normally carried out in conventional NVDLA circuits.

[0029] According to one example, the flip-flops of the first and second flip-flop pairs are D-type flip-flops. This ensures a stable output state between two execution cycle edges. This also allows bandwidth optimization.

[0030] According to one example, the accumulator comprises at least two adders, preferably eight adders. This makes it possible to perform partial summations after each stage, possibly at the output of each multiplier.

[0031] According to one example, the adders are parallel carry-ahead adders. This makes it possible to produce the partial products in parallel and not one by one, while avoiding increasing the size of the circuit.

[0032] According to one example, the accumulator comprises eight adders, typically: a first accumulator configured to perform the operation A1 + A2 = A12, a second accumulator configured to perform the operation A12 + A3 = A123, a third accumulator configured to perform the operation A4 + A5 = A45, a fourth accumulator configured to perform the operation A45 + A6 = A456, a fifth accumulator configured to perform the operation A7 + A8 = A78, a sixth accumulator configured to perform the operation A78 + A9 = A789, a seventh accumulator configured to perform the operation A123 + A456 = A16, an eighth accumulator configured to perform the operation A16 + A789 = A19.

[0033] According to one example, the system includes a first set of depthwise Atomic-K circuits dedicated to a two-dimensional (2D) convolution calculation, and a second set of NVDLA-standard Atomic-K multiplier-accumulator circuits, dedicated to a three-dimensional (3D) convolution calculation. According to one example, the system is configured such that one of the first and second sets receives the at least one input data and the at least one weight data.

[0034] According to one example, the system comprises at least two circuit flip-flops configured to respectively assign the input data and the weight data to one of the first and second sets.

[0035] According to an example, the system further comprises at least one filter associated with at least one depthwise circuit, said at least one filter being configured to decompose a weight data item comprising more than three times three values ​​at the input of the filter, into several sub-weight data items comprising three times three values ​​at the output of the filter, said output of the filter being connected to the second input of the depthwise circuit. This allows the depthwise circuit to support any size of weight data item.

[0036] According to an example, an accumulation value Vacc is calculated during each n-th execution cycle (n=3 to N) of the input data processing phase, after the first two execution cycles intended to provide input data values ​​to all the multipliers M1-M9. This makes it possible, after three initialization cycles, to carry out nine multiplications and additions simultaneously per cycle in order to obtain an output data item.

[0037] According to one example, the at least one phase of initializing the weight data is performed before the at least one phase of processing the input data. This makes it possible to load a convolution kernel or kernel prior to processing a plurality of input data.

[0038] According to one example, the at least one phase of initializing the weight data is performed periodically during the at least one phase of processing the input data. This optionally makes it possible to change the convolution kernel for processing the input data.

[0039] According to an example, when a weight data item comprises more than three times three values, said weight data item is decomposed into several weight sub-data items comprising three times three values ​​and said weight sub-data are provided to the multipliers M1-M9. Filtering allows to support any size of weight data.

[0040] According to one example, the decomposition of the weight data consists of adding zero values ​​to the weight data, then dividing the weight data to form the weight sub-data comprising three times three values. This makes it possible to have weight data in the expected format, i.e. three times three values.

[0041] In the following description, the term "flip-flop" is used. A flip-flop is understood as a logic circuit capable, under certain circumstances, of maintaining the values ​​of its outputs despite changes in input values, i.e. comprising a memory state thus allowing the transition from combinational logic to sequential logic.

[0042] In the following description the terms "MAC" and "MAC-cell" are used. These terms relate to the calculation of the product of two numbers and the aggregation of the result to the contents of an accumulator. The operation itself (multiplication-addition) is often abbreviated as MAC or "MAC operation". A "MAC-cell" is a calculation block that performs C MAC operations; those skilled in the art are perfectly capable of determining what "MAC" refers to in its context of use. The electronic circuit that performs this operation is called a "multiplier-accumulator circuit".

[0043] In the application, the parameters K, atomic_K, C, atomic_C are notably used. Atomic-K is the number of MAC cells in the accelerator.

[0044] K is a data dimension, it is the number of kernels involved in the convolution calculation (see for example [Fig.lB]).

[0045] Atomic-K also corresponds to the number of kernels processed in parallel in the accelerator. The convolution operation typically requires K / Atomic-K MAC operations.

[0046] C is a data dimension (see for example [Fig. 1 A]). Atomic_C is the number of MAC operations per MAC cell.

[0047] The total number of MAC operations performed in parallel is therefore Atomic_C*Atomic_K.

[0048] In the following description, the term "execution cycle" is used. An execution cycle is understood as a clock cycle corresponding to a period of an oscillating electrical signal which sets the rhythm for the actions of a circuit. Thus, at each clock or execution cycle, calculations can be performed using the flip-flop outputs. The clock ensures that the data is valid at the next clock cycle, i.e. that the calculations are completed and the results stabilized. The flip-flops used here have a "Clock" input and are typically called "synchronous".

[0049] The NVDLA standard (acronym for “NVIDIA Deep Learning Accelerator” if NVIDIA Deep Learning Accelerator (NVIDIA Open NVDLA License) is an open standard (NVIDIA Open NVDLA License) for neural network acceleration chips for deep learning, created by NVIDIA. The processor of this NVDLA standard is written in Verilog format (hardware description language for logic circuits).

[0050] The present invention relates to an electronic circuit for depth convolution, hereinafter referred to as depthwise circuit 10. The depthwise circuit 10 makes it possible to perform MAC operations optimized for depthwise or two-dimensional (2D) convolutions. It thus allows the calculation of depthwise convolution by passing data through a three-stage pipeline comprising nine operators.

[0051] The depthwise circuit 10 will now be described according to several exemplary embodiments with reference to [Fig.2].

[0052] The depthwise circuit 10 is intended to be integrated on a neural network acceleration chip. The depthwise circuit 10 is configured to sequentially convolve at least one input data 40 by at least one weight data 50.

[0053] The depthwise circuit 10 thus comprises a first input 101. According to one example, the first input 101 is configured to receive the at least one input data 40.

[0054] The at least one input data 40 comprises three values ​​respectively denoted VI, V2, V3. According to one example, the three values ​​respectively denoted VI, V2, V3 can be represented in a matrix format of a column of three lines.

[0055] The depthwise circuit 10 also comprises a second input 102. According to one example, the second input 102 is configured to receive the at least one data item of weight 50.

[0056] The at least one data item of weight 50 comprises three times three values ​​respectively denoted W1, W2, W3, W4, W5, W6, W7, W8, W9. According to one example, the three times three values ​​denoted W1, W2, W3, W4, W5, W6, W7, W8, W9 can be represented in a matrix format of three columns of three rows.

[0057] The depthwise circuit 10 is structured as a three-stage pipeline. It comprises a first sequential processing stage 11, a second sequential processing stage 12, and a third sequential processing stage 13.

[0058] According to an example, the first stage 11 comprises three multipliers respectively denoted M1, M2, M3. The three multipliers M1, M2, M3 can be configured to multiply respectively, during a first execution cycle, the values ​​VI, V2, V3 of the at least one input data item 40 respectively by the values ​​W1, W2, W3 of the at least one weight data item 50. Thus, the multiplication operation carried out by the three multipliers M1, M2, M3 can respectively give product values ​​A1 = V1*W1, A2 = V2*W2 and A3 = V3*W3. The multiplier M1 typically carries out the multiplication between the value VI of the at least one input data item 40 by the value W1 of the at least one data item of weight 50 during the first execution cycle to give the product value A1. Similarly, the multiplier M2 typically performs the multiplication between the value V2 of the at least one input data item 40 by the value W2 of the at least one data item of weight 50 during the first execution cycle to give the product value A2. Similarly, the multiplier M3 typically performs the multiplication between the value V3 of the at least one input data item 40 by the value W3 of the at least one data item of weight 50 during the first execution cycle to give the product value A3.

[0059] According to an example, the second sequential processing stage 12 has an architecture similar to that of the first sequential processing stage 11, and comprises three multipliers respectively denoted M4, M5, M6. The three multipliers M4, M5, M6 can be configured to multiply, during a second execution cycle, the values ​​VI, V2, V3 of the at least one input data item 40 respectively by the values ​​W4, W5, W6 of the at least one weight data item 50. Thus, the multiplication operation carried out by the three multipliers M4, M5, M6 can respectively give product values ​​A4 = V1*W4, A5 = V2*W5 and A6 = V3*W6. The multiplier M4 typically performs the multiplication between the value VI of the at least one input data 40 by the value W4 of the at least one data of weight 50 during the second execution cycle to give the product value A4.Similarly, the multiplier M5 typically performs the multiplication between the value V2 of the at least one input data item 40 by the value W5 of the at least one data item of weight 50 during the second execution cycle to give the product value A5. Similarly, the multiplier M6 typically performs the multiplication between the value V3 of the at least one input data item 40 by the value W6 of the at least one data item of weight 50 during the second execution cycle to give the product value A6.

[0060] According to an example, the third sequential processing stage 13 has an architecture similar to those of the first and second sequential processing stages 11, 12, and comprises three multipliers respectively denoted M7, M8, M9. The three multipliers M7, M8, M9 can be configured to multiply, during a third execution cycle, the values ​​VI, V2, V3 of the at least one input data item 40 respectively by the values ​​W7, W8, W9 of the at least one weight data item 50. Thus, the multiplication operation carried out by the three multipliers M7, M8, M9 can respectively give product values ​​A7 = V1*W7, A8 = V2*W8 and A9 = V3*W9. The multiplier M7 typically performs the multiplication between the value VI of the at least one input data 40 by the value W7 of the at least one data of weight 50 during the third execution cycle to give the product value A7.Similarly, the multiplier M8 typically performs the multiplication between the value V2 of the at least one input data 40 by the value W8 of the at least one . data of weight 50 during the third execution cycle to give the product value A8. Similarly, the multiplier M9 typically performs the multiplication between the value V3 of the at least one input data 40 by the value W9 of the at least one data of weight 50 during the third execution cycle to give the product value A9.

[0061] The depthwise circuit 10 comprises an accumulator 103. The accumulator 103 comprises at least one adder 1030, preferably the accumulator 103 comprises a plurality of adders 1030. The accumulator 103 is configured to perform the addition of the product values ​​A1, A2, A3, A4, A5, A6, A7, A8 and A9. Thus, the addition of the product values ​​A1, A2, A3, A4, A5, A6, A7, A8 and A9 makes it possible to obtain an accumulation value Vacc. According to one example, the accumulator 103 comprises at least two adders 1030. Preferably, the accumulator 103 comprises eight adders 1030. The use of several adders 1030 makes it possible to calculate a result in a time logarithmic to the size of the inputs. This also helps to limit the increase in operators.

[0062] According to one example, the adders 1030 are parallel carry-ahead adders 1030. These adders 1030 are configured to accelerate multiple additions and thus allow the sums of the partial products to be performed in parallel with adders connected in series. The additions performed by the eight adders 1030 are thus performed simultaneously in order to give the accumulation value Vacc.

[0063] According to an example, the first adder 1030 performs the addition of the product values ​​A1 and A2, the second adder 1030 performs the addition of the product value A3 with the result from the first adder 1030, the third adder 1030 performs the addition of the product values ​​A4 with A5, the fourth adder 1030 performs the addition between the result obtained by the third adder 1030 with the product value A6, the fifth adder 1030 performs the addition between the product values ​​A7 and A8, the sixth adder 1030 performs the addition between the result obtained at the fifth adder 1030 and the product value A9, the seventh adder 1030 performs the addition between the results of the second and fourth adder 1030, and the eighth adder 1030 performs the addition between the results obtained at the sixth adder 1030 and the seventh adder 1030.Thus, the eighth adder 1030 makes it possible to obtain the accumulation value Vacc.

[0064] The depthwise circuit 10 also includes a first pair of flip-flops 104a, 104b. In the following, it is considered, without limitation, that the first pair of flip-flops 104a, 104b includes a flip-flop 104a and a flip-flop 104b. According to one example, the flip-flops 104a, 104b are synchronous flip-flops. The flip-flops 104a, 104b are placed between the first and second stages 11, 12 of the pipeline. They are configured to sequentially transmit, during a clock cycle, input data 40 and / or weight data 50 to the multipliers M4, M5, M6 of the second stage 12. According to one example, the flip-flop 104a makes it possible to transmit at least one input data 40 to the multipliers M4, M5, M6. Similarly, the flip-flop 104b can transmit at least one weight data 50 to the multipliers M4, M5, M6. The sequential operation and the different execution cycles for processing the weight data 50 and the input data 40 are explained below.

[0065] The depthwise circuit 10 further comprises a second pair of flip-flops 105a, 105b. In the following, it is considered, without limitation, that the second pair of flip-flops 105a, 105b comprises a flip-flop 105a and a flip-flop 105b. According to one example, the flip-flops 105a, 105b are synchronous flip-flops. The flip-flops 105a, 105b are placed between the second and third stages 12, 13 of the pipeline. They are configured to sequentially transmit, during a clock cycle, input data 40 and / or weight data 50 to the multipliers M7, M8, M9 of the third stage 13. The flip-flops 105a, 105b are respectively connected in series to the flip-flops 104a, 104b. The flip-flop 105a typically receives as input the at least one input data 40 transferred by the flip-flop 104a. The flip-flop 105a then transmits the at least one input data 40 to the multipliers M7, M8, M9.Similarly, flip-flop 105b typically receives as input the at least one data item of weight 50 transferred by flip-flop 104b. Flip-flop 105b then transmits the at least one data item of weight 50 to multipliers M7, M8, M9.

[0066] According to an example, the first pair of synchronous flip-flops 104a, 104b is configured to assign the different values ​​VI, V2, V3 of the at least one input data item 40 and the different values ​​W1, W2, W3, W4, W5, W6, W7, W8, W9 of the at least one data item of weight 50 to the multipliers M4, M5, M6 of the second stage 12. Similarly, according to an example, the second pair of synchronous flip-flops 105a, 105b is configured to assign the different values ​​VI, V2, V3 of the at least one input data item 40 and W1, W2, W3, W4, W5, W6, W7, W8, W9 of the at least one data item of weight 50 to the different multipliers M7, M8, M9 of the third stage 13.

[0067] According to one example, the flip-flops 104a, 104b, 105a, 105b of the first and second pairs of flip-flops are D-type flip-flops. Typically, D-type flip-flops have only one data input. The value of the input is thus copied to the output at each execution cycle. The D-type flip-flops make it possible to ensure a stable output state between two execution cycles, and to ignore any transient value appearing on their inputs during an additional cycle. Other electronic elements making it possible to record the data and transmit it to the upper stage after an execution cycle could be used.

[0068] Therefore, according to one example, the values ​​VI, V2, V3 of the at least one input data 40 enter the flip-flop 104a of the first pair of flip-flops during a first cycle and come out identically from the flip-flop 104a of the first pair of flip-flops during a second cycle. Similarly, the values ​​VI, V2, V3 of the at least one input data 40 enter the flip-flop 105a of the second pair of flip-flops during the second cycle and come out identically from the flip-flop 105a of the second pair of flip-flops during the third cycle. The flip-flops 104a, 105a thus allow optimization of the bandwidth thanks to the redundancy of input data 40. The flip-flops 104b and 105b act in a similar manner with the values ​​of the at least one data item of weight 50. The flip-flops 104b and 105b thus typically allow the values ​​W7, W8, W9 of the data item of weight 50 to be routed to the multipliers M7, M8, M9.The flip-flop 104b typically allows the values ​​W4, W5, W6 of the data of weight 50 to be routed to the multipliers M4, M5, M6. The loading of the different values ​​W1, W2, W3, W4, W5, W6, W7, W8, W9 of the data of weight 50 onto the multipliers M1, M2, M3, M4, M5, M6, M7, M8, M9 is described in more detail below.

[0069] The depthwise circuit 10 also includes an output 106. The output 106 is configured to output the accumulation value Vacc. Thus, the accumulator 103 calculates the accumulation value Vacc to provide it to the output 106.

[0070] According to one example, the different values ​​VI, V2, V3 of the at least one input data item 40 are all coded in n bits. Similarly, the different values ​​W1, W2, W3, W4, W5, W6, W7, W8, W9 of the at least one weight data item 50 are all coded in n bits. The different values ​​are coded so that they can be calculated by the multipliers M1, M2, M3, M4, M5, M6, M7, M8, M9 of the three stages 11, 12, 13. Thus the multipliers M1, M2, M3, M4, M5, M6, M7, M8, M9 are configured to perform operations on n bits. According to an example, n can be equal to 8, or to 16 or to 32. Thus, the accumulation value Vacc resulting from the nine MAC operations carried out in the depthwise circuit 10 can be coded in 3 xn bits. The digital signal processing method implemented by the depthwise circuit 10 will now be described with reference to [Fig.3]. This so-called calculation method is implemented to calculate the accumulation value Vacc.

[0071] According to one example, the method for calculating the accumulation value Vacc comprises at least one phase of initializing the weight data 50 and at least one phase of processing the input data 40. The phase of initializing the weight data 50 makes it possible to send the values ​​W1, W2, W3, W4, W5, W6, W7, W8, W9 of the weight data 50 to the corresponding multipliers M1, M2, M3, M4, M5, M6, M7, M8, M9. The phase of initializing the weight data 50 is preferably carried out before the at least one phase of processing the input data 40. This corresponds ty loading a convolution filter prior to processing all the data of an image by this same convolution filter. According to one possibility, if the image processing must change, the at least one phase of initialization of the weight data 50 can be carried out periodically during the at least one phase of processing the input data 40.

[0072] According to an example, the initialization phase of the weight data 50 comprises three execution cycles. During a first execution cycle, three values ​​W7, W8, W9 of the weight data 50 can be supplied 110 to one of the synchronous flip-flops of the first pair, called the first weight flip-flop 104b. During this first cycle, the three values ​​W7, W8, W9 of the weight data 50 can also be supplied 110 to the multipliers M1, M2, M3 of the first stage 11.

[0073] During a second execution cycle following the first execution cycle, two actions can be performed simultaneously or successively. The first action consists of supplying 120, via said first weight flip-flop 104b, the three values ​​W7, W8, W9 of the weight data 50 to one of the synchronous flip-flops of the second pair, called second weight flip-flop 105b, and possibly to the multipliers M4, M5, M6 of the second stage 12. The second action consists of supplying 121 three values ​​W4, W5, W6 of the weight data 50 to the first weight flip-flop 104b, and possibly to the multipliers M1, M2, M3 of the first stage 11.

[0074] During a third execution cycle, three actions can be performed simultaneously or successively. The first action can consist of providing 130, via said second weight flip-flop 105b, the three values ​​W7, W8, W9 of the weight data 50 to the multipliers M7, M8, M9 of the third stage 13. The second action can consist of providing 131, via the first weight flip-flop 104b, the three values ​​W4, W5, W6 of the weight data to the multipliers M4, M5, M6 of the second stage 12, and possibly to the second weight flip-flop 105b. The third action can consist of providing 132 three values ​​W1, W2, W3 of the weight data 50 to the multipliers M1, M2, M3 of the first stage 11, and possibly to the first weight flip-flop 104b.

[0075] According to an example, at the end of the third execution cycle, the weight value W1 is recorded on the register allocated to the multiplier M1, the weight value W2 is recorded on the register allocated to the multiplier M2, the weight value W3 is recorded on the register allocated to the multiplier M3, the weight value W4 is recorded on the register allocated to the multiplier M4, the weight value W5 is recorded on the register allocated to the multiplier M5, the weight value W6 is recorded on the register allocated to the multiplier M6, the weight value W7 is recorded on the register allocated to the multiplier M7, the weight value W8 is recorded on the register allocated to the multiplier M8, the weight value W9 is recorded on the register allocated to the multiplier M9. plus the values ​​Wl, W2, W3 can be recorded on the first weight scale 104b and the values ​​W4, W5, W6 can be recorded on the second weight scale 105b.

[0076] According to one example, the method for calculating the accumulation value Vacc comprises at least one phase of processing the input data 40. The input data 40 may be in the form of a first input data item comprising the values ​​VI, V2, V3, a second input data item comprising the values ​​VI', V2', V3', a third input data item comprising the values ​​VI”, V2”, V3”. The processing phase typically makes it possible to send the values ​​VI, V2, V3, VI', V2', V3', VI”, V2”, V3” of the input data 40 to the corresponding multipliers M1, M2, M3, M4, M5, M6, M7, M8, M9.

[0077] According to one example, the input data processing phase 40 comprises at least three execution cycles. Preferably, the input data processing phase 40 comprises strictly more than three execution cycles.

[0078] According to an example, during a first execution cycle three values ​​VI, V2, V3 of a first input data item are supplied 210 to the multipliers M1, M2, M3 of the first stage 11. These same three values ​​VI, V2, V3 are also supplied 210 to the other of the synchronous flip-flops of the first pair, called first data flip-flop 104a.

[0079] During a second execution cycle, two actions can be performed simultaneously or successively. The first action can consist of supplying 220, via said first data flip-flop 104a, the three values ​​VI, V2, V3 of the first input data 40 to the multipliers M4, M5, M6 of the second stage 12 and to the other of the synchronous flip-flops of the second pair, called second data flip-flop 105a. The second action can consist of supplying 221 three values ​​VI', V2', V3' of a second input data 40 to the multipliers M1, M2, M3 of the first stage 11 and to the first data flip-flop 104a.

[0080] During a third execution cycle, three actions can be performed simultaneously or successively. The first action can consist of supplying 230, via said second data flip-flop 105a, the three values ​​VI, V2, V3 of the first input data 40 to the multipliers M7, M8, M9 of the third stage 13. The second action can consist of supplying 231, via the first data flip-flop 104a, the three values ​​VI', V2', V3' of the second input data 40 to the multipliers M4, M5, M6 of the second stage 12 and possibly to the second data flip-flop 105a. The third action can consist of supplying 232 three values ​​VI”, V2”, V3” of a third input data 40 to the multipliers M1, M2, M3 of the first stage 11 and possibly to the first data flip-flop 104a.

[0081] According to an example, at the end of actions 230, 231, 232, the data value VI” is in recorded on the multiplier M1, the data value V2” is recorded on the multiplier M2, the data value V3” is recorded on the multiplier M3, the data value V4' is recorded on the multiplier M4, the data value V5' is recorded on the multiplier M5, the data value V6' is recorded on the multiplier M6, the data value V7 is recorded on the multiplier M7, the data value V8 is recorded on the multiplier M8, the data value V9 is recorded on the multiplier M9. In addition, the values ​​VI”, V2”, V3” can be recorded on the first data flip-flop 104a and the values ​​VI', V2', V3' can be recorded on the second data flip-flop 105a.

[0082] According to an example, during the third execution cycle, after the supply 230, 231, 232 of the values ​​of the first, second and third input data 40, at least one calculation 233 is carried out. The calculation 233 can be carried out via the multipliers M1-M9 and can correspond to the multiplication of the values ​​of the weight data 50 and the values ​​of the input data 40 supplied to the multipliers M1-M9. Thus the calculation 233 makes it possible to obtain the product values ​​A1” = V1”*W1, A2” = V2”*W2, A3” = V3”*W3, A4' = V1'*W4, A5' = V2'*W5, A6' = V3'*W6, A7 = V1*W7, A8 = V2*W8, A9 = V3*W9.

[0083] According to an example, during the third execution cycle, a calculation 234 is performed after the calculation 233. The calculation 234 can be performed via the accumulator 103 and can correspond to the addition of the product values ​​A1”, A2”, A3”, A4', A5', A6', A7, A8, A9. The calculation 234 can thus make it possible to obtain an accumulation value Vacc from the sum of the product values ​​A1”, A2”, A3”, A4', A5', A6', A7, A8, A9. According to one possibility, the calculation 234 can be performed by several adders 1030.

[0084] According to an example, during an i-th execution cycle three actions can again be performed simultaneously or successively. The first action can consist of supplying 2i0, via the second data flip-flop 105a, the three values ​​of the (i-2)-th input data 40 to the multipliers M7, M8, M9 of the third stage 13. The second action can consist of supplying 2il, via the first data flip-flop 104a, the three values ​​of the (i-1)-th input data 40 to the multipliers M4, M5, M6 of the second stage 12, and possibly to the second data flip-flop 105a. The third action can consist of supplying 2i2 three values ​​of an i-th input data 40 to the multipliers M1, M2, M3 of the first stage 11, and possibly to the first data flip-flop 104a.

[0085] According to an example, during the i-th execution cycle, after the supply 2i0, 2il, 2i2 of the values ​​of the (i-2)-th, (i-1)-th and i-th input data 40, at least one calculation 2i3 is carried out. The calculation 2i3 can be carried out via the multipliers M1-M9 and can correspond to the multiplication of the values ​​of the weight data 50 and the data input 40 supplied to the multipliers M1-M9. Thus the calculation 2i3 makes it possible to obtain the corresponding product values.

[0086] According to one example, during the i-th execution cycle, a 2i4 calculation is performed after the 2i3 calculation. The 2i4 calculation can be performed via the accumulator 103 and typically corresponds to the addition of the corresponding product values. The 2i4 calculation can thus make it possible to obtain an accumulation value Vacc from the sum of the product values ​​obtained during the 2i3 calculation. According to one possibility, the 2i4 calculation can be performed by several adders 1030.

[0087] Thus, according to an example, an accumulation value Vacc is calculated during each n-th execution cycle (n=3 to N) of the input data processing phase 40. More precisely, an accumulation value Vacc is calculated after the first two execution cycles intended to provide input data values ​​40 to all the multipliers M1-M9. The accumulation value Vacc can then be provided to the output 106, during each n-th execution cycle (n=3 to N).

[0088] According to one example, the depthwise circuit 10 is intended to be associated with a multiplier-accumulator circuit 20 (MAC cell) integrated on a neural network acceleration chip. The two circuits 10, 20 are configured to be used independently of each other. In particular, the circuit 20 is envisaged as an alternative to the circuit 10 for convolution processing. The two circuits 10, 20 thus correspond to two complementary possibilities for convolution calculation. Preferably, the multiplier-accumulator circuit 20 is a 3D convolution circuit to the NVDLA standard, called MAC cell 20 standard. The system 1 may comprise Atomic-K standard MAC cell 20 circuits and Atomic-K depthwise circuits 10. Such a system 1 is illustrated in [Fig.4].

[0089] According to an example, in system 1, there are as many conventional multiplier-accumulator circuits 20 as depthwise circuits 10. In operation, the standard MAC cell circuits 20 or the depthwise circuits 10 are used depending on the type of convolution to be performed. Thus, for the calculation of 2D convolutions the Atomic-K depthwise circuits 10 can be used. For the calculation of other types of convolutions, in particular 3D convolutions, the Atomic-K multiplier-accumulator circuits can be used.

[0090] According to an example, the system 1 comprises circuit flip-flops 70. The circuit flip-flops 70 advantageously make it possible to select the Atomic-K depthwise circuits 10 or the Atomic-K multiplier-accumulator circuits 20. Thus, the circuit flip-flops 70 can be positioned before the data inputs 101, 102. At least one circuit flip-flop among the circuit flip-flops 70 can transmit the input data 40 either to the first input 101 of the depthwise circuit 10, or to a data input 201 of the Atomic-K multiplier-accumulator circuits 20. Similarly, at least one flip-flop among the circuit flip-flops 70 can transmit the data of weight 50 either to the second input 102 of the depthwise circuit 10, or to a weight input 202 of the Atomic-K multiplier-accumulator circuits 20. Thus, the calculation of the convolutions in the system 1 is managed either by the depthwise circuits 10, or by the standard multiplier-accumulator circuits 20. Advantageously, the standard multiplier-accumulator circuits integrated in the NVDLA environment are retained, and the depthwise circuits are added as an alternative. This makes it possible to avoid too significant a modification of the system while making it possible to optimize the convolution calculation. The Atomic-K depthwise circuit(s) 10 according to the invention advantageously make it possible to optimize a convolution processing, in substitution for the standard multiplier-accumulator circuits in particular.

[0091] According to an example, the calculated accumulation value Vacc 234, 2i4 is provided 235, 2i5 at output 106 of the depthwise circuit 10. The accumulation value Vacc can be of the same format as the data calculated at output 206 of a standard multiplier-accumulator circuit 20.

[0092] As indicated previously, the architecture of the depthwise circuit 10 makes it possible to support data of weight 50 of size comprising three times three values. In order to support larger data sizes of weight 50, the system 1 may further comprise at least one filter 30. The at least one filter 30 may be associated with at least one depthwise circuit 10. In the following, it is considered, without limitation, that a filter 30 is associated with the Atomic-K depthwise circuits 10.

[0093] According to an example illustrated in [Fig.5], the filter 30 is configured to decompose 500 a weight data 50 comprising more than three times three values ​​at the input 301 of the filter 30, into several sub-weight data 501a, 501b, 501c, 501d comprising three times three values ​​at the output 302 of the filter 30. The output 302 of the filter 30 is typically connected to the second input 102 of the depthwise circuit 10. The depthwise circuit 10 preceded by the filter 30 can thus support weight data 50 of different sizes. The size of the weight data 50 is not a limiting factor for the implementation of the depthwise circuit 10 and / or the system 1. The use of such a filter 30 also makes it possible to minimize the use of hardware resources.

[0094] As illustrated in [Fig.5], in order to produce the weight sub-data 501a, 501b, 501c, 501d, the decomposition 500 of the weight data 50 consists of: - adding zero values ​​to the weight data 50, - cutting the weight data 50 to form the weight sub-data 501a, 501b, 501c, 501d comprising three times three values.

[0095] The weight sub-data 501a, 501b, 501c, 501d can then be provided to the multipliers M1-M9. The calculation method is then the same as described previously. The calculation method is therefore not limited by the size of the data of 50 weight supported, while maintaining increased performance.

[0096] From the above, it appears that the invention provides a particularly effective solution for the convolutional processing of data in NVDLA standard neural network acceleration circuits.

[0097] DIGITAL REFERENCES 1: System 10: depthwise circuit 101: first entry 102: second entrance 11: first floor 12: second floor 13: third floor 103: accumulator 1030: adder Vacc: accumulation value 104a, 104b: first pair of flip-flops 104a: first data switch 104b: first weight shift 105a, 105b: second pair of flip-flops 105a: second data flip-flop 105b: second weight shift 106: exit 20: multiplier-accumulator circuit 201: Multiplier-accumulator circuit data input 202: weight input multiplier-accumulator circuit 206: output of the multiplier-accumulator circuit 30: filter 301: filter input 302: filter output 40: input data 50: weight data 500: breakdown of weight data 501a, 501b, 501c, 501d: weight subdata 70: circuit switch 110: supply of three values ​​W7, W8, W9 of the weight data to the multipliers M1, M2, M3 of the first stage and to one of the synchronous flip-flops of the first pair, called the first weight flip-flop. 120: supply via said first weight scale, of the three values ​​W7, W8, W9 of the weight data to the multipliers M4, M5, M6 of the second stage and to one of the synchronous flip-flops of the second pair, called the second weight flip-flop. 121: supply of three values ​​W4, W5, W6 of the weight data to the multipliers M1, M2, M3 of the first stage and to the first weight scale. 130: supply via said second weight scale, of the three values ​​W7, W8, W9 of the weight data to the multipliers M7, M8, M9 of the third stage. 131: supply via the first weight scale, the three values ​​W4, W5, W6 of the weight data to the multipliers M4, M5, M6 of the second stage and to the second weight scale. 132: supply of three values ​​Wl, W2, W3 of the weight data to the multipliers Ml, M2, M3 of the first stage and to the first weight scale. 210: supply of three values ​​VI, V2, V3 of a first input data to the multipliers M1, M2, M3 of the first stage and to the other of the synchronous flip-flops of the first pair, called the first data flip-flop. 220: supplying via said first data flip-flop, the three values ​​VI, V2, V3 of the first input data to the multipliers M4, M5, M6 of the second stage and to the other of the synchronous flip-flops of the second pair, called the second data flip-flop. 221: supply of three values ​​VI', V2', V3' of a second input data to the multipliers Ml, M2, M3 of the first stage and to the first data flip-flop. 230: supplying via said second data flip-flop, the three values ​​VI, V2, V3 of the first input data to the multipliers M7, M8, M9 of the third stage. 231: supply via the first data flip-flop, the three values ​​VI', V2', V3' of the second input data to the multipliers M4, M5, M6 of the second stage and to the second data flip-flop. 232: supply of three values ​​VI”, V2”, V3” of a third input data to the multipliers Ml, M2, M3 of the first stage and to the first data flip-flop. 233: calculation via multipliers M1-M9, of the product values ​​Al” = V1”*W1, A2” = V2”*W2, A3” = V3”*W3, A4' = V1'*W4, A5' = V2'*W5, A6' = V3'*W6, A7 = V1*W7, A8 = V2*W8, A9 = V3*W9 234: calculation via the accumulator, of an accumulation value Vacc from the sum of the product values ​​Al”, A2”, A3”, A4', A5', A6', A7, A8, A9. 235: provision of Vaccen accumulation data output 106. 2i0: supply via the second data flip-flop, of the three values ​​of the (i-2)-th input data to the multipliers M7, M8, M9 of the third stage. 2il: supply via the first data flip-flop, of the three values ​​of the (il)-th input data to the multipliers M4, M5, M6 of the second stage and to the second data flip-flop, 2i2: supply of the three values ​​of an i-th input data to the multipliers Ml, M2, M3 of the first stage and to the first data flip-flop. 2i3: calculation via multipliers M1-M9, of the corresponding product values. 2i4: calculation via the accumulator, of an (i-2)-th accumulation value Vacc from the sum of said corresponding product values. 2i5: provision of Vaccen accumulation data output 106.

Claims

Claims

1. Electronic depth convolution circuit, hereinafter referred to as depthwise circuit (10), intended to be integrated on a neural network acceleration chip, and configured to sequentially convolve at least one input data (40) by at least one weight data (50), said depthwise circuit (10) comprising: a first input (101) configured to receive at least one input data item (40) comprising three values ​​respectively denoted VI, V2, V3, a second input (102) configured to receive the at least one weight data item (50) comprising three times three values ​​respectively noted W1, W2, W3, W4, W5, W6, W7, W8, W9, a first sequential processing stage (11) comprising three multipliers respectively denoted M1, M2, M3, said multipliers being configured to multiply, during a first execution cycle, the values ​​VI, V2, V3 of the at least one input data item (40) respectively by the values ​​W1, W2, W3 of the at least one weight data item (50), to respectively give the product values ​​A1 = V1*W1, A2 = V2*W2, A3 = V3*W3, a second sequential processing stage (12) comprising three multipliers respectively denoted M4, M5, M6, said multipliers being configured to multiply, during a second execution cycle, the values ​​VI, V2, V3 of the at least one input data item (40) respectively by the values ​​W4, W5, W6 of the at least one weight data item (50), to give respectively the product values ​​A4 = V1*W4, A5 = V2*W5, A6 = V3*W6, a third sequential processing stage (13) comprising three multipliers respectively denoted M7, M8, M9, said multipliers being configured to multiply, during a third execution cycle, the values ​​VI, V2, V3 of the at least one input data item (40) respectively by the values ​​W7, W8, W9 of the at least one weight data item (50), to give respectively the product values ​​A7 = V1*W7, A8 = V2*W8, A9 = V3*W9, - an accumulator (103) comprising at least one adder (1030), the accumulator (103) being configured to add the product values ​​of the three stages (11, 12, 13) to obtain an accumulation value Vacc, - a first pair of synchronous flip-flops (104a, 104b) between the first stage (11) and the second stage (12), said synchronous flip-flops (104a, 104b) being configured to transmit respectively the at least one input data (40) and / or the at least one weight data (50) to the multipliers M4, M5, M6 of the second stage (12), after the second execution cycle, - a second pair of synchronous flip-flops (105a, 105b) between the second stage (12) and the third stage (13), said flip-flops (105a, 105b) synchronous being configured to transmit respectively the at least one input data (40) and / or the at least one weight data (50) to the multipliers M7, M8, M9 of the third stage (13), after the third execution cycle,- an output (106) configured to deliver the accumulation value Vacc.,

2. Depthwise circuit (10) according to the preceding claim, wherein the first (104a, 104b) and second (105a, 105b) pairs of synchronous flip-flops are configured to assign the different values ​​of the at least one input data (40) and the at least one weight data (50) to the different multipliers of each stage.

3. Depthwise circuit (10) according to any one of the preceding claims, wherein the different values ​​of the at least one input data (40) and the at least one weight data (50) are all coded in n bits (n = 8, 16, 32), and wherein the accumulation value Vacc is coded in 3*n bits.

4. A depthwise circuit (10) according to any preceding claim, wherein the flip-flops (104a, 104b, 105a, 105b) of the first and second flip-flop pairs are D-type flip-flops.

5. A depthwise circuit (10) according to any preceding claim, wherein the accumulator (103) comprises at least two adders (1030), preferably eight adders (1030).

6. A depthwise circuit according to the preceding claim, wherein the adders (1030) are parallel carry-ahead adders.

7. System (1) comprising a first set of Atomic-K depthwise circuits (10) according to any one of the preceding claims, dedicated to a two-dimensional (2D) convolution calculation, and a second set of Atomic-K multiplier-accumulator circuits (20) to the NVDLA standard, dedicated to a three-dimensional (3D) convolution calculation, the system being configured so that one of the first and second sets receives the at least one input data (40) and the at least one weight data (50).

8. System (1) according to the preceding claim comprising at least two circuit flip-flops (70) configured to respectively assign the input data and the weight data to one of the first and second sets.

9. System (1) according to any one of the two preceding claims, further comprising at least one filter (30) associated with at least one depthwise circuit (10), said at least one filter (30) being configured to decompose a weight data item (50) comprising more than three times three values ​​at the input (301) of the filter, into several weight sub-data items (501a, 501b, 501c, 501d) comprising three times three values ​​at the output (302) of the filter (30), said output (302) of the filter (30) being connected to the second input (102) of the depthwise circuit (10).

10. A method of digital signal processing implemented by the depthwise circuit (10) according to any one of claims 1 to 6, comprising: - At least one phase of initializing the weight data (50) comprising: • During a first execution cycle: • providing (110) three values ​​W7, W8, W9 of the weight data (50) to the multipliers M1, M2, M3 of the first stage (11) and to one of the synchronous flip-flops of the first pair (104a, 104b), called the first weight flip-flop (104b), During a second execution cycle: Supply (120), via said first weight flip-flop (104b), the three values ​​W7, W8, W9 of the weight data (50) to the multipliers M4, M5, M6 of the second stage (12) and to one of the synchronous flip-flops of the second pair (105a, 105b), called the second weight flip-flop (105b), supply (121) three values ​​W4, W5, W6 of the weight data (50) to the multipliers M1, M2, M3 of the first stage (11) and to the first weight flip-flop (104b), During a third execution cycle: Supply (130), via said second weight scale (105b), the three values ​​W7, W8, W9 of the weight data (50) to the multipliers M7, M8, M9 of the third stage (13), Supply (131), via the first weight scale (104b), the three values ​​W4, W5, W6 of the weight data (50) to the multipliers M4, M5, M6 of the second stage (12) and to the second weight scale (105b), supply (132) three values ​​Wl, W2, W3 of the weight data (50) to the multipliers Ml, M2, M3 of the first stage (11) and to the first weight scale (104b), at least one input data processing phase comprising: During a first execution cycle: supplying (210) three values ​​VI, V2, V3 of a first input data (40) to the multipliers M1, M2, M3 of the first stage and to the other of the synchronous flip-flops of the first pair (104a, 104b), called first data flip-flop (104a), During a second execution cycle: Supply (220), via said first data flip-flop (104a), the three values ​​VI, V2, V3 of the first input data (40) to the multipliers M4, M5, M6 of the second stage (12) and to the other of the synchronous flip-flops of the second pair (105a, 105b), called second data flip-flop (105a), supply (221) three values ​​VI', V2', V3' of a second input data (40) to the multipliers M1, M2, M3 of the first stage (11) and to the first data flip-flop (104a), During a third execution cycle: Supply (230), via said second data flip-flop (105a), the three values ​​VI, V2, V3 of the first input data (40) to the multipliers M7, M8, M9 of the third stage (13), Supply (231), via the first data flip-flop (104a), the three values ​​VI', V2', V3' of the second input data (40) to the multipliers M4, M5, M6 of the second stage (12) and to the second data flip-flop (105a), Supply (232) three values ​​VI”, V2”, V3” of a third input data (40) to the multipliers M1, M2, M3 of the first stage (11) and to the first data flip-flop (104a), Calculate (233), via the multipliers M1-M9, the product values ​​A1” = V1”*W1, A2” = V2”*W2, A3” = V3”*W3, A4' = V1'*W4, A5' = V2'*W5, A6' = V3'*W6, A7 = V1*W7, A8 = V2*W8, A9 = V3*W9, calculate (234), via the accumulator (103), an accumulation value Vacc from the sum of the product values ​​Al”, A2”, A3”, A4', A5', A6', A7, A8, A9, supply (235) the accumulation value Vacc to the output 106, During an i-th following execution cycle (i=4 to N): • Supply (2i0), via the second data flip-flop (105a), the three values ​​of the (i-2)-th input data (40) to the multipliers M7, M8, M9 of the third stage (13), • Supply (2il), via the first data flip-flop (104a), the three values ​​of the (il)-th input data (40) to the multipliers M4, M5, M6 of the second stage (12) and to the second data flip-flop (105a), • Supply (2i2) three values ​​of an i-th input data (40) to the multipliers M1, M2, M3 of the first stage (11) and to the first data flip-flop (104a), • Calculate (2i3), via the multipliers M1-M9, the corresponding product values, • Calculate (2i4), via the accumulator (103), an (i-2)-th accumulation value Vacc from of the sum of said corresponding product values, • provide (2i5) the accumulation value Vacc at the output (106).

11. Digital signal processing method according to the preceding claim in which an accumulation value Vacc is calculated during each n-th execution cycle (n=3 to N) of the input data processing phase (40), after the first two execution cycles intended to provide input data values ​​(40) to all the multipliers M1-M9.

12. A digital signal processing method according to any one of the two preceding claims wherein the at least one phase of initializing the weight data (50) is carried out before the at least one phase of processing the input data (40).

13. A digital signal processing method according to any one of claims 10 to 12 wherein the at least one phase of initializing the weight data (50) is carried out periodically during the at least one phase of processing the input data (40).

14. A digital signal processing method according to any one of claims 10 to 13 wherein, when a weight data item (50) comprises more than three times three values, said weight data item (50) is decomposed (500) into several weight sub-data items (501a, 501b, 501c, 501d) comprising three times three values ​​and said weight sub-data (501a, 501b, 501c, 501d) are provided to the multipliers M1-M9.

15. Digital signal processing method according to the preceding claim, in which the decomposition (500) of the weight data (50) consists of adding zero values ​​to the weight data (50), then dividing the weight data to form the weight sub-data (501a, 501b, 501c, 501d) comprising three times three values.

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