Method for manufacturing a purified 28Si silicon semiconductor device

Abstract

A process for manufacturing a semiconductor device, the process comprising, starting from an initial silicon-on-insulator (SOI) structure, comprising a silicon substrate (2), a buried oxide layer (4), BOX, and a first upper layer (6) of silicon on the buried oxide layer (4), the epitaxial formation of a first epitaxial layer (8) of silicon with the 28Si isotope on the first upper layer (6), a homogenizing anneal by which the first epitaxial layer (8) of silicon with the 28Si isotope and the first upper layer (6) of silicon then form a second upper layer with a lower concentration of the 29Si isotope than initially, and a thinning of the second upper layer. Figure 3

Description

Title of the invention: Method for manufacturing a silicon semiconductor device 28 So purified technical field

[0001] The invention relates to the field of semiconductor devices, and more specifically to a method for manufacturing a semiconductor device having a top layer of silicon in the 28Si isotope with very little 29Si isotope, which is particularly advantageous for realizing spin qubits with silicon technology. Technological background

[0002] Standard silicon natively contains the 14- and 15-neutron isotopes, denoted 28Si and 29Si, respectively. Thus, silicon commonly used in electronics contains approximately 4% of the 29Si isotope. However, for certain applications, it is desirable to have a silicon layer with a very low concentration of 29Si. This is particularly the case for devices with spin qubits in silicon technology, where it is desirable to have a silicon layer housing the qubits that is as pure as possible in 28Si, in order to avoid rapid qubit decoherence.

[0003] While it is known to grow pure silicon layers of the 28Si isotope by epitaxy, a problem arises when it is desired to have a pure silicon layer of the 28Si isotope on a silicon-on-insulator (SOI) substrate. Such an SOI substrate comprises a silicon substrate, a buried oxide layer (BOX) on the silicon substrate, and a first upper silicon layer on the buried oxide layer.

[0004] The formation of pure silicon layers of the 28Si isotope is very expensive, because the purified precursor gas containing only the 28Si isotope is very costly. It is therefore not economically feasible to manufacture a completely pure SOI substrate of the 28Si isotope. The first top silicon layer and / or the buried oxide layer therefore generally also contain silicon of the 29Si isotope.

[0005] A pure silicon layer of the 28Si isotope formed on the first upper silicon layer becomes contaminated by 29Si isotopes migrating from the first upper silicon layer and / or the buried oxide layer, since these layers contain them, particularly during subsequent stages of semiconductor device fabrication, such as the fabrication of transistors, which generally involve high temperatures conducive to the migration of 29Si isotopes. The performance of the qubits in this silicon layer is therefore not optimal. Presentation of the invention

[0006] The invention therefore aims to provide a method for obtaining at a lower cost a semiconductor device having a top layer of silicon with a very low concentration of 29Si isotope.

[0007] To this end, the invention proposes a method for manufacturing a semiconductor device, the method comprising, starting from an initial silicon-on-insulator structure, SOI, comprising a silicon substrate, a buried oxide layer, BOX, and a first upper silicon layer on the buried oxide layer, the first upper silicon layer having a first concentration of the 28Si isotope and a first concentration of the 29Si isotope: a) the formation by epitaxy of a first epitaxial layer of silicon of isotope 28Si on the first upper layer (6) of silicon, the first upper layer of silicon having a first thickness and the first layer of silicon epitaxially of isotope 28Si having a second thickness; b) a first homogenization anneal, the first epitaxial layer of silicon of isotope 28Si and the first upper layer of silicon then forming a second upper layer of silicon with a second concentration of the isotope 28Si higher than the first concentration of the isotope 28Si, and a second concentration of the isotope 29Si lower than the first concentration of the isotope 29Si; c) a thinning of the second upper layer to a third thickness.

[0008] The process is advantageously complemented by the following various features taken alone or in their various possible combinations: - the first thickness is less than the third thickness; - the first thickness is less than 5 nm, and preferably less than or equal to 3 nm; - the second thickness is greater than 50 nm, and preferably greater than 100 nm; - the third thickness is between 12 nm and 25 nm.

[0009] Advantageously, the process may include, following the thinning of the second upper layer: d) the formation by epitaxy of a second epitaxial layer of silicon of isotope 28Si on the second upper layer of silicon thinned to the third thickness, the second epitaxial layer of silicon of isotope 28Si having a fourth thickness; e) a second homogenizing anneal, the second epitaxial layer of silicon of isotope 28Si and the second upper silicon layer thinned to the third thickness (T3) then forming a third upper silicon layer with a third concentration of the isotope 28Si higher than the second concentration of the isotope 28Si, and a third concentration of the isotope 29Si lower than the second concentration of the isotope 29Si.

[0010] In this case, preferably the third thickness is less than or equal to 6 nm. Preferably also, the second and fourth thicknesses are greater than 20 nm. Preferably, the second and / or fourth thicknesses are less than 60 nm, and even more preferably less than 50 nm.

[0011] In all cases, the process can advantageously be complemented by the following various features taken alone or according to their various possible combinations: - the formation by epitaxy of a first epitaxial layer of silicon of isotope 28Si and the formation by epitaxy of a second epitaxial layer of silicon of isotope 28Si are carried out from a purified precursor gas containing only the isotope 28Si; - the steps of the process are implemented for a first area of ​​a surface of the semiconductor device, and not implemented for a second area of ​​the surface of the semiconductor device, the process subsequently including the formation of transistors on the second area of ​​the surface of the semiconductor device, the first area of ​​the surface being configured to house qubits; - the first zone has a thickness at least 2 nm greater than the thickness of the second zone; - the process may subsequently include the creation of insulation trenches, and the filling of insulation trenches using a purified precursor gas containing only the isotope 28Si; - the process may include a subsequent step of localized bombardment of a surface of the structure with argon to uniformize the thickness of the third silicon layer; - the process may include a preliminary step of thinning the first upper layer of silicon to the first thickness. Presentation of the figures

[0012] Other features, objectives and advantages of the invention will become apparent from the following description, which is purely illustrative and not limiting, and which should be read in conjunction with the accompanying drawings on which: - Fig. 1 illustrates an initial silicon-on-insulator structure, according to one possible embodiment of the invention; - [Fig.2] illustrates the structure after thinning of the first upper silicon layer, according to one possible embodiment of the invention; - [Fig.3] illustrates the structure after the formation by epitaxy of a first layer of silicon of isotope 28Si, according to a possible embodiment of the invention; - Figure 4 illustrates the structure after the first homogenization annealing, according to a possible embodiment of the invention; - [Fig.5] illustrates the structure after thinning of the second upper silicon layer, according to one possible embodiment of the invention; - [Fig.6] illustrates the structure after the formation by epitaxy of a second layer of silicon of isotope 28Si, according to a possible embodiment of the invention; - Fig. 7 illustrates the structure after a second homogenization anneal, according to one possible embodiment of the invention; - Fig. 8 illustrates the structure after the formation of isolation trenches, according to one possible embodiment of the invention. Detailed description

[0013] With reference to [Fig. 1], the process for manufacturing a semiconductor device is implemented starting from an initial silicon-on-insulator (SOI) structure 1, comprising a silicon substrate 2, a buried oxide layer 4, BOX, and a first upper silicon layer 6 on the buried oxide layer. The first upper silicon layer 6 has a first concentration Ci>28 of the 28Si isotope and a first concentration Ci>29 of the 29Si isotope. The silicon in the initial structure 1 is standard, i.e., it has not been substantially purified of its 29Si isotopes. Typically, the first concentration Ci>28 of the 28Si isotope is between 92% and 93%, while the first concentration Ci>29 of the 29Si isotope is between 4% and 5%.The 30Si isotope is also typically present at around 3%, but has no significant consequences and will not be discussed further, although the process results in the removal of this 30Si isotope in the same way as the 29Si isotope. For non-limiting demonstration purposes, the values ​​of 96% for Ci>28 and 4% for Ci>29 are used. In this text, the concentrations indicated are molar concentrations.

[0014] The initial silicon-on-insulator structure 1 is preferably a fully depleted silicon-on-insulator (FDSOI) structure, where at least the first upper layer 6 is completely depleted. The buried oxide layer 4 is typically made of silicon oxide.

[0015] If the first upper silicon layer 6 is not sufficiently thin, and for example if it is thicker than a first thickness of 5 nm or less, the process may include a preliminary step of thinning the first upper silicon layer 6 to a first thickness Ti of 5 nm or less, and preferably 4 nm or less, and preferably 3 nm or less. For the purposes of demonstration in the following examples, 3 nm is used as the first thickness Tb. The thinning may, for example, be carried out by oxidation in a furnace, followed by etching, for example chemical etching, in particular by using hydrofluoric acid (HF), known by the English term "HF wet etching", or by a so-called dry etch, for example using a plasma. Figure 2 shows the structure with the first upper silicon layer 6 at the first thickness Ti.

[0016] The process comprises the formation by epitaxy of a first epitaxial layer 8 of silicon of the 28Si isotope on the first upper layer 6 of silicon, the first epitaxial layer 8 of silicon of the 28Si isotope having a second thickness T2. Preferably, the second thickness T2 is greater than or equal to 15 nm, and even more preferably greater than or equal to 20 nm. The epitaxy can be carried out from a purified precursor gas containing only the 28Si isotope, i.e. at least 99.9% of the 28Si isotope. For example, from a SiF4 gas, sorting according to mass allows only the 28SiF4 to be retained. Chloride compounds then allow the 28Si isotope silicon atom to be obtained. The result is then, as illustrated in [Fig.3], a first epitaxial layer 8 of silicon with the isotope 28Si on the first upper layer 6 of silicon, with therefore a thickness above the buried oxide layer 4 corresponding to the sum of the first thickness Ti and the second thickness T2. .

[0017] The process then comprises a first homogenizing thermal anneal, aimed at homogenizing the concentrations of 28Si and 29Si isotopes between the first epitaxial layer 8 of silicon and the first upper layer 6 of silicon, which then form a second upper layer 10 of silicon, as illustrated in [Fig. 4]. The second upper layer 10 of silicon has a second concentration C2>28 of the 28Si isotope higher than the first concentration Ci>28 of the 28Si isotope, and a second concentration C2j29 of the 29Si isotope lower than the first concentration Cij29 of the 29Si isotope. During the first homogenizing thermal anneal, heating of structure 1 allows the 29Si isotopes to migrate from the first upper layer 6 of silicon to the first epitaxial layer 8 of silicon.For example, homogenizing thermal annealing can be carried out at a temperature of at least 1000°C for at least 20 minutes, and preferably at least 1050°C for at least 30 minutes. However, it is possible to modify the temperature and duration of the thermal annealing as long as the thermal budget allows sufficient migration of the 29Si isotopes towards the upper part of the second upper layer 10. For example, see the article by V. Mazzocchi et al., “99.992% 28Si CVD-grown epilayer on 300 nm substrates for large scale integration of Silicon spin qubits”, Journal of Crystal Growth 509 (2019) 1-7, for information on both epitaxial growth and homogenizing thermal annealing in this context.

[0018] The second concentration C2>29 of the 29Si isotope depends on the first thickness Ti and the second thickness T2, as well as the first concentration Ci>29 of the isotope 29Si:

[0019] (7 -(7 x_Zi_

[0020] Taking Cij29=4%, Ti=3 nm, and T2=30 nm, we obtain C2j29=0.36%, representing a tenfold reduction in the concentration of the 29Si isotope in the second upper silicon layer 10 compared to the first upper silicon layer 6, i.e., compared to standard silicon. However, it is possible that some 29Si isotopes may migrate from the buried oxide layer 4 to the second upper silicon layer 10 during the homogenizing thermal anneal. This effect does not, however, negate the substantial decrease in the second concentration C2>29 of the 29Si isotope compared to the first concentration Ci>29 of the 29Si isotope, and it is possible to limit this effect by reducing the thermal budget of the first homogenizing thermal anneal.

[0021] The process then comprises thinning the second upper layer 10 to a third thickness T3, as illustrated in [Fig. 5]. The same methods as for the possible thinning of the first upper layer 6 can be used. Preferably, the third thickness T3 is less than or equal to 6 nm, and even more preferably less than or equal to 4 nm. The third thickness T3 may, however, be greater than the first thickness Tb.

[0022] The process then comprises the formation by epitaxy of a second epitaxial layer 12 of silicon of the 28Si isotope on the second upper layer 10 of silicon thinned to the third thickness T3, the second epitaxial layer 12 of silicon of the 28Si isotope having a fourth thickness T4. Preferably, the fourth thickness T4 is greater than or equal to 15 nm, and even more preferably greater than or equal to 20 nm. As illustrated in [Fig. 6], a second epitaxial layer 12 of silicon of the 28Si isotope is then obtained on the second upper layer 10 of silicon, with a thickness above the buried oxide layer corresponding to the sum of the third thickness T3 and the fourth thickness T4.

[0023] The process then includes a second homogenization anneal, aimed at homogenizing the concentrations of 28Si and 29Si isotopes between the second epitaxial layer 12 of silicon and the second upper layer 10 of silicon, which then form a third upper layer 14 of silicon, as illustrated in [Fig.7].

[0024] The upper third silicon layer 14 has a third concentration C3>28 of the 28Si isotope higher than the second concentration C2>28 of the 28Si isotope, and a third concentration C3>29 of the 29Si isotope lower than the second concentration C2>29 of the 29Si isotope. As in the first homogenizing thermal annealing, heating the structure allows the 29Si isotopes to migrate from the second layer upper silicon layer 10 towards the second epitaxial layer 12 of silicon. For example, the homogenizing thermal annealing can be carried out at a temperature of at least 1000°C for at least 20 minutes, and preferably at least 1050°C for at least 30 minutes. However, it is possible to modify the temperature and duration of the thermal annealing as long as the thermal budget allows sufficient migration of the 29Si isotopes towards the upper part of the third upper layer.

[0025] The third concentration C3>29 of the 29Si isotope depends on the third thickness T3 and the fourth thickness T3, as well as on the second concentration C2>29 of the 29Si isotope:

[0026] pcv l JC 3 29 ~ c 2.29 x

[0027] which can also be expressed as a function of the first concentration Ci>29 of the 29Si isotope:

[0028] (j _ (jx Ll.., x Z?

[0029] Taking Cij29=4%, Ti=3 nm, T2=30 nm, T3=5 nm and T4=25 nm, we obtain C3>29 =0.06%, which represents a reduction by more than 50 in the concentration of the 29Si isotope in the third upper silicon layer 14 compared to the first upper silicon layer 6, i.e., compared to standard silicon. A possible migration of 29Si isotopes from the buried oxide layer 4 to the third upper silicon layer 14 during the second homogenizing thermal anneal may occur, but even less pronounced than before, because the concentration of 29Si isotopes in the buried oxide layer 4 decreases with each migration. It is also possible to limit this effect by limiting the thermal budget of the second homogenizing thermal anneal. In all cases, it is possible to obtain a third upper layer 14 of silicon comprising less than 0.1% of the 29Si isotope.

[0030] A semiconductor device is then obtained comprising a top silicon layer 14 on the buried oxide layer 4, which is practically devoid of the 29Si isotope, with only two thinning-epitaxial-thermal annealing iterations. The process is therefore very economical because it typically requires only between 30 nm and 80 nm of epitaxial growth using an expensive precursor gas consisting solely of 28Si isotopes. It is possible to increase the purity obtained by repeating a thinning and epitaxial cycle as described, and / or by further thinning the top silicon layers 6, 10 during their thinning, and / or by increasing the thickness of the epitaxial layers 8, 12. Simply decreasing the thickness of the epitaxial layers 8, 12 reduces costs, possibly at the expense of the degree of purity obtained.

[0031] These thinning-epitaxy-thermal annealing cycles may have the disadvantage of deteriorating the thickness uniformity of the upper layer 14 of The final silicon layer, intended to be the active layer of the semiconductor device, is formed. However, small variations in thickness are acceptable for forming qubits in the semiconductor device since qubits are generally formed in a thicker channel (for example, between 10 and 15 nm) than for a channel in a conventional transistor, which is typically 7 to 10 nm thick. If it is desired to improve the homogeneity of the thickness of the final top silicon layer 14, which is above the buried oxide layer 4, it is possible to perform trimming, for example, by bombarding the top silicon layer with argon.

[0032] The process can be implemented on an entire wafer, or only on the areas intended to house qubits, in order to reduce the consumption of pure 28Si precursor gas. Furthermore, not implementing the process on certain areas allows for maintaining the thinner and more uniform thickness of the top silicon layer in the areas intended to form transistors, and for a greater thickness in the purified areas intended for qubits. Thus, preferably, the steps of the process are implemented on a first area of ​​the semiconductor device surface, and not on a second area of ​​the semiconductor device surface, the process subsequently comprising the formation of transistors on the second area of ​​the semiconductor device surface, the first area of ​​the surface being configured to house qubits.Preferably, the first zone has a thickness at least 2 nm greater than the thickness of the second zone, and even more preferably at least 4 nm greater than the thickness of the second zone. For example, a silicon nitride mask can be used on the second zone of the semiconductor device surface during the implementation of the described process steps.

[0033] As mentioned previously, subsequent manufacturing steps, for example for producing transistors, can involve a temperature increase in the semiconductor device, promoting the diffusion of 29Si isotopes into the final top layer 14, from which they were practically absent. In order to limit this diffusion, it is possible to perform, following the described process, the creation of shallow trench isolation (STI) trenches 16, and the filling of these trenches using a purified precursor gas containing only the 28Si isotope, as illustrated in [Fig. 8]. Thus, the shallow trench isolation 16 is devoid of 29Si isotopes, and these cannot therefore migrate into the final top layer 14 of silicon purified by the described steps of the process. Advantageously, this applies at least to the shallow trench isolation 16 located near the areas intended to house qubits.Such insulation trenches 16 cross at least the top layer 14, typically also the buried oxide layer 4, and . generally reach substrate 2. However, it is possible to plan insulation trenches 16 with shallower depths.

[0034] It is also possible, using the same methods unless otherwise specified, to carry out only one cycle of formation by epitaxial growth of a first epitaxial layer 8 of a second thickness T2 followed by a first homogenization anneal, and thinning of the upper second layer 10 to the third thickness T3. In this case, the second thickness T2 is preferably greater than or equal to 50 nm, and preferably even greater than 100 nm. As before, the second concentration C2>29 of the 29Si isotope depends on the first thickness Ti and the second thickness T2, as well as on the first concentration Ci>29 of the 29Si isotope:

[0035] c — C v Tt LJ C2.29 “ 1-1.29 x ft+T,

[0036] Taking Cij29=4%, Ti=3 nm, and T2=60 nm, we obtain C2j29=0.48%, representing a reduction by more than 8 times in the concentration of the 29Si isotope in the second upper silicon layer 10 compared to the first upper silicon layer 6, i.e., compared to standard silicon. The greater the second thickness T2, the greater the purification, but the cost may be higher than in multi-cycle variants, which consume less epitaxial layer thickness.

[0037] Typically, the thinning reduces the second upper layer 10 by at least 30 nm, and preferably by at least 45 nm. The third layer T3 is thicker, since the thinning of the second upper layer is not followed by the formation, by epitaxy, of a second epitaxial layer 12. Preferably, the third layer T3 is between 12 nm and 25 nm. The invention is not limited to the embodiment described and shown in the accompanying figures. Modifications remain possible, particularly with regard to the composition of the various technical features or by substitution of technical equivalents, without departing from the scope of protection of the invention, which is defined by the following claims.

Claims

Demands

1. A method for manufacturing a semiconductor device, the method comprising, from an initial silicon-on-insulator (1) structure, SOI, comprising a silicon substrate (2), a buried oxide layer (4), BOX, and a first upper layer (6) of silicon on the buried oxide layer (4), the first upper layer (6) of silicon having a first concentration of the 28Si isotope and a first concentration of the 29Si isotope: a) the formation by epitaxy of a first epitaxial layer (8) of silicon of the 28Si isotope on the first upper layer (6) of silicon, the first upper layer (6) of silicon having a first thickness (TJ) and the first epitaxial silicon layer (8) of the 28Si isotope having a second thickness (T2);b) a first homogenizing anneal, the first epitaxial layer (8) of silicon of isotope 28Si and the first upper layer (6) of silicon then forming a second upper layer (10) of silicon with a second concentration of the isotope 28Si higher than the first concentration of the isotope 28Si, and a second concentration of the isotope 29Si lower than the first concentration of the isotope 29Si; c) a thinning of the second upper layer (10) to a third thickness (T3).;

2. Method according to claim 1, wherein the first thickness (TJ) is less than the third thickness (T3).

3. A method according to any one of the preceding claims, wherein the first thickness (Ti) is less than 5 nm, and preferably less than or equal to 3 nm.

4. A method according to any one of the preceding claims, wherein the second thickness (T2) is greater than 50 nm, and preferably greater than 100 nm.

5. A method according to any one of the preceding claims, wherein the third thickness (T3) is between 12 nm and 25 nm.

6. A method according to any one of claims 1 to 3, comprising, following thinning of the second upper layer (10): d) the formation by epitaxy of a second epitaxial layer (12) of 28Si isotope silicon on the second upper layer (10) of silicon thinned to the third thickness (T3), the second epitaxial layer (12) of 28Si isotope silicon having a fourth thickness (T4); e) a second homogenizing anneal, the second epitaxial layer (12) of silicon of isotope 28Si and the second upper layer (10) of silicon thinned to the third thickness (T3) then forming a third upper layer (14) of silicon with a third concentration of the isotope 28Si greater than the second concentration of the isotope 28Si, and a third concentration of the isotope 29Si less than the second concentration of the isotope 29Si.

7. Method according to claim 6, wherein the third thickness (T3) is less than or equal to 6 nm.

8. A method according to any one of claims 6 to 7, wherein the second thickness (T2) and the fourth thickness (T4) are greater than 20 nm.

9. A method according to any one of the preceding claims, wherein the formation by epitaxy of a first epitaxial layer (8) of silicon of isotope 28Si and the formation by epitaxy of a second epitaxial layer (12) of silicon of isotope 28Si are carried out from a purified precursor gas containing only the isotope 28Si.

10. A method according to any one of the preceding claims, wherein the steps of the method are carried out for a first area of ​​a surface of the semiconductor device, and not carried out for a second area of ​​the surface of the semiconductor device, the method subsequently comprising the formation of transistors on the second area of ​​the surface of the semiconductor device, the first area of ​​the surface being configured to house qubits.

11. A method according to the preceding claim, wherein the first zone has a thickness at least 2 nm greater than the thickness of the second zone.

12. A method according to any one of the preceding claims, further comprising the creation of insulation trenches (16), and the filling of insulation trenches (16) using a purified precursor gas containing only the isotope 28Si.

13. A method according to any one of the preceding claims, comprising a further step of localized bombardment of a surface of the structure with argon to uniformize the thickness of the third layer (14) of silicon.

14. A method according to any one of the preceding claims, comprising a preliminary step of thinning the first layer upper (6) of silicon up to the first thickness (Ti).

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