Nonlinear analog control of multi-phase electrical circuit

Abstract

The invention relates to a multi-phase electrical circuit, for supplying a target load, comprising: a power cell comprising N supply branches which converge towards the output node. a control circuit comprising; a voltage regulation circuit configured to generate an alternating binary regulation signal from a combination of the output voltage with a noise voltage. a distribution circuit configured to generate for each supply branch, at least one dedicated activation signal from the regulation signal; the plurality of activation signals being phase-shifted with each other according to a phase shift which varies over time. Figure for the abstract: Fig. 1

Description

Title of the invention: Non-linear analog control of multi-phase electrical circuit

[0001] Scope of application

[0002] The present invention relates to multi-phase electrical circuits for space applications. More particularly, the invention relates to the realization of non-linear and analog control of multi-phase circuits.

[0003] Problem raised

[0004] Multi-phase converters are integrated into power supply systems to improve energy efficiency, optimize voltage regulation, and manage loads in a more balanced manner. They operate with electrical signals distributed across multiple phases, allowing for balanced load distribution. These converters are versatile, being able to convert between DC and AC voltage, and regulate voltage or current to meet the specific needs of electrical devices.

[0005] In the context of a multi-phase converter, a "phase" means an individual power branch of the electrical circuit that performs the conversion of electrical energy. Multi-phase converters use several of these phases, typically two, three, or more, operating independently to perform the energy conversion. Each phase operates with a time lag relative to the others, creating a time sequence in which each phase successively contributes to the total converter output. This approach distributes the electrical load and reduces current variations, which can lead to improved efficiency and reduced current ripple. For example, in a two-phase converter, two phases operate alternately to reduce voltage. Similarly, a three-phase converter would involve three phases operating successively.

[0006] A multi-phase converter generally comprises a power cell formed by the plurality of phases and a control circuit configured to control the activation and deactivation of the different phases to obtain the time shift of operation of the phases relative to each other.

[0007] With the increasing power requirements of computing units, voltage regulator modules (VRMs) must provide more current while improving their responsiveness to the load transistors. To achieve this, the use of multi-phase or multi-phase series-capacitor topologies is preferred. Combining these topologies with non-linear control makes it possible to optimize the performance of these converters. However, it is complex to apply efficient nonlinear control to multi-phase or multi-phase series-capable converters, especially in applications that do not include a digital controller such as a microprocessor, FPGA, or CPU.

[0008] More particularly, the implementation of the control circuit by digital controllers results in a circuit with degraded technological robustness in the context of space application. Indeed, conventional digital control circuits often have limitations in terms of reliability in the extreme environments of space. Currently available solutions are often based on conventional digital control circuits which are not optimized for the specific constraints of space, in particular radiation resistance, reliability and stability.

[0009] Furthermore, the invention attempts to solve the problem relating to changes in operating frequencies of the control signals of the different out-of-phase phases. Indeed, when the control circuit is not governed by a fixed clock frequency, it becomes difficult to generate out-of-phase phase control signals with an indeterminate frequency. In this case, the control circuit must phase-shift the control signals, from a single input signal, without knowing beforehand the triggering time of the next phase. In this case, we speak of the design of a “non-linear” control circuit.

[0010] For the description of the invention, we will use the terminology “power supply branch” to designate the electrical phases of a multi-phase circuit.

[0011] Response to the problem and provision of solution

[0012] To overcome the limitations of existing solutions, the invention proposes a multi-phase electrical circuit with a non-linear and analog phase control circuit. The non-linearity of the control circuit makes it possible to phase shift a main control over several phases without knowing its period. In addition, the architecture proposed according to the invention makes it possible to improve the stability of the operation of the multi-phase circuit independently of the output load which is adjustable according to the intended application.

[0013] The analog implementation of the control circuit according to the invention makes it possible to ensure the compatibility of the multi-phase circuit with a hostile environment and more particularly with a space environment. This presents a reliability superior to digital microcontrollers sensitive to environmental constraints for a space application.

[0014] Abstract / Claims

[0015] The invention relates to a multi-phase electrical circuit configured to generate an output current or an output voltage to supply a target load. Said circuit multi-phase electrical system including: - a power cell comprising: • an input node to provide an input voltage; • an electrical ground; • an output node to provide said output voltage, • N feeder branches that converge towards the output node, N being a natural integer greater than 1, each supply branch, comprising: • a central node separated from the input node by at least a first switch and from the electrical ground by at least a second switch; - a control circuit comprising: • a voltage regulation circuit configured to generate an alternating binary regulation signal from the combination of the output voltage with an alternating noise voltage; said noise voltage being generated by the voltage regulation circuit from • the electrical potential of the central node of a chosen supply branch; • or from the input voltage; • a distribution circuit configured to generate for each supply branch, at least one dedicated activation signal from the regulation signal; the plurality of activation signals being phase-shifted with each other according to a phase shift that varies over time.

[0016] According to a particular aspect of the invention, the voltage regulation circuit comprises a comparator for comparing an intermediate signal with a predetermined reference voltage. Said intermediate signal having a DC component corresponding to the output voltage and an AC component corresponding to the noise voltage.

[0017] According to a particular aspect of the invention, the voltage regulation circuit comprises a divider bridge comprising a pair of resistors separated by a third switch and configured to generate a fraction of the input voltage when the third switch is on; the third switch being controlled by the regulation signal.

[0018] According to a particular aspect of the invention, the voltage regulation circuit comprises N diodes such that each diode has an anode connected to the central node of a supply branch associated with said diode and such that the cathodes of the diodes are connected to a common node separated from the electrical ground by a fourth switch controlled by the regulation signal.

[0019] According to a particular aspect of the invention, the distribution circuit comprises a chain of N D-type flip-flops all synchronized according to the regulation signal and mounted such that: the output of a flip-flop of rank i=1 to N1 is connected to the input of the following flip-flop of rank i+1.

[0020] According to a particular aspect of the invention, the distribution circuit further comprises an OR type logic cell having a first input connected to the output of the flip-flop of rank N, a second input receiving an initialization signal and an output connected to the input of the flip-flop of rank i=l.

[0021] According to a particular aspect of the invention, the distribution circuit further comprises N AND type logic cells; each AND type cell having a first input receiving the output of an associated D flip-flop and a second input receiving the regulation signal and an output for providing the activation signal to an associated power supply branch.

[0022] According to a particular aspect of the invention, the control circuit further comprises a protection circuit inserted between the voltage regulation circuit and the distribution circuit and configured to limit the duration of the setting of the regulation signal at a predetermined threshold.

[0023] According to a particular aspect of the invention, the control circuit further comprises a dead time circuit inserted between the distribution circuit and the power cell and configured to generate for each power supply branch, a first and a second complementary activation signal, each transition edge of the second activation signal being temporally offset relative to the first activation signal.

[0024] According to a particular aspect of the invention, each supply branch comprises an associated elementary inductor mounted between the central node and the output node; each supply branch being configured to generate an elementary current through the associated elementary inductor.

[0025] Detailed Description of the Figures

[0026] Other characteristics and advantages of the present invention will appear more clearly on reading the description which follows in relation to the following appended drawings.

[0027] [Fig.l] [Fig.l] illustrates a multi-phase electrical circuit according to a first embodiment of the invention.

[0028] [Fig.2a] [Fig.2a] illustrates a first example of a power cell of the circuit multi-phase electric according to the invention.

[0029] [Fig.2b] [Fig.2b] illustrates a second example of a power cell of the circuit multi-phase electric according to the invention.

[0030] [Fig.3a] [Fig.3a] illustrates a first example of a voltage regulation circuit of the multi-phase electrical circuit according to the invention.

[0031] [Fig.3b] [Fig.3b] illustrates a second example of a voltage regulation circuit of the multi-phase electrical circuit according to the invention.

[0032] [Fig.4] [Fig.4] illustrates the control signal distribution circuit of the circuit multi-phase electric according to the invention.

[0033] [Fig.5] [Fig.5] illustrates a timing diagram of the internal and external signals of the circuit control of the multi-phase electrical circuit according to the invention.

[0034] [Fig.6] [Fig.6] illustrates a multi-phase electrical circuit according to a second mode of realization of the invention.

[0035] [Fig.7a] [Fig.7a] illustrates an example of implementation of the protection circuit in the multi-phase electrical circuit according to a second embodiment of the invention.

[0036] [Fig.7b] [Fig.7b] illustrates one in the multi-phase electrical circuit according to a second embodiment of the invention.

[0037] [Fig.7c] [Fig.7c] illustrates a multi-phase electrical circuit according to a second mode of carrying out the invention.

[0038] [Fig.l] illustrates a multi-phase electrical circuit DI according to a first embodiment of the invention. The multi-phase electrical circuit DI comprises a power cell 1 and a control circuit 2. The power circuit 1 is formed by N power supply branches of indices i=1 to N configured to generate an output current Lut towards a load 3 to be supplied. The control circuit 2 is configured to generate activation signals CMD;, with i=1 to N, phase-shifted with each other according to a phase shift that varies over time. Each activation signal CMD; is dedicated to the power supply branch of the same index i to trigger said power supply branch to supply the load 3 for a duration. The activated power supply branch is then in a conduction state.

[0039] The power cell 1 comprises an input node 12 for providing an input voltage Vin; an electrical ground GND; an output node 11 for providing said output voltage Vout and the N power supply branches which converge towards the output node 11. The load to be supplied 3 is mounted between the output node 11 and the ground GND. The power cell 1 generates: - the output current Iout through the load to be supplied 3; - the output voltage Vout at the terminals of load 3 and propagated via a first feedback loop to control circuit 2 - at least one noise voltage Vml to VmN reinjected(s) via a second feedback loop to the control circuit 2.

[0040] The control circuit 2 comprises a voltage regulation circuit 21 and a distribution circuit 22. The voltage regulation circuit 21 is configured to generate a regulation signal Vreg from the combination of the DC component of the back-propagated output voltage Vout with the AC component of the noise voltage chosen from at least one noise voltage Vmi to VmN reinjected via the second feedback loop. The regulation signal Vregest is a binary and periodic digital signal intended for the distribution circuit 22.

[0041] The distribution circuit 22 is configured to generate, for each power supply branch, a dedicated activation signal CMDi, CMD2, CMD3 from the regulation signal Vreg. The activation signals are phase-shifted with respect to each other according to a variable phase shift over time. The regulation signal Vreg represents a source signal from which the multiple activation signals CMD will be generated; with a variable phase shift making it possible to activate the power supply branches of the power cell 1 sequentially without the need for a synchronization clock signal.

[0042] The reinjection of the output voltage Vout and the noise voltage Vmi into the control circuit 2 makes it possible to obtain a stable multi-phase electrical circuit DI independently of the activation frequency of the required supply branches.

[0043] The noise voltage Vmi is in phase with the conduction of each of the supply branches so as to obtain operation independent of the load and adjustable according to the intended application. In addition, this generation of noise allows the generation of a regulation signal Vreg which reproduces the variation over time of the current passing through the associated supply branch.

[0044] [Fig.2a] illustrates a first example of a power cell 2 of the multi-phase electrical circuit DI according to the invention. In this illustrative and non-limiting example, the power cell 2 is a multi-phase Buck converter for converting the DC input voltage Vin to an output voltage Vout lower than the input voltage. The output voltage Vout is measured on the output node 11. The power cell 2 comprises a plurality of power supply branches PHI to PHN which converge towards the output node 11. The target load 3 is constituted, for example, by a load capacitor Cout and a load resistor Rload connected in parallel between the output node 11 and the electrical ground GND.

[0045] Each power supply branch PH; comprises a first switch Qu, a second switch Qi2, a central node 13, and an associated elementary inductance L; mounted between the central node 13 and the output node 11. For each power supply branch PH;, the central node 13 is separated from the input node 12 by at least the first associated switch Qlh. For each power supply branch PH;, the central node 13 is separated from the ground GND by at least the second associated switch Qi2. The first switch Q^ is controlled by the activation signal CMD; associated with the power supply branch PH;. The second switch Qi2 is controlled by the complement of the activation signal CMD; associated with the power supply branch PH;. For example, when the activation signal CMD; is in a high state, the first switch Qu is in a high state. passing and the second switch Qi2 is in a blocking state. This induces a current flow through the supply branch PH; from the input node 12 to the output node 11 through the associated central node 13 and the associated elementary inductance L;. Conversely, when the activation signal CMD; is in a low state, the first switch Qu is in a blocking state and the second switch Qi2 is in a passing state. This induces the connection of the central node 13 to ground GND and the absence of current in the supply branch PH;. The different activation signals CMD; are phase-shifted such that each supply branch operates with a time lag relative to the others, which helps to distribute the load and reduce current fluctuations. This allows a reduction in current ripples and a decrease in energy losses.By distributing the load across multiple PH power branches, the converter can better handle current fluctuations.

[0046] [Fig.2b] illustrates a second example of a power cell 2 of the multi-phase electrical circuit DI according to the invention. In this illustrative and non-limiting example, the power cell 2 is a multi-phase Buck converter with series capacitor for converting the DC input voltage Vin to an output voltage Vout lower than the input voltage. The power cell 2 according to the second example incorporates all the characteristics and advantages detailed for the first example. The power cell 2 according to the second example is distinguished from the first example by the following: Each power supply branch PH; with i=1 to N1 further comprises an intermediate capacitor Cfly mounted in series between the first switch Qu and the central node 13.Furthermore, for each power supply branch PH; with i=1 to N1, the common node between intermediate capacitance Cfly and the first switch Qu is connected to the first switch Q(i+i) of the following power supply branch PHi+i. The last power supply branch of rank i=N is devoid of the intermediate capacitance Cfly. Only the initial power supply branch PHi is connected to the input node 12 through its first switch Qu. The power cell 2 according to the second example has better technical robustness compared to the first example, because the first and second switches Q^ and Qi2 see at their terminals voltages lower than the input voltage Vin.

[0047] [Fig.3a] illustrates a first example of the voltage regulation circuit 21 of the control circuit 2 according to the invention. The voltage regulation circuit 21 is configured to generate an alternating binary regulation signal Vreg from the combination of the output voltage Vout with a noise voltage Vnoise.

[0048] In the first example, the voltage regulation circuit 21 comprises a resistive divider bridge formed by a pair of resistors R4,R6 separated by a switch Qi. The resistive divider bridge R4,R6 is configured to generate a fraction of the input voltage Vin when the switch Qi is on. The third switch Qi is controlled by the regulation signal Vreg via a feedback loop internal to the voltage regulation circuit 21. The divider bridge R4,R6 controlled by the regulation signal Vreg generates a noise voltage Vnoise synchronized with the regulation signal Vreg. The resistive divider bridge is sized so as to obtain a noise voltage Vnoise when the switch Qi is on equal to the measurable voltage at the central node 13 of the activated power supply branch PH;. The injection of the synchronized noise voltage Vnoise ensures that the currents flowing through the different power supply branches are equal. Thus, the stability of the converter DI is guaranteed without the need for current measurement. On the other hand, the voltage regulation circuit 21 receives the output voltage Vout of the output node 11 propagated via the first feedback loop of the multi-phase electrical circuit DI described in [Fig. 1].The combination of the internally generated noise voltage Vnoise with the back-propagated output voltage Voutforms an intermediate voltage Vint. The voltage regulation circuit 21 further comprises a comparator COMP configured to compare an intermediate signal Vint with a predetermined reference voltage Vref. The output signal of the comparator COMP is the regulation signal Vreg which is a periodic binary signal.

[0049] The voltage regulation circuit 21 further comprises a resistor R2 connected between the output node providing the output voltage Vout and the non-inverting input of the comparator COMP corresponding to the intermediate signal Vint. The resistor R2 makes it possible to superimpose the DC component of the output voltage Vout on the non-inverting input of the comparator COMP.

[0050] The voltage regulation circuit 21 further comprises a capacitor C2 mounted between, on the one hand, the node providing the output voltage Vout and, on the other hand, the node providing the noise voltage Vnoise. The capacitor C2 makes it possible to integrate the noise voltage Vnoise across at least the resistor R4 so as to obtain a triangular signal between the output voltage Vout and the noise voltage Vnoise.

[0051] The voltage regulation circuit 21 further comprises a capacitor Cl mounted between, on the one hand, the output node providing the output voltage Vout and, on the other hand, the non-inverting input of the comparator COMP corresponding to the intermediate signal Vint. The capacitor Cl acts as a high-pass filter. The capacitor Cl makes it possible to superimpose the alternating component of the noise voltage Vnoise on the non-inverting input of the comparator COMP. This gives an intermediate signal Vint having a direct component corresponding to the output voltage Vout and an alternating component corresponding to the noise voltage Vnoise. The impedance of the capacitor Cl is lower than the impedance of the resistor R2 at the operating frequency. This makes it possible to avoid a voltage drop between the noise voltage Vnoise and the intermediate signal Vint.

[0052] The voltage regulation circuit 21 internally generates an intermediate signal Vint triangular synchronized with the branch current on an input of the COMP comparator having two activation thresholds. The intermediate signal Vint reproduces the shape of the current flowing through the inductance of the supply branch in conduction. We thus obtain the periodic binary regulation signal Vreg according to a frequency fregdetermined by the time constant R4.C2 and by the values ​​of the two hysteresis thresholds of the COMP comparator.

[0053] Optionally, the voltage regulation circuit 21 further comprises a resistor R5 mounted between, on the other hand, the node providing the noise voltage Vnoise and, on the other hand, the output of the voltage divider bridge R4, R6. In this case, the frequency freg is determined by the time constant (R4+R5).C2 by the values ​​of the two hysteresis thresholds of the comparator COMP. The addition of the resistor R5 makes it possible to obtain an additional degree of freedom for the dimensioning of the frequency freg

[0054] [Fig.3b] illustrates a second example of the voltage regulation circuit 21 of the control circuit 2 according to the invention. The voltage regulation circuit 21 is configured to generate an alternating binary regulation signal Vreg from the combination of the output voltage Vout with a noise voltage Vnoise.

[0055] In the second example, the voltage regulation circuit 21 comprises N diodes D; of rank i=1 to N with N the number of power supply branches PH;. In this example, it is considered that N=3. Each diode D; of rank i has an anode connected to the central node 13 of the power supply branch PH; associated with said diode D;. The cathodes of the diodes D; are connected to a common node 211. The common node 211 is separated from the electrical ground GND by a switch Q2. The switch Q2 is controlled by the regulation signal Vreg via a feedback loop internal to the voltage regulation circuit 21. For any one of the power supply branches PH;, when the first switch Qu is conducting, the central node 13 is at a central voltage Vmino zero. The corresponding diode D; is subjected to a positive voltage and thus becomes conducting. The other diodes Dj(with j^i) are in the blocking state.The central voltage Vmi is thus propagated towards the common node 211 in order to form the noise voltage Vnoise. This noise signal makes it possible to add to the regulation loop the image of the current passing through the elementary inductance L; of the activated supply branch PH;. This makes it possible to ensure the distribution of the currents in the inductances L; if these are identical. Activation of the switch Q2 ensures the return to ground of the common node 211 when all supply branches are deactivated.

[0056] On the other hand, the voltage regulation circuit 21 receives the output voltage Vout from the output node 11 propagated via the first feedback loop of the multi-phase electrical circuit DI described in [Fig.l]. The combination of the internally generated noise voltage Vnoise with the back-propagated output voltage Vout forms an intermediate voltage Vint. The noise voltage Vnoise is propagated to a common node with the output voltage Vout. The intermediate signal Vint thus has a direct component corresponding to the output voltage Vout and an alternating component corresponding to the noise voltage Vnoise.

[0057] The voltage regulation circuit 21 further comprises a comparator COMP configured to compare an intermediate signal Vint with a predetermined reference voltage Vref. The output signal of the comparator COMP is the regulation signal Vreg which is a periodic binary signal.

[0058] Generally, the voltage regulation circuit 21 generates a periodic binary regulation signal Vreg from an intermediate voltage Vint having a DC component corresponding to the output voltage Vout and an AC component corresponding to the noise voltage Vnoise. This combination ensures that the currents flowing through the different supply branches are equal and thus improves the stability of the converter DI.

[0059] Alternatively, according to a particular embodiment, the N diodes D; of rank i=1 to N are replaced by N switches controlled by external signals. For example, the switches are made by transistors. In this case, it is possible to do without the switch Q2.

[0060] [Fig.4] illustrates the distribution circuit 22 of the control circuit 2 according to the invention. The distribution circuit 22 receives the regulation signal Vreg generated by the voltage regulation circuit 21. The distribution circuit 22 is configured to generate for each power supply branch PH;, a dedicated activation signal CMD; from the regulation signal Vreg. The activation signals CMD; are phase-shifted with each other according to a phase shift without the need for an external clock signal with a fixed frequency. The distribution circuit 22 comprises a chain of N D-type flip-flops, with N the number of power supply branches PH;. As a non-limiting example, an example is described with three power supply branches and therefore three D-type flip-flops denoted 221, 222, 223. The flip-flops 221, 222, 223 are all synchronized by the regulation signal Vreg.The flip-flops 221, 222, 223 are connected such that the output s; of a flip-flop of rank i=1 to N1 is connected to the input of the next flip-flop of rank i+1. The chain of N flip-flops forms a shift register.

[0061] The distribution circuit 22 comprises a logic cell 230 of the OR type having a first input connected to the output s3 of the last flip-flop 223; a second input receiving an initialization signal Initl; and an output connected to the input of the flip-flop of rank i=l. The logic cell 230 makes it possible to initialize the chain of flip-flops by injecting a high logic state on the input of the initial flip-flop of rank i=l when the initialization signal Initl is at a high logic state. During an initialization step which precedes the operation of the converter, the initialization signal Initl is at a high state “1” so as to obtain a logic value “1” on the input of the flip-flop 221 of rank i=l. The inputs and outputs of the other flip-flops in the chain are at a low logic state “0”. Initially, the output of flip-flop 221 of rank i=l is at the low logic state “0”. The distribution circuit 22 further comprises N AND-type logic cells. In the example illustrated, these are the three AND cells denoted 231, 232 and 233. Each AND-type cell has a first input receiving the output of an associated D flip-flop. Each AND-type cell has a second input receiving the regulation signal Vreg. Each AND-type cell is intended to provide the activation signal CMD; to an associated power supply branch PH;. The first AND cell 231 receives the output signal Si from flip-flop 221 and generates the activation signal CMDi to control the power supply branch PHi of rank i=l.The second AND cell 232 receives the output signal s2 from the flip-flop 222 and generates the activation signal CMD2 to control the power supply branch PH2 of rank i=2. The third AND cell 233 receives the output signal s3 from the flip-flop 223 and generates the activation signal CMD3 to control the power supply branch PH3 of rank i=3.

[0062] Generally, a power supply branch PHi supplies current to the load circuit when the associated activation signal CMD; is at a high logic state “1”. The associated activation signal CMD; is at a high logic state “1” when the output signal s; of the associated flip-flop and the regulation signal Vreg are simultaneously at the high logic state “1”.

[0063] In the following, we will describe the temporal evolution of the output signals sb s2 and s3 during a control cycle Cyc comprising three successive steps E1, E2 and E3 as illustrated by the timing diagrams of [Fig.5]. [Fig.5] describes a timing diagram of the internal and external signals of the control circuit 3 so as to illustrate the operation of the distribution circuit 22.

[0064] The first step El is triggered by the initial rising edge FMI on the regulation signal Vreg. Said rising edge causes the transmission of the high logic state "1" from the input of the first flip-flop 221 to its output sb. A high logic state "1" is thus obtained only on the first output sb. The high logic state "1" on the first output Si is also transmitted to the input of the second flip-flop 222. The high logic state "1" is maintained on the output s^ant that there has been no rising edge following the initial rising edge FMI. The output signals s2 and s3 of the other D flip-flops in the chain are maintained at a low logic state "0".Thus, at the beginning of step El, the following configuration is obtained: the output signal Side, flip-flop 221, and the regulation signal Vreg are simultaneously in the high logic state “1”, which generates a high pulse on the activation signal CMDi while maintaining the other activation signals CMD2 and CMD3 in a low logic state. Only the supply branch PHi of rank i=1 is conductive and injects a supply current towards the target load 3.

[0065] The second step E2 is triggered by the rising edge FM2 on the regulation signal Vreg. Said rising edge FM2 causes the transmission of the high logic state “1” from the input of the second flip-flop 222 to its output s2. A high logic state “1” is thus obtained only on the second output s2. The high logic state “1” on the second output s2 is also transmitted to the input of the third flip-flop 223. The OR logic cell 230 receives two low logic states “0” on its two inputs. The output Si of the flip-flop 221 goes to the low logic state “0”. The high logic state “1” is maintained on the output s2 as long as there has been no rising edge following the rising edge FM2. The output signals Si and s3 of the other D flip-flops in the chain are maintained at a low logic state “0”.Thus, at the beginning of step E2, the following configuration is obtained: the output signal s2 of flip-flop 222 and the regulation signal Vreg are simultaneously in the high logic state “1”, which generates a high state pulse on the activation signal CMD2 while maintaining the other activation signals CMDi and CMD3 in a low logic state. Only the power supply branch PH2 of rank i=2 is conductive and injects a power supply current towards the target load 3.

[0066] The third step E3 is triggered by the rising edge FM3 on the regulation signal Vreg. Said rising edge FM3 causes the transmission of the high logic state “1” from the input of the third flip-flop 223 to its output s23. A high logic state “1” is thus obtained only on the third output s3. The high logic state “1” on the third output s3 is also transmitted to the input of the first flip-flop 221 via the OR logic cell 230. The high logic state “1” is maintained on the output s3 as long as there has been no rising edge following the rising edge FM3. Similarly, the rising edge FM3 causes the propagation of the low logic state “0” from the input of the second flip-flop 222 to its output s2. Likewise, for the output si of flip-flop 221. The output signals Si and s2 of the other D flip-flops in the chain are thus maintained at a low logic state “0”.Thus, at the beginning of step E3, the following configuration is obtained: the output signal s3 of flip-flop 223 and the regulation signal Vreg are simultaneously in the high logic state “1”, which generates a high pulse on the activation signal CMD3 while maintaining the other activation signals CMDi and CMD2 in a low logic state. Only the supply branch PH3 of rank i=3 is conductive and injects a supply current towards the target load 3.

[0067] The distribution circuit 22 then makes it possible to generate phase-shifted activation signals CMD; without first knowing a predetermined value of the targeted phase shift or the frequency of the regulation signal Vreg. The number of flip-flops and AND logic cells is equal to the number of power supply branches PH;. The frequency of the regulation signal Vreg which synchronizes the flip-flop chain is divided by the number of power supply branches N. The switching frequency of each of the power supply branches PH; of the converter DI is governed by the following relationship '.fcMD =freg / N; with / regla frequency of the regulation signal Vreg and N the number of PH supply branches;

[0068] The control circuit 2 further comprises means for generating signals complementary to the activation signals CMD; for controlling the second switches Qi2. Said means cover, for example, inverter circuits.

[0069] [Fig.6] illustrates a multi-phase electrical circuit DI according to a second embodiment of the invention. In the second embodiment, the control circuit 2 further comprises a protection circuit 23 inserted between the voltage regulation circuit 21 and the distribution circuit 22. The protection circuit 23 receives the regulation signal Vreg from the voltage regulation circuit 21 and generates a master signal VCmd to the distribution circuit 22. The master signal VcMo plays the role of clock signal for the D flip-flops connected in chain in place of the regulation signal Vreg in comparison with the first embodiment. The protection circuit 23 is configured to limit the duration of the setting high or low of the regulation signal Vreg to a predetermined threshold T0N,max* The protection circuit 23 makes it possible to limit the conduction time of a power supply branch PH;.The control of the maximum conduction time T0N,max makes it possible to cause a controlled and temporary imbalance of the current flowing through the converter supply branches during a transient current front. This imbalance is generally to be avoided but it has been shown that it makes it possible to improve the converter response time if it is allowed for a controlled duration.

[0070] As an example, to implement the protection circuit 23, it is possible to use a D flip-flop used in SET / RESET mode as illustrated in [Fig.7a]. The SET signal sets the master signal VCmd to a high state, and the RESET signal sets it to a low state. In the event of a conflict, the RESET signal prevails. [Fig.7b] illustrates the circuit for generating the RESET signal in the protection circuit 23. The master signal VCMD is injected at the input of a Ton_gen circuit making it possible to set the maximum activation time to T0Njmax. The Ton_gen circuit comprises an RC filter formed by a resistor R23 and a capacitor C23 across which the voltage of the master signal VcMD is applied. The Ton_gen circuit further comprises a diode D23 having its anode connected to the common node between the resistor R23 and the capacitor C23. The cathode of diode D23 is connected to the other pole of resistor R23.The output signal of the Ton_gen circuit is recovered at the common node between the resistor R23 and the capacitor C 23 and it is propagated to a first input of an AND logic cell. The second input of the AND logic cell receives the complement of the regulation signal Vreg (provided by the negative output of the comparator COMP for example). The RESET signal is generated by the memory cell to the D flip-flop of the protection circuit 23.

[0071] [Fig.7c] illustrates the circuit for generating the RESET signal in the protection circuit 23. This is an AND cell receiving the signal on a first input RESET already generated and on the other input the regulation signal Vreg.

[0072] Preferably, according to the second embodiment described in [Fig.6], the control circuit 2 further comprises a dead time circuit 24 inserted between the distribution circuit 22 and the power cell 1. The dead time circuit 24 is configured to generate for each power supply branch, a first CMD; and a second complementary activation signal CMDban-e,i, each transition edge of the second activation signal CMDban-e,i is temporally offset with respect to the first activation signal. This makes it possible to avoid cross-conduction problems between the first switch Qu and the second switch Qi2 in a power supply branch PH;.

[0073] The implementation of the dead time circuit 24 is independent of the implementation of the protection circuit 23 in the control circuit 2 according to the invention. According to a third embodiment, the control circuit 2 comprises the voltage regulation circuit 21, a protection circuit 23 and the distribution circuit 22 as described previously. According to a fourth embodiment, the control circuit 2 comprises the voltage regulation circuit 21, the distribution circuit 22 and the dead time circuit 24 as described previously.

[0074] The invention is compatible with several types of multi-phase circuits, including power converters such as DC / DC, AC / AC, AC / DC, DC / AC, as well as in switched-mode power supplies (SMPS). This solution would be beneficial for any multi-phase, multi-level, or hybrid converter using non-linear control. In addition, inverters for converting direct current to alternating current (DC-AC) in solar, wind, and energy storage systems could also benefit from the generation of controls according to the invention.

Claims

Claims

1. Multi-phase electrical circuit (Dl) configured to generate an output current (Iout) or an output voltage (Vout) to power a target load (3); said multi-phase electrical circuit (Dl) comprising: a power cell (1) comprising: • an input node (12) for providing an input voltage (Vin); • an electrical ground (GND); • an output node (11) for providing said output voltage (Vout), • N feed branches (PHi, PHN) which converge towards the output node (11), N being a natural integer greater than 1, each feed branch (PHi, PHn), comprising: • a central node (13) separated from the input node (12) by at least a first switch (Qn, QNi) and from the electrical ground (GND) by at least a second switch (Q12> Qn2); a control circuit (2) comprising: • a voltage regulation circuit (21) configured to generate an alternating binary regulation signal (Vreg) from the combination of the output voltage (Vout) with an alternating noise voltage (Vnoise); said noise voltage (Vnoise) being generated by the voltage regulation circuit (21) from • the electrical potential of the central node (13) of a chosen supply branch (PHb PHN); • or from the input voltage (Vin); • a distribution circuit (22) configured to generate for each supply branch, at least one dedicated activation signal (CMDi, CMD2, CMD3) from the regulation signal (Vreg); the plurality of activation signals being phase-shifted with each other according to a phase shift which varies over time.

2. A multi-phase electrical circuit (Dl) according to claim 1 wherein the voltage regulating circuit (21) comprises a comparator (COMP) for comparing an intermediate signal (Vint) with a predetermined reference voltage; said intermediate signal (Vint) having a DC component corresponding to the output voltage (Vout) and an AC component corresponding to the noise voltage (Vnoise).

3. Multi-phase electrical circuit (Dl) according to any one of claims 1 or 2 wherein the voltage regulation circuit (21) comprises a divider bridge comprising a pair of resistors (R4, R6) separated by a third switch (Qi) and configured to generate a fraction of the input voltage (Vin) when the third switch is on; the third switch (Qi) being controlled by the regulation signal (Vreg).

4. Multi-phase electrical circuit (Dl) according to any one of claims 1 or 2 wherein the voltage regulation circuit (21) comprises N diodes (Db D2, D3) such that each diode (Db D2, D3) has an anode connected to the central node (13) of a supply branch associated with said diode and such that the cathodes of the diodes are connected to a common node (211) separated from the electrical ground (GND) by a fourth switch (Q2) controlled by the regulation signal (Vreg).

5. Multi-phase electrical circuit (Dl) according to any one of claims 1 to 4 in which the distribution circuit (22) comprises a chain of N D-type flip-flops (221, 222, 223) all synchronized according to the regulation signal (Vreg) and mounted such that: the output of a flip-flop of rank i=l to Nl is connected to the input of the following flip-flop of rank i+1.

6. Multi-phase electrical circuit (Dl) according to claim 5 wherein the distribution circuit (22) further comprises an OR type logic cell having a first input connected to the output of the flip-flop of rank N, a second input receiving an initialization signal (Initl) and an output connected to the input of the flip-flop of rank i=l.

7. A multi-phase electrical circuit (Dl) according to any one of claims 5 or 6 wherein the distribution circuit (22) further comprises N AND-type logic cells; each AND-type cell having a first input receiving the output of an associated D flip-flop and a second input receiving the regulation signal (Vreg) and an output for providing the activation signal (CMDi, CMD2, CMD3) to a branch associated power supply.

8. Multi-phase electrical circuit (Dl) according to any one of claims 1 to 7 wherein the control circuit (2) further comprises a protection circuit (23) inserted between the voltage regulation circuit (21) and the distribution circuit (22) and configured to limit the duration of the setting up or down of the regulation signal (Vreg) to a predetermined threshold.

9. Multi-phase electrical circuit (Dl) according to any one of claims 1 to 8 wherein the control circuit (2) further comprises a dead time circuit (24) inserted between the distribution circuit (22) and the power cell (1) and configured to generate for each power supply branch, a first (CMDb CMD2, CMD3) and a second complementary activation signal (CMDNi, CMDN2, CMDN3), each transition edge of the second activation signal being temporally offset relative to the first activation signal.

10. Multi-phase electrical circuit (Dl) according to any one of claims 1 to 9 in which each supply branch (PHi, PHN) comprises an associated elementary inductance (Lb LN) mounted between the central node (13) and the output node (11); each supply branch (PHi, PHN) being configured to generate an elementary current (h, IN) through the associated elementary inductance.

Images