One-time programmable memory cell

Abstract

One-time programmable memory cell The present description relates to a one-time programmable memory cell (101) comprising:- a first transistor (110) connected between a first selection node (140) and an intermediate node (148); and- a second transistor (120) connected between the intermediate node (148) and a first electrode (152) of a programming element (130), a second electrode (144) of the programming element being connected to a programming voltage rail (HV), the first transistor (110) having a first width and the second transistor (120) having a second width smaller than the first width. Figure for abstract: Fig. 2

Description

Title of the invention: One-time programmable memory cell Technical field

[0001] The present description relates generally to electronic circuits and in particular to single-time programmable memory cells and to methods of manufacturing these cells. Prior art

[0002] In a one-time programmable (OTP) memory, each cell is irreversibly programmable. After a single programming, each one-time programmable cell is no longer programmable and is accessible in read-only mode. After all the cells in the memory have been programmed, the memory then becomes a read-only memory.

[0003] One-time programmable memories are used, for example, for data storage or in trimming circuits.

[0004] Such memories may comprise a large number of memory cells. There is therefore a need for single-programmable memory cells with a small footprint. Summary of the invention

[0005] One embodiment provides a one-time programmable memory cell comprising: - a first transistor connected between a first selection node and an intermediate node; and - a second transistor connected between the intermediate node and a first electrode of a programming element, a second electrode of the programming element being connected to a programming voltage rail, the first transistor having a first width and the second transistor having a second width less than the first width.

[0006] According to one embodiment, the programming voltage rail is configured to receive a voltage greater than a voltage applied to the gate of the second transistor.

[0007] According to one embodiment, the programming element is a third transistor having its gate connected to the programming voltage rail, the gate of the third transistor forming the second electrode of the programming element.

[0008] According to one embodiment, the second width is equal to a third width, the third width corresponding to the width of the third transistor.

[0009] According to one embodiment, the first electrode of the programming element is produced by the source or the drain of the third transistor.

[0010] According to one embodiment, the programming element is a capacitor.

[0011] According to one embodiment, the transistors are MOS type transistors.

[0012] According to one embodiment, the first width corresponds to the grid width of the first transistor and the second width corresponds to the gate width of the second transistor.

[0013] According to one embodiment, the sum of the second width and the third width is less than the first width.

[0014] Another embodiment provides a memory array comprising: - a first memory cell as described above; and - a second memory cell as described above; the second electrode of the programming element of the first and second cells being made of a single continuous conductor.

[0015] According to one embodiment, the first and second memory cells are nested relative to each other and the sum of the second width and the third width is less than the difference of the first width and the width of an isolation trench separating the first and second memory cells.

[0016] Another embodiment provides an electronic device comprising a memory comprising one-time programmable cells, the memory comprising the memory array described above.

[0017] Another embodiment provides a method of manufacturing a one-time programmable memory cell, comprising: - forming a first transistor connected between a first selection node and an intermediate node, with a first width; - forming a second transistor, with a second width less than the first width, connected between the intermediate node and a first electrode of a programming element; and - forming the programming element, a second electrode of the programming element being connected to a programming voltage rail.

[0018] Another embodiment provides a method of manufacturing a memory array comprising: - manufacturing a first memory cell according to the method described above; and - the manufacture of a second memory cell according to the method described above; the second electrode of the programming element of the first and second cells being produced by a single continuous conductor.

[0019] According to one embodiment, the first and second memory cells are nested relative to each other and the sum of the second width and the third width is less than the difference of the first width and the width of an isolation trench separating the first and second memory cells. Brief description of the drawings

[0020] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0021] [Fig.l] schematically represents an example of a one-time programmable memory comprising several memory cells;

[0022] [Fig.2] represents a circuit of a one-time programmable memory cell of [Fig.l] according to an embodiment of the present description;

[0023] [Fig. 3] is a sectional view of a one-time programmable memory cell according to another embodiment of the present disclosure;

[0024] [Fig.4] is a top view of a memory comprising 6 one-time programmable memory cells, according to an embodiment of the present description;

[0025] [Fig.5] is a top view of two one-time programmable memory cells of [Fig.3]; and

[0026] [Fig.6] schematically represents an example of a device comprising the one-time programmable memory cell of [Fig.2] or 3. Description of the embodiments

[0027] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0028] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular, the operation and manufacturing methods of a transistor are known to those skilled in the art and will not be detailed.

[0029] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0030] In the following description, when referring to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., are referred to, unless otherwise specified, the orientation of the figures.

[0031] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0032] [Fig.l] schematically represents an example of a one-time programmable memory 100 comprising 4 memory cells 101 to 104.

[0033] Although in the example of [Fig.l], the memory 100 comprises four memory cells 101 to 104, it will be obvious to those skilled in the art that a smaller or larger number of memory cells may be present in the memory 100.

[0034] The four memory cells are arranged in rows and columns so that the memory cells of the same row are connected to the same row conductor configured to be powered by selection voltages BL0, BL1 and the memory cells of the same column are connected to the same column conductor configured to be powered by selection voltages WL0, WL1. Each of the memory cells is thus connected to one of the selection voltages BL0, BL1 and to one of the selection voltages WL0, WL1.

[0035] Each of the memory cells 101 to 104 comprises a programming element, not illustrated in [Fig.l]. The programming element may for example be in one of two states: a first blank state, before programming, and a second state, after programming, which allows storage of one bit of binary data. The electrical conductivity of the programming element is for example irreversibly modified during programming. For example, the conductivity of the programming element is higher in the second state than in the first state. Measuring the electrical conductivity of one of the memory cells 101 to 104 makes it possible to determine the state of the programming element.

[0036] During a step of programming or reading one of the memory cells 101 to 104, a memory cell is selected by means of the selection voltage BL0, BL1 and the selection voltage WL0, WL1.

[0037] Each of the selection voltages WL0, WL1, BL0, BL1 can for example take one of two voltage values: a low voltage level and a high voltage level. Applying the low voltage level for the selection voltage BL0 activates for example all the memory cells of the corresponding row of cells, the memory cells 101 and 103 in the example of [Fig.l], and applying the high voltage level for the selection voltage WL0 activates for example all the memory cells of the corresponding column of cells, the memory cells 101 and 102 in the example of [Fig.l]. Only the memory cell 101 then simultaneously receiving the low voltage level as selection voltage BL0 and the high voltage level as selection voltage WL0 is configured so that its programming element changes from the first state to the second state during a programming step and so that its electrical conductivity can be measured during a reading step. Such a memory 100 can be programmed and read one memory cell at a time. According to one embodiment, several memory cells of the same row or of the same column can be programmed simultaneously by applying for example a selection voltage WLO and several selection voltages BLO, BL1 or vice versa.

[0038] [Fig.2] shows a circuit of a one-time programmable memory cell 101 of [Fig.l] according to an embodiment of the present description.

[0039] The memory cell 101 comprises for example a transistor 110, a transistor 120, and the programming element 130, connected in series between a selection node 140 and a power supply node 144.

[0040] The selection node 140 is for example configured to receive the selection voltage BLO. The power supply node 144 is for example connected to a voltage rail configured to be supplied by an HV voltage.

[0041] The transistor 110 is connected between the selection node 140 and an intermediate node 148. The gate of the transistor 110 is configured to be supplied by the selection voltage WLO.

[0042] The transistor 120 is connected between the intermediate node 148 and another intermediate node 152. The gate of the transistor 120 is for example connected to a voltage rail configured to be powered by a LV voltage. The transistors 110 and 120 are for example p- or n-channel MOS (Metal Oxide Semiconductor) type transistors. According to one embodiment, the transistors 110 and 120 are silicon-on-insulator (SOI) MOS (Silicon On Insulator) type transistors.

[0043] The programming element 130 has a first electrode connected to the node 152 and a second electrode connected to the node 144. In the example of [Fig. 2], the programming element 130 is a capacitor. According to other embodiments, not illustrated in [Fig. 2], the programming element 130 is a transistor. The programming element 130 comprises for example a layer of an insulating material positioned between two conductive layers. The application of a high voltage, sometimes called breakdown voltage, between the two conductive layers irreversibly modifies the conductivity of the insulating layer. The programming element 130 is therefore in the first state before application of this high voltage and in the second state thereafter. This makes it possible to program the memory cell 101. The reading of the memory cell 101 is carried out by measuring the conductivity of the programming element, which is for example higher in the second state.

[0044] The HV voltage is for example between 3V and 5V during programming, for example between 4V and 5V.

[0045] The low voltage level of the selection voltages BLO and WLO is for example equal to 0V. The high voltage level, for the selection voltages BLO and WLO, is for example between 0.5V and 1.5V, for example between 0.9V and 1.1V.

[0046] The voltage BT is for example higher than the high voltage level of the voltage WLO and lower than the voltage HV, for example between 2V and 2.5V. According to one embodiment, during a reading step, the voltages HV and BT are reduced to avoid involuntary programming of a programming element and reduce the consumption of the memory 100 while still remaining sufficient to ensure the reading of the state of the programming element 130.

[0047] The width of the transistor 120 is less than the width of the transistor 110, which makes it possible to reduce the size of the cell, without reducing the programming current during a write operation. Indeed, in the case where the transistors 110 and 120 have the same width, since the voltage BT is greater than the high voltage level of the voltage WLO, the transistor 110 limits the maximum current which can flow through the memory cell 101, between the node 140 and the node 144. Thus, the width of the transistor 120 can be reduced to a certain extent without impacting the value of the maximum current. For example, the width of the transistor 120 is chosen so that this transistor has a resistance RON, when the voltage BT is applied to its gate, less than or equal to the resistance RON of the transistor 110, when the high voltage level of the voltage WLO is applied to its gate.

[0048] During a programming step, the selection voltage BLO takes the value of the low voltage level and the selection voltage WLO takes the value of the high voltage level. The voltage levels are configured so that the transistor 110 is then on and a current flows between the selection node 140 and the node 148. The voltage BT is chosen so that, when the transistor 110 is on, the transistor 120 is also on and the current flows between the node 148 and the first electrode of the programming element 130. The voltage HV, applied to the second electrode of the programming element 130, is chosen to be high enough so that the breakdown voltage is reached between the first and second electrodes and the programming element 130 passes from the first state to the second state.

[0049] During a reading step, the selection voltage BLO takes the value of the low voltage level and the selection voltage WLO takes the value of the high voltage level so that a current flows between the selection node 140 and the node 144, as described above for a writing step. However, the voltages BLO, WLO, BT and HV are then configured so that the voltage between the two electrodes of the programming element 130 is lower than the breakdown voltage to ensure that the cell of memory 101 is only read and not programmed.

[0050] The voltages HV, BT, WLO and BLO are also chosen so that the breakdown voltage is not reached when the selection voltage BLO is at the high voltage level or the selection voltage WLO is at the low voltage level.

[0051] Although two access transistors 110, 120 are shown in [Fig. 2], a larger number of access transistors, for example three, can be connected in series with the programming element 130. For example, among the access transistors, one of the transistors is the transistor 110, and the others are transistors similar to the transistor 120, and receive at their gate fixed voltages which are for example increasing as they approach the programming element 130.

[0052] [Fig. 3] is a sectional view of a one-time programmable memory cell 301 according to another embodiment of the present disclosure.

[0053] Certain elements of [Fig.3] are similar to those of [Fig.2] and have been referenced with the same reference numbers and will not be described again in detail.

[0054] In the example of [Fig. 3], the transistor 110 and the transistor 120 are n-channel MOS transistors. The programming element 130 of the memory cell 301 is an n-channel MOS transistor 330. The first electrode of the programming element corresponds to a connection node of the transistor 330, for example its source, and the second electrode of the programming element corresponds to the gate of the transistor 330. The third connection node of the transistor 330, for example its drain, is for example not supplied with voltage, and is therefore floating. According to another embodiment, the drain and the source of the transistor 330 are connected to each other.When a sufficiently high voltage is applied between node 152, for example the source of transistor 330, and node 144 corresponding to the gate of transistor 330, the oxide layer located between the gate and the substrate of the third transistor 330 is irreversibly modified and its electrical conductivity is increased.

[0055] In the example of [Fig. 3], the substrate of the transistors 110, 120, 330 is p-doped (“(p)”) and the drain and source of the transistors 110, 120, 330 are heavily n-doped (“(n+)”). Two neighboring transistors share a connection node, for example the drain of the transistor 110 is the same as the source of the transistor 120 and the drain of the transistor 120 is the same as the source of the transistor 330. The transistors are for example surrounded by shallow trench isolation (STI) 360 making it possible to isolate the memory cell 301 from its close environment, for example from another memory cell 301.

[0056] According to embodiments, the transistors 110, 120, 130 are fully depleted MOS SOI (FDSOI, from the English “Fully Depleted Silicon On Insulator”) type transistors. In such SOI structures, an insulating layer is for example present between the doped silicon regions of the transistors and the substrate.

[0057] The gate of each transistor 110, 120, 330 is for example formed from a gate stack comprising a gate conductor 370, 374 and 378 respectively, separated from the silicon substrate by an insulating layer 380, for example oxide.

[0058] [Fig.4] is a top view of a memory 400 comprising 6 memory cells, each produced for example by the one-time programmable memory cell 301 of [Fig.3], according to an embodiment of the present description.

[0059] Certain elements of [Fig.4] are similar to those of [Fig.2] or 3 and have been referenced with the same reference numbers and will not be described again in detail.

[0060] [Fig.4] illustrates certain layers of the architecture of a one-time programmable memory 400 comprising a row formed of 6 memory cells 301. Represented are polysilicon conductive tracks 405, for example gate conductors for transistors or an electrode of a capacitor, metal contacts 420, 422, 424, 428 configured to receive a voltage and doped silicon layers 415, for example the substrate of the transistors.

[0061] Although not visible in the view of [Fig. 4], each transistor 110, 120, 330 comprises the gate stack illustrated in [Fig. 3] extending over the doped silicon region 415 covered by the conductive track 405. The gate conductor 370, 374, 378 of each transistor 110, 120, 330 is for example formed by the portion of the conductive track 405 above the doped region 415, and the extension of this conductive track 405 serves to provide the connection between the gate conductors and the metal contacts 420, 422, 424.

[0062] In the example of [Fig.4], the gate of the transistor 120 has a width L2 less than a width L1 of the gate of the transistor 110. In the example of [Fig.4], the width L2 of the gate of the transistor 120 is equal to a width L3 of the gate of the transistor 330. In other embodiments, the width L2 of the gate of the transistor 120 is between L3 and LL

[0063] Each of the 6 memory cells 301 is configured to receive the same selection voltage BL0, applied, via the metal contacts 428, to its selection node 140, not shown in [Fig.4], connected to the source of its transistor 110. Each of the 6 memory cells 301 is configured to receive one of the selection voltages WL0, WL1, WL2, WL3, WL4, WL5, via the metal contacts 420 connected to its gate conductor 370. Each of the 6 memory cells 301 is configured to receive the voltage BT, via the metal contacts 422 connected to its gate conductor 374. Each of the 6 memory cells 301 is configured to receive the voltage HV, via the metal contacts 424 connected to its gate conductor 378.

[0064] The 415 doped silicon regions are for example surrounded by isolation trenches shallow, for example to be isolated from other neighboring memory cells 301.

[0065] The doped silicon region 415 of each memory cell 301 does not have the shape of a rectangle since the width L1 of the gate of the transistor 110 is greater than the widths L2 and L3. In the example of [Fig.4], the widths L2 and L3 being equal, each memory cell 301 has the shape of an “L”.

[0066] A first and a second neighboring memory cell 301 are for example rotated 180° in the plane relative to each other, so that the first of the two cells has the shape of an “L” and the second has the shape of an inverted “L”. In addition, the two neighboring memory cells 301 are for example nested. To illustrate this characteristic, a first rectangle 440 of width L1 and having the length of the first memory cell 301, surrounding the first memory cell 301 and a second rectangle 445 of width L1 and having the length of the second memory cell 301 surrounding the second memory cell 301 are drawn in [Fig. 4]. The first and second rectangles partially overlap, over a length d.Consequently, the length of a pattern consisting of two neighboring memory cells 301, arranged as described above, is less than twice the length of a memory cell 301, while respecting minimum spacings, determined by manufacturing methods used during the manufacture of the memory 400, between the neighboring doped silicon regions 415 and between the conductive tracks 405.

[0067] In the case where the widths L2 and L3 are equal, this arrangement of nested cells is possible when L2 and L3 are less than L1 divided by 2 and preferably less than (L1-e) / 2, where e is the width of the isolation trench separating two doped silicon regions 415 of neighboring memory cells 301. For example, the width e is equal to or greater than a minimum spacing between two doped silicon regions 415, in the direction of the width of the transistors, the minimum spacing being for example determined by manufacturing methods used during the manufacturing of the memory 400.

[0068] A first pattern and a second pattern are for example juxtaposed so that the source of the transistor 110 of the second memory cell 301 of the first pattern is merged with the source of the transistor 110 of the first memory cell 301 of the second pattern. These sources are for example connected to the same metal contacts 428.

[0069] The arrangement of the memory cells 301 and the difference between the width L1 of the gate of the transistor 110 and the width L2 of the gate of the transistor 120 make it possible, for example, to use the same metal contact 424 and the same conductive track 405 to form the second electrodes of the programming elements 130 of two neighboring memory cells 301. In the example of [Fig.4], the metal contacts 424 and the gate conductors 378 of the transistors 330 of two neighboring memory cells 301 are shared. As a result, only 5 conductive tracks 405, instead of 6, are used to power two memory cells 301.

[0070] The minimum distance separating two conductive tracks 405 (“P”, in English “pitch”) is for example imposed for the manufacturing processes and constrains the minimum width that the memory 400 can have. By using one less conductive line 405 per pattern, the memory 400 has a reduced width of at least P / 2 per memory cell 301 present on a line.

[0071] According to embodiments in which a greater number of access transistors are connected in series with the programming element 130, the width of a memory cell 301 remains reduced by at least P / 2. For example, the width of a memory cell 301 comprising two access transistors 110, 120 is 5P / 2 because 5 conductive tracks are used for two memory cells 301. For example, the width of a memory cell comprising three access transistors, not illustrated in [Fig. 4], is 7P / 2 and one conductive track is used by two neighboring memory cells.

[0072] Although memory 400 comprising memory cells 301 comprising three transistors has been detailed, memory cells 101 comprising a capacitor or other programming element 130 in place of transistor 330 is also possible such that each memory cell 101 comprises two transistors.

[0073] [Fig.5] is a top view of a pattern comprising two one-time programmable memory cells 301 of [Fig.3].

[0074] Certain elements of [Fig.5] are similar to those of [Fig.4] and have been referenced with the same reference numbers and will not be described again in detail.

[0075] [Fig. 5] illustrates an example of an arrangement of two memory cells 301 in which the width L2 of the gate of the transistor 120 is between L3 and LL

[0076] Since the widths L2 and L3 are no longer equal in the example of [Fig. 5], the memory cells 301 no longer have the shape of an “L”. The staggered arrangement described for [Fig. 4] with two nested memory cells 301 remains possible and is reproduced in [Fig. 5]. As for the example of [Fig. 4], the same conductive line 405 is used to form the gate conductors 378 of the transistor 330 of each of the two memory cells 301.

[0077] In the case of [Fig.5], it is possible to nest the cells when L2+L3 is less than Ll, and preferably when L2+L3 is less than Ll-e.

[0078] The surface area of ​​the memory cells 301 remains reduced by reducing the width L2 of the gate of the transistor 120 and only 5 conductive tracks 405 are for example used to power two 301 memory cells.

[0079] [Fig.6] schematically represents an example of a device 600 comprising the memory cell 101 of [Fig.2] or the memory cell 301 of [Fig.3].

[0080] The device 600 is an electronic device comprising a memory 605 (MEM), for example the memory 400 of [Fig. 4]. The memory 605 comprises a matrix formed of a plurality of memory cells 101 or 301 arranged in rows and columns, as well as circuits, not shown in [Fig. 6], configured to program and read the memory cells. The device 600 also comprises, for example, a data processing circuit, such as a processor (“CPU” from the English “Central Processing Unit”) connected to the memory 605.

[0081] The device 600 is for example a laptop, a mobile phone, an electronic tablet or a similar device.

[0082] An advantage of providing a one-time programmable memory cell according to the embodiments described in the present description, in which the width L2 of the gate of the transistor 120 is less than the width L1 of the transistor 110, is to reduce the area of ​​the memory cell and to reduce the area of ​​the memory 400 comprising these memory cells. An advantage of using a single conductive track 405 to power the programming elements 130 of two separate memory cells, in addition to the area gain, is a security gain by making it more difficult to detect data stored in the memory 400. For example, the position of two neighboring programming elements 130 is close together and it will be more difficult for a criminal to distinguish their states by observation techniques of the device containing the memory cells.

[0083] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art. In particular, the number of memory cells and the number of rows and columns comprised by the memory 400 may be different from the examples illustrated in the figures.

[0084] Finally, the practical implementation of the embodiments and variants described is within the reach of the person skilled in the art from the functional indications given above. In particular, the methods of manufacturing transistors and capacitors are within the reach of the person skilled in the art and have not been detailed.

Claims

Claims

1. A one-time programmable memory cell (101, 301) comprising: - a first transistor (110) connected between a first selection node (140) and an intermediate node (148); and - a second transistor (120) connected between the intermediate node (148) and a first electrode (152) of a programming element (130), a second electrode (144) of the programming element being connected to a programming voltage rail (HV), the first transistor (110) having a first width (L1) and the second transistor (120) having a second width (L2) smaller than the first width.

2. The memory cell of claim 1, wherein the programming voltage rail is configured to receive a voltage (HV) greater than a voltage (BT) applied to the gate of the second transistor (120).

3. Memory cell according to any one of claims 1 to 2, in which the programming element (130) is a third transistor (330) having its gate connected to the programming voltage rail (HV), the gate of the third transistor realizing the second electrode of the programming element.

4. The memory cell of claim 3, wherein the second width (L2) is equal to a third width (L3), the third width corresponding to the width of the third transistor (330).

5. Memory cell according to any one of claims 3 to 4, wherein the first electrode (152) of the programming element is realized by the source or the drain of the third transistor (330).

6. A memory cell according to any one of claims 1 to 2, wherein the programming element (130) is a capacitor.

7. A memory cell according to any one of claims 1 to 6, wherein the transistors (110, 120, 330) are MOS type transistors.

8. A memory cell according to any one of claims 1 to 7, wherein the first width (L1) corresponds to the gate width of the first transistor (110) and the second width (L2) corresponds to the gate width of the second transistor (120).

9. A memory cell according to any one of claims 1 to 8, wherein the sum of the second width (L2) and the third width (L3) is less than the first width (L1).

10. Memory matrix comprising: - a first memory cell (101, 301) according to any one of claims 1 to 9; and - a second memory cell (101, 301) according to any one of claims 1 to 9; the second electrode (144) of the programming element of the first and second cells being produced by a single continuous conductor.

11. The memory array of claim 10, wherein the first and second memory cells are nested relative to each other and the sum of the second width (L2) and the third width (L3) is less than the difference of the first width (L1) and the width (e) of an isolation trench separating the first and second memory cells (101, 301).

12. An electronic device comprising a memory comprising one-time programmable cells, the memory comprising the memory array of any one of claims 10 to 11.

13. A method of manufacturing a one-time programmable memory cell, comprising: - forming a first transistor (110) connected between a first selection node (140) and an intermediate node (148), with a first width (L1); - forming a second transistor (120), with a second width (L2) smaller than the first width, connected between the intermediate node (148) and a first electrode (152) of a programming element (130); and - forming the programming element (130), a second electrode (144) of the programming element being connected to a programming voltage rail (HV).

14. A method of manufacturing a memory array comprising: - manufacturing a first memory cell (101, 301) according to the method of claim 13; and - manufacturing a second memory cell (101, 301) according to the method of claim 13; the second electrode (144) of the programming element of the first and second cells being made by a single continuous conductor.

15. A method of manufacturing a memory array according to claim 14, wherein the first and second memory cells are nested relative to each other and the sum of the second width (L2) and the third width (L3) is less than the difference of the first width (L1) and the width (e) of an isolation trench separating the first and second memory cells (101, 301).

Images