Heterostructure comprising a rough exposed portion of a support substrate

Abstract

The present invention relates to a method of manufacturing a heterostructure for manufacturing a piezoelectric-on-insulator, POI, structure, comprising providing a support substrate, forming a block of piezoelectric material on or above the support substrate, removing a first peripheral portion of the block of piezoelectric material and a first peripheral portion of the support substrate to obtain an exposed portion of the support substrate having a roughness with a root mean square height, Sq, in the range of 0.4 µm to 0.8 µm, thinning the block of piezoelectric material after removing the first peripheral portion of the block of piezoelectric material to obtain a piezoelectric substrate, and implanting a species into the piezoelectric substrate to obtain a weakened layer in the piezoelectric substrate. Figure for abstract: Fig. 2C

Description

Title of the invention: Heterostructure comprising a rough exposed portion of a support substrate

[0001] The present invention relates to heterostructures intended for the manufacture of piezoelectric on insulator, POI, structures, in particular POI structures usable for the manufacture of microelectronic, micromechanical and photonic devices, and to processes for manufacturing such heterostructures.

[0002] In the field of microelectronics, micromechanics and photonics, POI structures are of increasing importance due to, for example, superior sensitivity and information propagation properties. For example, devices such as surface acoustic wave (SAW) devices, or bulk acoustic wave (BAW) devices, using the piezoelectric effect to transduce an electrical signal into a mechanical / acoustic wave offer particularly advantageous options, not only for telecommunication applications, due to a wide variety of measurable ambient parameters, including temperature, pressure, strain and torque, for example.

[0003] A typical POI structure comprises a layer of piezoelectric material, in particular, a single-crystal material, such as, for example, lithium niobate (LiNbO3) or lithium tantalate (LiTaO3), formed on a substrate, for example, made of silicon. Various processes for forming a thin layer of piezoelectric material on the substrate are known in the art. The application of Smart Cut™ technology has proven particularly advantageous. According to this technology (see, for example, WO 2019 / 186032 and WO 2020 / 200986 A1), a heterostructure (virtual donor or pseudo-donor structure) comprising a piezoelectric substrate formed on a supporting substrate is provided. The piezoelectric substrate is implanted by light species (H and / or He) to form a weakened region in the piezoelectric substrate, and then the piezoelectric substrate is bonded to a target substrate.By fracturing at the weakened region, a thin layer of piezoelectric material can be obtained on the target substrate.

[0004] A problem that arises when producing such a pseudo-donor is its fragility. Specifically, piezoelectric substrates used in microelectronics are provided with a peripheral chamfer that makes it possible to avoid sharp corners, which are particularly fragile, on the edge of the piezoelectric substrates. The chamfers make it easier to handle the substrates and they avoid edge fragments that could be produced if these edges were protruding edges, these fragments being sources of particulate contamination of the wafer surface. Given the thinness of the thinned piezoelectric substrate, said piezoelectric substrate has a sloped edge due to the chamfer and thus forms a very thin and fragile strip. However, the debris created by this strip breakage is likely to contaminate the production line and the substrates produced on this line. Therefore, it has been proposed (WO 2022 / 195225 A1) to remove an annular portion of the piezoelectric substrate before or after bonding this piezoelectric substrate to the pseudo-donor support substrate, which makes it possible to prevent the formation of a fragile strip of piezoelectric material.

[0005] Due to the removal of the annular portion of the piezoelectric substrate, however, the support substrate is partially exposed to ion implantation for each layer transfer for which the pseudo-donor is (re)used since current refresh procedures for reuse only address the preparation of the surface of the piezoelectric layer. Due to the exposure of a portion of the support substrate, species implanted to form the weakened layer in the piezoelectric substrate also accumulate in this portion, which, disadvantageously, can lead to blistering and flaking if a certain threshold of the concentration of the accumulated implantation in the exposed portion of the support substrate is exceeded.

[0006] Therefore, an object of the present invention is to provide a high quality heterostructure for the manufacture of POI structures which is free from blistering and chipping.

[0007] The present invention meets this object by providing a method for manufacturing a heterostructure (pseudo-donor, PSD, or virtual donor structure) for the manufacture of a structure of the piezoelectric on insulator type, POI for "Piezoelectric on Insulator" in English, comprising the steps of (carried out subsequently in the given order):

[0008] providing a supporting (handling) substrate (e.g., a silicon substrate);

[0009] forming a block of a piezoelectric material (e.g., consisting of, or comprising, a lithium tantalite or lithium niobate substrate) on or above the support substrate;

[0010] removing a first peripheral portion of the block of piezoelectric material and a first peripheral portion of the support substrate (below a portion of the first peripheral portion of the block) to obtain an exposed portion of the support substrate (free of removed piezoelectric material) having a roughness with a root mean square height, Sq, in the range of 0.4 pm to 0.8 pm, for example, 0.5 pm to 0.7 pm;

[0011] thinning the block of piezoelectric material after removing the first peripheral portion of the block of piezoelectric material to obtain a piezoelectric substrate; and

[0012] implanting a species (e.g., hydrogen, optionally supplemented with helium) into the piezoelectric substrate to obtain a weakened layer in the piezoelectric substrate.

[0013] Here and hereafter, the parameters related to roughness are defined by the ISO 25178 standard and measured by a 3D optical profilometer from Wyko, for example, with a 15X or 75X objective.

[0014] It has been found that a roughness with a root mean square height, Sq, in the range of 0.4 pm to 0.8 pm, e.g., 0.5 pm to 0.7 pm, advantageously allows during a heat treatment at a subsequent processing step (e.g., for detachment of a piezoelectric layer to be transferred) an efficient outward diffusion of species which are inevitably implanted into the exposed portion of the support substrate during the process of implanting the species into the piezoelectric substrate to form the weakened layer necessary to facilitate the layer transfer onto a target substrate. The root mean square height, Sq, may be of the same order of magnitude as the implantation depth of the species (which depends on the chosen implantation energy). Blistering and flaking of the support substrate may be effectively prevented by the outward diffusion of the implanted species.

[0015] It is noted that after refreshing the piezoelectric substrate after a first layer transfer process, another layer transfer process, in fact, a number (e.g., 6) of subsequent layer transfer processes, may be performed using the heterostructure. Thus, the exposed portion of the support substrate is subjected to a number of implantation processes. The claimed root mean square height, Sq, effectively counteracts the accumulation of implanted species in the exposed portion of the support substrate which could otherwise give rise to a significant risk of blistering and flaking.

[0016] The piezoelectric substrate obtained by thinning the block of piezoelectric material may be subjected to chemical mechanical polishing, CMP. Forming the block of piezoelectric material on or above the support substrate may comprise bonding the block of piezoelectric material to the support substrate by means of a dielectric bonding layer, for example, a photopolymer (UV) layer or a layer consisting of, or comprising, silicon oxide and / or silicon nitride.

[0017] According to one embodiment, the exposed portion of the support substrate is obtained having a roughness with a maximum height, Sz, in the range of 4 pm to 8 pm, by e.g., 5 pm to 7 pm. A maximum height in this range may further facilitate outward diffusion of implanted species from the exposed portion of the supporting substrate.

[0018] Other roughness parameters which, based on experiments, have been found to be advantageous with respect to the out-diffusion of species implanted into the exposed portion of the support substrate during subsequent heat treatment include a roughness period in the range of 0.15 pm to 1.5 pm, in particular, 0.3 pm to 0.5 pm.

[0019] In particular, the block of piezoelectric material and the support substrate are both chamfered. According to one embodiment, the method of manufacturing a heterostructure further comprises forming a chamfer in a second peripheral portion of the block of piezoelectric material and forming a chamfer in a second peripheral portion of the support substrate before forming the block of piezoelectric material on or above the support substrate. For example, the first peripheral portion of the block of piezoelectric material includes at least a portion of the second peripheral portion thereof such that some or even all of the chamfered portion of the block of piezoelectric material is no longer present in the piezoelectric substrate due to the removal of the first peripheral portion of the block of piezoelectric material.For example, only a small portion of the chamfered portion of the support substrate is removed by removing the first peripheral portion of the support substrate.

[0020] According to one embodiment, the removal of the first peripheral portion of the block of piezoelectric material and the first peripheral portion of the support substrate is performed by grinding using an abrasive wheel. In this case, the method may further comprise placing the support substrate, with the block of piezoelectric material formed thereon or above it, on a support that is rotatable about a first axis and rotating the abrasive wheel about a second axis parallel to the first axis. The abrasive wheel is gradually moved toward the substrate in a direction parallel to the first axis to gradually grind the material off the substrate. It has been found that this particular grinding procedure can reliably produce the desired roughness characteristics that facilitate the outward diffusion of species implanted in the exposed portion of the support substrate.It is noted that, depending on the width of the peripheral portions to be removed, the abrasive wheel can be moved in a direction perpendicular to the first axis in order to gradually grind the material of the intermediate heterostructure in the radial direction.

[0021] Further, there is provided a method of manufacturing a piezoelectric-on-insulator, POI, type structure, comprising carrying out the steps of the method of fabricating a hetero structure according to one of the examples described above and transferring a piezoelectric layer from the piezoelectric substrate to a target substrate comprising bonding the hetero structure to the target substrate on the side of the piezoelectric substrate and fracturing the piezoelectric substrate at the weakened layer, for example, in an annealing process.

[0022] Thus, the piezoelectric layer can be reliably transferred to the target substrate without excessively heavy defects. Additional post-processing (annealing and polishing) may, however, still be necessary to provide a piezoelectric layer suitable for particular applications. It is noted that naturally occurring silicon oxide may be present between the transferred piezoelectric layer and the target substrate. Furthermore, a dielectric assembly layer may be formed on or above a surface of the target substrate prior to the transfer of the piezoelectric layer to that surface. This dielectric assembly layer may consist of, or include, silicon oxide and / or silicon nitride or a stack of layers composed of these materials.Additionally, depending on the actual application, a charge trapping layer may be formed on or above a surface of the target substrate prior to transferring the piezoelectric layer to that surface. The charge trapping layer may consist of, or include, polycrystalline silicon.

[0023] Once the layer transfer of the heterostructure onto the target substrate is completed, the piezoelectric substrate may be refreshed (in particular, polished) for reuse of the heterostructure for a subsequent layer transfer process.

[0024] Further, there is provided a piezoelectric-on-insulator, POI, structure comprising a piezoelectric layer formed on or above a target substrate and obtainable by the method of manufacturing a POI structure. Further, there is provided a microelectronic, micromechanical or photonic device or a microelectromechanical system comprising such a POI structure.

[0025] The above-mentioned object of the present invention is also achieved by providing a heterostructure for manufacturing a piezoelectric-on-insulator, POI, structure, the heterostructure comprising a support substrate (e.g., a silicon substrate), a piezoelectric substrate (e.g., a lithium tantalite or lithium niobate substrate) formed on or above the support substrate, and a weakened layer formed in the piezoelectric substrate by ion implantation. The support substrate includes an exposed peripheral portion free of material of the piezoelectric substrate, and the peripheral portion of the support substrate has a roughness with a root mean square height, Sq, in the range of 0.4 μm to 0.8 μm. In particular, the peripheral portion of the support substrate of the heterostructure may have a roughness with a maximum height in the range from 4 pm to 8 pm. More particularly, the peripheral portion of the support substrate of the heterostructure may have a roughness with a period in the range of 0.15 pm to 1.5 pm. The support substrate of the provided heterostructure may be chamfered.

[0026] The heterostructure may be formed according to one of the above-described examples of a method for manufacturing a heterostructure or may be a refreshed heterostructure obtained by refreshing the piezoelectric substrate after a previously performed transfer of a piezoelectric layer (part of the piezoelectric substrate) onto a target substrate. After respective refresh processes performed on the piezoelectric substrate, the heterostructure may be used multiple times (e.g., 6) for subsequent layer transfer processes.

[0027] Additional features and advantages of the present invention will be described with reference to the drawings. In the description, reference is made to the accompanying drawings, which are intended to illustrate preferred embodiments of the invention. It should be understood that such embodiments do not represent the full scope of the invention.

[0028] [Fig-1] illustrates steps of a method of manufacturing a heterostructure according to a embodiment of the present invention.

[0029] [Fig.2A] illustrates different states of fabrication of a heterostructure according to an embodiment of the present invention.

[0030] [Fig.2B] illustrates different states of fabrication of a heterostructure according to an embodiment of the present invention.

[0031] [Fig.2C] illustrates different states of fabrication of a heterostructure according to an embodiment of the present invention.

[0032] [Fig.3] illustrates a procedure for removing peripheral portions of a solid block of piezoelectric material and a supporting substrate of an intermediate heterostructure according to an embodiment of the present invention.

[0033] Herein, there is provided a method of manufacturing a heterostructure comprising a piezoelectric substrate formed on or above a support substrate, wherein the heterostructure is intended to be used for manufacturing a POI structure. The present invention is however not limited to piezoelectric materials, and can be applied to any type of material suitable for subsequent transfer to a final substrate. In particular, for materials acting as donor material which have a coefficient of thermal expansion which is substantially different from the coefficient of thermal expansion of the final target substrate, it appears advantageous to form the above-mentioned heterostructure facilitating said transfer using SmartCut™ technology.The present invention makes it possible to avoid any complication concerning the use of said heterostructure for several transfers by avoiding the accumulation of ionic species, in particular hydrogen and / or helium, which are. used to determine the weakened area of ​​the layer to be transferred, in the support substrate and, thus, avoiding blistering or flaking of any kind. The support substrate of the resulting heterostructure comprises an exposed peripheral portion free from the donor material, in particular from the piezoelectric substrate, in which the exposed peripheral portion has a dedicated roughness which allows efficient external diffusion of the unintentionally implanted ions (used for the generation of a weakened layer in the piezoelectric substrate) during a certain heat treatment. The method can be represented by a method for manufacturing a POI structure according to the Smart Cut™ technology.

[0034] [Fig.l] illustrates steps of a method of manufacturing a hetero structure according to an embodiment of the present invention. The method comprises forming 11 a chamfered solid block of piezoelectric material on or above a chamfered support substrate. The piezoelectric material may be lithium tantalate (LiTaO3) or lithium niobate (LiNbO3). The function of the support substrate is to temporarily support a piezoelectric substrate to be formed from the solid block of piezoelectric material until a portion of the piezoelectric substrate (piezoelectric layer) is transferred to a target substrate.

[0035] The thickness of the support substrate may be a few hundred micrometers. The support substrate may be made of a material (or a plurality of materials) having a coefficient of thermal expansion close to that exhibited by a target substrate onto which a piezoelectric layer is to be transferred. In particular, the coefficient of thermal expansion of the support substrate may differ from that of the target substrate by a value less than the difference in the coefficient of thermal expansion of the piezoelectric substrate and that of the target substrate. The support substrate and the target substrate may have identical coefficients of thermal expansion and both substrates may, for example, consist of, or comprise, silicon. Other possible materials of the support substrate include glass, quartz, sapphire, a ceramic or polycrystalline aluminum nitride (AIN).As already mentioned, the present invention is not limited to piezoelectric materials, and similar reasoning can be applied to other materials suitable for transferring a layer onto a target substrate.

[0036] The chamfers of the support substrate and the solid block of piezoelectric material may have angles of 22° to 40° relative to the respective main surfaces and may extend over a height in the range of 200 to 300 pm in the direction of the respective thicknesses and a width in the range of 200 to 300 pm in the radial direction of the respective substrate / block.

[0037] Forming 11 the chamfered solid block of piezoelectric material on or above the chamfered support substrate may include securing the solid block chamfered block of piezoelectric material to the chamfered support substrate using a bonding technique. The bonding may be of the molecular adhesion type and / or induced by a dielectric bonding layer (adhesion), for example, a photopolymer (UV) layer or a layer consisting of, or comprising, silicon oxide and / or silicon nitride. The polymer layer may be formed by depositing a photopolymerizable layer on the surface of at least one of the block and the support substrate, bonding the block to the support substrate via the photopolymerizable layer and irradiating the resulting assembly. The bonding process may comprise the application of a low temperature heat treatment (for example, at a temperature between 50 and 300 °C, typically 100 °C) making it possible to strengthen the bonding energy sufficiently to allow a subsequent procedural step of thinning the block of piezoelectric material.

[0038] Due to the thinning of the solid block of piezoelectric material, however, a remaining chamfer of the resulting piezoelectric substrate would have a peripheral chamfered edge comprising an acute angle at the major face. An edge with such an acute angle is susceptible to breakage when the heterostructure is handled, in particular, bonded to a target substrate. This breakage effect, called "chip-off," is particularly harmful, as debris from the thinned donor substrate could contaminate and damage the entire production line using the heterostructure. Such an effect can be avoided by removing a peripheral portion of the solid block of piezoelectric material or the piezoelectric substrate. In principle, the peripheral portion can be removed from the block before or preferably after bonding to the supporting substrate.By removing the peripheral portion, a chamfer remaining in the piezoelectric substrate after thinning the block can be at least partially, in particular completely, removed from the piezoelectric substrate.

[0039] The method illustrated in [Fig.l] comprises removing 12 a peripheral portion of the chamfered block of piezoelectric material and a peripheral portion of the chamfered support substrate after bonding, but before thinning the block. After removing 12 the respective peripheral portions, a step 13 of thinning the solid block of piezoelectric material is performed to obtain a piezoelectric substrate.

[0040] During step 12 of removing the peripheral portion of the chamfered block of piezoelectric material and the peripheral portion of the chamfered support substrate, the resulting exposed portion of the support substrate is provided with dedicated roughness characteristics.

[0041] The thinning step 13 is carried out such that the resulting piezoelectric substrate has a sufficiently low thickness so that the stresses generated during the heat treatment applied in a subsequent treatment step are reduced. On the other hand, the thickness must be sufficiently high to provide one piezoelectric layer to be transferred onto a target substrate or to provide a plurality of such layers to be transferred one after the other in multiple transfer steps (after the respective regeneration of the piezoelectric substrate) onto respective target substrates. The thickness of the piezoelectric substrate resulting from the thinning of the bulk block may be, for example, between 5 and 400 pm, for example, 10 pm to 100 pm or 200 pm, in particular between 15 pm and 40 pm.

[0042] Thinning 13 of the block of piezoelectric material may be accomplished by grinding, chemical mechanical polishing, or etching which may be performed in a number of steps. A first portion of the block may be removed by rough grinding, thereby rapidly reducing the thickness of the block. Then, finer grinding may be performed to further reduce the thickness of the block, while decreasing the surface roughness of the resulting piezoelectric substrate. Finally, chemical mechanical polishing (CMP) may be performed to smooth the surface of the piezoelectric substrate to achieve desired surface smoothness characteristics.

[0043] In step 14 of the method illustrated in [Fig.l], hydrogen and / or helium is implanted into the piezoelectric substrate to form a weakened layer that defines a piezoelectric layer to be transferred from the remaining portion of the piezoelectric substrate. The nature and dose of the implanted species and the implantation energy may be chosen depending on the thickness of the piezoelectric layer that is to be transferred to a target substrate and the physicochemical properties of the piezoelectric substrate 1a. For example, for a lithium tantalate substrate, a dose of hydrogen ions between 1016 and 5-1017 at / cm2 with an energy between 30 keV and 300 keV may be implanted to delimit a piezoelectric layer with a thickness of approximately 200 nm, for example.

[0044] The heterostructure thus obtained can be easily used for transferring the piezoelectric layer onto a target substrate. For this purpose, the heterostructure is attached to the target substrate on the side of the piezoelectric substrate by molecular adhesion and / or electrostatic bonding. A dielectric assembly layer can be provided between the piezoelectric substrate of the heterostructure and the target substrate. The dielectric assembly layer can comprise an oxide and can consist of, or comprise, silicon oxide and / or silicon nitride or a stack of layers composed of these materials, or be made of amorphous silicon when an adiabatic bond is envisaged. Furthermore, a charge trapping layer, for example, consisting of, or comprising, polycrystalline silicon, can be formed on or above the target substrate to enhance the electrical resistivity thereof if desired by an actual application.

[0045] The piezoelectric layer is then detached from the remaining portion of the heterostructure to obtain a POI structure comprising the target substrate, the dielectric assembly layer (if provided), the charge trapping layer (if provided) and the piezoelectric layer. Detachment at the weakened layer may be facilitated by heat treatment in a temperature range of about 100°C to 600°C to allow transfer of the piezoelectric layer to the target substrate. Alternatively or additionally, detachment at the weakened layer may be facilitated by the application of a blade or jet of gaseous or liquid fluid or any other mechanical force applied to the weakened layer.

[0046] Post-processing of the transferred piezoelectric layer is necessary to obtain a transferred piezoelectric layer 3 having satisfactory single-domain crystal and surface quality (reduced roughness) and thickness uniformity as required by actual applications. The post-processing may include heat treatment and a polishing process.

[0047] During ion implantation 14, ions are inevitably implanted into the exposed portion of the support substrate formed in step 12 of the method illustrated in [Fig.l]. After the layer transfer described above, the heterostructure can be reused separately after refreshing the piezoelectric substrate for further layer transfer processes and each refresh again includes ion implantation. Accumulation of implanted ions in the exposed portion of the support substrate is prevented by the roughness characteristics intentionally provided for this exposed portion of the support substrate in step 12. The implantation region in the support substrate has an average depth that depends on the ion implantation energy.The average path length of implanted species for outward diffusion during any heat treatment is, however, much smaller than this depth due to the provided roughness profile. The implanted species can be easily mobilized and can rapidly diffuse out of the supporting substrate, thus significantly reducing the risk of blistering caused by an accumulated dose of implanted species.

[0048] Experiments have proven that a roughness with a root mean square height, Sq, in the range of 0.4 pm to 0.8 pm, in particular, 0.5 pm to 0.7 pm, is suitable for reliably achieving this external scattering effect, in particular, in the case of a silicon substrate and hydrogen ions implanted with an energy between 30 keV and 300 keV. The external scattering of the implanted species from the supporting substrate can be further facilitated by a roughness with a height maximum, Sz, i.e. the difference between the maximum peak height and the maximum valley height, in the range from 4 pm to 8 pm, in particular, from 5 pm to 7 pm. The external diffusion of implanted species from the supporting substrate can be further facilitated by a roughness having a period in the range from 0.15 pm to 1.5 pm, in particular from 0.3 pm to 0.5 pm. All given parameters are determined according to ISO 25178 and measured by a 3D optical profilometer from Wyko, for example, with a 15X or 75X objective.

[0049] Figures 2A to 2C illustrate various fabrication states of a heterostructure (intermediate) according to one embodiment of the present invention. The fabrication states shown can be obtained by means of the method steps illustrated in [Fig. 1]. As shown in [Fig.2A], a solid block of a piezoelectric material 1 is formed on or above a support substrate 2 to obtain an intermediate heterostructure. Although no bonding layer is shown in [Fig.2A], a polymer layer as described above can be used to provide the bond between the block 1 and the support substrate 2.

[0050] Each of the block 1 and the support substrate 2 has a peripheral chamfer C on each of their respective main faces. [Fig. 2A] schematically illustrates the operation of removing a peripheral portion of the solid block of a piezoelectric material 1 after its bonding to the support substrate 2, but before the thinning of the block 1 to obtain a piezoelectric substrate (already indicated by the reference numeral 10 in [Fig. 2A]) of thickness e. In the illustrated example, the thickness e is less than the thickness of the chamfer C of the piezoelectric substrate to be formed from the block 1. The thick dotted line in [Fig. 2A] delimits the peripheral portions of the block 1 and the support substrate 2 which are removed. In the illustrated example, the width L of the removed peripheral portion is greater than the entire width of the chamfers C, in particular, the width L is between 0.1 mm and up to 5 mm.The support substrate 2 is removed to a depth ranging from 0.4 pm up to 0.8 pm, in particular at least to the depth corresponding to the predetermined level of roughness necessary to diffuse implanted species out of the support substrate 2.

[0051] [Fig.2B] is a cross-sectional view of the periphery of an intermediate heterostructure comprising the solid block of a piezoelectric material 1 (before its thinning) and the support substrate 2 after the removal of the respective peripheral portions.

[0052] [Fig.2C] is a cross-sectional view of the periphery of the heterostructure H resulting from the thinning of the block 1 to obtain the piezoelectric substrate 10. In the example illustrated, only the support substrate 2 of the heterostructure H still has a chamfer while the edge of the piezoelectric substrate 10 forms an angle right angle (alternatively, an obtuse angle) with the surface of the support substrate 1, and is therefore less likely to break.

[0053] [Fig. 3] illustrates a procedure for removing peripheral portions of a solid block of piezoelectric material and a supporting substrate of an intermediate heterostructure according to an embodiment of the present invention. The procedure can be used to perform step 12 of the method illustrated in [Fig. 1] or to obtain the intermediate heterostructure shown in [Fig. 2B].

[0054] The intermediate heterostructure is positioned on a support S rotated about an axis XI (of revolution) of the intermediate heterostructure. A cutting tool T, such as an abrasive wheel, is rotated about an axis X2 parallel to the axis XI and is brought towards the peripheral portions to be removed. Said tool is gradually moved towards the intermediate heterostructure in a direction parallel to the axis XI in order to gradually grind the material of the intermediate heterostructure with which it comes into contact. As a grinding wheel, one can choose in a non-limiting example, for example, a diamond wheel with synthetic diamond as abrasive material with an average grain size ranging from 10 μm to 100 μm, in particular around 50 μm.

[0055] The effect of grinding is to locally harden the material ground by the tool so that the exposed surface has a predetermined roughness. It may be advantageous to perform polishing, for example chemical mechanical polishing (CMP), of the surface of the piezoelectric substrate in order to avoid bonding defects during subsequent transfer to a receiving substrate. The exposed portion of the support substrate is not polished and has the roughness characteristics described above which, advantageously, facilitate external diffusion of implanted species during any subsequent heat treatment.

Claims

Claims

1. A method of manufacturing a heterostructure (H) for manufacturing a piezoelectric-on-insulator, POI, structure, comprising providing a support substrate (2); forming (11) a block of piezoelectric material (1) on or above the support substrate (2); removing (12) a first peripheral portion of the block of piezoelectric material (1) and a first peripheral portion of the support substrate (2) to obtain an exposed portion of the support substrate (2) having a roughness with a root mean square height, Sq, in the range of 0.4 pm to 0.8 pm; thinning (13) the block of piezoelectric material (1) after removing the first peripheral portion of the block of piezoelectric material (1) to obtain a piezoelectric substrate (10); and implanting (14) a species into the piezoelectric substrate (10) to obtain a weakened layer in the piezoelectric substrate (10).

2. The method according to claim 1, wherein the first peripheral portion of the block of a piezoelectric material (1) and the first peripheral portion of the support substrate (2) are removed to obtain an exposed portion of the support substrate (2) having a roughness with a maximum height, Sz, in the range of 4 pm to 8 pm.

3. The method according to claim 1 or 2, wherein the first peripheral portion of the block of a piezoelectric material (1) and the first peripheral portion of the support substrate (2) are removed to obtain an exposed portion of the support substrate (2) having a roughness period in the range of 0.5 pm to 1.5 pm.

4. The method according to one of the preceding claims, wherein the block of piezoelectric material (1) and the support substrate (2) are chamfered before forming (11) the block of a piezoelectric material (1) on or above the support substrate (2).

5. The method according to one of the preceding claims, wherein the removal of the first peripheral portion of the block of piezoelectric material (1) and the first peripheral portion of the support substrate (2) is carried out by grinding by means of an abrasive wheel (T).

6. The method of claim 5, further comprising placing the support substrate (2), with the block of piezoelectric material (1) formed thereon or above it, on a support (S) which is rotatable about a first axis (XI); and wherein the grinding comprises rotating the abrasive wheel (T) about a second axis (X2) parallel to the first axis (XI).

7. A method of manufacturing a piezoelectric-on-insulator, POI, structure, comprising performing the steps of one of the preceding claims; and transferring a piezoelectric layer from the piezoelectric substrate (10) to a target substrate comprising bonding the heterostructure (H) to the target substrate on the side of the piezoelectric substrate (10) and fracturing the piezoelectric substrate (10) at the weakened layer.

8. A piezoelectric-on-insulator, POI, structure comprising a piezoelectric layer formed on or above a target substrate and obtainable by the method of claim 7.

9. Microelectronic, micromechanical or photonic device or micro-electro-mechanical system comprising the POI structure (9) according to claim 8.

10. A heterostructure (1) for manufacturing a piezoelectric-on-insulator, POI, type structure, the heterostructure comprising a support substrate (3); a piezoelectric substrate (10) formed on or above the support substrate (2); and a weakened layer formed in the piezoelectric substrate (10) by ion implantation; wherein the support substrate (2) includes an exposed peripheral portion free of material of the piezoelectric substrate (10) and the peripheral portion of the support substrate (2) has a roughness with a root mean square height, Sq, in the range of 0.4 pm to 0.8 pm.

11. The heterostructure according to claim 10, wherein the peripheral portion of the support substrate (2) has a roughness with a maximum height in the range of 4 pm to 8 pm.

12. 15 The heterostructure according to claim 10 or 11, wherein the peripheral portion of the support substrate has a roughness with a roughness period in the range of 0.5 pm to 1.5 pm.

13. The heterostructure according to any one of claims 10 to 12, wherein the support substrate (2) is chamfered.

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