Method and device for controlling the output resistance of a data transmitter

Abstract

Method and device for controlling an output resistor of a data transmitter. This description relates to a data transmission circuit (100) comprising: - an output branch (101) including a first resistor (102), a first transistor (104) and a second transistor (106) connected in series between a first voltage rail (108) and a first output node (OUT_P), the second transistor (106) being configured to receive a data signal (DATAP) on its gate; - a duplication branch (110) of the output branch (101), between the first voltage rail (108) and a second node (118); - a current source connecting the second node (118) and a second voltage rail (119); - a voltage control circuit (OA1) configured to control a gate voltage. Figure for the abstract: Fig. 1

Description

Title of the invention: Method and device for controlling the output resistance of a data transmitter. Technical field

[0001] This description relates generally to electronic circuits and more particularly to a circuit and a method for transmitting data. Previous technique

[0002] A data transmission circuit is associated with an output resistor. In some cases, it is desirable to maintain an output resistance within a range of values ​​to limit losses during data transmission or when a standard constrains the output resistance within a range of values.

[0003] Solutions exist for adjusting the output resistances of a data transmission circuit. However, existing solutions do not compensate with sufficient accuracy for variations in temperature and / or manufacturing processes. Summary of the invention

[0004] According to a first aspect, a data transmission circuit is planned comprising: - an output branch comprising a first resistor, a first transistor and a second transistor connected in series between a first voltage rail and a first output node, the second transistor being configured to receive a data signal on its gate; - a duplication branch of the output branch with equal dimensions or a fixed ratio N with respect to the output branch, the duplication branch comprising a second resistor, a third transistor and a fourth transistor connected in series between the first voltage rail and a second node, the fourth transistor being configured to receive the data signal on its gate; - a current source connecting the second node and a second voltage rail; - a voltage control circuit comprising an input coupled to the second node and configured to control a gate voltage of the first and third transistors based on a reference voltage.

[0005] According to one embodiment, the output branch is duplicated with a fixed ratio N, the second resistor having a resistance N times greater than the first resistor, the third transistor having a width N times less than a width of the first transistor and the fourth transistor having a width N times less than a width of the second transistor.

[0006] According to one embodiment, the fixed ratio N is between 100 and 1000.

[0007] According to one embodiment, the circuit further comprises a fifth transistor connected between the second node and the power source.

[0008] According to one embodiment, the current source comprises a current mirror including a sixth transistor connected between the second node and the second voltage rail and a seventh transistor connected in series with a variable current source between the first and second voltage rails.

[0009] According to one embodiment, the variable current source includes a current value adjustment circuit, the adjustment circuit comprising a plurality of memory elements programmable only once.

[0010] According to one embodiment, the voltage control circuit includes an operational amplifier.

[0011] According to one embodiment, the control circuit is configured to control the gate voltage of the first transistor via a voltage buffer.

[0012] According to one embodiment, the first, second, third and fourth transistors are p-channel MOS type transistors.

[0013] According to one embodiment, the first, second, third and fourth transistors are n-channel MOS type transistors.

[0014] According to another aspect, an electronic circuit is provided comprising a first data transmission circuit as described above and further comprising a second data transmission circuit comprising: - an output branch comprising a first resistor, a first transistor and a second transistor connected in series between the second voltage rail and a first output node, the second transistor being configured to receive a data signal on its gate; - a duplication branch of the output branch with equal dimensions or a fixed ratio N with respect to the output branch, the duplication branch comprising a second resistor, a third transistor and a fourth transistor connected in series between the second voltage rail and a second node, the fourth transistor being configured to receive the data signal on its gate; - a voltage control circuit comprising an input coupled to the second node and configured to control the gate voltage of the first and third transistors based on a reference voltage in which the current source of the first circuit connects the second node of the second circuit and the first tension rail.

[0015] According to another aspect, an electronic device is provided comprising the circuit described above and a data processing circuit configured to generate the data signal.

[0016] According to another aspect, a method for regulating the resistance of a data transmission circuit is provided, comprising: - the duplication of an output branch comprising a first resistor, a first transistor and a second transistor connected in series between a first voltage rail and a first output node, the second transistor being configured to have its gate coupled to a data signal by a duplication branch of the first branch comprising a second resistor, a third transistor and a fourth transistor connected in series between the voltage rail and a second node and sized identically or with a fixed ratio N with respect to the output branch, the fourth transistor being configured to have its gate coupled to the data signal; - the generation of a current by a current source connecting the second node and a second voltage rail; and - the control of a gate voltage of the first and third transistors on the basis of a reference voltage by a voltage control circuit comprising an input coupled to the second node.

[0017] According to one embodiment, the second resistor, the third transistor and the fourth transistor are dimensioned with a fixed ratio N, the second resistor having a resistance N times greater than the first resistor, the third transistor having a width N times less than a width of the first transistor and the fourth transistor having a width N times less than a width of the second transistor.

[0018] According to one embodiment, the fixed ratio N is between 100 and 1000. Brief description of the drawings

[0019] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0020] [Fig.1] represents an example of an electronic data transmission circuit according to an embodiment of the present description;

[0021] [Fig.2] represents another example of an electronic data transmission circuit according to another embodiment of the present description;

[0022] [Fig.3] schematically represents, in block form, an electronic circuit for transmitting complementary data comprising the electronic circuits of figures 1 and 2;

[0023] [Fig.4] represents an example of a circuit of a variable current source of figures 1 to 3;

[0024] [Fig.5] is a graph representing an example of probability density of output resistances of the device of [Fig.3];

[0025] [Fig. 6] represents in block form an example of a communication circuit comprising the circuit of [Fig. 1], 2 or 3; and

[0026] [Fig.7] represents in block form an example of a communication device comprising the circuit of [Fig.1], 2, 3 or 6. Description of the implementation methods

[0027] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0028] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and detailed. In particular, once-programmable memories are known to those skilled in the art and have not been described in detail.

[0029] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements coupled together, this means that these two elements can be connected or linked through one or more other elements, such as one or more resistors or one or more voltage buffers.

[0030] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0031] Unless otherwise specified, the expressions "approximately", "roughly", and "in the order of" mean within 10%, preferably within 5%.

[0032] Fig. 1 represents an example of an electronic data transmission circuit 100 according to an embodiment of the present description.

[0033] The electronic circuit 100 includes an output branch 101 comprising a first resistor 102, a first transistor 104, and a second transistor 106 connected in series between an output node OUT_P and a voltage rail 108 to which a POWERIO voltage is, for example, applied. The equivalent resistance ROUT at the output of the circuit 100 is equal to the sum of the value of the first resistor 102, the equivalent resistance of the first transistor 104, and the equivalent resistance of the second transistor 106. In the example of [Fig. 1], transistors 104 and 106 are p-channel MOS transistors, although other types of transistors could be used.

[0034] In the example of [Fig. 1], the source of transistor 106 is connected to the voltage rail 108 and the drain of transistor 106 is connected to the source of transistor 104. The drain of transistor 104 is connected to a first node of resistor 102 and a second node of resistor 102 is connected to the output node OUT_P. According to some embodiments, the order of elements 102, 104 and 106 could be different from that of the example in [Fig. 1].

[0035] Transistor 106 is configured to receive on its gate a DATAP data signal to be transmitted via the output node OUT_P.

[0036] The circuit 100 also includes a duplication branch 110 of the output branch 101 comprising a second resistor 112, a third transistor 114 and a fourth transistor 116 connected in series between the voltage rail 108 and a node 118.

[0037] Transistors 114 and 116 are, for example, transistors of the same type as transistors 104 and 106.

[0038] In the example of [Fig.1], the source of transistor 116 is connected to the voltage rail 108 and the drain of transistor 116 is connected to the source of transistor 114. The drain of transistor 114 is connected to a first node of resistor 112 and a second node of resistor 112 is connected to node 118. According to some embodiments, the order of elements 112, 114 and 116 could be different from that of the example in [Fig.1].

[0039] Transistor 116 is configured to receive the DATAP data signal on its gate.

[0040] According to one embodiment, branches 101 and 110 have equal dimensions. In this case, resistor 112 has a value equal to the value of resistor 102, transistor 114 has a width equal to the width of transistor 104, and transistor 116 has a width equal to the width of transistor 106, so that the equivalent resistance of these three components in series is identical to ROUT within 5%.

[0041] According to another embodiment, branch 110 has dimensions at a fixed ratio N relative to branch 101. In this case, resistor 112 has a value N times greater than resistor 102, transistor 114 has a width N times smaller than transistor 104, and transistor 116 has a width N times smaller than transistor 106. For example, the fixed ratio N is between 100 and 1000, so that the equivalent resistance of components 112, 114, and 116 in series is within 5% of ROUT multiplied by the fixed ratio N. An advantage of using components with higher equivalent resistances is that a lower current flows through these components for the same voltage values. This facilitates adjustment of the equivalent resistance of the components.

[0042] Components 112, 114 and 116 are positioned so that they undergo temperature variations similar to components 102, 104 and 106 and to reproduce the corresponding ROUT variations.

[0043] Node 118 is connected to a second voltage rail 119, for example a ground rail, via a current source 126. The current source 126 is, for example, implemented by a transistor 126, a current mirror comprising the transistor 126, and a variable current source 120. The transistor 126 forms one branch of the current mirror, the second branch of the current mirror being, for example, implemented by a transistor 122 connected in series with the variable current source 120 between the voltage rails 108 and 119. In the example of [Fig. 1], the drain of transistor 126 is connected to node 118, the source of transistor 126 is connected to the voltage rail 119, and the gate of transistor 126 is connected to the gate and drain of transistor 122. The source of transistor 122 is connected to the voltage rail 119, and the drain of transistor 126 is connected to the gate and drain of transistor 122. 122 is connected to the gates of transistors 122 and 126 and to the variable current source 120.For example, the presence of the current mirror allows for better powering of the variable current source 120 and for a better mirror between the IREF current and the current on the branch of the current mirror formed by the transistor 126. According to one embodiment, the current mirror formed by the transistors 122 and 126 is omitted and the variable current source 120 is directly connected to the node 118.

[0044] The variable current source 120 is configured to generate an IREF current. The value of the IREF current is, for example, adjusted to compensate for variations due to variability in the manufacturing processes involved in the production of the electronic circuit 100.

[0045] In one embodiment, a transistor 128 is connected between the current source 126 and the node 118. The gate of the transistor 128 is connected to the voltage rail 108. The transistor 128 is configured to be cascoded with the current source 126. In current-mirroring embodiments, the transistor 128 is configured to ensure that the voltage difference between the drain and the source of the transistor 126 is similar to the voltage difference between the drain and the source of the transistor 122, which allows the current at the drain output of the transistor 126 to be very similar to IREF. In other embodiments, the transistor 128 is not present in the circuit 100, and the drain of the transistor 126 or the variable current source 120 is directly connected to the node 118.

[0046] In the example of [Fig.1], transistors 122, 126 and 128 are n-channel MOS transistors, although other types of transistors may be used.

[0047] The electronic circuit 100 also includes a voltage control circuit OA1. The circuit OA1 includes an input connected to node 118 and an output connected to the gate of transistor 114 and to the gate of transistor 104. For example, Circuit 0A1 is implemented using an operational amplifier configured so that its positive input is connected to node 118, its negative input is supplied with a voltage VREF, and its output is connected to the gate of transistor 114. The feedback control circuit OA1 is configured to adjust the voltage across the gate of transistor 114 so that the voltage at node 118 is equal to the voltage VREF. Thus, when the current flowing through resistor 112 and transistors 114 and 116 varies, for example, in response to a temperature change, the voltage at node 118 also varies, and this variation is corrected by the feedback control circuit OA1. Since the variations experienced by the duplication branch 110 are similar to the variations experienced by the output branch 101, the same voltage correction applied to the gate of transistor 104 also corrects the current variations flowing through resistor 102 and transistors 104 and 106.

[0048] According to one embodiment, the circuit 100 further comprises, for example, a voltage buffer 132 (“BUF”). In the example of [Fig. 1], the control circuit OA1 is configured to control the gate voltage of the first transistor 104 via a voltage buffer 132. The voltage buffer 132 is, for example, implemented by an even number of inverters connected in series or, as illustrated in [Fig. 1], by an operational amplifier configured as a voltage follower. The operational amplifier 132 is configured to receive the output signal of the control circuit OA1 at its positive input and to have its output connected to its negative input. The output of the voltage buffer 132 is also connected to the gate of transistor 104.

[0049] The voltage buffer 132 is configured to isolate branches 101 and 110 and, for example, prevent variations in current intensity on the gate of transistor 104, for example due to the transmission of the DATAP data signal, from being reflected on the gate of transistor 114.

[0050] The circuit 100 includes, for example, additional components not shown in [Fig.1].

[0051] Although not illustrated in the example in [Fig.1], the circuit 100 includes, for example, other circuits and / or electronic components connected between the OUT_P node and a data transmission terminal.

[0052] Fig. 2 represents another example of an electronic data transmission circuit 200 according to another embodiment of the present description.

[0053] Some elements of [Fig.2] are identical to elements of [Fig.1]. They are represented with the same reference and will not be detailed again.

[0054] Circuit 200 of [Fig.2] corresponds to circuit 100 of [Fig.1] in which: - the voltage rail 108 becomes a voltage rail 208 configured to be a ground rail and the voltage rail 119 becomes a voltage rail 219 configured to be powered by the POWERIO voltage; - the output branch 101 becomes an output branch 201 and the duplication branch 110 becomes a duplication branch 210; - the p-channel MOS transistors 104, 106, 114 and 116 become n-channel MOS transistors 204, 206, 214 and 216 and the n-channel MOS transistors 122, 126 and 128 become p-channel MOS transistors 222, 226 and 228; - the DAT AP data signal to be transmitted via the output node OUT_P by circuit 100 becomes a DAT AN data signal to be transmitted via an output node OUT_N by circuit 200; - The control circuit 130 uses a reference voltage VREF', for example the dual of the voltage VREF used for circuit 100, i.e. the same voltage as the reference voltage VREF but referenced with respect to the POWERIO voltage. For example, VREF'=POWERIO-VREF; - The variable current source 120 is connected to the voltage rail 208 and is connected in series with the transistor 222.

[0055] Fig. 3 schematically represents, in block form, an electronic circuit 300 for transmitting complementary data signals comprising the electronic circuits 100, 200 of figures 1 and 2.

[0056] The variable current sources 120 represented in circuit 100 of [Fig.1] and in circuit 200 of [Fig.2] are for example made by a single circuit 120 (“IREF GENERATION”) of [Fig.3] configured to generate the reference current IREF at an output 306 connected to the two circuits 100, 200.

[0057] The circuit 120 includes, for example, a circuit 308 (“IREF TRIMMING”) configured to adjust the value of the IREF current.

[0058] Circuit 100 (“P-SIDE BUFFER”) is configured to receive the DAT AP data signal at one input and to provide an output signal through the OUT_P node and circuit 200 (“N-SIDE BUFFER”) is configured to receive the DATAN data signal at one input and to provide an output signal through the OUT_N node.

[0059] Fig. 4 represents an example of a circuit of the variable current source 120 of figures 1 to 3.

[0060] The variable current source 120 includes for example a circuit 400 including for example a current generator 402 for example connected to the voltage rail 108 and configured to generate a current 10 ("BIAS CURRENT") at an output 404. The current 10 is for example between InA and 1mA and for example between IpA and 20pA and for example on the order of I OpA.

[0061] The circuit 400 includes, for example, other electronic components, for example a voltage generator 410 configured to generate a bias voltage ("BIAS VOLTAGE").

[0062] The variable current source 120 further comprises, for example, a circuit 420 connected to the circuit 400 and configured to receive the current 10 at an input 422. The circuit 420 comprises, for example, two transistors 424 and 426 configured to form a current mirror. The circuit 420 is, for example, configured to replicate the current 10 at an output 428. According to another embodiment, the circuit 420 is configured to transmit to the output 428 a current with a value proportional to the current 10. The substrate of the transistors 424 and 426 is, for example, connected to the voltage rail 119.

[0063] The variable current source 120 further includes circuit 308. Circuit 308 includes, for example, an input 438 connected to the output 428 of circuit 420 and configured to receive current 10. Circuit 308 includes, for example, 5 transistors, for example, p-channel MOS type, for example, a transistor 440 and transistors 441 to 445. Transistors 441 to 445 are each configured to form a current mirror with transistor 440. Each of the sources of transistors 440 to 445 is connected to the voltage rail 108, and each of the gates of transistors 441 to 445 is connected to the gate and drain of transistor 440, which are connected to input 438. Circuit 308 further includes, for example, 4 transistors 446 to 449 configured to activate or deactivate the branches of the mirror. current including transistors 441 to 444 respectively.Each of the sources of transistors 446 to 449 is connected to the drain of transistors 441 to 444 respectively, and activation signals "NOTEN1,..., NOTEN4" are received on each of the gates of transistors 446 to 449 respectively. The activation signals allow one or more branches of the current mirror composed of transistor 440 and transistors 441 to 445 to be activated independently in order to modify the value of the IREF current flowing at an output 450 of circuit 308 and connected to the output 306 of the variable current source 120.

[0064] According to one embodiment, each of the activation signals received on each of the grids of transistors 446 to 449 is programmed irreversibly during a calibration phase (in English, "trimming"), for example by a memory cell programmable only once (in English, "one time programmable").

[0065] For example, if the NOTEN1 signal at the gate of transistor 446 is at the voltage rail value 108, transistor 446 is cut off and this branch of the current mirror composed of transistors 440 and 441 is deactivated. Conversely, if the NOTEN1 signal is at the voltage rail value 119, transistor 446 is conducting and this branch of the current mirror composed of transistors 440 and 441 is activated. The drains of transistors 446 to 449, as well as the drain of transistor 445, are connected to output 450. where the currents from the 5 branches of the current mirror are added together. The current from each branch of the current mirror depends on the sizing of transistors 441 to 445, and in particular, for example, on the width of their gate, relative to the sizing of transistor 440. The substrate of transistors 440 to 449 is, for example, connected to the voltage rail 108.

[0066] According to one embodiment, transistors 440 to 445 have the same dimensions and the value of IREF can take the values ​​10, 2x10, 3x10, 4x10 and 5x10 depending on the number of branches of the current mirror activated.

[0067] According to another embodiment, transistor 445 has the same dimensions as transistor 440, the gate width of transistor 444 is half the gate width of transistor 440, the gate width of transistor 443 is a quarter of the gate width of transistor 440, and the gate width of transistor 442 is eight times smaller than the gate width of transistor 440. The gate width of transistor 441 is, for example, sized to optionally add an offset to the value of the IREF current. This sizing allows for a greater number of possible values ​​for IREF, for example, equal to two to the power of three, and greater accuracy in the IREF current value, the accuracy being determined by the current mirror branch formed by transistor 442.

[0068] Although a current mirror with 5 branches is illustrated in circuit 308 of [Fig.4], it will be obvious to the person skilled in the art that a current mirror with a different number of branches can be implemented.

[0069] Although, in the example of [Fig.4], transistors 440 to 449 of circuit 308 are p-channel MOS transistors, other types of transistor may be used.

[0070] Circuit 308 allows the value of the reference current IREF used by circuits 100 and 200 to be varied. This circuit is used for example to compensate for possible variations in the parameters and quantities of circuits 100, 120 and 200 due to variations in manufacturing processes.

[0071] Fig. 5 is a graph representing an example of probability density (“P”) of the output resistances (“ROUT”) of the device of Fig. 3 and in particular, the resistance of components 102, 104 and 106 of circuit 100 of Fig. 1 and the resistance of components 102, 204 and 206 of circuit 200 of Fig. 2.

[0072] For example, a standard may impose a range of permissible values ​​for an output resistance of a circuit. For example, for the USB LSFS standard (Universal Serial Bus Low Speed ​​Fast Speed), the output resistance ROUT is defined as being between 28 and 44 Ohms.

[0073] Curve 502 represents the distribution of the output resistances ROUT of device 300 in [Fig. 3]. For example, device 300 has a 20% chance of having an output resistance of 36 Ohms.

[0074] Curve 504 represents an example of output resistance distribution of a circuit, not shown, suboptimal, not including the duplication branch 101, 201, the control circuit OA1 and the current source 120, 122, 126, 222, 226 of Figures 1 and 2.

[0075] The probability that the output resistance of device 300 is equal to 36 Ohms is greater than that of the device in curve 504. Furthermore, the probability that the output resistance of device 300 is less than 33.5 Ohms and greater than 38.5 Ohms is lower than that of the device in curve 504. Device 300 exhibits less variability in the distribution of the output resistance.

[0076] [Fig.6] represents in block form an example of a communication circuit 600 comprising the circuit 100, 200 or 300 of [Fig.1], 2 or 3 respectively.

[0077] The communication circuit 600 includes, for example, a set of input connection terminals 610 configured to receive signals from an electronic circuit not shown in [Fig. 6] and to transmit the signals to a receiving circuit 620 (“RECEIVER”). The receiving circuit 620 includes, for example, inputs connected to the connection terminals 610 and is configured, for example, to receive the signals and transmit them to a transmitter 630 (“TRANSMITTER”). The transmitter 630 is configured to emit a signal to an output terminal 660 (“IOFT”, 5V tolerant input / output, from the English “Input / Output Five Volt Tolerant”) and includes, for example, circuit 100, 200 or 300 of [Fig.1], 2 or 3 respectively to ensure that the resistance at the output of the transmitter 630 and the communication circuit 600 at the terminal 660 is temperature stable and stable with respect to variations in manufacturing processes.The communication circuit 600 also includes a pull-up resistor 640 (RPU) and a pull-down resistor 645 (RPD) connected to an output of the transmitter 630. A test circuit 650 (TM) is, for example, connected to the output of the transmitter 630 to test the communication circuit 600, for example, during its development.

[0078] [Fig.7] represents in block form an example of a communication device 700 comprising the circuit 100, 200, 300 or 600 of [Fig.1], 2, 3 or 6 respectively.

[0079] The device 700 includes for example a set of circuits including a memory (“MEM”), an analog circuit (“ANA”), a digital circuit (“DIG”) and a power supply circuit (“SUPPLY”).

[0080] The device 700 includes, for example, a set of input and output connection terminals 710 configured to transmit and / or receive signals (only a portion of which is referenced to avoid cluttering the figure). One or more connection terminals 710 include, for example, circuit 100, 200, 300 or 600 of [Fig. 1], 2, 3 or 6 respectively.

[0081] Device 700 is, for example, an electronic chip embedded in a laptop, an electronic tablet, a mobile phone, a USB key or a similar device.

[0082] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will be apparent to those skilled in the art. In particular, although the examples have been described using MOS transistors, in other embodiments the use of bipolar transistors may be envisaged.

[0083] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.

Claims

Demands

1. Data transmission circuit (100, 200) comprising: - an output branch (101, 201) comprising a first resistor (102), a first transistor (104, 204) and a second transistor (106, 206) connected in series between a first voltage rail (108, 208) and a first output node (OUT_P, OUT_N), the second transistor (106, 206) being configured to receive on its gate a data signal (DATAP, DATAN); - a duplication branch (110, 210) of the output branch (101, 201) with equal dimensions or a fixed ratio N with respect to the output branch, the duplication branch comprising a second resistor (112), a third transistor (114, 214) and a fourth transistor (116, 216) connected in series between the first voltage rail (108, 208) and a second node (118), the fourth transistor (116, 216) being configured to receive the data signal (DATAP, DATAN) on its gate;- a current source connecting the second node (118) and a second voltage rail (119, 219); - a voltage control circuit (OA1) comprising an input coupled to the second node (118) and configured to control a gate voltage of the first (104, 204) and third (114, 214) transistors on the basis of a reference voltage (VREF, VREF').

2. Circuit according to claim 1, wherein the output branch (101, 201) is duplicated with a fixed ratio N, the second resistor having a resistance N times greater than the first resistor, the third transistor having a width N times less than a width of the first transistor and the fourth transistor having a width N times less than a width of the second transistor.

3. Circuit according to claim 2, wherein the fixed ratio N is between 100 and 1000.

4. Circuit according to any one of claims 1 to 3, further comprising a fifth transistor (128, 228) connected between the second node (118) and the current source (120, 122, 126).

5. Circuit according to any one of claims 1 to 4, wherein the current source comprises a current mirror including a sixth transistor (126, 226) connected between the second node (118) and the second voltage rail (119, 219) and a seventh (122, 222) transistor connected in series with a variable current source (120) between the first (108, 208) and second (119, 219) voltage rails.

6. Circuit according to claim 5, wherein the variable current source (120) includes a current value adjustment circuit, the adjustment circuit comprising a plurality of memory elements programmable only once.

7. Circuit according to any one of claims 1 to 6, wherein the voltage control circuit (OA1) includes an operational amplifier.

8. Circuit according to any one of claims 1 to 7, wherein the servo circuit is configured to servo the gate voltage of the first (104, 204) transistor via a voltage buffer (132).

9. A circuit according to any one of claims 1 to 8, wherein the first (104), second (106), third (114), and fourth (116) transistors are channel MOS transistors

10. P-Circuit according to any one of claims 1 to 8, wherein the first (204), second (206), third (214) and fourth (216) transistors are channel MOS transistors

11. 11.Electronic circuit (300) comprising a first data transmission circuit (100) according to claim 9 and further comprising a second data transmission circuit (200) comprising: - an output branch (201) comprising a first resistor (102), a first transistor (204) and a second transistor (206) connected in series between the second voltage rail (208) and a first output node (OUT_N), the second transistor (206) being configured to receive a data signal (DATAN) on its gate; - a duplication branch (210) of the output branch (201) with equal dimensions or a fixed ratio N with respect to the output branch, the duplication branch comprising a second resistor (112), a third transistor (214) and a fourth transistor (216) connected in series between the second voltage rail (208) and a second node (118), the fourth transistor (216) being configured to receive the data signal (DATAN) on its gate; - a voltage control circuit (OA1) comprising an input coupled to the second node (118) and configured to control a gate voltage of the first (204) and third (214) transistors on the basis of a reference voltage (VREF') in which the current source of the first circuit connects the second node (118) of the second circuit and the first voltage rail (219).

12. Electronic device comprising the circuit according to any one of claims 1 to 11 and a data processing circuit (DIG) configured to generate the data signal (DATAP, DATAN).

13. A method for regulating a resistance in a data transmission circuit (100, 200) comprising: - duplication of an output branch comprising a first resistor (102), a first transistor (104, 204) and a second transistor (106, 206) connected in series between a first voltage rail (108, 208) and a first output node (OUT_P, OUT_N), the second transistor (106, 206) being configured to have its gate coupled to a data signal by a duplication branch of the first branch comprising a second resistor (112), a third transistor (114, 214) and a fourth transistor (116, 216) connected in series between the voltage rail (108, 208) and a second node (118) and sized identically or with a fixed ratio N with respect to the output branch, the fourth transistor (116, 216) being configured to have its grid coupled to the data signal;- the generation of a current (IREF) by a current source connecting the second node (118) and a second voltage rail (119, 219); and - the control of a gate voltage of the first (104, 204) and third (114, 214) transistors on the basis of a reference voltage (VREF, VREF') by a voltage control circuit comprising an input coupled to the second node (118).

14. A method according to claim 13, wherein the second resistor (112), the third transistor (114, 214), and the fourth transistor (116, 216) are sized with a fixed ratio N, the second resistor having a resistance N times greater than the first resistor (102), the third transistor having a width N times less than the width of the first transistor (104, 204), and the

15. fourth transistor having a width N times less than a width of the second transistor (106, 206). A method according to claim 14, wherein the fixed ratio N is between 100 and 1000.

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