Electronic chip with a connection pillar

Abstract

Electronic chip comprising a connecting pillar. This description relates to an electronic chip (11) comprising: - a passivation layer (21) having a through-hole opposite a connecting metallization (19) of the circuit; - a connecting pillar (15) on an upper face of the circuit metallization, the pillar comprising a lower part (151) and an upper part (153) of the same material, the upper part having a rounded upper face, the pillar being mushroom-shaped, the stem of which corresponds to the lower part of the pillar and the cap to the upper part of the pillar, wherein the upper part of the pillar is covered by an electrically conductive layer (22), itself covered by a layer (23) of a solder material, wherein the lower part of the pillar has a portion of its lateral sides freely accessible. Figure for the abbreviation: Fig. 1

Description

Title of the invention: Electronic chip comprising a connection pillar. Technical field

[0001] The present description relates generally to electronic chips. Previous technique

[0002] We are interested here in an electronic chip intended to be connected and soldered to an external device, more precisely to connection pads of the external device, via connection pillars formed on the front face of the chip. Such a connection is made possible by a solder material deposited at the interface between the connection pillars of the electronic chip and the connection pads of the external device.

[0003] It would be desirable to improve at least some aspects of such electronic chips. Summary of the invention

[0004] To this end, one embodiment provides an electronic chip comprising, on an integrated circuit formed in and on a semiconductor substrate: - a passivation layer covering an upper face of the integrated circuit, the passivation layer having a through-hole opposite a connection metallization of the integrated circuit; - a connecting pillar, on and in contact with an upper face of the connecting metallization of the integrated circuit, the connecting pillar comprising a lower part and an upper part, the lower and upper parts of the connecting pillar being made of the same material and the upper part having a flat lower face and a rounded upper face, in which the lower face of the upper part of the connecting pillar has a surface area greater than the surface area of ​​an upper face of the lower part of the connecting pillar, such that the connecting pillar has the shape of a mushroom whose stem corresponds to the lower part of the connecting pillar and whose cap corresponds to the upper part of the connecting pillar, in which the upper face of the upper part of the connecting pillar is covered by, and in contact with, an electrically conductive layer, itself covered by, and in contact with, a layer of brazing material, and in which the lower part of the connecting pillar has a portion of its lateral sides freely accessible and the upper part of the connecting pillar has a portion of its lower face freely accessible.

[0005] According to one embodiment, the connecting pillar is made of copper.

[0006] According to one embodiment, the conductive layer is nickel-based.

[0007] According to one embodiment, the brazing material is tin and silver based.

[0008] According to one embodiment, the lateral sides of the lower part of the pillar of Connections are freely accessible between 8 pm and 8 pm.

[0009] According to one embodiment, the portion of the lower face of the upper part of the connecting pillar not covered by the lower part of the connecting pillar and freely accessible has a width between 5 pm and 20 pm.

[0010] According to one embodiment, the width of the freely accessible portion of the lower face due to the upper part of the connecting pillar not covered by the lower part of the connecting pillar is equal to the height of the upper part of the connecting pillar.

[0011] Another embodiment provides a method for manufacturing an electronic chip comprising the successive formation steps, on an integrated circuit formed in and on a semiconductor substrate, : - a passivation layer covering an upper face of the integrated circuit, the passivation layer having a through-hole opposite a connection metallization of the integrated circuit; - of a connecting pillar, on and in contact with an upper face of the connection metallization of the integrated circuit, the connecting pillar comprising a lower part and an upper part, the lower and upper parts of the connecting pillar being made of the same material and the upper part having a flat lower face and a rounded upper face, in which the lower face of the upper part of the connecting pillar has a surface area greater than the surface area of ​​an upper face of the lower part of the connecting pillar, such that the connecting pillar has the shape of a mushroom whose stem corresponds to the lower part of the connecting pillar and whose cap corresponds to the upper part of the connecting pillar, in which the upper face of the upper part of the connecting pillar is covered with, and in contact with, an electrically conductive layer, itself covered with, and in contact with, a layer of a brazing material, and in which, the lower part of the connecting pillar has a portion of its lateral sides freely accessible and the upper part of the connecting pillar has a portion of its lower face freely accessible.

[0012] According to one embodiment, the step of forming the connection pillar comprises: - a step of depositing a seed layer directly above the connection metallization of the integrated circuit; - a step of forming a layer in a photosensitive resin and photolithography in order to form a trench opposite the metallization of the connection of the integrated circuit; - an electrolysis step enabling the growth of the connecting pillar and the formation of the lower part of the connecting pillar in the trench formed in the layer of photosensitive resin and the upper part of the connecting pillar outside said opening on the upper face of the layer of photosensitive resin.

[0013] According to one embodiment, the process comprises, after the electrolysis step, a step of removing the layer in the photosensitive resin so as to make a portion of the lateral sides of the lower part of the connecting pillar and a portion of the lower face of the upper part of the connecting pillar freely accessible.

[0014] According to one embodiment, the method includes a step of transferring the connection post onto a connection pad of an external device, the connection pad being covered with another layer of the solder material, the transfer step consisting of heating the two layers of the solder material, and compressing the electronic chip onto the external device so that the solder material wets a part of the lower face of the upper part of the connection post of the electronic chip. Brief description of the drawings

[0015] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0016] [Fig.1] is a partial and schematic cross-sectional view, illustrating an example of an electronic chip comprising a connection pillar according to one embodiment;

[0017] Fig. 2A, Fig. 2B, Fig. 2C, Fig. 2D, Fig. 2E, Fig. 2F, Fig. 2G, Fig. 2H and Fig. 2I are partial, schematic cross-sectional views illustrating steps in an example of a manufacturing process for the electronic chip shown in Fig. 1 according to one embodiment; and

[0018] [Fig.3A] and [Fig.3B] are partial and schematic cross-sectional views, illustrating steps of an example of a soldering process of the electronic chip illustrated in [Fig.1] on an external device according to one embodiment. Description of the implementation methods

[0019] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0020] For the sake of clarity, only the steps and elements necessary for understanding the described embodiments have been shown and are detailed. In particular, only the portion of the electronic chip corresponding to the connection pillars and their connections to the electronic chip has been detailed. The implementation of the other elements of the chip, and in particular the integrated circuits and electronic components present on the chip, has not been detailed.

[0021] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") together, this means that these two elements can be connected or linked through one or more other elements.

[0022] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0023] Unless otherwise specified, the expressions "approximately", "roughly", and "on the order of" mean to within 10% or 10°, preferably to within 5% or 5°.

[0024] Fig. 1 is a partial, schematic cross-sectional view illustrating an example of an electronic chip 11 comprising a connection pillar according to one embodiment.

[0025] The electronic chip 11 comprises an integrated circuit 13, on which a connecting pillar 15 has been formed. The integrated circuit 13 is formed on and within a semiconductor substrate, for example, silicon. By way of example, the circuit 13 comprises an interconnect stack, a surface-mounted connecting metallization 19 of which is flush with the top face of the circuit 13. The metallization 19 has, in top view, for example, a round shape. Alternatively, the metallization 19 may have, in top view, a square or rectangular shape. By way of example, the metallizations 19 are made of a metallic material, for example, aluminum.

[0026] The connection pillar 15 is, in [Fig.1] formed on the upper face of the circuit 13. In [Fig.1], a single pillar 15 has been shown, however, in practice, the electronic chip 11 may have a plurality of connection pillars 15. As an example, the connection pillars 15 are arranged, on the upper face of the circuit 13 according to a matrix of rows and columns.

[0027] The pillar 15 is formed directly above the connection metallization 19 of the integrated circuit 13 and is in contact with the metallization 19 via a set of conductive layers 17. The set of conductive layers 17 comprises, for example, several layers that ensure good ohmicity of the contact between the pillar 15 and the metallization 19 of the circuit 13. The set of conductive layers 17 also serves as a barrier to metal diffusion in the circuit 13, and ensures good adhesion of the pillar 15 to the metallization 19. The set of conductive layers 17 has, for example, a round shape when viewed from above. Alternatively, this set 17 may have a square or rectangular shape when viewed from above.

[0028] By way of example, the assembly 17 comprises a stack of two conductive layers. By way of example, the assembly 17 comprises a first conductive layer 171 on and in contact with the metallization 19. By way of example, the assembly 17 comprises a second conductive layer 173 on and in contact with the first conductive layer 171. By way of example, the second conductive layer 173 extends over all or part of the surface of the first conductive layer 171. The first layer 171 is, for example, made of a metallic material, for example, the same material as the metallizations 19. The first layer 171 is, for example, made of aluminum. By way of example, the second layer is made of a metallic material, for example, titanium. For example, layer 171 has a thickness between 0.5 pm and 5 pm, for example, on the order of 1.5 pm. For example, layer 173 has a thickness between 0.01 pm and 0.2 pm, for example, on the order of 0.02 pm.

[0029] The electronic chip 11 further comprises a passivation layer 21 covering the upper face of the integrated circuit 13, the passivation layer having a through-hole opposite the metallization 19 and opposite layers 171 and 173 such that the passivation layer 21 surrounds layers 171 and 173 without covering them. For example, the passivation layer 21 covers the sides of layers 171 and 173. For example, if layer 173 extends over only a portion of the surface of the underlying layer 171, the passivation layer 21 then covers the portion of layer 171 not covered by layer 173.

[0030] By way of example, the passivation layer 21 has a thickness between 1 pm and 6 pm, for example on the order of 3 pm.

[0031] The pillar 15 extends vertically above the opening formed in the passivation layer 21 and the metallization 19. The pillar 15 has its lower face in contact with the set of conductive layers 17 and more particularly with layer 173. By way of example, the pillar 15 covers, by its lower face, the entire upper face of layer 173 and only part of the passivation layer 21, around layers 171 and 173.

[0032] The pillar 15 has two parts, a lower part 151 and an upper part 153. By way of example, the two parts of the pillar 15 are round in top view.

[0033] The pillar 15 and more particularly the lower 151 and upper 153 parts of the pillar 15 are made of one and the same material.

[0034] By way of example, the pillar 15 extends over a height H1, from the lower face of the lower part 151 of the pillar 15 to the upper end of the upper face of the upper part 153 of the pillar 15. The height H1 is for example between 20 pm and 100 pm, for example between 30 pm and 80 pm, for example around 50 pm.

[0035] The lower part 151 of the pillar 15 is in contact, by its lower face, with the layer 173 and extends vertically above the layer 173. The lower part 151 of the pillar 15 includes, for example, a narrower region extending into the opening formed in the passivation layer 21, between the upper face of the layer 173 and the upper face of the passivation layer 21. The lower part 151 of the pillar 15 has, above the aforementioned region, a portion of its lateral sides exposed or freely accessible, i.e., they are not covered, for example, not covered by an insulating layer and more particularly by the passivation layer 21. By way of example, the portion of the freely accessible lateral sides are straight and extend, for example, orthogonally to the lower face of the pillar 15.For example, the portion of the freely accessible lateral sides of the lower part 151 of pillar 15 extends over a height H2, for example, between 20 pm and 80 pm, for example, on the order of 30 pm.

[0036] By way of example, the lower part 151 of the pillar 15 extends over a width Ll, for example corresponding to the diameter of the lower part 151 of the pillar 15 taken in the plane of its upper face. By way of example, the width Ll is between 50 pm and 150 pm, and is for example on the order of 100 pm.

[0037] The upper part 153 of the pillar 15 is in contact, by its lower face, with the upper face of the lower part 151 of the pillar 15. The upper part 153 of the pillar 15 has a flat lower face. The upper part 153 of the pillar 15 has a rounded upper face, for example, in the shape of an arc of a circle. By way of example, the lower and upper faces of the upper part 153 of the pillar 15 meet at their peripheries.

[0038] By way of example, the upper part 153 of the pillar 15 extends over a height H3, from the upper face of the lower part 151 of the pillar 15 to the upper end of the upper face of the upper part 153 of the pillar 15. The height H3 is for example between 5 pm and 20 pm, for example on the order of 10 pm.

[0039] By way of example, the upper part 153 of the pillar 15 is centered on the lower part 151 of the pillar 15. That is to say, the center of the upper part 153 of the pillar 15 and the center of the lower part 151 of the pillar 15 are aligned. By way of example, the upper part 153 of the pillar 15 extends over a surface, taken at its lower face, which is greater than the surface of the lower part 151 of the pillar 15, taken at its upper face. In other words, the lower face of the part The upper part 153 of pillar 15 extends over the entire surface of the upper face of the lower part 151 of pillar 15 and beyond. Pillar 15 thus has the shape of a mushroom whose stem corresponds to the lower part 151 and whose cap corresponds to the upper part 153.

[0040] By way of example, the upper part 153 of the pillar 15, more precisely the lower face of the upper part 153 of the pillar 15, extends, for example, around its entire circumference, beyond the lower part 151 of the pillar 15 by a width L2. The portion of the lower face of the upper part 153 not covered by the lower part 151 is then exposed, that is to say, freely accessible and not covered by a layer of another material, in particular an insulating layer. By way of example, the upper part 153 of the pillar 15 has a width, for example, corresponding to the diameter of the lower face of the upper part 153 of the pillar 15, equal to L1 + 2 x L2.

[0041] By way of example, the ratio between the value L2 and half the width L1 is between 10% and 30%, for example between 10% and 20%.

[0042] For example, the width L2 is equal to the height H3. For example, the width L2 is between 5 pm and 20 pm, for example on the order of 10 pm.

[0043] The pillar 15, more particularly the upper part 153 of the pillar 15, is covered by a conductive layer 22. The upper part 153 of the pillar 15 is in contact, by its upper face, with the lower face of the conductive layer 22. The layer 22 covers, for example, the entire surface of the upper face of the upper part 153 of the pillar 15. The layer 22 has, for example, a constant thickness, for example less than 5 pm, for example less than 3 pm, for example on the order of 3 pm.

[0044] By way of example, layer 22 is made of a metallic material, for example nickel.

[0045] The conductive layer 22 is covered by a layer of a solder material 23. Layer 23 is in contact, by its upper face, with the lower face of layer 22. Layer 23 has, for example, a constant thickness, for example between 2 pm and 20 pm, for example between 5 pm and 17 pm, for example on the order of 15 pm.

[0046] By way of example, layer 23 is, for example, made of a tin-based material, for example tin and silver (SnAg).

[0047] By way of example, layers 22 and 23 do not extend over the lower face of the upper part 153 of the pillar 15.

[0048] Fig. 2A, Fig. 2B, Fig. 2C, Fig. 2D, Fig. 2E, Fig. 2F, Fig. 2G, Fig. 2H and Fig. 21 are partial and schematic cross-sectional views illustrating steps of an example of a manufacturing process for the electronic chip 11 shown in Fig. 1 according to one embodiment.

[0049] Fig. 2A illustrates a starting structure comprising the passivation layer 21 and the layer 171 formed on the integrated circuit 13.

[0050] Fig. 2B illustrates a structure obtained after a step of depositing layer 173 on the upper face of the structure illustrated in Fig. 2A.

[0051] During this step, the conductive layer 173 is deposited full plate on the entire upper face of the structure illustrated in [Fig.2A] and more specifically, on the upper face of the passivation layer 21 and on the upper face of the conductive layer 171. At the end of this step, the conductive layer 173 is thus in contact, by its lower face, with the upper face of the passivation layer and with the upper face of the conductive layer 171.

[0052] Fig. 2C illustrates a structure obtained after a step of depositing a seed layer 25 on the upper face of the structure illustrated in Fig. 2B.

[0053] During this step, the seed layer 25 is deposited in full plate on the entire upper face of the structure illustrated in [Fig.2B] and more precisely on the upper face of the conductive layer 173. At the end of this step, the seed layer 25 is in contact, by its lower face, with the upper face of the conductive layer 173.

[0054] The germ layer 25 is for example made of a metallic material, for example copper.

[0055] Fig. 2D illustrates a structure obtained after a step of depositing a layer of resin 27 on the upper face of the structure illustrated in Fig. 2C.

[0056] During this step, the resin layer 27 is deposited in full plate over the entire upper face of the structure illustrated in [Fig. 2C]. The resin layer 27 is, for example, a photosensitive resin, for example a positive resin.

[0057] Fig. 2E illustrates a structure obtained after a photolithography step of layer 27 of the structure illustrated in Fig. 2D.

[0058] During this step, a portion of the resin layer 27, directly above the metallization 19, is exposed. For example, this portion of the layer 27 is exposed to ultraviolet (UV) radiation.

[0059] At the end of the exposure step, the layer 27 undergoes a rinsing step during which the part that has been exposed, soluble in the rinsing solution, is removed.

[0060] At the end of this step, the structure thus includes an opening in the resin layer 27, directly above the metallization 19. The aforementioned opening is through, that is to say, it opens onto the upper face of the layer 25.

[0061] Fig. 2F illustrates a structure obtained at the end of a pillar 15 formation step.

[0062] During this step, the pillar 15 is formed in a single step by electrolysis. During this step, the pillar 15 grows from the seed layer 25. In a In the first stage, the pillar 15 grows within the opening formed in the resin layer 27, thus forming the lower part 151 of the pillar. Electrolysis continues while the upper surface of the pillar 15 extends beyond the upper surface of the resin layer 27. In the second stage, the pillar 15 then grows outside the opening formed in the layer 27. In this second stage, the growth of the pillar 15 is no longer guided, and the pillar 15 thus grows both vertically and horizontally. During this stage, the pillar 15 therefore grows on the upper surface of the resin layer 27, outside the opening formed directly above the metallization 19.

[0063] By way of example, electrolysis is stopped when the pillar 15 has extended horizontally, on the upper face of the layer 27, over the width L2 and the height H3.

[0064] Fig. 2G illustrates a structure obtained at the end of a step of formation of layers 22 and 23 on the upper face of pillar 15 of the structure illustrated in Fig. 2F.

[0065] Initially, during this step, layer 22 is formed on, and in contact with, the upper face of pillar 15. Layer 22 is formed, for example, by electrolysis. Layer 22 is formed, for example, only in contact with pillar 15; it is not formed, for example, on the upper face of layer 27.

[0066] In a second step, during this stage, layer 23 is formed on, and in contact with, the upper surface of layer 22. Layer 23 is formed, for example, by electrolysis. Layer 23 is formed, for example, only in contact with layer 22; it is not, for example, formed on the upper surface of layer 27.

[0067] Fig. 2H illustrates a structure obtained after a step of removing the resin layer 27 from the structure illustrated in Fig. 2G.

[0068] During this step, layer 27 is removed, thus leaving part of the lateral sides of pillar 15 accessible and uncovered. During this step, layer 27 is removed, revealing the upper surface of the seed layer 25.

[0069] Fig. 21 illustrates a structure obtained after an engraving step of the structure illustrated in Fig. 2H.

[0070] During this step, the structure is engraved so as to remove the seed layer 25 and the conductive layer 173 around the pillar 15. As an example, during this step, the layer 23 is deformed by thinning on the periphery of the upper face of the upper part 153 of the pillar 15.

[0071] At the end of this step, the upper surface of the passivation layer is exposed around the pillar 15. The conductive layer 173 is, at the end of this step, preserved only between the pillar 15 and the conductive layer 171.

[0072] Fig. 3A and Fig. 3B are partial, schematic cross-sectional views illustrating steps of an example of a soldering process for the electronic chip 11 shown in Fig. 1 on an external device 29 according to one embodiment.

[0073] Fig. 3A illustrates a step consisting of aligning the chip 11 shown in Fig. 1 with the external device 29.

[0074] In [Fig. 3A], the electronic chip 11 is shown in the upper part of the figure and the external device 29 is shown in the lower part of the figure. The electronic chip 11 is shown in [Fig. 3A] inverted with respect to its orientation in [Fig. 1].

[0075] The external device 29 is, for example, a printed circuit board, another chip or an electronic element different from the chip 11.

[0076] The external device 29 includes a connection pad 31. The connection pad 31 is, for example, made of a conductive material, for example, a metallic material, for example, copper. The connection pad 31 has, for example, a round shape when viewed from above. Alternatively, the connection pad 31 has a square or rectangular shape.

[0077] The external device 29 further comprises, around and above the connecting pad 31, a layer of a solder material 33. By way of example, the layer 33 extends over the upper face and the lateral sides of the connecting pad 31. By way of example, the layer 33 does not extend over the upper face of the device 29 beyond the vicinity of the connecting pad 31. By way of example, the solder material of the layer 33 is the same material as that of the layer 23. By way of example, the layer 33 is made of a tin-based material, for example, a tin-silver (SnAg) material. By way of example, the layer 33 of the solder material has a thickness of between 2 µm and 50 µm, for example, between 5 µm and 50 µm.

[0078] During the alignment step, the electronic chip 11 is aligned with the external device 29 so that the pillar 15 is aligned with the connection pad 31, the layer 23 of the chip 11 facing the layer 33 of the external device 29.

[0079] Fig. 3B illustrates a structure obtained after a thermocompression step of the chip on the external device 29.

[0080] During this step, the chip 11 is compressed onto the external device 29, so as to bring the layers 33 and 23 into contact. During this step, in addition to compression, the layers 23 and 33 are heated so that the solder material of the layers 23 and 33 becomes liquid. For example, the layers 23 and 33 are heated to a temperature equal to or higher than the melting temperature of the layers 23 and 33. For example, the layers 23 and 33 are heated to a temperature between 140 °C and 240 °C.

[0081] During this step, layer 33 wets, that is, it comes into contact with, layer 23. Furthermore, during this step, layer 33 extends up the edges of part 153 of the pillar 15, covering and encircling part 153 of the pillar 15. For example, during this step, layer 33 covers part of the face upper, in the orientation of [Fig.3B], of part 153, not covered by part 151 of pillar 15. This is referred to as the rivet effect.

[0082] An advantage of the present embodiment is that it allows increasing the wettability between the pillar 15 of the chip 11 and the connection pad 31 of the external device 29.

[0083] Another advantage of the present embodiment is that it allows better mechanical holding of the chip 11 on the external device 29 by the rivet effect of the layer 33 in the brazing material of the external device 29 on the part 153 of the pillar 15.

[0084] Many applications are likely to benefit from the advantages provided by the electronic chip 11, the electronic chip 11 thus being able to be integrated into various types of devices.

[0085] By way of example, the chip 11 can be integrated into a device intended for the automotive industry. The electrification of motor vehicles is causing a sharp increase in the number of electronic components present in vehicles. The device includes, for example, transient voltage suppression diodes, modules, etc., intended to be incorporated into said vehicles. Furthermore, driver assistance and automated driving are leading to an increase in the number of electronic components in vehicles. The device includes, for example, transient voltage suppression diodes, electrostatic discharge protection, and common-mode filters to protect the device against electrical hazards.

[0086] By way of example, the chip 11 can be integrated into a device intended for industrial use. In particular, the device is used, for example, for the development of green energy or for the electrification of infrastructure, for example, for charging stations or for solar energy harvesting. The device can also be used in the field of the Internet of Things or in the field of smart homes. The device can also be used for the implementation of cloud computing systems, 5G radio frequency communication networks, data centers, and servers. The device includes, for example, wide bandgap materials.

[0087] By way of example, the chip 11 can be integrated into a device intended for use in personal electronics, for example, to increase the volume of information exchanged via radio frequency communication, in 5G communication systems, or more generally in any connected device. The device is, for example, a mobile phone, or smartphone, or is part of an Internet of Things network. The device is, for example, connected via 5G, Wi-Fi, or broadband communication. The device includes, for example, interfaces to high speed, for example with advanced filtering and protection against electrostatic discharge.

[0088] By way of example, the chip 11 can be integrated into a device intended for use in communication equipment, or in computers and peripherals. The device is used, for example, in 5G infrastructures and dedicated data centers. The device includes, for example, diodes for suppressing transient voltages. The device can also be used in satellites, including, for example, integrated passive devices for radio frequency applications.

[0089] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.

[0090] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.

Claims

Demands

1. Electronic chip (11) comprising, on an integrated circuit (13) formed in and on a semiconductor substrate: - a passivation layer (21) covering an upper face of the integrated circuit (13), the passivation layer (21) having a through-hole opposite a connection metallization (19) of the integrated circuit (13); - a connection pillar (15), on and in contact with an upper face of the connection metallization (19) of the integrated circuit (13), the connection pillar (15) comprising a lower part (151) and an upper part (153), the lower part (151) and the upper part (153) of the connection pillar (15) being made of the same material and the upper part (153) having a flat lower face and a rounded upper face,in which the lower face of the upper part (153) of the connecting pillar (15) has a surface area greater than the surface area of ​​an upper face of the lower part (151) of the connecting pillar (15) such that the connecting pillar (15) has the shape of a mushroom whose stem corresponds to the lower part (151) of the connecting pillar (15) and whose cap corresponds to the upper part (153) of the connecting pillar (15), in which the upper face of the upper part (153) of the connecting pillar (15) is covered by, and in contact with, an electrically conductive layer (22), itself covered by, and in contact with, a layer (23) of a brazing material, and in which the lower part of the connecting pillar (15) has a portion of its lateral sides freely accessible and the upper part (153) of the connecting pillar (15) has a portion of its lower face freely accessible.

2. Electronic chip according to claim 1, wherein the connecting pillar (15) is made of copper.

3. Electronic chip according to claim 1 or 2, wherein the conductive layer (22) is nickel-based.

4. Electronic chip according to any one of claims 1 to 3, wherein the solder material is tin and silver based.

5. Electronic chip according to any one of claims 1 to 4, wherein the lateral sides of the lower part (151) of the pillar connection points (15) are freely accessible over a height (H2) between 20 pm and 80 pm.

6. Electronic chip according to any one of claims 1 to 5, wherein the portion of the lower face of the upper part (153) of the connecting pillar (15) not covered by the lower part (151) of the connecting pillar (15) and freely accessible has a width (L2) between 5 pm and 20 pm.

7. Electronic chip according to any one of claims 1 to 6, wherein the width (L2) of the free-access portion of the lower face of the upper part (153) of the connecting pillar (15) not covered by the lower part (151) of the connecting pillar (15) is equal to the height (H3) of the upper part (153) of the connecting pillar (15).

8. A method for manufacturing an electronic chip (11) comprising the successive steps of forming, on an integrated circuit (13) formed in and on a semiconductor substrate: - a passivation layer (21) covering an upper face of the integrated circuit (13), the passivation layer (21) having a through-hole opposite a connection metallization (19) of the integrated circuit (13); - a connection pillar (15), on and in contact with an upper face of the connection metallization (19) of the integrated circuit (13), the connection pillar (15) having a lower part (151) and an upper part (153), the lower part (151) and the upper part (153) of the connection pillar (15) being made of the same material and the upper part (153) having a flat lower face and a rounded upper face,in which the lower face of the upper part (153) of the connecting pillar (15) has a surface area greater than the surface area of ​​an upper face of the lower part (151) of the connecting pillar (15) such that the connecting pillar (15) has the shape of a mushroom whose stem corresponds to the lower part (151) of the connecting pillar (15) and whose cap corresponds to the upper part (153) of the connecting pillar (15), in which the upper face of the upper part (153) of the connecting pillar (15) is covered with, and in contact with, an electrically conductive layer (22), itself covered with, and in contact with, a layer (23) of a brazing material, and, in which the lower part (151) of the connecting pillar (15) has a portion of its lateral sides freely accessible and the upper part (153) of the connecting pillar (15) has a portion of its lower face freely accessible.

9. A manufacturing method according to claim 8, wherein the step of forming the connecting pillar (15) comprises: - a step of depositing a seed layer (25) in line with the connecting metallization (19) of the integrated circuit (13); - a step of forming a layer in a photosensitive resin (27) and photolithography so as to form a trench opposite the connecting metallization (19) of the integrated circuit (13); - an electrolysis step enabling the connecting pillar (15) to grow and form the lower part (151) of the connecting pillar (15) in the trench formed in the layer in the photosensitive resin (27) and the upper part (153) of the connecting pillar (15) outside said opening on the upper face of the layer in the photosensitive resin (27).

10. A manufacturing method according to claim 9, comprising, after the electrolysis step, a step of removing the layer in the photosensitive resin (27) so as to make freely accessible a portion of the lateral sides of the lower part (151) of the connecting pillar (15) and a portion of the lower face of the upper part (153) of the connecting pillar (15).

11. A method of using an electronic chip (11) according to any one of claims 1 to 7, comprising a step of transferring the connecting post (15) onto a connecting pad (31) of an external device (29), the connecting pad (31) being covered with another layer (33) of the solder material, the transfer step consisting of heating the two layers (23, 33) of the solder material, and compressing the electronic chip (11) onto the external device (29) so that the solder material wets a part of the lower face of the upper part (153) of the connecting post (15) of the electronic chip (11).

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