Analog computing circuit with compression

Abstract

Analog Calculation Circuit with Compression This description concerns an analog vector multiplier circuit comprising a first circuit including: - a first branch comprising the series connection of a first programmable resistive element and a first transistor; - a second branch comprising the series connection of a second programmable resistive element and a second transistor; - a control circuit configured to control the first and second transistors to select the first or second branch; and - a first current mirror configured to apply a generated current to the branch selected by the control circuit in order to generate a first voltage. Figure for the abstract: Fig. 3

Description

Title of the invention: Analog computing circuit with compression technical field

[0001] This description relates generally to analog computing circuits configured to perform multiplication and accumulation operations. Prior art

[0002] Neural networks are a powerful tool for certain classification and regression tasks such as image classification. A trained classification model can generate, for given input data, a set of prediction scores for each class from among a set of classes recognizable by the model and a predicted class, selected as the class with the highest prediction score.

[0003] However, one problem that can arise is that a trained classification model may be overly presumptuous and generate a very high probability of predicting an incorrect class. For example, this can occur when the model is oversized, when the input data are out of distribution, meaning that the data type was not encountered during training, or in the case of ambiguous data points.

[0004] One proposed solution to this problem is to train multiple models, such as dozens or even hundreds of models for the same dataset. This technique is often called ensemble learning and is described, for example, in more detail in the publication by Stanislav Fort, Huiyi Hu, and Balaji Lakshminarayanan entitled “Deep Ensembles: A Loss Landscape Perspective”, June 24, 2020, available at http: / / arxiv.org / abs / 1912.02757. Such methods have been found to work well in practice, both in terms of classification accuracy and uncertainty calibration.

[0005] However, a difficulty with existing implementations of neural networks capable of applying a set of multiple models lies in the fact that memory requirements, energy consumption, and processing time are also multiplied by the number of models that are implemented. For example, implementing a neural network applying a set of 100 models requires up to 100 times more memory and energy than a neural network implementing a single model.

[0006] There is therefore a need for a neural network architecture which at least partially overcomes this difficulty of the previous technique. Summary of the invention

[0007] One embodiment provides an analog vector multiplier circuit comprising a first circuit for implementing a first multiplication of a first or second value with a third value, the first circuit comprising: - a first branch comprising the series connection of a first programmable resistive element and a first transistor, the first programmable resistive element being programmed to have a first resistance representative of the first value; - a second branch comprising the series connection of a second programmable resistive element and a second transistor, the second programmable resistive element being programmed to have a second resistance representative of the second value; - a control circuit configured to control the first and second transistors to select the first or second branch; and - a first current mirror configured to apply a current generated on the basis of the third value to the branch selected by the control circuit in order to generate, across the terminals of the selected branch, a first voltage proportional to the result of the first multiplication.

[0008] According to one embodiment, the analog vector multiplier further comprises a second circuit for implementing, in parallel with the first multiplication, a second multiplication of a fourth or fifth value with a sixth value, the second circuit comprising: - a third branch comprising the series connection of a third programmable resistive element and a third transistor, the third programmable resistive element being programmed to have a third resistance representative of the fourth value; - a fourth branch comprising the series connection of a fourth programmable resistive element and a fourth transistor, the fourth programmable resistive element being programmed to have a fourth resistance representative of the fifth value, in which the control circuit is configured to command the third and fourth transistors to select the third or fourth branch; - a second current mirror configured to apply a current generated on the basis of the sixth value to the branch of the second circuit selected by the control circuit in order to generate, across the terminals of the selected branch, a second voltage proportional to the result of the second multiplication.

[0009] One embodiment provides for the preceding neural network comprising the analog vector multiplier circuit.

[0010] According to one embodiment, the preceding neural network further comprises a first cross-branch network circuit configured to provide as output one or more second current values ​​by implementing one or more multiplication and / or accumulation operations on the basis of at least the first voltage.

[0011] According to one embodiment, the preceding neural network further includes an additional vector multiplier analog circuit configured to generate one or more output voltages by implementing one or more multiplication operations on the basis of one or more second current values.

[0012] According to one embodiment, the preceding neural network further comprises: - a first voltage replication circuit configured to replicate the first voltage generated by the first circuit and provide the replicated voltage to the cross-branch circuit, the first voltage replication circuit comprising an operational amplifier.

[0013] According to one embodiment, the third and sixth values ​​are components of an input vector of size n, n being an integer, the circuit being further configured to perform a number K of sequences of operations and multiplication, K being an integer representing a number of models implemented by the neural network.

[0014] According to one embodiment: - the analog vector multiplier circuit comprises a number K xn of resistive elements programmed to the coefficient values ​​of K horizontal vectors of size n; - the cross-branch circuit comprises nxn resistive elements programmed to inverse values ​​of coefficients of a shared matrix (S) of size nx n.

[0015] According to one embodiment, the additional vector multiplier analog circuit comprises a number Kxn of resistive elements programmed with coefficient values ​​of K vertical vectors of size n.

[0016] According to one embodiment: - the analog vector multiplier circuit comprises a number xn of resistive elements programmed with inverse values ​​of coefficients of a shared matrix of size nxn; - the cross-branch circuit comprises a number Kxn of resistive elements programmed with coefficient values ​​of K horizontal vectors of size n; and - the additional vector multiplier analog circuit comprises a number Kxn of resistive elements programmed with inverse coefficient values ​​of K vertical vectors of size n.

[0017] According to one embodiment, the preceding neural network is configured to generate, for each model k among the K models implemented by the neural network, n output voltages corresponding to n output values ​​y^, l

[0018] y^ = vf x (hk x Xj x [ + „ + h„ x xnx sin ) '

[0019] where 1 jn, is the value of the j-th coefficient of the k-th horizontal vector / ^, 1 < j < n, S'J is the value of the i-th row and j-th column of the shared matrix and XJ, 1 j is the j-th component of the input vector. ​

[0020] According to one embodiment, the preceding neural network is configured to perform classification operations.

[0021] An embodiment provides a method for implementing, by a first circuit of an analog vector multiplier circuit, a first multiplication of a first or second value by a third value, the method comprising: - programming a first programmable resistive element so that it has a first resistance representative of the first value, the first programmable resistive element being connected in series with a first transistor in a first branch of the first circuit; - the programming of a second programmable resistive element so that it has a second resistance representative of the second value, the second programmable resistive element being connected in series with a second transistor in a second branch of the first circuit; - the control, by a control circuit, of the first and second transistors to select the first or second branch; and - the application, by a first current mirror, of a current generated on the basis of the third value to the branch selected by the control circuit in order to generate, at the terminals of the selected branch, a first voltage proportional to the result of the first multiplication.

[0022] According to one embodiment, the preceding process further includes the conversion, by an analog-to-digital converter, of the first voltage into a digital value.

[0023] According to one embodiment, the second and third values ​​are values ​​of an image.

[0024] One embodiment provides a method for learning the preceding neural network, the method comprising determining the first and second values ​​using a Markov chain Monte Carlo learning approach.

[0025] According to one embodiment, the analog vector multiplier circuit includes OxRAM devices and the Markov chain Monte Carlo learning approach includes an application of a Metropolis-Hastings algorithm.

[0026] According to one embodiment, the analog vector multiplier circuit includes magnetic domain wall devices and the Markov chain Monte Carlo learning approach includes a stochastic Langevin gradient dynamics application. Brief description of the drawings

[0027] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0028] Fig. 1 represents examples of prediction calculations based on several models;

[0029] [Fig.2A] and [Fig.2B] represent a prediction calculation based on a BatchEnsemble calculation;

[0030] [Fig.3] is a schematic representation of an analog circuit configured to perform multiplication and accumulation operations according to an embodiment of the present description;

[0031] [Fig.4A] schematically represents a vector multiplier circuit according to an embodiment of the present description;

[0032] [Fig.4B] schematically represents a vector multiplier circuit according to another embodiment which is a variant of that of [Fig.4A];

[0033] [Fig.5A] schematically represents a network circuit with transverse branches according to an embodiment of the present description;

[0034] [Fig.5B] schematically represents the cross-branch network circuit of [Fig.5A] and an example of a transition circuit;

[0035] [Fig.6A] schematically represents a vector multiplier circuit according to an embodiment of the present description;

[0036] [Fig.6B] schematically represents a vector multiplier circuit according to another embodiment of the present description;

[0037] [Fig.7] schematically represents an example of a current mirror circuit according to an embodiment of the present description;

[0038] [Fig.8A] schematically represents another example of a network circuit with transverse branches according to an embodiment of the present description;

[0039] [Fig.8B] schematically represents another example of a vector multiplier circuit according to an embodiment of the present description;

[0040] [Fig.9] is a schematic representation of another analog circuit configured to perform multiplication and accumulation operations according to an embodiment of the present description;

[0041] [Fig. 10] represents an example of prediction calculations based on several models for a model put in parallel according to an embodiment of the present description;

[0042] [Fig.1 1] is a schematic representation of yet another analog circuit configured to perform multiplication and accumulation operations according to an embodiment of the present description;

[0043] [Fig.12A] is a graph representing an example of probabilities of conductance levels of a programmable resistive element;

[0044] [Fig.12B] is a flowchart representing a learning process for an analog circuit according to an embodiment of the present description;

[0045] [Fig. 13A] is a graph representing an example of the SGLD algorithm (of (English "Stochastic Gradient Langevin Dynamics", stochastic gradient Langevin dynamics), which involves random sampling; and

[0046] [Fig.13B] is a flowchart representing a learning method for an analog circuit according to an embodiment of the present description. Description of the implementation methods

[0047] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0048] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular, the operation of neural networks, and especially neural networks configured to implement prediction operations, is not detailed.

[0049] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements coupled together, this means that these two elements can be connected or linked through one or more other elements.

[0050] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0051] Unless otherwise specified, the expressions "approximately", "about", "Approximately" and "on the order of" mean within 10%, preferably within 5%.

[0052] In the following description, examples of neural network architectures are described that can apply several models, for example, a number K of models ranging from 10 to 1,000. For clarity in the figures below, the implementation of only three models is shown. Furthermore, also for clarity in the figures, the input data comprises only two elements. Generally, for example, when classification is performed on images, the input data supplied to the neural network comprises many more than two elements. For example, in the case of image classification, the size of the input data corresponds to the number of pixels in an input image multiplied by the number of channels, such as color channels, in the images.

[0053] Figure 1 illustrates examples of prediction calculations based on three models of an ensemble. In particular, Figure 1 illustrates multiplication operations between input data X and weighting matrices W1, W2, and W3. The input data X is, for example, a vector X = (xB x2) of size 2, where Xi and x2 are, for example, real values. In one example, the values ​​xi and x2 are normalized values, belonging, for example, to the interval [0,1] or the interval [-1,1], or to any other suitable interval.

[0054] The weighting matrices W1, W2, and W3 are each associated with a linear layer of the neural network. Each model describes a neural network, for example, a classification neural network, and, in the example of [Fig. 1], each model comprises a single linear layer described by the corresponding weighting matrix. More generally, each model can comprise one or more linear layers, each associated with a corresponding weighting matrix and, optionally, by an activation function. In some embodiments, the activation functions of the hidden layers are identity functions. The computation by the neural network is performed, for example, sequentially, from an input layer, through the hidden layers, to an output layer. Data arriving at the next layer in the chain of layers are output data from the previous layer in the chain.

[0055] The models as a whole have for example been adapted during a learning phase using, for example, different initialization parameters and / or using different learning algorithms, such that the generated models and their generated parameter values ​​are not identical to each other. In particular, in some embodiments, no two matrices among the weighting matrices W1, W2 and W3 are exactly equal to each other.

[0056] Figure 1 shows an example of three matrix multiplication operations, one for each model, performed during an inference operation using the neural network. Each weighting matrix is ​​2x2 in size and represents the element in the i-th row and j-th column of the k-th model, with 1L i, j < 2 and 1 < k < 3. In practice, the size of each weighting matrix is, for example, significantly larger, with each matrix having a size between 100 x 100 and 10,000 x 10,000. More generally, each weighting matrix W has, for example, dimension nxm, in the case where the input vector X is of dimension m and the output vector y is of dimension n.

[0057] Matrix multiplication between matrix W1 and input vector X results in an output vector F1 = (y*.y'), the matrix U'1 * P' is a matrix between matrix W2 and The input vector X results in an output vector y2 = (j2 yi) and the matrix multiplication between the matrix W3 and the input vector X results in an output vector

[0058] Storing each of the weighting matrices for each model is costly in terms of memory storage. Furthermore, performing multiple matrix multiplications, equal in number to the number of models, is costly in terms of time and energy.

[0059] Figure 2A represents an example of a BatchEnsemble computation. BatchEnsemble is an algorithm that performs ensemble approximation while using relatively little memory space, as proposed by Yeming Wen, Dustin Tran, and Jimmy Ba in their publication “BatchEnsemble: An Alternative Approach to Efficient Ensemble and Lifelong Learning”, 2020-02-19. In particular, the BatchEnsemble computation allows the computation of an approximation of the weighting matrices W1, W2, and W3 based on a single matrix S, shared by the three weighting matrices, and a pair of vectors for each of the matrices W1, W2, and W3. The matrix S has the same dimensions as each of the weighting matrices and, in the example in Figure 2A, it has, for example, a size of 2 x 2 and includes elements Si,j, with 1 i, j < 2.In particular, the matrix S is such that there exist matrices P1, P2 and P3 such that P1 * S = W1, P2 * S = W2 and P3 * S = W3, where * is the element indicating the multiplication operation, also known as scalar-scalar multiplication or point-by-point multiplication.

[0060] Furthermore, there are three horizontal vectors, of size 1x2, H2 _ ( ^3 ^2 ) ^3 _ ^3 ^3 ) and the vertical vectors, of size 2 x 1,V*,V2 and V3 such that their transpositions are respectively equal to (vj. vl), (v^. and (Vp v} ). These vectors are constructed such that / / '0 V1 = P1, H2^V1 = P1 and H3® V3 = P3, where 0 is the exterior product.

[0061] The shared matrix S and the horizontal and vertical vectors H1, H2, H3, V1, V2 and V3 are therefore such that (h1 0 = W1, (H20 V2>S = W2 and {H30 = Wx

[0062] Figure 2B represents a complete Batch calculation of the output data y1, y2, y3. Considering the shared matrix S, the horizontal and vertical vectors H1, H2, H3, V1, V2 and V3 and the input data X described in relation to Figures 1 and 2A, the output data values ​​y1, y2, y3 are therefore respectively equal to X [(^0^5] -Xet[(H303>S] X, where • denotes a classic matrix - vector multiplication.

[0063] The elements J* and J*, 1 k <3, can then be expressed as sequences of scalar multiplications, denoted by x, and additions. In particular, the elements and J*, and for each model k, with k 1 k <3, are such that:

[0064] [Math.l] = yk [Math.l] J* “ V2

[0065] A person skilled in the art will understand how to extend these equations when the shared matrix S, each horizontal vector, and each vertical vector are respectively of size n x n, 1 x n, and n x 1, where n is an integer, for example, of at least 2 or any other number, and for example, of at least 10 and generally between 10 and 1000, representing the size of the input and output data. For example, in the case where the shared matrix S has a size of 2, the total storage and compression costs are the same for all values ​​of k. Starting with a matrix of size 3 x 3, the compression cost becomes smaller than the total cost. Indeed, for full matrices, i.e., without compression, the total number of elements to be stored is equal to n x m x k, whereas, for compressed matrices, this number is equal to n x m + k x (n + m).Furthermore, a person skilled in the art will understand how to generalize to a number K of models, where K is an integer equal to at least 2 and preferably at least 10, and for example between 10 and 1000. In this case, there will be a number K of horizontal vectors and a number K of vertical vectors.

[0066] The use of BatchEnsemble calculations leads to a reduced amount of memory storage to store K weighting matrices, instead of storing K weighting matrices each of size nxm, only the shared matrix S of size nxn is stored, as well as 2K vectors of size n.

[0067] Figure 3 is a schematic representation of an analog circuit 300 configured to perform MAC operations according to an embodiment of the present description. In particular, the circuit 300 comprises three circuit blocks 302, 304, and 306 configured to implement BatchEnsemble computation, as described in relation to Figure 2B. The analog circuit 300 implements, for example, a linear layer of a neural network.

[0068] Circuit blocks 302 and 306 are, for example, multiplier circuits configured to provide output voltage values ​​based on input currents. Circuit block 304 is, for example, a cross-branch network configured to provide output currents based on voltage inputs.

[0069] The circuit block 302 is, for example, configured to receive, via two input lines, currents F and I2 encoding respectively the values ​​of the input data xi and x2. The currents F and I2 are, for example, supplied by the control circuit 310.

[0070] The circuit block 302 is further configured to perform multiplication between the input data values ​​Xi and x2 and the elements of the horizontal vectors Hk, 1 ≤ k < 3. The circuit block 302 also receives, on corresponding input lines, input voltages Vlk, with 1 ≤ & < 3, to activate a multiplication operation involving the currents F and I2 and a vector selected from the horizontal vectors Hk. In particular, to activate the k model, the voltage Vlk is set to an enabled level, for example, to a supply voltage Vdd of the circuit 300, and the other input voltages are set to a disabled level, for example, to ground. The voltages VI1, VI2, and VI3 are, for example, generated by the control circuit 310.

[0071] Furthermore, the circuit block 302 includes resistive elements (not shown in Figure 3) encoding the values ​​of the elements of the horizontal vectors Hk. Thus, by activating the k-th line, the circuit block 302 is configured to perform the multiplications x and x. Since the input values ​​Xi and x2 are encoded by currents and the values ​​ct / ^ are encoded by the resistances of the resistive elements, the outputs are, for example, voltages, in which an output voltage Vai of the circuit block 302 is equal to the product x and an output voltage Va2 of the circuit block 302 is equal to the product xx

[0072] In the general case, where the input data vector X and the horizontal vectors Hk are each of size n and where the neural network implements K models, the circuit block 302 comprises, for example, n input lines receiving the input currents and K input voltage lines receiving the voltages Vlk, for 1 k < K. In this case, the circuit block 302 is configured to provide as output, for a model k selected by the activation of the voltage Vlk, a number n of output voltage values ​​encoding the products Xm x for 1 m < n.

[0073] The circuit block 304 in the example of Figure 3 consists of a cross-branch network comprising two rows and two columns. In particular, the circuit block 304 models a multiplication operation by the shared matrix S. The circuit block 304 comprises, for example, 2x2 resistive elements (not shown in Figure 3). The resistive element in an i-th row and a j-th column of the cross-branch network has, for example, a resistance of l / Sjj ohms corresponding to a conductance of Sij Siemens. The circuit block 304 receives, on corresponding input lines, the voltages Val and V.l2 generated by the circuit block 302 and is configured to provide two current values ​​Ibi and Ib2 at the output. The output current Ibi encodes the value $(xx) + S, ? ( X x ) ct 'c output current Ib2 encodes the value 5½ ,( / rxx ) + S-> 7 ( X x ), °ù k designates the model which is executed.In some embodiments, the circuit block 304 also receives an EN enable input signal, generated by the control circuit 310, to activate the circuit block 304 when an inference operation is to be performed. For example, the enable signal is active high and is set to a maximum supply voltage, such as VDD, of the circuit during inference operations.

[0074] Circuit block 306 is similar to circuit block 302 and is configured to receive, on respective input lines, the currents Ibi and Ib2. Circuit block 306 is configured to perform multiplications of the values ​​encoded by the currents Ibi and Ib2 with the elements of a vector selected from among the vertical vectors Vk. Circuit block 306 receives, for example, on corresponding input lines, the selection voltages VI1, VI2, and VI3 and is configured, for example, to select the vertical vector Vk associated with model k in a manner similar to circuit block 302, by setting the input voltage Vlk to an on level, for example, the supply voltage Vdd, and setting the other voltage inputs to a off level, for example, the ground voltage.

[0075] The circuit block 306 further includes resistive elements (not shown in Figure 3) encoding the coefficients of each of the vertical vectors Vk. When the voltage VI1 is set to the on level and the other voltages are set to ground, The 306 circuit block is configured to provide output voltages Vci and Vc2 encoding the output values ​​y] and yf respectively. In particular, for each model k, the output values ​​y] and y* are such that:

[0076] yk=Ytop,Yci-vkxih} = vkx +Sl^XX2))',

[0077] The control circuit 310 receives, for example, the input data values ​​xi and x2, for example in the form of digital signals, and generates the currents h and I2 based on the input data values ​​xi and x2, using, for example, a digital-to-analog converter (DAC). The control circuit 310 also receives, for example, a clock signal CLK and generates the control voltages VI1, VI2, and VI3 so that the k models are applied sequentially to the input data values.

[0078] The circuit block 306 is for example connected to an analog-to-digital converter 312 (ADC) configured to convert the output voltages Vci and Vc2 into the voltage and y^ values ​​in the digital domain.

[0079] The resistive elements described herein are, for example, non-volatile programmable resistive devices. The way in which such devices are programmed depends on the particular technology. Once programmed, the resistance of the element remains relatively constant over time. For example, suitable types of programmable resistive elements include: - PCM memory elements (from the English “Phase Change Memory”) - see for example the publication by La Barbera, Selina, et al. “Narrow Heater Bottom Electrode-Based Phase Change Memory as a Bidirectional Artificial Synapse”, Adv. Electron. Mater. 2018, 4, 1800223; - OxRAM memory elements (from the English "Oxide RAM," oxide-based RAM) - see, for example, the publication by HS Philip Wong et al. entitled "Metal-Oxide RAM," Proceedings of the IEEE, 2012; and / or - CBRAM memory elements (from the English "Conductive Bridging RAM", conductive bridge memory) - see for example the publication by D. Jana et al. entitled "Conductive - bridging random access memory: challenges and opportunity for 3D architecture", Nanoscale Research Letters, 2015.

[0080] The resistances of the resistive elements of the circuit blocks 302, 304 and 306 are, for example, programmed during a programming phase. For example, the resistance values ​​are determined during a learning phase of the neural network.

[0081] In operation, during an inference based on given input data values ​​Xi and x2, the circuit 300 of Figure 3 is activated over k cycles and, during each cycle, a corresponding voltage among the control voltages VI1, VI2 and VI3 is activated to generate the output values ​​y| and y* for each model k. During each cycle, for a given value of k, the input data values ​​xi and x2 and the control voltages VI1, VI2 and VI3 are for example kept constant for a stabilization period to allow the output values ​​y^ and y^ to stabilize at their final levels before the start of the next cycle.

[0082] Figure 4A schematically represents a vector multiplier circuit according to an embodiment of the present description. For example, the circuit in Figure 4A implements the circuit block 302 of Figure 3. The multiplier circuit includes, for example, two sub-circuits 400 and 400' configured respectively to calculate the output voltage Val based on the input data value Xi represented by the current h and the output voltage Va2 based on the input data value x2 represented by the current I2.

[0083] The subcircuit 400 comprises conductive branches 402_1, 402_2, and 402_3. Each conductive branch 402_k, 1 k < 3, comprises a resistive element / / *', whose resistance is programmed to encode the value of the horizontal vector Hk. Furthermore, each conductive branch 402_k, 1 k < 3, also comprises a transistor 404_k connected in series with the resistive element Hk. For example, the gates of the transistors 404_k, 1 k < 3, are respectively connected to a corresponding control line that receives the corresponding voltage Vlk. The conductive branches 402_k, 1 k < 3, are respectively connected between a common voltage rail 406 supplied with a voltage Vtop and a common output line 408. The common output line 408 is configured to conduct a current l'i.For example, the current l'i is imposed on the common output line 408 by a current mirror 410 (CM1) connected to a ground rail (GND) and having one of its branches connected to the line 408 and its reference branch connected to a line carrying the current h encoding the value of the input data xb. The current l'i is, for example, equal to, or proportional to, the current L.

[0084] Similarly, the subcircuit 400' comprises conductive branches 4O2'_1, 4O2'_2, and 4O2'_3. Each conductive branch 4O2'_k, 1 k < 3, includes a resistive element Hk whose resistance is programmed to encode the value of the horizontal vector Hk. Furthermore, each conductive branch 4O2'_k, 1 k < 3, also includes a transistor 4O4'_k connected in series with the resistive element Hy. For example, the gates of the transistors 4O4'_k, 1 k < 3, are respectively connected to a corresponding control line that receives the corresponding voltage Vlk. The conductive branches 4O2'_k, 1 k < 3, are respectively connected between a common voltage rail 406' supplied at the voltage Vtop and a common output line 408'. The common output line 408' is configured to conduct a current I'2. By For example, the current I'2 is imposed on the common output line 408' by a current mirror 410' (CM2) connected to the ground rail (GND) and having one of its branches connected to the line 408' and its reference branch connected to a line carrying the current I2 encoding the value of the input data x2. The current I'2 is, for example, equal to, or proportional to, the current I2.

[0085] In operation, in order to perform the multiplications, transistors 404_1 and 404_1 are made conductive by the control circuit 310 by setting the voltage V11 to the on level. Transistors 404_2, 404_2, 404_3, and 404_3 are made non-conductive by setting the voltages V12 and V13 to the off level. The voltage on lines 408 and 408' will then be equal to V1 and V12, respectively, where V1 = V11, and V2 = . The multiplications h1x2 « h1xt can be performed in a similar manner by activating voltages VI2 and VI3, respectively.

[0086] Thus, in the column vector multiplier circuit of [Fig. 4A], the number of conducting branches 402, 402' of each subcircuit 400, 400' is equal to the number of models K to be implemented. In the case where the input data is of size n, each subcircuit 400, 400' of the multiplier circuit comprises n subcircuits, each having an implementation similar to subcircuits 400 and 400'.

[0087] In each of the conducting branches 402_k, 4O2'_k, 1 k < 3 of Figure 4A, the transistors 404_k and 4O4'_k are placed between the resistive element of the conducting branch and the output line 408 and 408'. In another embodiment, the transistors 404_k and 4O4'_k, 1 k < 3, are placed between the voltage rail 406 or 406' and the resistive elements.

[0088] Figure 4B schematically represents a vector multiplier circuit according to another embodiment which is a variant of that of Figure 4A. In particular, Figure 4B represents the subcircuits 400, 400' of Figure 4A according to a variant in which the common conducting lines 406, 406' are connected to the ground rail GND rather than to the voltage rail Vtop, and the current mirrors 410, 410' (CM1, CM2) are connected to the voltage rail Vtop rather than to the ground rail GND. In this case, when a kth model is selected using the voltages VI1 to VI3, the voltages on the lines 408 and 408' will thus be equal to Vai and V^, respectively, where y Qty 7=zh^x^- In the example shown in [Fig. 4B], The currents from the cross-branch circuit of circuit block 304 are copied, and the copied currents are supplied to circuit block 306. [Fig. 5A] represents schematically a cross-branch network circuit 500 which is an example of a possible implementation of the circuit block 304 of [Fig.3].

[0089] The cross-branch network circuit 500 includes input voltage lines 502_l and 502_2 connected respectively, for example, to the output voltage lines 408, 408' of [Fig.4A] or 4B in order to receive the voltages Val and Va2, respectively.

[0090] The cross-branch network circuit 500 comprises: - a first conductive branch 503_l 1 comprising the series connection of a resistive element Si,i and a transistor 504_l 1 connected between the input voltage line 502_l and a first output current line 506_l; - a second conductive branch 503_12 comprising the series connection of a resistive element Si>2 and a transistor 504_12 connected between the input voltage line 502_2 and the first output current line 506_1; - a third conductive branch 503_21 comprising the series connection of a resistive element S2ji and a transistor 504_21 connected between the input voltage line 502_1 and a second output current line 506_2; and - a fourth conductive branch 503_22 comprising the series connection of a resistive element S2>2 and a transistor 504_22 connected between the input voltage line 502_2 and the second output current line 506_2.

[0091] Transistors 504-11, 504-12, 504-21 and 504-22 are, for example, controlled by the EN enable signal. When in the enabled state, the enabled state voltage level of the enable signal is, for example, chosen to be relatively high, for example the supply voltage VDD of the circuit, in order to obtain a relatively low on-state resistance Ron of transistors 504-11, 504-12, 504-21 and 504-22.

[0092] Each of the resistive elements Sij, for 1 i ^2 and 1 < j < 2, codes, for example, the inverse 1 / Sij of the coefficients of the shared matrix S.

[0093] In the case where the circuit block 302 supplying the voltages Val and Va2 is that of [Fig.4A], the output lines 506_l and 506_2 are, for example, pulled at the voltage level Vtop, so that the current Ibb generated by the common output line 506_l and the current Ib2, generated by the common output line 506_2, are such that: [Math 3] = (Vtop-Val) xsM + (Vtop-xsL2 = xlh{slA + x2hi2sL2, ^2 - ( Vtop - Va\) x s21 + ( Vtop - Va2 ) x S2y2 = ^1^^,1 + -^2^2,2-

[0094] According to one variant, in the case where the circuit block 302 supplying the voltages Val and Va2 is that of [Fig. 4B], the output lines 506_1 and 506_2 are, for example, pulled to ground voltage GND, so that the current Ibi generated by the output line common 506_l and the current Ib2 generated by the common output line 506_2 are such that: [Math 4] / ¼ = x $1.1+ K / 2 x $1.2 = *i^î$li + ^2$1.2? Ib2 = Val

[0095] In the case where the input and output data are of size n, the circuit 500 comprises, for example, n common output lines each connected, via n branches 503, to n input voltage lines Vaj, 1 j' < n.

[0096] In Figure 5A, each transistor 504_ij, 1 i, j 2, is placed between the resistive element Si,j and the common output line 506_i. In another example of an embodiment, the order of the transistor and the resistive element in each branch is switched so that each transistor 504_ij, 1 i, j 2, is placed between the input line 502j and the resistive element S;, j.

[0097] Fig. 5B schematically represents the cross-branch network circuit of Fig. 5A and an example transition circuit providing an interface with circuit blocks 302 and 306.

[0098] For example, in order to impose the voltage Vai on the input line 502_1, an operational amplifier 512_1 (Albot) is provided, the positive input of which is connected to the output line 408 of the subcircuit 400 and the negative input and output of which are connected to the input line 502_1. Similarly, in order to impose the voltage Va2 on the input line 502_2, an operational amplifier 512_2 (A2bot) is provided, the positive input of which is connected to the output node 408' of the subcircuit 400' and the negative input and output of which are connected to the input line 502_2.

[0099] In order to impose the voltage Vtop on the output line 506_l, a transistor 514_1 is, for example, connected between the output line 506_l and the supply rail Vdd, and an operational amplifier 516_1 is, for example, arranged so that its positive input is connected to the output line 506_l, its negative input is connected to the voltage rail Vtop, and its output is connected to the gate of transistor 514_1. Similarly, in order to impose the voltage Vtop on the output line 506_2, a transistor 514_2 is, for example, connected between the output line 506_2 and the supply rail Vdd, and an operational amplifier 516_2 is, for example, arranged so that its positive input is connected to the output line 506_2, its negative input is connected to the voltage rail Vtop, and its output is connected to the gate of transistor 514_2.

[0100] In order to generate an output current Ibi' to control the circuit block 306 based on the current Ibi, a current mirror 610 is provided, for example. A reference branch of the current mirror 610 comprises PMOS transistors 518_1 and 520_1 connected in series via their source / drain nodes between the transistor 514_1 and the supply voltage rail Vdd. A current duplication branch of the current mirror 610 comprises PMOS transistors 522_1 and 524_1 connected in series via their source / drain nodes between an output line 608 and the supply voltage rail Vdd. The gates of transistors 518_1 and 522_1 are, for example, connected together and to a bias voltage Vcasc. The gates of transistors 520_1 and 524_1 are, for example, connected together and to an intermediate node between transistors 518_1 and 514_1.

[0101] Similarly, in order to generate an output current Ib2' to control the circuit block 306 based on the current Ib2, a current mirror 610' is provided, for example. A reference branch of the current mirror 610' comprises PMOS transistors 518_2 and 520_2 connected in series via their source / drain nodes between transistor 514_2 and the supply voltage rail Vdd. A current duplication branch of the current mirror 610' comprises PMOS transistors 522_2 and 524_2 connected in series via their source / drain nodes between an output line 608' and the supply voltage rail Vdd. The gates of transistors 518_2 and 522_2 are, for example, connected together and to the bias voltage Vcasc. The gates of transistors 520_2 and 524_2 are for example connected together and at an intermediate node between transistors 518_2 and 514_2.

[0102] Figure 6A schematically represents a vector multiplier circuit according to an embodiment of the present description. For example, the circuit in Figure 6A provides an example of an implementation of circuit block 306 in Figure 3. This multiplier circuit includes, for example, two subcircuits 600 and 600', which are similar to subcircuits 400 and 400', respectively, in Figure 4A. Subcircuits 600 and 600' are configured to perform multiplications with the coefficients of the vertical vectors V1, V2, and V3.

[0103] The subcircuit 600 comprises conductive branches 602_1, 602_2, and 602_3. Each conductive branch 602_k, 1 k < 3, comprises a resistive element y*, the resistance of which is programmed to encode the value of the vertical vector Vk. Furthermore, each conductive branch 602_k, 1 k < 3, also comprises a transistor 604_k connected in series with the resistive element y*. For example, the gates of the transistors 604_k, 1 < k < 3, are respectively connected to a corresponding control line that receives the corresponding voltage Vlk. The conductive branches 602_k, 1 k < 3, are respectively connected between a common voltage rail 606 supplied with voltage Vtop and the common output line 608 providing an output voltage Vci of the circuit. The common output line 608 is configured to conduct the current Ibi', which is for example the mirror of the current Ibi generated by the circuit block 304.For example, the current Ibi' is imposed on the common output line 608 by the current mirror. 610 (CM1) is described in relation to [Fig. 5B], which is connected to the ground rail (GND) and has one of its branches connected to line 608 and its reference branch connected to the output line 506 of the cross-branch network circuit 500 of [Fig. 5A], carrying the current Ibb

[0104] Similarly, the subcircuit 600' comprises conducting branches 6O2'_1, 6O2'_2, and 6O2'_3. Each conducting branch 6O2'_k, 1 k < 3, comprises a resistive element y*, whose resistance is programmed to encode the value of the vertical vector Vlk. Furthermore, each conducting branch 6O2'_k, 1 k < 3, also comprises a transistor 6O4'_k connected in series with the resistive element y*. For example, the gates of the transistors 6O4'_k, 1 < 3, are respectively connected to A corresponding control line receives the corresponding voltage Vlk. The conducting branches 602'_k, 1 k < 3, are respectively connected between a common voltage rail 606' supplied at voltage Vtop and the common output line 608' providing an output voltage Vc2 of the circuit. The common output line 608' is configured to conduct the current Ib2', which is, for example, the mirror of the current Ib2 generated by the circuit block 304. For example, the current Ib2' is imposed on the common output line 608' by the current mirror 610' (CM2) described in relation to [Fig. 5B], which is connected to the ground rail (GND) and has one of its branches connected to line 608' and its reference branch connected to the output line 506_2 of the cross-branch network circuit 500 of [Fig. 5A], conducting the current Ib2.

[0105] The voltages Vci and Vc2 supplied at output by subcircuits 600 and 600' are, for example, such that, when the voltage Vlk, 1 k < 3, is set to be on, for example at Vdd, and the other voltages are set to ground: [Math 5] Vtop - vcl = = yf ( + *2^12 ) = VtoP - Vc2 = ~ V2 ( + ^2^2,2 ) =

[0106] In the line vector multiplier circuit of [Fig. 6A], the number of conducting branches 602, 602' of each subcircuit 600, 600' is equal to the number of models K to be implemented. In the case where the input data is of size n, each subcircuit 600, 600' of the multiplier circuit comprises n subcircuits, each having an implementation similar to subcircuits 600 and 600'.

[0107] In each of the conducting branches 602_k, 1 -k < 3, of figure 6A, the transistors 604_k and 6O4'_k are placed between the resistive element of the conducting branch and the output line 608 or 608'. In another embodiment, the transistors 604_k and 6O4'_k, 1 < ≤ 3, are placed between the voltage rail 606 or 606' and the resistive elements.

[0108] Figure 6B schematically represents a vector multiplier circuit according to another embodiment of the present description. In particular, Figure 6B represents a variant of the circuit block of Figure 6A in which the common conductive lines 606, 606' are connected to the ground rail GND rather than to the voltage rail Vtop, and the current mirrors 610, 610' are connected to the voltage rail Vdd rather than to the ground rail GND.

[0109] Furthermore, examples of embodiments of current mirrors 610, 610' are shown in [Fig.6B].

[0110] The current mirror 610 includes, for example, PMOS transistors 612 and 614. The PMOS transistor 612 forms a reference branch of the current mirror and has its source connected to the supply voltage rail Vdd and its drain connected to its gate and to the current input line that receives the current Ibi. The PMOS 614 forms a current duplication branch of the current mirror and has its source connected to the supply voltage rail Vdd, its drain connected to the output line 608, and its gate connected to the gate of the PMOS transistor 612.

[0111] Similarly, the current mirror 610' comprises, for example, PMOS transistors 612' and 614'. The PMOS transistor 612' constitutes a reference branch of the current mirror and has its source connected to the supply voltage rail Vdd and its drain connected to its gate and to the current input line receiving the current Ib2. The PMOS 614' constitutes a current duplication branch of the current mirror, and has its source connected to the supply voltage rail Vdd, its drain connected to the output line 608', and its gate connected to the gate of the PMOS transistor 612'.

[0112] Compared to the implementation of [Fig.6A], the implementation of [Fig.6B] allows the output voltages, generated by the sub-circuits 600 and 600', to be referenced to ground and avoids subtracting the output voltage from the Vtop voltage.

[0113] Fig. 7 is an example of a 700 current mirror circuit and proposes a setting in possible work of each of the current mirrors 410, 410' of figures 4A and 4B and of the current mirrors 610, 610' of [Fig.6A].

[0114] The circuit 700 includes a reference branch comprising transistors 702 and 706 connected in series via their source and drain nodes between a linear current input line and the ground voltage rail GND. The gates of transistors 702 and 706 are connected to their drains.

[0115] The circuit 700 further includes an additional branch comprising transistors 704 and 708 connected in series via their source and drain nodes between a current output line Icopy and the ground voltage rail GND. The gates of transistors 704 and 708 are connected respectively to the gates of transistors 702 and 706.

[0116] Fig. 8A is another example of a cross-branch network circuit 800 according to an embodiment of the present description. In particular, the circuit 800 implements a cross-branch network circuit for a shared-matrix BatchEnsemble algorithm. For example, in the case where the shared matrix S is equal to the identity matrix, the output data Y1, Y2, Y3 are then equal, respectively, to y1) . y, (H2® V2) • X and (ff3® V3) X'. In other words, for each k < 3, the output data are such that: [Math 6] X (h* XXj+&2 XX1) >y?~V2X +

[0117] Referring to Figure 3, this means that circuit blocks 302 and 304 can be replaced by the multiplier circuit 800, which is configured to generate the values ​​x → X; + x in a branching network circuit Transverse 800 comprises three output current lines 806_1, 806_2 and 806_3, and each of these lines is configured to provide a current Ibh Ib2 and Ib3, corresponding respectively to the values ​​x + xx Xj^ + X x2 and fe3 xxj + felxx^

[0118] The input value Xi is, for example, supplied in the form of a voltage Vx[ on a input voltage line 802_l and the input value x2 is for example supplied as a voltage Vx2 on an input voltage line 802_2.

[0119] Circuit 800, for example, comprises six conducting branches: - a first conductive branch 8O3_l 1 comprising the series connection of a resistive element jy* and a transistor 804_l 1 connected between the input voltage line 802_l and the output current line 806_l, the resistive element g1 being programmed to have a resistance that represents the inverse jy of the value of the vector horizontal and the transistor 804_l 1 being controlled at its gate by the voltage VI1; - a second conductive branch 803_12 comprising the series connection of a resistive element and a transistor 804_12 connected between the input voltage line 802_2 and the first output current line 806_1, the resistive element being programmed to have a resistance which represents the inverse ] / of the value of the horizontal vector the transistors 804_1 and 804_12 being controlled at the level of their gates by the voltage VI1; - a third conductive branch 803_21 comprising the series connection of a resistive element jjy and a transistor 804_21 connected between the input voltage line 802_1 and the second output current line 806_2, the resistive element being programmed to have a resistance that represents the inverse ] / je |a value of the horizontal vector |es transistors 804_11 and 804_12 being controlled at their gates by the voltage VI1; and - a fourth conductive branch 803_22 comprising the series connection of a resistive element H and a transistor 804_22 connected between the input voltage line 802_2 and the second output current line 806_2, the resistive element being programmed to have a resistance that represents the inverse of the value of the horizontal vector, the transistors 804_21 and 804_22 being controlled at their gates by the voltage VI2; and - a fifth conductive branch 803_31 comprising the series connection of a resistive element and a transistor 804_31 connected between the input voltage line 802_1 and a third output current line 806_3, the resistive element being programmed to have a resistance that represents the inverse of the value of the horizontal vector; and - a sixth conductive branch 803_32 comprising the series connection of a resistive element and a transistor 804_32 connected between the input voltage line 802_2 and the third output current line 806_3, the resistive element being programmed to have a resistance which represents the inverse j / of the value of the horizontal vector, the transistors 804_31 and 804_32 being controlled at the level of their gates by the voltage VI3.

[0120] For each 1 < A < 3, each 803_ki branch provides a current Ibki and Ibk2. Each resistive element 806_ki is for example programmed to the value ] / and is supplied by the voltage encoding the input value Xj.

[0121] Figure 8B is another example of a vector line multiplier circuit 808. In particular, circuit 808 is, for example, connected to circuit 800 to perform multiplication by the vertical vectors Vk. Circuit 808 is implemented, for example, when the shared matrix S is equal to the identity matrix.

[0122] The multiplier circuit 808 is, for example, similar to the multiplier circuit in Figure 6A, except that, rather than two subcircuits, it comprises three subcircuits 810_1, 810_2, and 810_3. Each subcircuit 810_k, l <fc< 3, correspond à The multiplication of the corresponding output current Ibk of the 800 circuit by the vertical vector Vk. In other words, each 810_k sub-circuit is configured to perform a multiplication by a vertical vector Vk associated with a model.

[0123] The subcircuit 810_l comprises conducting branches 812_11 and 812_12. Each conducting branch 812_li, I < 2, comprises a resistive element y], whose resistance is programmed to encode the value v / of the vertical vector V1. Furthermore, each conducting branch 812_li, I ^2, also comprises a transistor 814_li connected in series with the resistive element y J. For example, the gates of transistors 814_li, 1 ^2, are connected respectively to a corresponding control line which receives the corresponding voltage VI1. The conducting branches 812_li, 1 Si <2, are connected respectively between a common voltage rail 816_1 supplied at voltage Vtop and a common output line 818_1 providing an output voltage Vci of the circuit. The common output line 818_1 is configured to conduct a current Ibi', which is, for example, the mirror of the current Ibi generated by the circuit 800. For example, the current Ibi' is imposed on the common output line 818_1 by a current mirror 810 (CM1) connected to the ground rail (GND) and having one of its branches connected to the line 818_1, and its reference branch connected to the output line 806_l of the circuit 800 of [Fig. 8A] conducting the current Ibi.

[0124] Similarly, the subcircuit 810_2 comprises conductive branches 812_21 and 812_22. Each conductive branch 812_2i, 1 Si <2, comprises a resistive element y^, whose resistance is programmed to encode the value vj of the vertical vector V2. Furthermore, each conductive branch 812_2i, 1 Si <2, also includes a transistor 814_2i connected in series with the resistive element y2. For example, the gates £ Transistors 814_2i, 1 Si <2, are connected respectively to a corresponding control line that receives the corresponding voltage Vf. Conducting branches 812_2i, 1 Si <2, are connected respectively between a common voltage rail 816_2 supplied by the voltage Vtop and a common output line 818_2 providing an output voltage Vc2 of the circuit. The common output line 818_2 is configured to conduct a current Ib2', which is, for example, the mirror of the current Ib2 generated by the circuit 800. For example, the current Ib2' is imposed on the common output line 818_2 by a current mirror 810' (CM2) connected to the ground rail (GND) and having one of its branches connected to the line 818_2, and its reference branch connected to the output line 806_2 of the circuit 800 in [Fig. 8A], conducting the current Ib2.

[0125] Similarly, the subcircuit 810_3 comprises conductive branches 812_31 and 812_32. Each conductive branch 812_11, I^2, comprises a resistive element y,- whose resistance is programmed to encode the value v? of the vertical vector V3. Furthermore, each conducting branch 812_3i, 1 <i <2, comprend en outre un transistor 814_3i relié en série avec l’élément résistif y?. Par exemple, les grilles des transistors 814_3i, I < i < 2, sont reliées respectivement à une ligne de commande correspondante qui reçoit la tension correspondante, Vf. Les branches conductrices 812_3i, 1 <i < 2, sont reliées respectivement entre un rail de tension commune 816_3 alimenté à la tension Vtop et une ligne de sortie commune 818_3 fournissant une tension de sortie Vc 3 du circuit. La ligne de sortie commune 818_3 est configurée pour conduire un courant Ib3’, qui est par exemple le miroir du courant Ib3 généré par le circuit 800. Par exemple, le courant Ib3’ est imposé sur la ligne de sortie commune 818_3 par un miroir de courant 810” (CM3) relié au rail de masse (GND) et ayant une de ses branches reliée à la ligne 818_3, et sa branche de référence reliée à la ligne de sortie 806_3 du circuit 800 de la [Fig.8A] conducting the current Ib3. .

[0126] In operation, when voltage VI1 is activated, for example by setting it to Vdd, and voltage VI2 is deactivated, for example by setting it to ground, each of the 810_k, 1 k < 3 subcircuits is configured to have an output voltage Vck encoding yk — x Xj + h? X X2 ) ' When voltage VI2 is activated, for example by setting it to Vdd, and voltage VI1 is deactivated, for example by setting it to ground, each of the 810_k, 3 subcircuits is configured to obtain an output voltage Vck encoding = y* ( x Xj + x X2 ) •

[0127]

[0128] Figure 9 is another schematic representation of an analog circuit configured to perform multiplication and accumulation operations according to an example embodiment of the present description. In particular, the circuit is a variant of the architecture of Figure 3, which is capable of implementing MAC operations when one or more parameters, for example, one or more of the coefficients of the horizontal and vertical vectors or the shared matrix, is negative or equal to zero. Circuit 900, for example, comprises a sequence of circuit blocks 902, 904, and 906, and another sequence of circuit blocks 908, 910, and 912. Sequences 902, 904, and 906, and 908, 910, and 912 are each configured to perform the MAC operation as described in relation to Figure 3. For example, each coefficient of the horizontal and vertical vectors and each coefficient of the shared matrix is ​​decomposed into a positive and a negative part. For example, each coefficient for Ii ≥ 2 and 1^k < 3 is such that where and hk~ are positive values. Similarly, each coefficient y*, for nor J

[0129]

[0130]

[0131]

[0132]

[0133]

[0134]

[0135]

[0136] 1 < j < 2 and 1 ^k 3, is such that where and are positive values. JJ j JJ Again, in a similar way, each coefficient siJ of the matrix S is such that 1 / Sij = 1 / ¾ ^¾ where Sq and sij are positive values. Circuit blocks 802 and 908 are configured to generate voltage values ​​Val+, Va2+ and Val, Va2 respectively. The voltage values ​​Val+ and Va2+ are supplied to circuit block 904 and the voltage values ​​Val and Va2 are supplied to circuit block 910. Circuit blocks 904 and 910 are configured to generate currents Ib / , Ib2+ and Ibf and Ib2 respectively. Currents Ib / and Ib2+ are supplied to the circuit block 906 and the currents Ibf and Ib2 are supplied to the circuit block 912. Circuit blocks 906 and 912 are configured to generate voltage values ​​Vcl+, Vc2+ and Vcl, Vc2 respectively, such that Vcl = Vc\+ - Vcl and Vc2 = Vc2+ -Vcl. The subtraction performed to obtain the voltages Vci and Vc2 is, for example, carried out in the digital domain after the analog signals Vcl+, Vcl, Vc2+, and Vc2 have been converted into digital signals, for example, by an analog-to-digital converter. In another example, the subtraction is performed using a current subtractor circuit. Current subtractor circuits are known to the person in the trade and include, for example, two current mirrors. Embodiments have been described in which output components of a selected model are calculated in parallel. By modifying the calculation order and transposing the network, it is possible to parallelize the calculation of a single output component for all models, which will now be described in more detail in relationship with figures 10 and 11. Figure 10 represents an example of prediction calculations for a rendered computation parallel of the same output component for a plurality of models and by example for all K supported models. For example, a selection line (VI1, VI2) allows the selection of an output component so that the component the selected output is calculated for all models in a parallel manner. For example, as shown in Figure 10, the output components jd, j2 cj corresponding to the output component yi for each of the three models are for example, calculated in parallel by activating the VI1 selection line. The output components y^, y^ and j|, corresponding to the output component y2 for each of the three models, for example, are calculated in parallel by activating the VI2 selection line. Figure 11 is another schematic representation of an 1100 analog circuit configured to perform multiplication and accumulation operations. In particular, representation 1100 represents an example of an implementation mode of parallel calculation of an output component for all models as described in relation to [Fig. 10].

[0137] Representation 1100 includes circuit blocks 1102, 1104, and 1106. Circuit blocks 1102 and 1106 are, for example, multiplier circuits configured to provide output voltage values ​​based on input currents. Circuit block 1104 is, for example, a cross-branch network configured to provide output currents based on voltage inputs.

[0138] The circuit block 1102 is, for example, configured to receive, via two input lines, currents F and I2 encoding the input data values ​​xi and x2, respectively. The currents F and I2 are, for example, supplied by the control circuit 1110. In particular, the control circuit 1110 receives, for example, the input data values ​​Xi and x2, for example, in the form of digital signals, and generates the currents F and I2 based on the input data values ​​xi and x2, for example, using a digital-to-analog converter (DAC). The control circuit 1110 also receives, for example, a clock signal CLK.

[0139] Circuit blocks 1102 and 1106 are, for example, configured to receive the select line control signals (VI1, VI2) generated by the control circuit and used to select the output component to be generated. For example, signals VI1 and VI2 are two voltages, one connected to Vdd and the other to ground. Furthermore, the select line configuration is fixed for a cycle of operations performed by the sequence of circuit blocks 1102, 1104, and 1106. In other words, to calculate an output component in parallel for each model, the select line configuration does not change until the end of the operation performed by blocks 1102, 1104, and 1106. The configuration changes when another output component needs to be calculated.

[0140] The circuit block 1102 is configured to generate output voltages Vai and Va2 based on the select line control signals. In particular, the circuit block 1102 is configured to receive the two voltages VI1 and VI2, one of which is deactivated, for example by being connected to the ground voltage, and the other of which is activated, for example by being connected to the supply voltage Vdd.

[0141] The circuit block 1102 further includes a resistive element (not shown in Figure 11) encoding the coefficients of the shared matrix S. Moreover, when VI1 is on and VI2 is off, the circuit block 1102 is configured to generate the voltage Vai encoding the value $U x$ and to generate the voltage Va2 encoding the value $1.2 x^2$. When VI1 is off and VI2 is on, the circuit block 1102 is configured to generate the voltage Vai encoding the value • $2.1 x and to generate the voltage Va2 encoding the value $2.2 x x2.

[0142] For example, circuit block 1102 is a multiplier circuit having an architecture similar to multiplier circuit 400. In particular, a person skilled in the art will understand how to adapt circuit 400 to perform the multiplication carried out by circuit block 1102.

[0143] Circuit block 1104 receives, for example, an EN activation signal from control circuit 1110 and is configured to perform MAC operations based on horizontal vectors Vk, 1 - k < 3. Circuit block 1104 receives as inputs the voltages Vai and Va2 from circuit block 1102. Circuit block 1104 includes, for example, resistive elements (not shown in Figure 11) encoding the coefficients ]y1 i <2 and l <k < 3. Le bloc de circuit 1104 est par exemple configuré pour fournir en sortie des courants Ibi, Ib2 et Ib3. Par exemple, lorsque VI1 est activée, et que VI2 est désactivée, les courants Ibj, Ib2 et Ib3 codent respectivement les valeurs x S] j X X] + x s12 x x2’ h} x Sy x X] + hl x S y x x2 et hl X S y x Xj + x Sy x x2 Par ailleurs, lorsque VI1 est désactivée, et que VI2 est activée, les courants Ibi, Ib2 et Ib3 codent respectivement les valeurs x t x x, + h\ x x x2’ h\ x s2j X Xj + x s2 2 x x2 et X s2 i X Xj + h2 X s2 ? X Xv This selection is based on the voltages Vai and Va2 supplied by the circuit block 1102 and, therefore, the circuit block 1104 does not receive, for example, the voltages VI1 and VI2.

[0144] For example, circuit block 1104 is a cross-branch networked circuit having an architecture similar to that of cross-branch networked circuit 500. A person skilled in the art will understand how to adapt circuit 500 to implement the MAC operations performed by circuit block 1104.

[0145] Circuit block 1106 is, for example, configured to receive the current values ​​Ib1, Ib2, and Ib3 from circuit block 1104 and to generate the voltages Vc1, Vc2, and Vc3 based on the activated signal VI. In particular, depending on which VI selection line is activated, the three voltages Vc1, Vc2, and Vc3 correspond to one of the first output components for the three models or to the second output components for the three models. Circuit block 1106 includes, for example, resistive elements (not shown in Figure 11) encoding the coefficients l < js2 and 1k < 3. Circuit block 1106 is, for example, configured, when VI1 is activated and VI2 is deactivated, to perform, in parallel for each l <k < 3, la multiplication entre Ibk et Le bloc de circuit 1106 est également par configured example, when VI1 is enabled and Vl2 is disabled, to perform, in parallel for each 1 k < 3, the multiplication between Ibk and v2-

[0146] According to the configuration of the selection line signals VI1 and VI2, the sequence of circuit blocks 1102, 1104 and 1106 is configured to generate an output voltage encoding the output values ​​y^, 1 k <, 3. For example, circuit block 1106 is connected to an analog-to-digital converter 1112 (ADC) configured to convert the output voltages Vci and Vc2 into the output voltage values ​​y], yj ety? in the digital domain.

[0147] For example, circuit block 1106 is a vector multiplier circuit having an architecture similar to vector multiplier circuit 400 in Figures 4A and 4B. In particular, a person skilled in the art will understand how to adapt circuit 400 to perform the multiplication carried out by circuit block 1106.

[0148] In the general case of K models and n input data, circuit block 1102 is, for example, implemented by a multiplier circuit comprising n subcircuits, each subcircuit comprising n conductive lines, each with a resistive element. Each i-th conductive line of the subcircuits is supplied by an i-th voltage source, and the i-th conductive line of the j-th subcircuit is configured to perform the multiplication between the coefficient on the i-th row and the j-th column of the matrix shared with the j-th component of the input data. Alternatively, circuit block 1104 is, for example, implemented by a cross-branch network circuit comprising K conductive lines, each connected to n resistive elements.The 1106 circuit block is, for example, implemented by another vector multiplier circuit, comprising, for example, a number K of subcircuits, each of the subcircuits comprising a number n of conductive lines comprising a resistive element, each i-th conductive line of the subcircuits being supplied by the i-th voltage source, the i-th conductive line of the k-th subcircuit being configured to perform the multiplication between the i-th component of the k-th vertical vector and a value encoded by the current on the k-th conductive line of the cross-branch circuit.

[0149] In operation, during inference based on input data values ​​Xi and x2, the circuit 1100 of Figure 11 is made to operate for a number of cycles equal to the number of output components to be generated, which may be one or more. During each cycle, the control voltages VI1, VI2 and the input data values ​​Xi and x2 are, for example, held constant for a stabilization time to allow the output values ​​yl, y? and y^ output to stabilize at their final levels before the start of the next cycle.

[0150] An advantage of the embodiment shown in Figures 10 and 11 is that it allows the calculation of an output component of all models, for example, to determine the prediction and uncertainty provided as output by a neuron in a neural network. For example, this can be useful for applications such as object detection in an image.

[0151] The example circuits 300, 900 and 1100 are further capable of implementing multi-layer variants. In these variants, the output voltages are converted into currents, for example by applying the voltage across a resistor or a memristor, and copying these currents as inputs to the subsequent layers.

[0152] Figure 12A is a graph illustrating an example of the probability density (HCS) of conductance levels (CONDUCTANCE) in pS of a resistive OxRAM memory element. In particular, Figure 12A illustrates a cycle-to-cycle variation of the conductance for a single SET programming current. In a deterministic neural network, the conductance variations represented in Figure 12A can be a drawback. However, in Bayesian inference using a Markov chain Monte Carlo (MCMC) approach or variation inference, such randomness of the device conductance can be exploited. For example, the exploitation of the randomness of the conductance of an OxRAM device based on a Metropolis-Hastings MCMC is described in more detail in the publication by T. Dalgaty et al. entitled “In situ learning using intrinsic memristor variability via Markov chain Monte Carlo sampling.” Nature Electronics 4.2 (2021): 151-161.

[0153] For example, one embodiment of the present description involves the use of MCM-based machine learning to determine model parameters and, in particular, the values, for example, of the elements of the shared matrix S and of the horizontal and vertical vectors Hk, Vk.

[0154] Figure 12B is a flowchart illustrating a method for learning an analog multiplier circuit, for example, the 300 circuit of Figure 3, the 900 circuit of Figure 9, or the 1100 circuit of Figure 11, according to an embodiment of this description. In particular, Figure 12B illustrates a learning method using, for example, an MCMC method, described in relation to Figure 12A, where the analog circuit, and in particular the resistive elements, are implemented using OxRAM devices. In particular, the method described in relation to Figure 13A is an example of an on-chip implementation of the Metropolis-Hastings algorithm using OxRAM devices.

[0155] In this example, the shared matrix S is already determined. For example, the shared matrix S has been trained using a learning protocol of transfer. Only the K horizontal vectors and the K vertical vectors are trained using the process described in relation to Figure 12A. The set of K vertical vectors is then designated as a matrix V of size n x K, where each column of the matrix V designates a vertical vector. In other words, for each 0 <k <K-1, V[:;k-1] représente le vecteur vertical Vk. De façon similaire, l’ensemble des K vecteurs horizontaux est ensuite désigné comme étant une matrice H de taille K x n, où chaque ligne de la matrice H désigne un vecteur horizontal. En d’autres termes, pour chaque 0 < k < K -1, H[k-1;:] représente le vecteur vertical Hk.

[0156] The steps of the process in [Fig. 12B] are for example implemented by the control circuit 310 of the analog circuit 300 of [Fig.3], or by a similar circuit of the analog circuits of Figures 9 or 11.

[0157] For example, in a step 1200 (INITIALIZATION j=0), an index value j is set to an initial value, for example 0.

[0158] In a step 1201 (PROGRAM S), the shared matrix S is for example programmed into the analog circuit.

[0159] In a step 1202 (RDN V[0;:] AND H[:,0]), the resistive elements corresponding to the first row of matrix V and the first column of matrix H are programmed, for example with randomly generated values. The programmed currents follow, for example, a Gaussian distribution, the mean of which is determined by the programming current.

[0160] In a step 1203 (READ iv[j;:] AND ih[:;j]), the currents flowing in the resistive elements corresponding to the j-th row of the matrix V and the j-th column of the matrix H are read for example.

[0161] In a step 1204 (COMPUTE Vgs_v[:] AND Vgs_h[:]), a programming parameter is calculated, for example, for the j-th row and for the j-th column, respectively, of the matrices V and H. For example, the programming parameter is the gate-source voltage (Vgs). For example, the programming parameter is calculated based on an equation relating the conductance of the resistive element as a function of the gate-source voltage Vgs and / or by using a lookup table.

[0162] In a step 1205 (PROGRAM V[j+1;:] AND H[:,j+1]), the programming parameter calculated in step 1204 is used, for example, to program the resistive elements corresponding to the j+l-th row of matrix V and the j+l-th column of matrix H. For example, the programming parameter is used such that the resistive elements corresponding to the j+l-th row of matrix V and the j+l-th column of matrix V are respectively distributed following a Gaussian distribution centered around the values ​​V[j,:] and H[:;j].

[0163] In a step 1206 (COMPUTE ACCEPTANCE RATIO R), forward propagation is for example performed on V[j+1,: ] and H[:, j+1]. An acceptance rate value is calculated, for example, using a logarithmic likelihood ratio and logarithmic probability. A forward propagation method is described in more detail, for example, in the publication by T. Dalgaty et al. entitled "In-situ learning using intrinsic memristor variability via Markov chain Monte Carlo sampling." Nature Electronics 4.2 (2021): 151-161.

[0164] In a step 1207 (IF R>U(0,l) THEN j++), the acceptance rate value is compared, for example, to a random value, sampled, for example, on the basis of a uniform distribution U(0,l). If the acceptance rate value is greater than the random value, the index value is incremented at j+1 and the process continues, for example, at step 1203. If the acceptance rate value is less than the random sample, then the index remains the same and the process continues, for example, at step 1205. The process ends, for example, at step 1207 when the index value is equal to n-1.

[0165] Figure 13A is a graph representing an example of the SGLD (Stochastic Gradient Langevin Dynamics) algorithm, which involves random sampling. In particular, this algorithm is a type of Markov Chain Monte Carlo (MCMC) sampling approach widely applied in machine learning. It is a probabilistic alternative to approaches involving fully gradient-based learning of maximum probability models.

[0166] According to gradient-based learning, the algorithm is based on a loss function, and the goal is to determine an optimal model that minimizes losses. A major drawback of loss-based approaches is that, in the case of low-precision model parameters or parameter updates, the algorithm may not converge to the optimal model. This is often the case during learning using a resistive memory-based model.

[0167] In contrast, according to MCMC learning, the goal is to estimate the probability density of a posterior distribution. In particular, as shown in [Fig. 13A], MCMC learning is based on determining an approximation of the posterior distribution of the probability density of model 0. To do this, starting from an initial model, a chain of random samples is generated using localized random jumps guided by the Langevin gradient. [Fig. 13A] shows an example of a first random sampling operation in which a calculated weight gradient is added to the initial model and the weighted sample corresponds to a Random sampling around the new model (NEW MODEL). This process is repeated, for example based on an update equation of the SGLD algorithm, until a posterior approximation of the posterior distribution 1202 has been generated. In some cases, the approximation is further aided by rejection steps according to the modified Metropolis Langevin Algorithm (MALA).

[0168] One advantage of the approach represented by [Fig.13A] is that the resulting posterior approximation can be used to make accurate predictions, especially with a small amount of training noise data, in addition to providing well-calibrated uncertainty estimates related to these predictions.

[0169] Figure 13B is a flowchart representing a method for learning an analog circuit, such as circuit 300 of Figure 3, circuit 900 of Figure 9, or circuit 1100 of Figure 11, according to another embodiment of the present description. In particular, Figure 13B represents a learning method using, for example, a Langevin gradient method, described in relation to Figure 13A, where the analog circuit and, in particular, the resistive elements are implemented using a wall-mounted device in the magnetic domain. Wall-mounted devices in the magnetic domain are, for example, described in more detail in the publications: Kumar, Durgesh, et al. "Domain wall memory: Physics, materials, and devices." Physics Reports 958 (2022): 1-35; and Sbiaa, R., and SN Piramanayagam "Multi-level domain wall memory in constricted magnetic nanowires." Applied Physics A 114 (2014): 1347-1351.The method described in relation to [Fig. 13B] is an example of an on-chip implementation of a stochastic gradient Langevin dynamics on a walled device in the magnetic domain.

[0170] In a step 1300 (INITIALIZATION j=0, C) an index value j is set to an initial value, for example 0 and a down-cnt count value is set to a value C.

[0171] In a step 1301 (PROGRAM S), the shared matrix S is programmed into the analog circuit. For example, as in the process described in relation to [Fig. 12B], the shared matrix S has undergone training, for example using a transfer learning protocol.

[0172] A step 1302 (RDN V[0;:] AND H[:,0]) is similar to step 1202. The resistive elements corresponding to the first row of the matrix V and the first column of the matrix H are programmed, for example, with randomly generated values. The conductance values ​​of the resistive elements are, for example, programmed by applying pulses of random pulse widths to the resistive elements.

[0173] In a step 1303 (CALIBRATE), the count value is, for example, compared to a minimum value, for example 0. If the count value is equal to the minimum value, then calibration is performed. Calibration involves, for example, the programming the j+l-th row of matrix V and the j+l-th column of matrix H so that they correspond to the j+l-th row of matrix V and the j+l-th column of matrix H to within a minimal tolerated error.

[0174] In a step 1304 (FORWARD), the data is applied to the circuit 1100, for example in the form of input currents corresponding to the input data. The jth vectors of the V and H matrices are selected by generating a voltage output in the final circuit block. These output voltages correspond to output predictions of a single layer or, if several layers are chained together, of the output of a network. These outputs are, for example, compared to target values ​​and a Langevin gradient is calculated.

[0175] In a step 1305 (LANGEVIN GRAD), the Langevin gradient associated with the j-th row of the matrix V and the j-th column of the matrix H is calculated, for example. The implementation of this step is described, for example, in the publication by T. Dalgaty et al. entitled "Scaling-up Memristor Monte Carlo with magnetic domain-wall physics," Machine Learning with New Compute Paradigms, 2023.

[0176] The conductance values ​​of the j-th row of the V matrix and the j-th column of the H matrix are updated using each Langevin gradient calculated in step 1305. The conductance values ​​are further updated, for example, based on an additional noise term. This update includes, for example, the calculation, in a step 1306 (PUSH AND PULL), of two pulse widths for each j-th row of the V matrix and j-th column of the H matrix. For example, first pulses Tvpush and Thpush displace or "push" the domain wall in a first direction. Second pulses Tvpull and Thpull displace or "pull" the domain wall in the opposite direction.

[0177] In a step 1306 (APPLY PUSH), pulses of pulse widths Tvpush and Thpush are respectively applied to the j-th row of matrix V and to the j-th column of matrix H.

[0178] In a step 1307 (APPLY PULL), pulses of pulse widths Tvpull and Thpull are respectively applied to the j-th row of matrix V and to the j-th column of matrix H.

[0179] In a step 1309 (C—), the count value is decremented and the process resumes at step 1303. In the case where the count value is equal to 0, then a new loop begins with a new execution of step 1300, in which the index value j is incremented and the count value is reset to its original value.

[0180] In other examples, the shared matrix S undergoes training at the same time as the vertical vectors Vk and the horizontal vector Hk.

[0181] One advantage of the embodiments described herein is that performing the BatchEnsemble computation saves the required memory space by using the shared matrix. Another advantage of the embodiments described herein is that the complete hardware implementation of the MAC operations speeds up the execution of MAC operations associated with a plurality of models and reduces energy consumption.

[0182] Another advantage of the embodiments described in this description is that neural network learning can be implemented on a chip, directly by the analog circuit.

[0183] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to those skilled in the art. For example, although some embodiments have been described using NMOS or PMOS transistors, it will become apparent to those skilled in the art that the various circuits could be adapted to replace some or all of the PMOS transistors with NMOS transistors, or vice versa. Furthermore, the type of transistors implemented in the cross-branch network circuits and / or in the multiplier circuit may vary. For example, MOS transistors could be replaced by other types of transistors in the cross-branch network circuits and / or in the multiplier circuits.

[0184] Finally, the practical implementation of the described embodiments and variants is within the grasp of a person skilled in the art, based on the functional indications given above. For example, it will be apparent to a person skilled in the art how to adapt the implementations to different numbers of models and different data sizes. In particular, a person skilled in the art will know how to adapt the described circuit to the general case of K models, where the input and output data, the vertical and horizontal vectors are of size n and m, and the shared matrix is ​​of size n x m.

Claims

Demands

1. An analog vector multiplier circuit comprising a first circuit (400, 600, 810_l) for implementing a first multiplication of a first or second value with a third value, the first circuit comprising: - a first branch (402_l, 602_l, 812_l) comprising the series connection of a first programmable resistive element and a first transistor, the first programmable resistive element being programmed to have a first resistance representative of the first value yi^1); - a second branch (402_l, 602_l, 812_l) comprising the series connection of a second programmable resistive element and a second transistor, the second programmable resistive element being programmed to have a second resistance representative of the second value y2 $2); - a control circuit (310, 1110) configured to control the first and second transistors to select the first or second branch;and - a first current mirror (410, 610, 810) configured to apply a current (Ib I2) generated on the basis of the third value (v ■”. ) to the branch selected by the control circuit in order to generate, across the terminals of the selected branch, a first voltage - VP proportional to the result of the first multiplication.;

2. An analog vector multiplier circuit according to claim 1, further comprising a second circuit (400', 600', 810_2) for implementing, in parallel with the first multiplication, a second multiplication of a fourth or fifth value with a sixth value, the second circuit comprising: - a third branch (402'_1, 602'_1, 812_21) comprising the series connection of a third programmable resistive element and a third transistor, the third programmable resistive element being programmed to have a third resistance representative of the fourth value (^ y| ÿi); - a fourth branch (402'_2, 602'_2, 812_22) comprising the series connection of a fourth programmable resistive element and a fourth transistor, the fourth resistive element programmable being programmed to have a fourth resistance representative of the fifth value, (^2 gï) in which the control circuit (310, 1110) is configured to control the third and fourth transistors to select the third or fourth branch; - a second current mirror (410', 610', 810') configured to apply a current (Ib I2) generated on the basis of the sixth value to the branch of the second circuit selected by the control circuit in order to generate, across the terminals of the selected branch, a second voltage (y) proportional to the result of the second multiplication.

3. Neural network comprising the analog vector multiplier circuit according to claim 1 or 2.

4. Neural network according to claim 3, further comprising a first cross-branch network circuit (500, 800) configured to provide at output one or more second current values ​​by implementing one or more multiplication and / or accumulation operations on the basis of at least the first voltage ^y).

5. Neural network according to claim 4, further comprising an additional vector multiplier analog circuit (600) configured to generate one or more output voltages (V p Vc?) by implementing one or more multiplication operations on the basis of one or more second current values.

6. Neural network according to claim 5, further comprising: - a first voltage replication circuit configured to replicate the first voltage (Vaj) generated by the first circuit and provide the replicated voltage to the cross-branch circuit, the first voltage replication circuit comprising an operational amplifier.

7. A neural network according to any one of claims 4 to 6, wherein the third and sixth values ​​are components of an input vector of size n, n being an integer, the circuit being further configured to perform a number K of sequences of accumulation and multiplication operations, K being a number integer representing a number of models implemented by the neural network.

8. Neural network according to any one of claims 4 to 7, wherein: - the analog vector multiplier circuit comprises a number Kxn of resistive elements programmed to the coefficient values ​​of K horizontal vectors of size n; - the cross-branch circuit comprises nxn resistive elements programmed to the inverse values ​​of coefficients of a shared matrix (S) of size nxn.

9. Neural network according to claim 5 or according to any one of claims 6 to 8 in their dependence on claim 5, wherein: - the additional vector multiplier analog circuit comprises a number Kxn of resistive elements programmed to the coefficient values ​​of K vertical vectors of size n.

10. Neural network according to claim 5 or according to any one of claims 6 to 8 in their dependence on claim 5, wherein: - the analog vector multiplier circuit comprises an nxn number of resistive elements programmed to the inverse values ​​of coefficients of a shared matrix of size nxn; - the cross-branch circuit comprises a Kxn number of resistive elements programmed to the coefficient values ​​of K horizontal vectors of size n; and - the additional analog vector multiplier circuit comprises a Kxn number of resistive elements programmed to the inverse values ​​of coefficients of K vertical vectors of size n.

11. A neural network according to claim 10 in its dependence on claim 7, configured to generate, for each model k among the K models implemented by the neural network, n output voltages (yyj) corresponding to n output values ​​j*1 < i <H-vérifiant l’équation suivante : yk y* x ( X X „ + h* X Xn X SiA ) ’ où 1 j , est la valeur du j-ième coefficient du k-ième vecteur horizontal 1 j n, sij est la valeur des i-ième ligne et j-th column of the shared matrix and xj, 1< j < n, is the j-th component of the input vector.

12. Neural network according to any one of claims 3 to 11, wherein the neural network is configured to perform classification operations.

13. Method of implementing, by a first circuit (400, 600, 810_l) of an analog vector multiplier circuit, a first multiplication of a first or second value by a third value, the method comprising: - programming a first programmable resistive element so that it has a first resistance representative of the first value pi ^p, the first programmable resistive element being connected in series with a first transistor in a first branch (402_l, 602_l, 812_11) of the first circuit; - programming a second programmable resistive element so that it has a second resistance representative of the second value y2 ^2), the second programmable resistive element being connected in series with a second transistor in a second branch (402_2, 602_2, 812_12) of the first circuit;- the control, by a control circuit (310, 1110), of the first and second transistors to select the first or second branch; and - the application, by a first current mirror (410, 610, 810), of a current (h, I2) generated on the basis of the third value to the branch selected by the control circuit in order to generate, across the terminals of the selected branch, a first voltage (VP proportional to the result of the first multiplication proportional to the result of the first multiplication.;

14. Method according to claim 13, further comprising the conversion, by an analog-to-digital converter, of the first voltage (Val) into a digital value.

15. A method according to claim 13 or 14, wherein the second and third values ​​are values ​​of an image.

16. A method for learning the neural network according to any one of claims 13 to 15, comprising determining first and second values ​​using a Markov Chain Monte Carlo (MCMC) learning approach.

17. A method according to claim 16, wherein the analog vector multiplier circuit comprises OxRAM devices and the Markov Chain Monte Carlo (MCMC) learning approach comprises an application of a Metropolis-Hastings algorithm.

18. A method according to claim 16, wherein the analog vector multiplier circuit comprises magnetic domain wall devices and the Markov chain Monte Carlo learning approach comprises an application of stochastic Langevin gradient dynamics.