Starting circuit of a bandgap reference voltage generation circuit

Abstract

Starting Circuit for a Band-Gap Reference Voltage Generation Circuit. This description concerns a starting circuit (420) for a band-gap reference voltage generation circuit (110) whose current mirror comprises a first MOS transistor (MP2), including: a second transistor (MNR) and a third transistor (MNP) in current mirror configuration whose control terminals are connected by a first resistor (ROFF); and a fourth MOS transistor (MP1) between a supply voltage application terminal (Vcc) and a control terminal (NB) of the second transistor (MNR), the fourth MOS transistor (MP1) being mounted in current mirror configuration with the first MOS transistor (MP2). Figure for the abbreviation: Fig. 4

Description

Title of the invention: Starting circuit for a bandgap reference voltage generation circuit. Technical field

[0001] This description relates generally to the starting circuits of bandgap reference voltage generation circuits and their associated operating methods. Previous technique

[0002] Many known electronic devices include a bandgap reference voltage generation circuit configured to generate a reference voltage that does not vary globally with temperature.

[0003] These devices require a starting circuit which will allow them to operate according to a preferred operating point.

[0004] Current starting circuits have various disadvantages. Summary of the invention

[0005] There is a need to improve the starting circuits of the bandgap reference voltage generation circuits.

[0006] One embodiment overcomes all or part of the drawbacks of known starting circuits.

[0007] One embodiment provides a starting circuit for a bandgap reference voltage generation circuit, the current mirror of which includes a first MOS transistor, comprising: a second transistor and a third current-mirror transistor whose control terminals are connected by a first resistor; and a fourth MOS transistor between a supply voltage application terminal and a control terminal of the second transistor, the fourth MOS transistor being mounted in current mirror to the first MOS transistor.

[0008] One embodiment provides a method for starting a bandgap reference voltage generation circuit, the current mirror of which includes a first MOS transistor, the method comprising disconnecting a starting circuit from the generation circuit, having: a second transistor and a third current mirror transistor whose control terminals are connected by a first resistor, and a fourth MOS transistor between a supply voltage application terminal and a control terminal of the second transistor, the fourth MOS transistor being mounted in current mirror to the first MOS transistor; by switching on the fourth transistor.

[0009] In one embodiment, a current source connects: the terminal applying a supply voltage to the control terminal of the third transistor and, the terminal for applying a supply voltage to a conduction node of the second transistor.

[0010] In one embodiment, the second transistor connects the control terminal of the third transistor to ground via a second resistor.

[0011] In one embodiment, the size of the third transistor is at least N times greater than that of the second transistor, N being between 2 inclusive and 10 inclusive.

[0012] In one embodiment, the second and third transistors are of the NMOS type, and the fourth transistor is of the PMOS type.

[0013] In one embodiment, the second and third transistors are of the bipolar type and the fourth transistor is of the PMOS type.

[0014] One embodiment provides a bandgap reference voltage generation device, comprising the starting circuit described above, and a bandgap reference voltage generation circuit comprising: a first branch having the first transistor in series with a fifth bipolar transistor; and a third resistor, connected to ground, in series with a fourth resistor connected to the emitter of the fifth transistor; the second resistor being configured to receive a voltage proportional to the absolute temperature between its terminals, and the third resistor being configured to receive a voltage complementary to the absolute temperature between its terminals.

[0015] In one embodiment: The fourth MOS transistor has a control terminal connected to a control terminal of the first transistor; and the third transistor connects, a midpoint of the first and fifth transistors, to a midpoint of the third and fourth resistors of the generation circuit.

[0016] In one embodiment, the generation circuit includes a second branch having a sixth transistor in series with a seventh bipolar transistor, the control terminals of the fifth and seventh transistors being connected together at a first node, and the control terminals of the first, fourth and sixth transistors being connected together.

[0017] In one embodiment, the midpoint of the sixth and seventh transistors is connected to the control terminals of the first, fourth and sixth transistors.

[0018] In one embodiment, the generation circuit includes a third branch having: an eighth transistor connecting the supply voltage application terminal to an output node of the generation circuit, the control terminal of the eighth transistor being connected to the midpoint of the first and fifth transistors; a fifth resistance connecting the first node to ground; and a sixth resistance connecting the output node to the first node.

[0019] In one embodiment, a capacitor connects the midpoint of the first and fifth transistors and the output node.

[0020] In one embodiment, the first, sixth and eighth transistors are of the PMOS type.

[0021] In one embodiment, the second resistance has a value equal to the value of the third resistance multiplied by N.

[0022] In one embodiment, the size of the fifth transistor is at least M times greater than that of the seventh transistor, M being between 2 inclusive and 10 inclusive.

[0023] One embodiment provides a method of using the device described above, comprising starting the generation circuit using the starting circuit and then stopping the starting circuit. Brief description of the drawings

[0024] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0025] [Fig.1] represents a device for generating a band gap reference voltage;

[0026] [Fig.2] represents a block of the device of [Fig.1];

[0027] [Fig. 3] represents a block of the device of [Fig. 1]; and

[0028] [Fig.4] represents a block of the device of [Fig.1]. Description of the implementation methods

[0029] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0030] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been represented and are detailed.

[0031] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") together, this means that these two elements can be connected or linked through one or more other elements.

[0032] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0033] Unless otherwise specified, the expressions "approximately", "about", "Sensibly" and "on the order of" mean to within 10% or 10°, preferably to within 5% or 5°.

[0034] Fig. 1 represents a band gap reference voltage generation device 100.

[0035] The device 100 includes a starting circuit 120 connected to a generation circuit 110 of a bandgap reference voltage.

[0036] In the example shown, the starting circuit 120 is connected, preferably connected, to an application terminal of a voltage Vcc as well as to ground.

[0037] In the example shown, the generation circuit 110 includes a first branch 102 having a transistor MP2 in series with a transistor Q1, which is bipolar, for example, of the NPN type. The transistor MP2 connects the supply voltage application terminal Vcc to the receiver of the transistor Q1. The first branch 102 also includes a resistor R2 that connects ground to a node NT. The resistor R2 is in series with a resistor RI connecting the node NT to the emitter of the transistor Q1. In one example, the resistor RI is between 1 kΩ and 10 kΩ, for example 3 kΩ, and the resistor R2 is between 1 kΩ and 20 kΩ.

[0038] In the example shown, the generation circuit 110 includes a second branch 103 having a transistor MP3, for example PMOS, in series with a bipolar transistor Q2. The control terminals of transistors Q1 and Q2 are connected, preferably connected, together and to a node N3. The emitter of transistor Q2 is connected, preferably connected, to node N1. The control terminals of transistors MP2 and MP3 are connected, preferably connected, together and to a node N4. In one example, node N4 is also connected, preferably connected, to the midpoint of transistors MP3 and Q2.

[0039] The MP2 and MP3 transistors are thus mounted in current mirror.

[0040] In one example, the size of transistor Ql is at least M times greater than that of the transistor Q2, where M is between 2 and 10 inclusive. In the text, the size of a bipolar transistor is, for example, the area of ​​its base. It is possible to obtain a transistor size M times larger by connecting M transistors in parallel.

[0041] In the example shown, the generation circuit 110 further includes a third branch 104. The third branch 104 includes a transistor MP4 connecting the supply voltage application terminal Vcc to an output node NOUT of the Generation circuit 110. The control terminal of transistor MP4 is connected to the midpoint N2 of transistors MP2 and Q1. The third branch 104 further includes a resistor R4 connecting node N3 to ground and a resistor R3 connecting the output node NOUT to node N3.

[0042] In one example, a capacitor Ce connects the midpoint N2 of transistors MP2 and Q1 and the output node NOUT. This capacitor is intended to stabilize the loop.

[0043] In the example shown, the generation circuit 110 optionally includes a transistor MP5 whose control terminal is connected, preferably connected, to the control terminals of transistors MP2 and MP3 so as to form a current mirror. The transistor MP5 connects the voltage application terminal Vcc to a node N5 on which the output current of device 100 can be measured.

[0044] In [Fig.1], transistors MP2, MP3, MP4 and MP5 are of the PMOS type.

[0045] By appropriately choosing the ratio of resistances R2 and RI, resistance R2 The resistor can be configured to receive a voltage Vptat proportional to the absolute temperature between its terminals, and the resistor RI is configured to receive a voltage Vctat that is complementary to the absolute temperature between its terminals. This results, as a first approximation, in a temperature-independent voltage at node N3 that is approximately equal to the silicon band gap, or 1.26 V. Resistors R3 and R4 then act as a voltage divider to obtain a reference voltage at the output node NOUT.

[0046] The generation circuit 110 includes two stable operating points. One of these operating points results in zero current at the output node NOUT. The starting circuit 120 avoids this operating point by temporarily grounding the control terminal of transistor MP4 to allow the generation circuit 110 to operate with its rated current.

[0047] [Fig.2] represents a block of the device of [Fig.1]. More particularly, [Fig.2] represents an example of a starting circuit 220.

[0048] The starting circuit 220 shown includes a current source 222 connecting the supply voltage application terminal Vcc to a node N20. A transistor MN1, for example of the NMOS type, connects the node N20 to ground.

[0049] The starting circuit 220 further includes a transistor MP21, for example of the PMOS type, connecting the supply voltage application terminal Vcc to a node N21. The control terminal of the transistor MP21 is connected, preferably connected, to the control terminal of the transistor MP2 of the generation circuit 110 so as to form a current mirror.

[0050] The starting circuit 220 also includes a transistor MN2, for example of the NMOS type, connecting node N21 to ground. The control terminals of transistors MN2 and MN1 are connected, preferably connected, to each other and to node N20.

[0051] Another MPST transistor, for example of the PMOS type, connects node N2 of the generation circuit 110 to ground. The MPST transistor has a control node connected, preferably connected, to node N21.

[0052] To start, transistor MNP1 is open, i.e., not conducting. The gate-source voltage of transistor MN2 is defined by the current 10 from the current source 222 through transistor MN1. Node N21 is then grounded. The drain-source voltage of transistor MPST is reduced by a few mV, and node N2 is grounded. The gate-source voltage of transistor MP4 is thus considerably increased, which lowers the resistance between its drain and source. A significant current flows through resistors R3 and R4, which in turn increases the voltage at node N3. Since the voltage at node N3 has increased, a current can flow through transistors Q1 and Q2, which lowers the voltage at node N4. The generation circuit 110 has thus started. Transistor MP21 copies the current flowing through transistors Q1 and Q2, which is greater than the current through transistor MN2.The N21 node has a voltage that increases up to Vcc, which opens the MPST transistor. This has the effect of turning off the 220 starter circuit.

[0053] The example in [Fig.2] certainly allows the start-up of the generation circuit 110 but it results in a significant current peak, for example more than ten times the nominal current, as well as a significant transition voltage, on the N5 and NOUT nodes at start-up before the voltage stabilizes.

[0054] In addition, oscillations may appear at startup.

[0055] [Fig.3] represents a block of the device of [Fig.1]. More specifically, [Fig.3] represents an example of the starting circuit.

[0056] The starting circuit 320 shown includes a current source 322 connecting the supply voltage application terminal Vcc to a node N30. A transistor QB1, for example of the bipolar NPN or NMOS type, connects node N30 to ground. Node N30 is connected, preferably connected, to the control terminal of transistor QB1.

[0057] The starting circuit 320 further includes a transistor QB2, for example of the bipolar NPN or NMOS type, connecting the node N2 to the node NT of the generation circuit 110. The control terminals of transistors QB1 and QB2 are connected, preferably connected, to each other and to the node N30.

[0058] At startup, a current is supplied by the current source 322 to discharge the capacitance Ce of the generation circuit 110. Node N2 is thus connected to node NT (which is close to ground). The current through resistors RI and R2 increases, which induces a gradual decrease in the base-emitter voltage, resulting in a reduction of the startup current. When the generation circuit is started, the base-emitter voltage of transistor QB2 is low enough to make transistor QB2 non-conducting and no current flows through it.

[0059] The 320 starting circuit allows the current peak to be limited at startup compared with the 220 circuit.

[0060] However, the establishment time of a stable signal at the output node NOUT can reach 20 ps, ​​whereas it would be desirable to obtain stability in less than 5 ps. Indeed, when the voltage at node NT reaches a few tens of mV, transistor QB2 is pinched off, which limits its ability to discharge the gate of transistor MP4.

[0061] In order to overcome the drawbacks of the starting circuit examples in Figures 2 and 3, the embodiments provide a starting circuit for the generation circuit in which a current mirror includes a first MOS transistor, the starting circuit comprising: a second transistor and a third current-mirror transistor whose control terminals are connected by a first resistor; and a fourth MOS transistor between a supply voltage application terminal and a control terminal of the second transistor, the fourth MOS transistor being mounted in current mirror to the first MOS transistor.

[0062] This helps to limit current overloads at startup but also helps to limit the time to establish a stable signal on the NOUT output node to a time of the order of 5 ps.

[0063] Figure 4 represents a block of the device of Figure 1. More particularly, Figure 4 represents an embodiment of a starting circuit.

[0064] The starting circuit 420 shown includes a current source 422 connecting the supply voltage application terminal Vcc to a node NI. In an example not shown, the current source is outside the starting circuit. An MNR transistor, for example of the NPN or NMOS bipolar type, connects the node NI to ground.

[0065] In the example shown, the starting circuit includes an MNP transistor, for example of the NPN or NMOS bipolar type, connecting node N2 to node NT of the generation circuit 110. A resistor ROFF connects, preferably connects, the control terminals of the MNR and MNP transistors. In one example, the resistance ROFF is between 100 kΩ and 900 kΩ. Node NI is connected, preferably connected, to the control terminal of the MNP transistor.

[0066] In the example shown, the starting circuit 420 includes an MPI transistor, for example of the PMOS type, connecting the voltage application terminal Vcc to the control terminal NB of the transistor MNR. The control terminal of the MPI transistor is connected, preferably connected, to node N4 of the generation circuit 110, i.e. said connected, preferably connected, to the control terminals of transistors MP2 and MP3 so as to form a current mirror with the latter.

[0067] In an optional example, the size of the MNP transistor is at least N times larger than that of the MNR transistor, where N is between 2 and 10 inclusive. In the text, the size of a MOS transistor is, for example, the area of ​​its gate or the width-to-length ratio. It is possible, for example, to obtain a transistor size N times larger by connecting N transistors in parallel. This reduces the output voltage stabilization time.

[0068] In an optional example, transistor MNR connects node NI to ground via a resistor RB. In one example, the resistor RB has a value such that the voltage drop is the same as across node NT. In another example, the resistor RB has a value equal to the value of resistor R2 multiplied by N. This prevents the voltage between nodes NI and NT from dropping too rapidly during startup. The current is then N times greater than in the example in [Fig. 3]. This reduces the output voltage stabilization time. In one example, the resistor RB is between 0 ohms and 900 kohms.

[0069] The start-up of the starting circuit 420 is, for example, broadly similar to that of [Fig. 3], except that, for the disconnection of the starting circuit, the MPI transistor copies the current and injects the current into the ROFF resistor, which consequently reduces the voltage present on the control terminal of the MNP transistor by several hundred mV, for example, between 100 mV and 1 V, i.e., below its threshold, thus quickly turning off the MNP transistor. The starting circuit is thus disconnected without overload and more quickly compared to the examples in Figures 2 and 3.

[0070] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to them. In particular, the MNR and MNP transistors in the example in [Fig. 4] could be bipolar transistors, for example, of the NPN type. Those skilled in the art will also be able to reverse the transistor types from NMOS to PMOS, or from NPN to PNP, and vice versa, by changing the associated voltages and arranging the circuits according to their knowledge.

[0071] Finally, the practical implementation of the described embodiments and variants is within the reach of a person skilled in the art, based on the functional specifications given above. In particular, the starting circuit 420 could be implemented by a person skilled in the art, with a generation circuit 110 different from that described in [Fig. 1]. For example, the generation circuit could be a Brokaw-type circuit, provided that it contains a current mirror that can be replicated with the transistor. MPI and that the copied current causes a voltage drop making the MNP transistor quickly non-conducting to cause the disconnection of the starting circuit.

Claims

Demands

1. Starting circuit (420) of a bandgap reference voltage generation circuit (110) having a current mirror comprising a first MOS transistor (MP2), comprising: a second transistor (MNR) and a third transistor (MNP) in current mirroring whose control terminals are connected by a first resistor (ROFF); and a fourth MOS transistor (MPI) between a supply voltage application terminal (Vcc) and a control terminal (NB) of the second transistor (MNR), the fourth MOS transistor (MPI) being mounted in current mirroring on the first MOS transistor (MP2).

2. Method of starting a bandgap reference voltage generation circuit (110) having a current mirror comprising a first MOS transistor (MP2, MP3), the method comprising disconnecting a starting circuit (420) from the generation circuit (110), having: a second transistor (MNR) and a third transistor (MNP) in current mirroring whose control terminals are connected by a first resistor (ROFF), and a fourth MOS transistor (MPI) between a supply voltage application terminal (Vcc) and a control terminal (NB) of the second transistor (MNR), the fourth MOS transistor (MPI) being mounted in current mirroring on the first MOS transistor (MP2); by turning on the fourth transistor (MPI).

3. Start-up circuit according to claim 1, or method according to claim 2, wherein a current source (10) connects: the supply voltage application terminal (Vcc) to the control terminal of the third transistor (MNP) and, the supply voltage application terminal (Vcc) to a conduction node of the second transistor (MNR).

4. Circuit according to claim 1 or 3, or method according to claim 2 or 3, wherein the second transistor (MNR) connects the control terminal of the third transistor (MNP) to ground via a second resistor (RB).

5. Circuit according to any one of claims 1 or 3 or 4, or method according to any one of claims 2 to 4, wherein the size of the third transistor (MNP) is at least N times greater than that of the second transistor (MNR), N being between 2 inclusive and 10 inclusive.

6. Circuit according to any one of claims 1 or 3 to 5, or method according to any one of claims 2 to 5, wherein the second and third transistors (MNR, MNP) are of the NMOS type, and the fourth transistor (MPI) is of the PMOS type.

7. Circuit according to any one of claims 1 or 3 to 6, or method according to any one of claims 2 to 6, wherein the second and third transistors (MNR, MNP) are of the bipolar type and the fourth transistor (MPI) is of the PMOS type.

8. A bandgap reference voltage generation device (100) comprising the starting circuit (420) according to any one of claims 1 or 3 to 7, and a bandgap reference voltage generation circuit (110) comprising: a first branch (102) having the first transistor (MP2) in series with a fifth bipolar transistor (Q1); and a third resistor (R2), connected to ground, in series with a fourth resistor (RI) connected to the emitter of the fifth transistor (QD); the second resistor (R2) being configured to receive a voltage (Vptat) proportional to the absolute temperature across its terminals, and the third resistor (RI) being configured to receive a voltage (Vctat) complementary to the absolute temperature across its terminals.

9. Device (100) according to claim 8, wherein: the fourth MOS transistor (MPI) has a control terminal connected to a control terminal of the first transistor (MP2); and the third transistor (MNP) connects, a midpoint (N2) of the first and fifth transistors (MP2, Q1), to a midpoint (NT) of the third and fourth resistors (R2, RI) of the generation circuit (110).

10. A device according to claim 8 or 9, wherein the generation circuit (110) comprises a second branch (103) having a sixth transistor (MP3) in series with a seventh bipolar transistor (Q2), the control terminals of the fifth and seventh transistors (Q1, Q2) being connected together to a first node (N3), and the control terminals of the first, fourth and sixth transistors (MP2, MPI, MP3) being connected together.

11. Device according to claim 10, wherein the midpoint (N4) of the sixth and seventh transistors (MP3, Q2) is connected to the control terminals of the first, fourth and sixth transistors (MP2, MPI, MP3).

12. Device according to claim 10 or 11, wherein the generation circuit (110) comprises a third branch (104) having: an eighth transistor (MP4) connecting the supply voltage application terminal (Vcc) to an output node (NOUT) of the generation circuit (110), the control terminal of the eighth transistor (MP4) being connected to the midpoint (N2) of the first and fifth transistors (MP2, Q1); a fifth resistor (R4) connecting the first node (N3) to ground; and a sixth resistor (R3) connecting the output node (NOUT) to the first node (N3).

13. Device according to claim 12 in its dependence on claim 9, wherein a capacitor (Ce) connects the midpoint (N2) of the first and fifth transistors (MP2, Q1) and the output node (NOUT).

14. Device according to claim 12 or 13, wherein the first, sixth and eighth transistor (MP2, MP3, MP4) are of the PMOS type.

15. Device according to any one of claims 8 to 14 in their dependence on claim 4, wherein the second resistance (RB) has a value equal to the value of the third resistance (R2) multiplied by N.

16. Device according to any one of claims 8 to 15, wherein the size of the fifth transistor (Q1) is at least M times greater than that of the seventh transistor (Q2), M being between 2 inclusive and 10 inclusive.

17. Method of using the device (100) according to any one of claims 8 to 16, comprising starting the generation circuit (110) using the starting circuit (420) and then stopping the starting circuit (420).

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