Detection of structural defects in an integrated circuit

Abstract

A system comprising an integrated circuit, including a semiconductor substrate (SB), an interconnection portion located above the substrate and having metal layers (M1-M5) and via and contact layers embedded in an electrically insulating region, as well as contact areas located at the last metal layer of the interconnection portion, and detection means configured to detect the possible presence of at least one type of structural defect (DFT1, DFT2) within at least one zone (ZD) of the interconnection portion located below at least one contact area (PD). Figure for the abstract: Fig 5

Description

Title of the invention: Detection of structural defects in an integrated circuit

[0001] Embodiments and implementation methods relate to integrated circuits, in particular the detection of structural defects in these integrated circuits, for example cracks and / or delaminations.

[0002] An integrated circuit classically comprises -a part known to those skilled in the art by the Anglo-Saxon acronym "FEOL" ("Front End Of Line" or more simply "front end") comprising the various components, such as transistors, fabricated in and on the semiconductor substrate of the integrated circuit, and -an interconnection part known to those skilled in the art by the Anglo-Saxon acronym "BEOL" ("Back End Of Line" or simply "back end") comprising a network of metallic tracks, vias between the different metal levels and contacts between the first metal level and the active areas of the substrate and / or the different components (gate regions, source and drain of transistors for example) embedded in a dielectric material and notably providing an interconnection between the components of the integrated circuit.

[0003] Integrated circuits are manufactured simultaneously on locations of a silicon wafer separated by cutting lines.

[0004] Then, once manufactured, the integrated circuits are individualized by cutting, typically by sawing, the wafer along the cutting lines.

[0005] During the sawing operation of the wafer mentioned above, cracks and / or a delamination phenomenon (i.e. a decohesion of layers) may occur in the BEOL part in particular at the periphery of the integrated circuit.

[0006] The French patent application filed by the applicant under number 2406877 describes a device comprising in particular an annular wall located on the periphery of the integrated circuit allowing the detection of cracks and / or delaminations resulting from the sawing operation mentioned above.

[0007] However, there is a constant need to further improve the detection of structural defects in an integrated circuit, in particular cracks and / or delaminations, which can allow moisture to penetrate the integrated circuit, which is detrimental to its proper functioning.

[0008] The inventor observed in this regard that such structural defects could also result from the manufacturing process of the integrated circuit itself, and in particular during the steps of soldering connecting wires (“wire bonding”) or forming balls of welds on the contact pads located at the last metal level of the interconnecting part (BEOL).

[0009] Indeed, the inventor observed that these steps at the level of these contact areas could locally create cracks and / or tearing of the structure.

[0010] According to one aspect, a system is proposed comprising -an integrated circuit, comprising a semiconductor substrate, an interconnection portion located above the substrate and having metal layers and via and contact layers embedded in an electrically insulating region, as well as contact areas located at the last metal layer of the interconnection portion, and -detection means configured to detect the possible presence of at least one type of structural defect, for example a crack and / or delamination, within at least one area of ​​the interconnecting part located at least below a contact range.

[0011] According to one embodiment, the detection means comprise an electrically conductive region located at least in said zone and a detection device configured to detect at least one electrical discontinuity in said region.

[0012] The detection device can be located within the integrated circuit.

[0013] In this respect it may for example include inverters associated with a processing unit, for example an electronic chip present in the integrated circuit.

[0014] Alternatively, the detection device may include a module external to the integrated circuit, for example a tester.

[0015] According to one variant, it is provided under the corresponding contact area, an electrically conductive path which does not come into contact with the contact area, which makes it possible, if desired, to continuously detect the appearance of a structural fault under the contact area, even when the integrated circuit is in its application operation.

[0016] More specifically, according to an embodiment of this variant, when the interconnecting part comprises N metal levels with N greater than or equal to 2, the metal level of rank 1 being the metal level closest to the substrate, the contact areas being located at the metal level of rank N, said electrically conductive region may comprise an electrically conductive path having -a first end and a second end located at the metal level of rank 1 and capable of being electrically coupled to the detection device, -a first branch extending from the first end to the metal level of rank N1, -a second branch extending from the Nl rank metal level to the second extremity, -the two branches being mutually connected at the level of Nl rank metal.

[0017] Each branch may, for example, include: -a stack of metallic portions, respectively located at metal levels from rank 1 to Nl, and vias between these metallic portions, -a metal connecting portion located at the level of metal of rank Nl connecting the two metal portions of the two branches located at the level of metal of rank Nl.

[0018] According to another embodiment of this variant, in which the interconnecting part again comprises N metal levels with N greater than or equal to 2, the first metal level being the metal level closest to the substrate, the contact areas being located at the Nth metal level, said electrically conductive region comprises a first active zone and a second active zone located in the semiconductor substrate as well as an electrically conductive path.

[0019] This electrically conductive path has: -a first end and a second end located at the level of metal of rank 1 and capable of being electrically coupled to the detection device, - a first contact connected between the first end and the first active zone, - a first branch extending from the first active zone up to the Nl rank metal level, -a second branch extending from the Nl rank metal level to the second active zone, -a second contact connected between the second active zone and the second end, -the two branches being mutually connected at the Nl rank metal level.

[0020] Such an embodiment in which the electrically conductive path does not contact the contact area but extends to the level of active areas of the substrate, allows, if desired, continuous detection of the appearance of a structural defect under the contact area, even when the integrated circuit is in its application operation, and this between the Nl rank metal level and the semiconductor substrate.

[0021] Each branch may, for example, comprise a stack of metallic portions, respectively located at metal levels of rank 1 to N1, vias between these metallic portions and a contact between the corresponding active zone and the metallic portion located at metal level of rank 1, -a metal connecting portion located at the level of metal of rank Nl connecting the two metal portions of the two branches located at the level of metal of rank Nl.

[0022] Said electrically conductive region may include several electrically conductive paths.

[0023] These paths can be individualized and each connected to a respective processing unit, or connected respectively to four input ports of a single processing unit, or connected in a multiplexed manner to a single input port of the processing unit, or connected in series to a single input port of the processing unit.

[0024] According to another embodiment, the electrically conductive path located below the contact area can make contact with it. This makes it possible to detect a fault located at the contact area or just below it. However, this detection cannot be performed during the application operation of the integrated circuit.

[0025] More specifically, in this other variant, said at least one area of ​​the interconnecting part (in which the possible presence of a structural defect can be detected) also incorporates the contact area.

[0026] According to an embodiment of this other variant, in which the interconnecting part comprises N metal levels, the first-rank metal level being the metal level closest to the substrate, the contact areas being located at the Nth-rank metal level, said electrically conductive region comprises an electrically conductive path having: -a first end located at the contact area and a second end located at the level of the first-order metal, both ends being capable of being electrically coupled to the detection device, -a branch extending between the first end and the second end.

[0027] This branch includes, for example, a stack -of metallic portions, respectively located at metal levels from rank 1 to Nl, -of vias between these metallic portions, and -of a via between the metallic portion located at the level of metal Nl and the contact area.

[0028] According to another embodiment of this other variant, in which the interconnecting part comprises N metal levels, the rank 1 metal level being the metal level closest to the substrate, the contact areas being located at the rank N metal level, said electrically conductive region comprises a third active area located in the semiconductor substrate and an electrically conductive path.

[0029] This electrically conductive path has: -a first end located at the contact area and a second end located at the level of the first-order metal, both ends being capable of being electrically coupled to the detection device, -a branch extending between the first extremity and the third active zone, -a third contact connected between the third active zone and the second end.

[0030] This alternative embodiment allows the detection of a fault located at the contact area, just below it, or between this contact area and the substrate. However, this detection cannot be performed during the application operation of the integrated circuit.

[0031] Said branch may include, for example: -a stack of metallic portions, respectively located at metal levels of rank 1 to Nl, of vias between these metallic portions, of a via between the metallic portion located at metal level Nl and the contact area and of a contact between the third active area and the metallic portion located at metal level of rank 1.

[0032] The detection means may include an upward pull-up resistor having a first terminal suitable for being coupled to a supply voltage and a second terminal coupled to the second end of the electrically conductive path.

[0033] The detection means may also include a pull-down resistor having a first terminal suitable for being coupled to a cold supply point, for example ground, and a second terminal coupled to the second end of the electrically conductive path.

[0034] Said electrically conductive region may comprise several electrically conductive paths connected in a star configuration, the contact area incorporating the first ends of all the paths.

[0035] According to another aspect, an integrated circuit belonging to the system as defined above is proposed.

[0036] According to another aspect, a method is proposed, comprising: -the supply of an integrated circuit, comprising a semiconductor substrate, an interconnecting portion situated above the substrate and having metal layers and via and contact layers embedded in an electrically insulating region, as well as contact areas situated at the last metal layer of the interconnecting portion, and -detection of the possible presence of at least one type of structural defect, for example a crack and / or delamination, within at least one area of ​​the interconnecting part located at least below a contact range.

[0037] According to one embodiment, said detection includes the detection of at least one electrical discontinuity in an electrically conductive region located at least in said zone.

[0038] Said zone may also incorporate the contact area.

[0039] The electrically conductive region may include at least one active element located in the semiconductor substrate.

[0040] Other advantages and features of the invention will become apparent upon examination of the detailed description of implementations and embodiments, which are by no means limiting, and the accompanying drawings in which: [Fig.l], [Fig.2], [Fig.3], [Fig.4] [Fig.5] [Fig.6] [Fig.7] [Fig.8] [Fig. 9]# [Fig. 10]# [Fig. 11], and - [Fig. 12], illustrate methods of implementation and realization of the invention.

[0041] In [Fig.1], the reference SYS designates a system comprising an integrated circuit IC and detection means MDET.

[0042] As will be seen in more detail below, these MDET detection means can be totally located in the integrated circuit IC or partially outside the integrated circuit IC.

[0043] This integrated circuit IC includes a PDR ring of PD contact pads and a peripheral sealing ring SR.

[0044] The integrated circuit IC also includes in this example a processing unit UT, for example an electronic chip which in some cases may be part of the detection means MDET.

[0045] As illustrated in [Fig.2], the integrated circuit comprises a semiconductor substrate SB and an interconnection portion INT (known to those skilled in the art by the Anglo-Saxon acronym "BEOL": "Back End Of Lines") located above the substrate SB.

[0046] This interconnecting part has metal levels, here 5 metal levels M1-M5 and via levels V embedded in an electrically insulating region DL, generally a dielectric material.

[0047] The interconnecting part also has PD contact areas located at the last metal level of the interconnecting part.

[0048] For the sake of simplifying the figure, only one contact area PD is shown.

[0049] The interconnecting part INT also has a level of contacts between the rank 1 metal level Ml and active regions of the substrate and / or components such as transistors.

[0050] In [Fig.2], for the sake of simplification, only one CT contact is shown between an active ZA region of the substrate (for example an N+ doped region) and a track of the metal level Ml.

[0051] Again, for reasons of simplification of the figure, insulating regions, for example of the "shallow trench" type (known to those skilled in the art under the Anglo-Saxon acronym "STI": Shallow Trench Isolation") isolating the active region from the rest of the substrate SB, are not shown.

[0052] The interconnection part INT is conventionally covered with a passivation layer CP having open areas ZB so as to expose the contact areas PD.

[0053] These contact areas are intended to receive by welding connecting wires (“wire bonding”) or welding balls.

[0054] These wire or ball welding operations can cause DFT defects to appear in a ZD zone located at least below the PD contact range and possibly at the level of this PD contact range.

[0055] These structural defects may be cracks and / or delaminations.

[0056] The MDET detection means mentioned above are configured to detect the possible presence of at least one type of structural fault DFT within at least one ZD zone of the interconnection part INT, this ZD zone being located at least under a PD contact range and being able to incorporate the contact range itself.

[0057] As illustrated in [Fig.1], the MDET detection means comprise an electrically conductive RGC region located in said zone ZD at least under a contact range, this electrically conductive RGC region being able to also incorporate, as will be seen in more detail below, the contact range itself.

[0058] The MDET detection means also include a detection device configured to detect at least one electrical discontinuity in the RGC region.

[0059] In the example of [Fig.1], the detection device may include the processing unit UT.

[0060] We will see below that the detection means can also be an external module to the integrated circuit, for example a tester.

[0061] Fig. 10 schematically illustrates steps in an implementation method of a process according to the invention.

[0062] More particularly, in a step S10, an integrated circuit IC is provided comprising -a semiconductor substrate, -an interconnecting part situated above the substrate and having metal levels and via levels embedded in an electrically insulating region, the interconnecting part also having contact areas situated at the last metal level of this interconnecting part.

[0063] Then, in a step SI 1, a possible presence of at least one type of structural defect is detected within at least one zone ZD of the interconnection part, said zone being located at least under a contact range.

[0064] More particularly, this SI 1 detection includes an SI 10 detection of at least one electrical discontinuity of an electrically conductive RGC region located in said ZD zone.

[0065] If such an electrical discontinuity is detected in step SI 10, then it can be concluded that there is a DFT fault in the ZD zone.

[0066] If, on the other hand, in step SI 10, no electrical discontinuity is detected in the RG region, then we can conclude that there is no fault detected in this ZD zone;

[0067] We now refer more particularly to [Fig.3] to describe one embodiment of the invention.

[0068] In this embodiment, the interconnecting part INT comprises N = 5 metal levels, the first metal level referenced Ml, being the metal level closest to the substrate SB.

[0069] The PD contact areas are located at the level of N-rank metal, referenced M5.

[0070] Metal levels M2, M3 and M4 are intermediate metal levels between the Ml metal level and M5 metal level.

[0071] The electrically conductive region RGC includes an electrically conductive path CH.

[0072] This electrically conductive path CH has a first end EX1 located at the level of the metal Ml of rank 1 and a second end EX2 also located at the level of the metal Ml of rank 1.

[0073] These two ends EX1 and EX2 are suitable for being electrically coupled to the detection device of the detection means MDET.

[0074] This detection device comprises, in this embodiment, -a first inverter INV1 whose output is connected to the first end EX1, -a second inverter INV2 whose input is connected to the second end EX2, and -the processing unit UT connected on one side to the input of the first inverter INV1 and on the other side to the output of the second inverter INV2.

[0075] The electrically conductive path CH also includes a first branch BRI extending from the first end EX1 to the metal level of rank Nl, here the metal level M4 of rank 4.

[0076] The electrically conductive path CH also includes a second branch BR2 extending from the metal level M4 of rank Nl to the second end EX2.

[0077] The two branches BRI and BR2 are mutually connected at the NL-rank metal level M4

[0078] More specifically, the first BRI branch comprises a stack of PM11, PM21, PM31, PM4 metal portions respectively located at the M1-M4 metal levels of ranks 1 to 4 and vias V1, V21, V31 between these metal portions.

[0079] The metallic portion PMI 1 forms the first end EX1 of the electrically conductive path CH.

[0080] The second branch BR2 comprises a stack of metal portions PM21, PM22, PM32, PM4 respectively located at the level of metal M1-M4 and vias VI2, V22, V32 between these metal portions.

[0081] The metallic portion PM21 forms the second end EX2 of the electrically conductive path CH.

[0082] The PM4 metal portion also forms a connecting metal portion connecting the two PM4 metal portions of the two branches located at the level of metal M4.

[0083] As illustrated in [Fig.3], it is possible, with this embodiment, to detect a structural defect DFT, of the type of cracks and / or delamination, located between the metal level M1 and the metal level M4 by detecting an electrical discontinuity DISC of the electrically conductive path CH.

[0084] For example, in the example of [Fig.3], the DFT fault causes a DISC electrical discontinuity located at the via V22.

[0085] On the other hand, this embodiment does not allow the detection of a DFT defect which would be located between the metal level M4 and the contact area PD.

[0086] In return, this embodiment makes it possible to perform a detection of a DFT defect in the ZD zone between the metal levels M1 and M4, including these levels M1 and M4, whether during a test of the integrated circuit or even during an application operation of the integrated circuit.

[0087] To perform this detection, the processing unit UT delivers, for example, to the inverter INV1 a voltage corresponding to a logic level 1.

[0088] The output of inverter INV1 is a logic level 0 which, if there is no DISC discontinuity, is also found at the input of inverter INV2. Therefore, the output of inverter INV2 is a logic level 1.

[0089] If we move the logic level at the input of the inverter INV1, we must, in the absence of discontinuity, find the same logic level at the output of the inverter INV2.

[0090] If, on the other hand, during a change in logic level at the input of the inverter INV1, this change is not found at the output of the inverter INV2, this means that there is an electrical discontinuity in the electrically conductive path CH, which is representative of the presence of a DFT fault.

[0091] In order to further improve fault detection, it is possible, as schematically illustrated in [Fig.4] which shows a top view of the PD contact area, to provide within the electrically conductive region RGC several electrically conductive paths, here four electrically conductive paths CH1-CH4 connected in series.

[0092] These paths are, in this schematic figure, represented at arbitrary positions of the contact range.

[0093] In practice they can for example be respectively arranged under the four corners of the PD contact area.

[0094] A first INV10 inverter has its output connected to the first end of the path CH1 and a second inverter INV1 have their input connected to the second end of the path CH4.

[0095] These two inverters are connected to the UT processing unit in a manner analogous to that described with reference to [Fig.3].

[0096] We can then detect one or more discontinuities in one or more of the CH1-CH4 paths.

[0097] Of course, more than four paths could be foreseen.

[0098] Thus a fifth path could also be arranged under the center of the contact area.

[0099] We now refer more particularly to [Fig.5] to describe another embodiment of the invention.

[0100] In this embodiment, the ZD zone in which a possible structural defect can be detected also incorporates the PD contact area located at the level of metal of rank N, here the metal level M5.

[0101] More specifically, for example, a DFT1 defect located between the metal level M2 and M3 can be detected, or a DFT2 defect located between the metal level M4 and the metal level M5, or possibly a structural defect in the contact range itself.

[0102] In this respect, the electrically conductive region RGC again includes an electrically conductive path CH5.

[0103] This CH5 path has a first end EX1 located at the contact area PD and a second end EX2 located at the level of the metal M1 of rank 1. Here again, the two ends EX1 and EX2 are suitable for being electrically coupled to the detection device which, in this embodiment, includes an external module such as a tester, TST.

[0104] The tester is looped back between the first end EX1 and the second end EX2, for example via another contact range not shown here.

[0105] The tester can for example apply a voltage difference between the two ends EX1 and EX2 and check whether or not there is a current flowing between these two ends EX1 and EX2.

[0106] The presence of a current is representative of an absence of electrical discontinuity in the CH5 path and therefore an absence of detection of a DFT1 or DFT2 fault.

[0107] On the other hand, the absence of current between these two ends is representative of the presence of at least one electrical discontinuity in this path and therefore of the presence of at least one DFT1 or DFT2 fault.

[0108] The path CH5 includes in this respect a branch BR5 extending between the first end EX1 and the second end EX2.

[0109] This branch comprises a stack of metal portions PM51, PM52, PM53, PM54 respectively located at the metal level M1-M4, of vias V51, V52, V53 between these metal portions and of a via V54 between the metal portion PM54 located at the metal level M4 and the contact area PD.

[0110] Fault detection is performed during a test of the integrated circuit but cannot be performed during the application operation of the integrated circuit.

[0111] As illustrated in [Fig.6], it is possible, in order to detect the possible presence of a fault, not to use an external tester TST but again the processing unit UT present within the integrated circuit in combination with two inverters INV100 and INV200.

[0112] The INV100 inverter has its output connected to the PD contact range and its input is connected to the UT processing unit.

[0113] The second inverter INV200 has its input connected to the second end EX2 of the CH5 path and its output connected to the UT processing unit.

[0114] By analogy to what has been described with reference to [Fig.3], a detection of a logic level fluctuation at the output of the second inverter INV200 in response to a logic level fluctuation at the input of the inverter INV100 is representative of the absence of an electrical discontinuity in the CH5 path and therefore of the absence of fault detection.

[0115] On the other hand, a failure to detect a logic level fluctuation at the output of the second inverter INV200 in response to a fluctuation at the input of the inverter INV100 is representative of at least one electrical discontinuity in the CH5 path and therefore of the presence of at least one structural defect in the ZD zone.

[0116] When using the UT processing unit for electrical discontinuity detection, it must be supplied between the supply voltage VDD and ground GND.

[0117] However, it is also possible to detect a DFT fault under a PDGND contact range intended to be connected to ground by placing, as illustrated in [Fig.7], a pull-up resistor RPP connected on one side to the supply voltage VDD and on the other side to the second end EX2 of the electrically conductive path CH6, the first end of which is located at the PDGND contact range.

[0118] Indeed, in the absence of electrical discontinuity in the CH6 path, the node ND1 connected to the second end EX2 of the CH6 path remains forced to ground, which allows the processing unit to detect an absence of fault.

[0119] On the other hand, in the presence of at least one electrical discontinuity in the CH6 path, the ND1 node is floating but will be pulled towards the VDD supply via the RPP resistor.

[0120] An increase in voltage at the node ND1, detected by the processing unit UT, is then representative of an electrical discontinuity in the path CH6 and therefore of the presence of a fault.

[0121] In the case where the processing unit UT is intended to detect the possible presence of a fault under a contact range PDVDD intended to be powered by the supply voltage VDD, it is then provided, as illustrated in [Fig.8], that a pull-down resistor RPD is connected between the node ND2 connected to the second end EX2 of the path CH7 and ground GND.

[0122] In the absence of an electrical discontinuity in the CH7 path, the voltage VDD is present at the node ND2, while in the presence of an electrical discontinuity in the CH7 path, the voltage at the node ND2 will be pulled to ground via the RPD resistance.

[0123] This voltage decrease, detected by the processing unit UT, is then representative of the presence of at least one electrical discontinuity in the CH7 path and therefore of the presence of at least one structural fault under the PD VDD contact range.

[0124] As illustrated in [Fig.9], it is also possible, in order to further improve fault detection, to provide several paths, here four paths, electrically conductive CH50, CH51, CH52, CH53 connected in star under the contact range PD.

[0125] More specifically, the contact area PD forms the respective first ends EX150, EX151, EX152, EX153 of the four paths CH50, CH51, CH52, CH53.

[0126] The respective second ends EX250, EX251, EX252 and EX253 of these paths are connected separately, for example to four input ports of the processing unit UT or in a multiplexed manner to a single input port of the processing unit.

[0127] In the example described here, the four paths are connected in the middle of the four edges of the PD contact range.

[0128] Of course, they could be located differently, for example at the four corners.

[0129] Other embodiments of the invention are also possible as will now be described with reference to Figures 11 and 12.

[0130] On [Fig. 11] the elements analogous or having functions analogous to those of [Fig. 3] have the same references as those of [Fig. 3].

[0131] Only the differences between these two figures are described.

[0132] Said electrically conductive region RGC comprises a first active zone ZA1 and a second active zone ZA2 located in the semiconductor substrate SB.

[0133] The substrate here is typically a substrate of conductivity type P and the active regions are N+ doped regions. They are mutually isolated and isolated from the rest of the substrate SB by insulating regions RIS for example of the "shallow trench" type.

[0134] The RGC region also includes an electrically conductive path CH7.

[0135] This electrically conductive path CH7 has a first end EX1 and a second end EX2 located at the level of rank 1 metal and suitable for being electrically coupled to the detection device, comprising as in [Fig.3] inverters INV1 and INV2 connected to the processing unit UT.

[0136] The first end of the CH7 path is formed here by a PM27 metallic portion.

[0137] The second end of the CH7 path is formed here by another metallic portion PM28.

[0138] The CH7 path also has a first contact CT10 connected between the first end EX1 (metal portion PM27) and the first active zone ZA1.

[0139] The CH7 path also includes a first branch BR7 extending from the first active zone ZA1 to the Nl rank metal level M4 (N=5 here), and a second branch BR8 extending from the Nl rank metal level M4 to the second active zone ZA2.

[0140] The electrically conductive path CH7 further includes a second contact CT21 connected between the second active zone ZA2 and the second end EX2 (metallic portion PM28).

[0141] Each branch BR7, BR8 here comprises a stack of metallic portions, respectively located at the metal levels Ml to M4 of rank 1 to Nl, of vias between these metallic portions and of a contact CTI 1, CT20 between the corresponding active zone ZA1, ZA2 and the corresponding metallic portion PM 17, PM 18 located at the metal level Ml of rank 1.

[0142] A PM4 connecting metal portion located at the Nl rank metal level connects the two metal portions of the two branches located at the Nl rank metal level.

[0143] Such an embodiment in which the electrically conductive path CH7 does not contact the contact area but extends to the active zones ZA1, ZA2 of the substrate, allows, if desired, continuous detection of the occurrence of a structural defect DFT6, DFT7 below the contact area, even when the integrated circuit is in its application operation, and this between the metal layer N1 and the semiconductor substrate. In particular, it is possible to detect a DFT7 defect such as delamination, very close to the substrate SB.

[0144] On [Fig. 12] the elements analogous or having functions analogous to those of [Fig. 5] have the same references as those of [Fig. 5].

[0145] Only the differences between these two figures are described.

[0146] The electrically conductive region RGC includes a third active region ZA3 located in the semiconductor substrate SB.

[0147] The substrate here is typically a substrate of type P conductivity and the active region ZA3 is here an N+ doped region. It is isolated from the rest of the substrate SB by insulating regions RIS for example of the "shallow trench" type.

[0148] The RGC region also includes an electrically conductive path CH9.

[0149] This electrically conductive path CH9 has a first end EX1 located at the contact area PD and a second end EX2 located at the level of the rank 1 metal, both ends being able to be electrically coupled to the detection device TST.

[0150] The second end EX2 is formed here by a metallic portion PM29 located at the level of metal Ml of rank 1.

[0151] The CHP path also includes a branch BR9 extending between the first end EX1 and the third active zone Z A3.

[0152] The CH9 path also includes a third contact CT91 connected between the third active zone ZA3 and the second end EX2 (metal portion PM29).

[0153] Branch BR9 here comprises: -a stack of metallic portions, respectively located at metal levels M1 to M4 of rank 1 to N1, of vias between these metallic portions, of a V94 via between the metallic portion located at metal level M4 and the contact area PD and of a CT90 contact between the third active zone ZA3 and the PM 19 metallic portion located at the level of the Ml rank 1 metal.

[0154] This other embodiment makes it possible to detect a DFT2 fault located at the level of the contact range or just below it, or a fault located between this contact range and the substrate, for example a DFT1 fault located in the middle of the BR2 branch or a DFTO fault located in the vicinity of the SB substrate.

[0155] Depending on the case, an upward pull-up resistor or a downward pull-down resistor can also be connected on the second end EX2 as described with reference to Figures 7 and 8.

[0156] Of course, what has been described above for a single contact area can in practice be applied to all contact areas, regardless of the embodiment envisaged.

[0157] In other words, the MDET detection means can be configured to detect the possible presence of at least one type of structural fault within ZD zones of the interconnecting part respectively located at least under each contact range.

[0158] Thus, it may be provided in this regard that the electrically conductive regions (RGCs) are present at least in each zone, and that at least one UT, TST detection device is provided, configured to detect at least one DISC electrical discontinuity in each RGC. It should also be noted that the present invention is consistent with the invention described in the aforementioned French patent application number 2406877, which provides for the presence of an annular wall inside or on one and / or the other side of the sealing ring.

Claims

Demands

1. System comprising -an integrated circuit, having a semiconductor substrate (SB), an interconnection part (INT) located above the substrate and having metal levels (M1-M5) and via levels (V) and contacts embedded in an electrically insulating region (DL) and contact areas (PD) located at the last metal level (M5) of the interconnection part, and -detection means (MDET) configured to detect the possible presence of at least one type of structural fault (DFT) within at least one zone (ZD) of the interconnection part located at least below one contact area.

2. System according to claim 1, wherein the detection means (MDET) comprise an electrically conductive region (RGC) located at least in said area and a detection device (UT; TST) configured to detect at least one electrical discontinuity (DISC) of said region (RGC).

3. System according to claim 2, wherein the detection device (UT) is located within the integrated circuit.

4. System according to claim 2, wherein the detection device comprises a module (TST) external to the integrated circuit.

5. A system according to any one of claims 2 to 4, wherein the interconnecting part (INT) comprises N metal levels with N greater than or equal to 2, the rank 1 metal level (M1) being the metal level closest to the substrate, the contact areas (PD) being located at the rank N metal level, and said electrically conductive region (RGC) comprises an electrically conductive path (CH) having -a first end (EX1) and a second end (EX2) located at the rank 1 metal level and capable of being electrically coupled to the sensing device (UT), -a first branch (BRI) extending from the first end to the rank N1 metal level, -a second branch (BR2) extending from the rank N1 metal level to the second end, -the two branches being mutually connected at the rank N1 metal level (M4).

6. System according to claim 5, wherein each branch (BRI, BR2) comprises -a stack of metal portions, respectively located at metal levels of rank 1 to N-1, and vias between these metal portions, -a connecting metal portion (PM4) located at metal level of rank Nl connecting the two metal portions of the two branches located at metal level of rank Nl.

7. A system according to any one of claims 2 to 4, wherein the interconnecting part (INT) comprises N metal levels with N greater than or equal to 2, the first-rank metal level (M1) being the metal level closest to the substrate, the contact areas (PD) being located at the N-rank metal level, and said electrically conductive region (RGC) comprises a first active zone (ZA1) and a second active zone (ZA2) located in the semiconductor substrate and an electrically conductive path (CH7) having: -a first end (EX1) and a second end (EX2) located at the first-rank metal level and capable of being electrically coupled to the sensing device (UT), -a first contact (CT10) connected between the first end and the first active zone (ZA1), -a first branch (BR7) extending from the first active zone (ZA1) to the N1-rank metal level,- a second branch (BR8) extending from the Nl metal level to the second active zone (ZA2), - a second contact (CT21) connected between the second active zone (ZA2) and the second endpoint (EX2), - the two branches being mutually connected at the Nl metal level (M4).

8. System according to claim 7, wherein -each branch (BR7, BR8) comprises a stack of metallic portions, respectively located at metal levels of rank 1 to N1, vias between these metallic portions and a contact (CTI1, CT20) between the corresponding active zone (ZA1, ZA2) and the corresponding metallic portion (PMU, PM18) located at metal level of rank 1, -a metallic connecting portion (PM4) located at the level of metal of rank Nl connecting the two metallic portions of the two branches (BR7, BR8) located at the level of metal of rank Nl.

9. System according to any one of claims 5 to 8, wherein said electrically conductive region (GCR) comprises several electrically conductive paths (CH1-CH4).

10. System according to claim 9, wherein the electrically conductive paths (CH1-CH4) are connected in series.

11. System according to any one of claims 2 to 4, wherein said at least one zone (ZD) also incorporates the contact range (PD).

12. System according to claim 11, wherein the interconnecting part comprises N metal levels, the rank 1 metal level being the metal level closest to the substrate, the contact areas being located at the rank N metal level, and said electrically conductive region (RGC) comprises an electrically conductive path (CH5) having -a first end (EX1) located at the contact area and a second end (EX2) located at the rank 1 metal level, both ends being capable of being electrically coupled to the sensing device (TST), -a branch (BR5) extending between the first end and the second end.

13. System according to claim 12, wherein said branch (BR5) comprises -a stack of metal portions, respectively located at metal levels of rank 1 to Nl, of vias between these metal portions and of a via between the metal portion located at metal level Nl and the contact range.

14. A system according to claim 11, wherein the interconnecting portion comprises N metal levels, the first-rank metal level being the metal level closest to the substrate, the contact areas being located at the N-rank metal level, and said electrically conductive region (GCR) comprises a third active area (ZA3) in the semiconductor substrate and an electrically conductive path (CH9) having a first end (EX1) located at the contact area (PD) and a second end (EX2) located at the level of metal (Ml) of rank 1, both ends being suitable for being electrically coupled to the detection device (TST), -a branch (BR9) extending between the first end and the third active zone, -a third contact (CT91) connected between the third active zone (ZA3) and the second end (EX2).

15. System according to claim 14, wherein said branch (BR9) comprises -a stack of metal portions, respectively located at metal levels (M1 to M4) of rank 1 to N1, of vias between these metal portions, of a via (V94) between the metal portion located at metal level N1 and the contact area and of a contact (CT90) between the third active zone (ZA3) and the metal portion (PM19) located at metal level of rank 1.

16. System according to any one of claims 12 to 15, wherein the detection means comprise an upward pull resistor (RPP) having a first terminal suitable for being coupled to a supply voltage (VDD) and a second terminal coupled to the second end (EX2) of the electrically conductive path.

17. System according to any one of claims 12 to 15, wherein the sensing means comprise a pull-down resistor (PDR) having a first terminal suitable for coupling to a cold supply point (GND) and a second terminal coupled to the second end of the electrically conductive path.

18. System according to any one of claims 12 to 17, wherein said electrically conductive region (GCR) comprises several electrically conductive paths (CH50, CH51, CH52, CH53) connected in a star configuration, the contact area incorporating the first ends of all the paths.

19. A system according to any one of the preceding claims, wherein the detection means (MDET) are configured to detect the possible presence of at least one type of structural defect within zones (ZD) of the interconnecting part respectively located at least below each contact range.

20. A system according to claims 2 and 19, wherein the detection means (MDET) comprise electrically conductive regions (RGC) respectively located at least in each zone and a detection device (UT; TST) configured to detect at least one electrical discontinuity (DISC) in each region (RGC).

21. System according to any one of the preceding claims, wherein the structural defect type (DFT) includes a crack and / or delamination.

22. System integrated circuit (SYS) according to any one of the preceding claims.

23. A method comprising -a supply (S 10) of an integrated circuit (IC), having a semiconductor substrate (SB), an interconnection part (INT) located above the substrate and having metal levels, via levels and contacts embedded in an electrically insulating region and contact areas (PD) located at the last metal level of the interconnection part, and -a detection (SU) of the possible presence of at least one type of structural defect within at least one area of ​​the interconnection part located at least below a contact area.

24. A method according to claim 23, wherein said detection (SU) comprises a detection (S 110) of at least one electrical discontinuity of an electrically conductive region located at least in said zone.

25. Method according to claim 23 or 24, wherein said area also incorporates the contact area (PA).

26. A method according to any one of claims 23 to 25, wherein said electrically conductive region (GCR) comprises at least one active region located in the semiconductor substrate.

27. ​​A method according to any one of claims 23 to 26, wherein the structural defect type (SDT) comprises a crack and / or delamination.

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