A depth image sensor including a means for resetting the photosensitive region

Abstract

The invention relates to a depth image sensor. Each pixel of the sensor comprises first and second detection nodes and a collection area located above a photosensitive region formed in a substrate; first and second transfer transistors comprising first and second vertical gates and first and second channels, respectively; and a multi-gate photosensitive region initialization transistor comprising a collection channel controllable by the first and second vertical gates. The transistor channels extend between the photosensitive region on one side and the detection nodes and the collection area on the other. The readout circuit is configured to apply first and second electrical signals to the first and second vertical gates, respectively, so as to alternately conduct each of the first channel, the second channel, and the collection channel, independently of the other two channels.Figure for the abbreviation: figure 1A.

Description

Title of the invention: Depth image sensor comprising a means for resetting the photosensitive region. Technical field

[0001] The field of the invention is that of depth image sensors operating on an indirect time-of-flight measurement principle. PREVIOUS STATE OF THE ART

[0002] Depth image sensors make it possible to obtain a three-dimensional image of a scene. Among these are depth image sensors operating on an indirect time-of-flight measurement principle, generally called "iToF image sensors" (iToF for "Indirect Time of Flight"). Such a depth image sensor typically comprises a depth pixel array. It is associated with a light source, for example a laser, to illuminate the scene. The light source emits a periodic light signal in amplitude, often sinusoidal. A pixel, or a group of contiguous pixels corresponding to a point in the image, samples the periodic signal received after reflection from the scene. The sensor includes processing means for determining a phase shift between the emitted and received periodic signals, and for converting the phase shift into a distance separating the image sensor from the scene point conjugate with the image point.

[0003] It is generally accepted that at least three samples over one period of the periodic signal are necessary to perform a distance measurement. It is preferable to use four samples. A sample is an integration of the periodic signal received by a pixel over one or more time periods, each equal to a fraction of the period of the periodic signal, the time periods being separated by one period of the periodic signal. Preferably, the fraction of the period of the periodic signal is the same for all samples, for example, equal to the inverse of the number of samples. Generally, the integration time periods of separate samples do not overlap.

[0004] A depth pixel comprises a photosensitive region configured to convert photons of the received light signal into electrical charges, a first transfer transistor, and a detection node. The transfer gate allows the electrical charges to be transferred from the photosensitive region to the detection node during time periods corresponding to a sample.

[0005] The depth pixel generally also includes a blind region dedicated to resetting the photosensitive region before each sampling phase. It contains an initialization transistor and a collection area. The initialization transistor allows the discharge of electrical charges from the photosensitive region to the collection area through its channel. US patent 10162048 proposes an iTOF image sensor with one initialization transistor per pixel. French patent FR3065320 proposes a more compact solution, as the initialization transistor has a vertical gate. However, it appears necessary to further reduce the volume occupied by the region dedicated to resetting the photosensitive area.

[0006] US patent 11581345 proposes an alternative solution to the transistor The initialization process is particularly attractive due to its compact size. Each pixel has a vertical electrode isolated from the photosensitive region by a dielectric layer containing charge traps at its interface with the photosensitive region. During the initialization of the photosensitive region, the vertical electrode is biased by a pulse train with a duration between 10 ns and 2 ms to generate alternating inversion and accumulation regimes in the photosensitive region, causing photo-generated charges in the photosensitive region to recombine in the charge traps.

[0007] However, it appears that resetting the photosensitive region is less efficient with this solution than with an initializing transistor. Furthermore, it would be advantageous to eliminate the interconnections specifically dedicated to initializing the photosensitive region. Description of the invention

[0008] The invention aims to remedy at least in part the disadvantages of the prior art, and more particularly to propose a depth image sensor comprising a plurality of pixels, each comprising a photosensitive region and a means of initializing the photosensitive region that is more compact than those of prior art devices.

[0009] To this end, the object of the invention is a depth image sensor comprising a readout circuit and a plurality of pixels formed in and on a sensor substrate. Each pixel comprises a photosensitive region formed in the substrate and configured to convert photons into electrical charges; a first detection node, a second detection node, and a collection zone located above the photosensitive region and doped with a first type of conductivity; a first transfer transistor comprising a first vertical gate and a first channel controllable by the first vertical gate; a second transfer transistor comprising a second vertical gate and a second channel controllable by the second vertical gate; and a multi-gate photosensitive region initialization transistor comprising the first and second vertical gates and a channel The collection channel is controlled by the first and second vertical grids. Each pixel is such that the first channel, the second channel, and the collection channel extend into the substrate between the photosensitive region and, respectively, the first detection node, the second detection node, and the collection area. The readout circuit is configured to apply a first electrical signal to the first vertical grid and a second electrical signal to the second vertical grid so as to alternately conduct each of the first channel, the second channel, and the collection channel, independently of the other two channels.

[0010] Some preferred but not limiting aspects of this sensor are as follows.

[0011] The collection zone can extend vertically into the substrate deeper than the first and second detection nodes.

[0012] Each pixel may further include a peripheral isolation trench that can extend vertically into the substrate from an upper face of the substrate and that can laterally delimit the photosensitive region.

[0013] The sensor may further comprise a housing doped with a second type of conductivity opposite to the first type of conductivity. The housing may be in contact with the peripheral insulation trench and may be flush with the upper surface of the substrate.

[0014] The peripheral isolation trench may include a vertical electrode made of a doped semiconductor material of the second type of conductivity.

[0015] The first and second vertical grids may have respective main portions facing each other, symmetrical to each other with respect to a vertical axis of symmetry passing through the center of the pixel and in which the collection area may extend from one main portion to the other.

[0016] The first and second vertical grids can each have a U-shape when viewed from above. The first detection node and the second detection node can each extend between two opposite branches of the U formed by, respectively, the first vertical grid and the second vertical grid.

[0017] The reading circuit may include an initialization contact. The pixel may further include a peripheral contact area of ​​the first type of conductivity, which may extend the collection area into a peripheral region of the pixel on which the initialization contact rests.

[0018] The reading circuit can be configured to switch in opposite phase, the first electrical signal and the second electrical signal between a first value and a second value so as to alternately make the first channel and the second channel pass during a sampling phase, while keeping the collection channel blocked.

[0019] The reading circuit can be configured to assign a third value to the first electrical signal and the second electrical signal so as to make the channel conductive collection during an initialization phase of the photosensitive region preceding the sampling phase.

[0020] The plurality of pixels can be arranged in a matrix. The reading circuit can be configured to assign an electrical potential equal to an intermediate value to the first and second vertical grids so as to prevent a transfer of photo-generated electrical charges in the photosensitive region to the first and second detection nodes during a matrix reading phase, the intermediate value being able to be different from the third value. Brief description of the drawings

[0021] Other aspects, objects, advantages and features of the invention will become more apparent upon reading the following detailed description of preferred embodiments thereof, given by way of non-limiting example, and made with reference to the accompanying drawings in which:

[0022] [Fig.1A] is a schematic top view of a first embodiment of a depth image sensor;

[0023] [Fig.1B] is an example of dopant atom mapping seen in the AA section plane of [Fig.1A];

[0024] [Fig.1C] is a schematic view of the first embodiment according to section AA of [Fig.1A];

[0025] [Fig.2A] is a schematic top view of a variant of the first embodiment of a depth image sensor;

[0026] [Fig.2B] is an example of dopant atom mapping seen in the AA section plane of [Fig.2A];

[0027] [Fig.2C] is the example of dopant atom mapping seen in the BB section plane of [Fig.2A];

[0028] [Fig.3A] is an electrical diagram representative of the first embodiment and its variant;

[0029] [Fig.3B] is an example of a timing diagram implemented by the first embodiment or its variant, when they are in operation;

[0030] [Fig.4A] is an example of mapping the electric potential in cross-sectional planes of the first embodiment and its variant, for a particular polarization state;

[0031] [Fig.4B] is an example of mapping the electrical potential in cross-sectional planes of the first embodiment and its variant, during a sampling phase;

[0032] [Fig.4C] is an example of mapping the electrical potential in cross-sectional planes of the first embodiment and its variant, during a phase of reading the plurality of pixels or during an initialization phase;

[0033] Figures 5A and 5B are curves giving the value of the electric potential of [Fig.4C], along particular horizontal segments;

[0034] Figures 6A, 6B, 6C, 6D, 6E, 6F and 6G are schematic top views of other embodiments according to the invention.

[0035] DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS

[0036] In the figures and throughout the description, the same reference numerals represent identical or similar elements. Furthermore, the various elements are not drawn to scale in order to enhance the clarity of the figures. Moreover, the different embodiments and variants are not mutually exclusive and may be combined. Unless otherwise indicated, the terms "approximately," "about," and "in the order of" mean within 10%, and preferably within 5%. Furthermore, the terms "between ... and ..." and equivalents mean that the limits are inclusive, unless otherwise stated.

[0037] The invention relates to a depth image sensor comprising a readout circuit and a plurality of pixels formed in and on an image sensor substrate. Each pixel includes a photosensitive region, a means for initializing the photosensitive region, at least two detection nodes, and a transfer grid for each detection node capable of transferring photogenerated electrical charges in the photosensitive region to a corresponding detection node.

[0038] In the sensor of the invention, the means for initializing the photosensitive region is a multi-gate initialization transistor, the gates of which are the transfer gates. Applying a non-zero electrical potential to all the transfer gates prioritizes the transfer of electrical charges from the photosensitive region to a drain of the initialization transistor, hereinafter referred to as the collection area. The collection area is a region of the pixel distinct from the detection nodes. Thus, it is possible to initialize the photosensitive region of the pixel without additional gates or interconnections, beyond those required for reading the samples.

[0039] In the description, a transfer of charges along a channel, or from one region to another, is said to have priority if at least 90% of the electrical charges transferred are carried out through that channel, or from the region to the other. Where applicable, the proportion is preferably greater than or equal to 95%, or even greater than or equal to 97%, or greater than or equal to 99%.

[0040] When a first channel of a transistor is conducting independently of another channel or other channels of transistors, the transfer of charges through the first channel has priority.

[0041] Specific embodiments will be described relating to a depth image sensor configured for voltage reading. However, these embodiments can be adapted to other optoelectronic devices.

[0042] Each embodiment described below adopts a particular combination of conductivities associated with the doped zones, it being understood that the combination can be reversed without departing from the scope of the invention. Thus, for a particular embodiment, all P-doped zones can be N-doped and all N-doped zones can be P-doped, provided that the type of conductivity of all the doped zones is changed.

[0043] A first embodiment of an image sensor according to the invention will now be described with reference to Figures IA, IB, and IC. Figures IA and IC are schematic top and cross-sectional views, respectively. The cross-sectional plane of [Fig. 1C] is represented by a dashed line in [Fig. 1A]. [Fig. 1B] represents a simulation-based map of the concentration of dopant elements in the cross-sectional plane of [Fig. 1C].

[0044] The grayscale maps in Figures IB, 2B, 2C, 4A, 4B, and 4C are simulation results obtained using technology computer-aided design (TCAD) software. To the right of Figures IB, 2B, and 2C, the numerical values ​​of dopant atom concentrations per cm³ are given, corresponding to contour lines appearing within regions marked by dashed lines in boxes on the left side of these figures. A negative value corresponds to P-type doping, and a positive value to N-type doping. Although a grayscale level is assigned to the dielectric parts of the pixel, it is not representative of a dopant atom concentration.

[0045] The first embodiment comprises a reading circuit and a plurality of pixels formed in and on a substrate 100. In Figures IA to IC, only one pixel is shown. To avoid cluttering the diagrams, certain elements have been omitted, such as the interconnecting lines. To improve readability, only the upper part of the substrate 100 is shown in the cross-sectional views. In the schematic views, the elements are represented by simple geometric shapes. These are reproduced on the manufactured device, with manufacturing errors such as misalignment, dimensional errors, or rounded corners due to insufficient resolution.

[0046] The substrate 100 has an upper face 100.1 and a lower face opposite the upper face 100.1. The lower and upper faces 100.1 are substantially flat and parallel to each other. The pixel comprises a photosensitive region 120, a first detection node 121, a second detection node 122, a zone of collection 130, a box P 141, a first vertical grid 111 and a second vertical grid 112. The first and second detection nodes 121, 122, the first and second vertical grids 111, 112, the collection area 130 and the box P 141 are flush with the top face 100.1.

[0047] A three-dimensional orthogonal (X, Y, Z) direct coordinate system is defined herein and for the remainder of this description, where the X and Y axes form a plane parallel to the upper face 100.1 of the substrate 100, the X axis being oriented parallel to the cutting plane AA, and where the Z axis is oriented substantially orthogonally to the upper face 100.1 of the substrate 100, from the lower face to the upper face 100.1. In the remainder of this description, the terms "vertical" and "vertically" refer to an orientation substantially parallel to the Z axis, and the terms "horizontal" and "horizontally" refer to an orientation substantially parallel to the (X, Y) plane. Furthermore, the terms "lower" and "upper" refer to an increasing position when moving along the +Z direction. The term "lateral" refers to an orientation substantially parallel to the Z axis.A top view is a view along the -Z direction.

[0048] The substrate 100 is made of a semiconductor material. Here, it is crystalline silicon. For example, it is a silicon wafer or part of a silicon wafer. It may comprise one or more epitaxial layers of crystalline silicon, as well as one or more passivation layers.

[0049] In this example, the pixel includes a peripheral isolation trench 105 extending vertically into the substrate 100 from the top face 100.1. Preferably, the peripheral isolation trench 105 passes completely through the substrate 100. Here, the peripheral isolation trench 105 is a capacitive isolation trench. It delimits the photosensitive region 120 in a horizontal plane. In a top view, it completely surrounds the photosensitive region 120 and has a closed contour, here substantially square in shape, with sides parallel to the X-axis or the Y-axis. In the plane of the top face 100.1, the distance Px separating an outer edge of one side of the square from an inner edge of the opposite side of the square defines a pixel size. In this example, the pixel size Px is equal to 1.2 pm. It can be less than or equal to 1.2 pm, or even less than or equal to 1 pm.

[0050] The peripheral insulating trench 105 has a transverse inner wall located on the side of the pixel center. It includes a vertical electrode 106 made of an electrically conductive material. The vertical electrode 106 may be made of a metal, a metal alloy, or a doped semiconductor material. Here, it is made of P-type doped polycrystalline silicon. It extends vertically opposite the photosensitive region 120, preferably opposite the entire photosensitive region 120.

[0051] The peripheral insulation trench 105 further comprises an intercalated dielectric layer 107 covering the vertical electrode 106, over the entire inner wall of the peripheral insulation trench 105. The intercalated dielectric layer 107 is made of any dielectric material. Here, it is made of silicon oxide.

[0052] The peripheral isolation trench 105 has, for example, a horizontal width between 20 nm and 300 nm, here equal to 100 nm. It has a vertical height between 1 pm and 20 pm, preferably equal to the thickness of the substrate 100.

[0053] In this example, the peripheral insulating trench 105 has, on the side of the upper face 100.1 of the substrate 100, an optional insulating region 108 resting on an upper end of the vertical electrode 106, so as to be in physical contact with it. The insulating region 108 is made of an electrically insulating material. It may be made of a dielectric material identical to the intercalated dielectric layer 107. Here, it is made of silicon oxide.

[0054] When the plurality of pixels is arranged in a matrix according to rows and columns, the rows and columns preferably extend, respectively, along the X and Y axes. Where appropriate, two neighboring pixels of the matrix may share a part of their peripheral isolation trenches 105. Thus, the peripheral isolation trenches 105 of all the pixels can together constitute an orthogonal mesh in top view, for example of square cells with sides parallel to the X and Y axes.

[0055] The pixel further comprises a first transfer transistor 51.1 and a second transfer transistor 51.2 (identified in the circuit diagram of [Fig. 3A]). The first transfer transistor 51.1 includes the first vertical gate 111 and a first channel controllable by the first vertical gate 111. Similarly, the second transfer transistor 51.2 includes the second vertical gate 112 and a second channel controllable by the second vertical gate 112. The first and second detection nodes 121, 122 constitute, respectively, a drain of the first transfer transistor 51.1 and the second transfer transistor 51.2.

[0056] In this example, to simplify the pixel design, the first and second vertical grids 111, 112 are identical, although this is not an essential feature of the invention. They are arranged in the pixel so as to be symmetrical to each other with respect to an axis of symmetry parallel to the Z-axis and perpendicular to the upper face 100.1 of the substrate 100. Here, the axis of symmetry passes through the center of the pixel. Thus, only the first vertical grid 111 is described in detail below.

[0057] The first vertical grid 111 extends vertically into the substrate 100, partly opposite the first channel, from the upper face 100.1, to a depth strictly less than the height of the peripheral isolation trench 105. Similarly, the second vertical grid 112 extends vertically into the substrate 100, partly opposite the second channel, from the upper face 100.1, to a depth equal to the depth of the first vertical grid 111.

[0058] The first vertical grid 111 has a U-shaped form when viewed from above. It comprises a main portion forming the base of the U, extending parallel to the (Y, Z) plane, as well as a first and second branch of the U extending parallel to the (X, Z) plane. In this example, the main portion and the first branch have horizontal widths substantially equal to a value W. The second branch has a horizontal width strictly greater than W. The horizontal width of the second branch is, for example, sufficient to ensure that a first grid contact 161 of the read circuit rests entirely on the second branch despite manufacturing uncertainties.

[0059] The first vertical grid 111 comprises a grid electrode 115, an insulating layer 116, and an optional insulating region 117. It has a structure analogous to the peripheral insulating trench 105. The grid electrode 115 is made of an electrically conductive material, for example, a metal, a metal alloy, or a doped semiconductor. It may be made of the same material as the vertical electrode 106. Here, it is made of P-type doped polycrystalline silicon.

[0060] The insulating layer 116 completely covers all the lateral faces and the lower face of the grid electrode 115. It is made of an electrically insulating material, for example any type of dielectric material. Here it is made of silicon oxide.

[0061] The insulating region 117 rests on an upper end of the grid electrode 115, so as to be in physical contact with it. It is made of an electrically insulating material, advantageously the same material as the insulating region 108. It may be made of a dielectric material identical to the insulating layer 116. Here, it is made of silicon oxide. When the insulating regions 108 and 117 are made of the same material and extend from the upper face 100.1 to the same depth, as shown here, they can be made simultaneously.

[0062] The first and second vertical grids 111, 112, for example, have a horizontal width W between 20 nm and 300 nm, here equal to 100 nm. They have a vertical height between 0.2 pm and 1.5 pm. Here, the second branch has a horizontal width of 200 nm. The insulating regions 108 and 117 have a vertical height of less than 600 nm, here equal to 100 nm.

[0063] The main portions of the first and second vertical grids 111, 112 are opposite each other in the plane of the upper face 100.1; preferably, as is the case here, the main portions are parallel to each other. Here, in top view, they are substantially straight and opposite each other along their entire length.

[0064] In this example, to simplify the pixel design, the first and second detection nodes 121, 122 are symmetrical to each other with respect to the axis of symmetry, although this is not an essential feature of the invention. Thus, only the second detection node 122 is described in detail below, with reference to Figures IA and IC. The constituent elements of the first detection node 121 are derived by the axial symmetry of symmetrical constituent elements of the second detection node 122. A characteristic or parameter defined for the second detection node 122 with respect to the second vertical grid 112 is transposed to the first detection node 121 with respect to the first vertical grid 111 by applying axial symmetry.

[0065] The second detection node 122 comprises an N-doped region 151 and an optional N-overdoped region 152. The N-overdoped region 152 has a donor-type dopant concentration strictly greater than the donor-type dopant concentration of the N-doped region 151. Preferably, the N-overdoped region 152 allows for ohmic contact between the second detection node 122 and the readout circuit.

[0066] The N-doped region 151 is interposed between the peripheral insulating trench 105 and the second vertical grid 112. It extends vertically into the substrate 100 from the upper face 100.1 to a depth greater than the height of the insulating region 117. In this example, it is laterally bounded by the second vertical grid 112, so that it is surrounded by the second vertical grid 112 on three of its sides in a top view. The N-doped region 151 extends horizontally over a length LN, from the first branch to the second branch of the second vertical grid 112. In a top view, it extends over a width WN, to the main portion of the second vertical grid 112. In this example, the first and second branches of the first and second vertical grids 111, 112 are of equal length.The N-doped region 151 has a width Wn, measured parallel to the X-axis, substantially equal to the length measured parallel to the X-axis of the first and second branches of the second vertical grid 112.

[0067] Each N 152 overdoped region is formed inside an N 151 doped region. It extends from the upper face 100.1 to a depth less than the N 151 doped region. Here, all its horizontal dimensions are strictly less than the corresponding horizontal dimensions of the N 151 doped region.

[0068] In this example, the N 151 doped region has a donor-type dopant concentration between 1E16 at / cm3 and 5E20 at / cm3. The N 152 overdoped region has a donor-type dopant concentration between 1E17 at / cm3 and 5E20 at / cm3. The N 151 doped region has a height measured along the Z-axis which exceeds the height of the insulating region 117 from 0 nm to 400 nm. The overdoped region N 152 has a height measured along the Z-axis between 10 nm and 200 nm. The width Wn is between 10% and 40% of the pixel size Px, here equal to 326 nm.

[0069] The P 141 box is doped with acceptor-type doping elements. In top view, the P 141 box preferably surrounds the first and second vertical grids 111, 112, and the first and second detection nodes 121, 122. Here, it also surrounds the collection zone 130. In this embodiment, it has a closed contour conforming to the peripheral insulation trench 105, in top view. It extends vertically into the substrate 100 from the upper face 100.1, to a depth greater than the height of the insulating region 108 of the peripheral insulation trench 105. Here, it extends along the Z-axis to a depth greater than the height of the doped region N 151, that is, to a depth greater than the heights of the first and second detection nodes 121, 122.

[0070] The housing P 141 is in contact with the inner wall of the peripheral insulating trench 105, thus forming a reservoir of holes drifting along the inner wall of the peripheral insulating trench 105, particularly when the peripheral insulating trench 105 is strongly reverse-biased. For this particular pixel, a negative potential is applied to the vertical electrode 106 when the sensor is operating, so as to attract holes from the housing P 141 along the inner wall. The holes contribute to the passivation of the interface between the substrate 100 and the inner wall, and to the formation of a potential barrier. Preferably, as shown here, the housing P 141 is in contact with the inner wall of the peripheral insulating trench 105 over substantially its entire circumference, as viewed from above.

[0071] The P 141 box, for example, has a concentration of acceptor-type dopant elements between 1E16 at / cm3 and 1E19 at / cm3. It has a height measured parallel to the Z axis which exceeds the height of the insulating region 108 from 0 nm to 400 nm.

[0072] The collection zone 130 includes an N 143 doped region. It comprises, as shown here, an optional N 144 overdoped region and an optional N 142 box. The N-doped region 143 extends horizontally from the main portion of the first vertical grid 111 to the main portion of the second vertical grid 112. The collection area 130 extends vertically into the substrate 100 from the upper face 100.1 to a depth greater than the height of the insulating regions 117 of the first and second vertical grids 111, 112. The N-overdoped region 144 is formed within the N-doped region 143. It has a higher concentration of donor-type dopant elements than the donor-type dopant concentration of the N-doped region 143. Preferably, the N-overdoped region 144 allows for ohmic contact between the collection area 130 and the readout circuit.

[0073] The N 142 box extends horizontally from the main portion of the first vertical grid 111 to the main portion of the second vertical grid 112. It extends vertically into the substrate 100 deeper than the overdoped region N 144 and the doped region N 143. In a top view, the doped region N 143, for example, occupies a pixel area located inside the N 142 box. Here, the N 142 box extends along the Y-axis, between the main portions of the first and second vertical grids 111, 112, over a length strictly less than the length of the opposite grid, along which the first and second vertical grids 111, 112 are opposite in a top view. Thus, the collection area 130 extends along the Y-axis over a length Lc strictly less than the length of the opposite grid. In [Fig.1A], it is centered on the center of the pixel.

[0074] Advantageously, the N 143 doped region (respectively the N 144 overdoped region) of the collection zone 130 and the N 151 doped regions (respectively the N 152 overdoped regions) of the first and second detection nodes 121, 122 are produced by the same process steps, so that they have substantially equal depths and substantially equal Z-doping profiles. A donor-type dopant concentration of the N 142 chamber and / or its depth are chosen to increase a proportion of electrical charges transferred by the collection channel and / or the first channel and / or the second channel during one or more operating phases of the depth image sensor.In this embodiment, the N 142 housing extends vertically into the substrate 100 deeper than the first and second detection nodes 121, 122 to promote the transfer of electrical charges from the photosensitive region 120 to the collection area 130, during an initialization phase of the photosensitive region 120 and / or a reading phase of samples collected on the first and second detection nodes 121, 122, when the sensor is in operation.

[0075] The length Lc is, for example, greater than or equal to 100 nm. The length LN can be between 15% and 60% of the pixel size Px, here equal to 584 nm. The N 143 doped region has a donor-type dopant concentration between 1E16 at / cm3 and 5E20 at / cm3. The N 144 overdoped region has a donor-type dopant concentration between 1E17 at / cm3 and 5E20 at / cm3. The N 142 box has a donor-type dopant concentration between 1E16 at / cm3 and 1E19 at / cm3.

[0076] The photosensitive region 120 is a region of the substrate 100 designed to collect photons and convert them into electrical charges. It occupies a region of the substrate 100 doped with type N, having a concentration of donor-type doping species between 1E12 at / cm3 and 1E18 at / cm3. In this example, the region photosensitive 120 is intended to receive photons from the underside of the substrate 100. The underside can be coated with a passivation layer, for example a P-doped silicon layer.

[0077] The first and second detection nodes 121, 122 and the collection zone 130 are located directly above the photosensitive region 120. The first channel (respectively second channel) is a region of the substrate 100 occupied by photo-generated electrical charges in the photosensitive region 120 during their transit from the photosensitive region 120 to the first (respectively second) detection node 121 (respectively 122) when the sensor is operating. Similarly, the collection channel is a region of the substrate 100 occupied by photo-generated electrical charges in the photosensitive region 120 during their transit from the photosensitive region 120 to the collection zone 130 when the sensor is operating.

[0078] The first and second channels, and the collection channel are located in the substrate 100 between the photosensitive region 120 and, respectively, the first detection node 121, the second detection node 122 and the collection area 130. The first channel is located at least partially between the first branch, the second branch and the main portion of the first vertical grid 111. The second channel is located at least partially between the first branch, the second branch and the main portion of the second vertical grid 112. The collection channel is located at least partially between the main portions of the first and second vertical grids 111, 112.

[0079] The U-shaped design of the first (respectively second) vertical grid 111 (respectively 112) improves control of the first (respectively second) channel. In particular, it increases the proportion of electrical charges transferred from the photosensitive region 120 to the first detection node 121 (respectively second detection node 122) when the first channel (respectively second channel) is conducting and the second channel (respectively first channel) is blocked.

[0080] In top view, the main portions of the first and second vertical grids 111, 112 are spaced a distance S apart, at the level of the collection area 130 and the collection channel.

[0081] The first channel, the second channel, and the collection channel are here doped with the same type as the first and second detection nodes 121, 122 and the same type as the collection zone 130, i.e., type N. They each have a concentration of doping species that is strictly lower than the respective minimum concentrations of the first and second detection nodes 121, 122 and the collection zone 130. Here, they have substantially the same concentration of doping atoms. They have for example a concentration of dopant atoms between 1E12 at / cm3 and 1E18 at / cm3.

[0082] The reading circuit is schematically represented in [Fig. 3A]. It comprises the first grid contact 161, a second grid contact 162, an initialization contact 163, a P contact 164, a peripheral contact 165, a first contact 166 and a second contact 167, as shown in [Fig. 1A]. Each of these contacts is preferably metallic.

[0083] The first and second grid contacts 161, 162 allow a first electrical signal TGZ1 to be applied respectively to the first vertical grid 111 and a second electrical signal TGZ2 to the second vertical grid 112. They are in physical contact with the grid electrode 115 of, respectively, the first vertical grid 111 and the second vertical grid 112. They pass completely through the insulating regions 117 of each vertical grid 111, 112. The electrical signals TGZ1, TGZ2 are time-varying electrical potentials.

[0084] The initialization contact 163 allows an electrical potential VRT to be applied to the collection area 130. It is in physical contact with the overdoped region N 144 of the collection area 130. In this embodiment, it is located at the center of the pixel, between the main portions of the first and second vertical grids 111, 112. For better control of the collection channel, the distance S is preferably chosen to be equal to a minimum distance permitted by the design rules of the technology used to implement the sensor. The design rules generally take into account a minimum permitted distance between an electrical contact and a vertical grid, and a minimum dimension for an electrical contact. For example, the distance S is between 10 nm and 300 nm, here equal to 108 nm.

[0085] The first and second contacts 166, 167 are in physical contact with the overdoped N-type region 152 of the, respectively, first detection node 121 and second detection node 122. In operation, their electrical potentials are respectively equal to Vechi and Vech2- values.

[0086] The contact P 164 allows an electrical potential VP to be applied to the box P 141. It is in physical contact with the box P 141 at the level of a peripheral region of the pixel, preferably maximizing a distance separating the contact P 164 from the first and second vertical grids 111, 112 and the peripheral insulation trench 105. It is located here in the plane parallel to the (Y, Z) plane passing through the center of the pixel.

[0087] The peripheral contact 165 allows an electrical potential VCdti to be applied to the peripheral insulation trench 105. It is in physical contact with the vertical electrode 106 and passes through the insulating region 108 of the peripheral insulation trench 105.

[0088] The photosensitive region 120 is electrically connected to the first detection node 121 and the second detection node 122 via, respectively, the first transfer transistor 51.1 and the second transfer transistor 51.2. It is electrically connected via the housing P 141 and the contact P 164 to a node or a rail supplying an electrical potential VP.

[0089] The readout circuit comprises single-sample readout blocks. In this example, the number of readout blocks is equal to the number of samples collected by the pixel. They are identical here, and there are two of them. Each of them is electrically connected to a detection node 121, 122 and to an output rail Vx1, Vx2 of the readout circuit. Each readout block comprises a preload transistor 52, a transistor 53 configured as a source follower, and a selector transistor 54.

[0090] The drains of the first and second transfer transistors 51.1, 51.2 are respectively electrically connected to the gate of transistor 53 and to the source of the preload transistor 52 of a separate readout block. The source of transistor 53 is connected to the drain of the selector transistor 54. The drain of transistor 53 is connected to a node or rail supplying an electrical potential VSF. The drain of the preload transistor 52 is connected to a node or rail supplying an electrical potential VRSt-. The source of the selector transistor 54 is connected to the output rail Vx1, if the readout block is connected to the first detect node 121, or to the output rail Vx2, otherwise. The preload transistors 52 initialize the first and second detect nodes 121, 122 at an electrical potential substantially equal to VRST-.

[0091] The initialization contact 163 is electrically connected to a node or rail supplying an electrical potential VRT. It is electrically connected to the photosensitive region 120 via the initialization transistor 50. In the first embodiment, the initialization transistor 50 is a dual-gate type transistor, the gates of which are the first and second vertical gates 111, 112.

[0092] The first vertical grid 111 is electrically connected to a node or rail supplying a first electrical signal TGZ1. The second vertical grid 112 is electrically connected to a node or rail supplying a second electrical signal TGZ2. The first and second electrical signals TGZ1, TGZ2 are time-varying electrical potentials.

[0093] A variant of the first embodiment will now be described, with reference to Figures 2A, 2B, and 2C. Figure 2A is a schematic top view. Figure 2A shows section plane AA of Figure 2B and section plane BB of Figure 2C. Figures 2B and 2C represent maps of the concentration of dopant elements in these section planes, obtained by simulation. Only the differences with the first embodiment are described below.

[0094] In this variant, the pixel further comprises a peripheral contact zone 130.1 on which the initialization contact 163 rests. The peripheral contact zone 130.1 is in physical and electrical contact with the collection zone 130. For example, it is formed as a single unit with the collection zone 130. It is doped with the same type of conductivity as the collection zone 130, here of type N. It extends deep into the substrate 100 from the upper face 100.1. In this example, it extends horizontally from the collection zone 130 and from the first and second vertical grids 111, 112, until it reaches the peripheral insulation trench 105. For example, its height along the Z-axis is less than or equal to the height of the collection zone 130, although this is not essential.

[0095] The peripheral contact area 130.1 has dimensions and a concentration of dopant elements adjusted so as not to create a barrier or potential well between the collection area 130 and the initialization contact 163 when the sensor is in operation. When the peripheral contact area 130.1 and the collection area 130 are of equal height, they can be produced by the same sequence of process steps. They then exhibit substantially identical doping profiles along the Z-axis, as is the case in [Fig. 2C].

[0096] In top view, the initialization contact 163 is relocated to a peripheral region of the pixel, allowing the first and second vertical grids 111, 112 to be brought closer together without violating a design rule of the technology used to implement the sensor, such as a minimum spacing rule between a contact and a vertical grid. The distance S can thus be reduced compared to the first embodiment. Here, it is equal to 70 nm. Bringing the first and second vertical grids 111, 112 closer together prioritizes the transfer of photogenerated charges from the photosensitive region 120 to the first and second detection nodes 121, 122 over transfer to the collection area 130.

[0097] In this variant, the contour of the box P 141 follows that of the peripheral isolation trench 105 in top view, with the exception of a region of the pixel inside which the peripheral contact area 130.1 is in contact with the peripheral isolation trench 105.

[0098] Figure 3B represents a timing diagram illustrating a possible operation of the reading circuit of the first embodiment or of the variant of the first embodiment. It is assumed here that the plurality of pixels is arranged in a matrix.

[0099] When a scene is illuminated by a periodic light source with periodic amplitude Ps, the timing diagram leads to an integration by each detection node 121, 122 of respective and distinct parts of the light signal reflected by the scene. Each detection node 121, 122 integrates the reflected light signal onto periodic time intervals of period equal to the period Ps and of duration equal to Ps / 4. The time intervals of the second detection node 122 are spaced from the time intervals of the first detection node 121 by a duration equal to Ps / 4.

[0100] The timing diagram includes a sampling phase T2 immediately followed by a matrix readout phase T3. The sampling phase T2 is preceded by an initialization phase TL. The sum of the consecutive phases T1 to T3 constitutes a depth image acquisition phase, or a frame acquisition phase, for example, if the sensor is capable of capturing several successive images. If applicable, the matrix readout phase T3 of a frame can be immediately followed by the initialization phase T1 of the next frame, as shown here. The matrix readout phase T3 includes a readout phase of the row T3.1 of the matrix to which the pixel belongs.

[0101] In order to determine depth information from the periodic light signal received by the sensor, the pixel can be associated with another identical pixel for which the timing diagram has its sampling phase T2 shifted by one-quarter of the period Ps, modulo the period Ps. Alternatively, the sampling phases T2 of two successive frames can be shifted by one-quarter of the period Ps, modulo the period Ps, and the depth information is determined from the samples collected by the pixel during the acquisition phases of the two successive frames.

[0102] During the sampling phase T2, the photogenerated charges in the photosensitive region 120 are transferred alternately to the first and second detection nodes 121, 122. For this purpose, the first and second transfer transistors 51.1, 51.2 are alternately switched on for periodic time intervals with a period equal to the period Ps, each time interval being equal to Ps / 4. During the sampling phase T2, the first electrical signal TGZ1 and the second electrical signal TGZ2 switch in opposite phase, between a first value Vi and a second value V2, passing through a third value V3 for a duration equal to Ps / 4.

[0103] When the electrical potentials applied to the first and second vertical gates 111, 112 are respectively equal to Vi and V2, the second transfer transistor 51.2 is in a conducting state, while the first transfer transistor 51.1 and the initializer transistor 50 are in blocking states. Conversely, when the electrical potentials applied to the first and second vertical gates 111, 112 are respectively equal to V2 and Vb, the first transfer transistor 51.1 is in a conducting state, while the second transfer transistor 51.2 and the initializer transistor 50 are in blocking states.

[0104] In this example, where the transferred charges are electrons, Vi is equal to -0.8 V and V2 is equal to 1.8 V. Under these conditions, a map of the simulated electrical potential is given in [Fig. 4B]. [Fig. 4B] represents a moment in the sampling phase T2 for which the second transfer transistor 51.2 is in a conducting state, while the first transfer transistor 51.1 and the initializer transistor 50 are in blocking states.

[0105] In the upper left of Figures 4A to 4C, a map of the electrical potential of the first embodiment is shown in section plane AA of [Fig. 1A]. In the lower left of Figures 4A to 4C, a map of the electrical potential of the variant of the first embodiment is shown in section plane AA of [Fig. 2A]. In the lower right of Figures 4A to 4C, a map of the electrical potential of the variant of the first embodiment is shown in section plane BB of [Fig. 2A]. The three maps in the same figure are obtained for the same electrical polarization state of the pixel. In the upper right, the equivalent in volts of the gray levels used in the maps is given. In these figures, the approximate positions of certain potential barriers are represented by double lines.We have also represented by a dashed arrow, a general direction of each priority transfer of photo-generated charges in the photosensitive region 120.

[0106] Figure 4C represents a moment in the read phase of matrix T3 or a moment in the initialization phase of the photosensitive region 120, similar to the initialization phase T1, in which the first and second vertical grids 111, 112 are biased at a lower electrical potential. Figure 4A represents a pixel bias state that can be used in a possible alternative timing diagram.

[0107] The simulation results in Figures 4A to 4C are obtained by setting VRT to 1.8 V, VRST to 1.8 V, Vcdti to -0.8 V, and VP to -0.5 V. For these simulations, the first and second contacts 166, 167 are at an electrical potential of 1.8 V, which is their initial electrical potential, i.e., before they have collected any electrical charges. The electrical potential of the initial contact 163 is equal to 1.8 V.

[0108] In [Fig.4B], the electric potential gradient reaches a maximum in absolute value in a direction (white dashed arrow) connecting the photosensitive region 120 to the second detection node 122, so that 99% of the charges transferred from the photosensitive region 120 reach the second detection node 122. Thus, the second channel is conducting independently of the first channel and the collection channel.

[0109] During the reading phase of matrix T3, the first and second vertical gates 111, 112 are simultaneously biased at an electrical bias voltage greater than or equal to a threshold voltage of the first and second transfer transistors 51.1, 51.2. However, the particular arrangement of the first and second vertical grids 111, 112, relative to each other, maintain the first and second transfer transistors 51.1, 51.2 in a blocked state.

[0110] During this phase, the first and second vertical gates 111, 112 are maintained at an electrical potential equal to an intermediate value Vi, preventing charge transfer from the photosensitive region 120 to a detection node 121, 122. Preferably, the first and second vertical gates 111, 112 are maintained at the electrical potential Vi throughout the readout phase of matrix T3, as shown here. The electrical potential Vi turns on the initializing transistor 50.

[0111] According to a first possibility, the application of the electric potential V lowers a potential barrier located between the collection zone 130 and the photosensitive region 120 so that it is lower than potential barriers located between, on the one hand, the photosensitive region 120, and on the other hand, the first and second detection nodes 121, 122.

[0112] According to a second possibility obtained in [Fig. 4C], the electric potential V applied to the first and second vertical grids 111, 112 is sufficient to create an electric field tending to preferentially converge the photogenerated charges towards the collection channel. Since the electric potential gradient is maximal in the direction of the collection zone 130, an electric potential difference ΔV exists between one face of each vertical grid 111, 112 opposite a detection node 121, 122 and an opposite face of the same vertical grid opposite the collection zone 130.

[0113] Figures 5A and 5B show the value of the electrical potential of [Fig. 4C] along horizontal segments [X'o, Xo] intersecting a central axis of the pixel and a lower face of each vertical grid 111, 112 (represented by dashed lines in [Fig. 4C]). In these figures, the electrical potential is given in volts on the y-axis. The x-axis shows the position within the pixel along [X'o, Xo], given in pm. The positions of the peripheral insulation trench 105 and the first and second vertical grids 111, 112 are shown in gray. [Fig. 5A] corresponds to the first embodiment, and [Fig. 5B] to the variant of the first embodiment. The potential difference ΔV is indicated in these figures. It is equal to 126 mV for [Fig.5A] and 111 mV for [Fig.5B]. These values ​​are sufficient for at least 97% of the charges transferred from the photosensitive region 120 to reach the collection area 130.

[0114] Thus, during the reading phase of matrix T3, the initializing transistor 50 has an anti-blooming function for the first and second detection nodes 121, 122, and the reading of the potentials electrical of the first and second detection nodes 121, 122 is not distorted during the reading phase of matrix T3.

[0115] The intermediate value V; is for example greater than or equal to V2. In this example, V; is equal to V2.

[0116] At a certain instant during the read phase of matrix T3, the read phase of line T3.1 begins when the selection transistor 54 is switched on (RD has a high value). A first read of the first and second detection nodes 121, 122 is performed at an instant ts during the read phase of line T3.1, corresponding to sample collection. Subsequently, a voltage spike is applied to the gate of the precharge transistors 52 to initialize the first and second detection nodes 121, 122 to an electrical potential Vechi, Vech2 substantially equal to VRST. Then, a reference potential read of each detection node 121, 122 is taken at an instant tR during the read phase of line T3.1.

[0117] During the initialization phase T1, the first and second vertical grids 111, 112 are simultaneously biased to an electrical potential equal to the third value V3, greater than or equal to V2 and V1. During this phase, the collection channel is conducting independently of the first and second channels. The photosensitive region 120 is therefore cleared of the electrical charges it contains. The photosensitive region 120 is thus initialized, or reset. On the timing diagram, V3 is strictly greater than V2 and equal to 2.5 V. Similarly, the photosensitive region 120 is initialized during the sampling phase T2 between each switching of the first and second electrical signals TGZ1, TGZ2.

[0118] In [Fig.4A], a situation is shown in which TGZ1 and TGZ2 are equal to -0.8 V, allowing a potential barrier to be created between the photosensitive region 120 on one side and the first and second detection nodes 121, 122 and the collection zone 130 on the other. In this case, no photo-generated charges in the photosensitive region 120 are transferred to a detection node 121, 122 or to the collection zone 130.

[0119] Other embodiments of the invention are now described. Only the differences with the first embodiment are explained. For some embodiments, the first and second vertical grids 111, 112 may have other shapes in top view, such as for example an I-shape with or without serifs at the top and / or base of the I. Figures 6A to 6C show examples of pixels having first and second vertical grids 111, 112 in the shape of a bar in top view (“I” without serifs).

[0120] In [Fig. 6A], the initialization contact 163 is positioned at the center of the pixel, similarly to the first embodiment. In [Fig. 6B], the initialization contact 163 is positioned at the periphery of the pixel, similarly to the variant of the first embodiment. [Fig. 6C] represents a situation similar to that of [Fig. 6A], in which the first and second vertical grids 111, 112 have been rotated by 45° around an axis parallel to the Z-axis passing through the center of the pixel.

[0121] The first and second vertical grids 111, 112 may each have only one branch. They then have a general L-shape when viewed from above. Such an example is illustrated in [Fig. 6D]. In this example, the main portions of the first and second vertical grids 111, 112 are not directly opposite each other, but it may be advantageous for them to be so. The initialization contact 163 can occupy any position on the pixel, whether offset or not. The first and second vertical grids 111, 112 can form any angle with the X or Y axes in a plane parallel to the (X, Y) plane.

[0122] According to one contribution of the invention, the pixel area dedicated to initializing the photosensitive region 120 is reduced compared to prior art embodiments. This advantage can be exploited to increase the number of transfer gates per pixel without increasing the pixel size Px. Thus, it is possible to increase the number of samples collected per pixel. Figures 6E to 6G illustrate embodiments of the invention having a number of transfer transistors strictly greater than 2, each comprising a distinct vertical transfer gate, a distinct channel controllable by the vertical gate, and a distinct detection node. All detection nodes and the collection region 130 are doped with the same type of conductivity.

[0123] In these embodiments, the initializing transistor 50 has as many gates as there are transfer gates in the pixel. Each gate of the initializing transistor 50 is a transfer gate of the pixel, enabling the collection of a sample. During operation, charges transferred from the photosensitive region 120 are preferentially transferred to the collection area 130 when all transfer gates are biased to potential V3. When all transfer gates are biased to potential Vi, the initializing transistor 50 provides an anti-glare function during a readout phase of the matrix T3. The readout circuit is configured to apply an electrical signal to each transfer gate so as to alternately conduct a single channel among all the channels associated with a transfer gate and the collection channel 130, and to transfer photogenerated electrical charges through this channel with priority.

[0124] In [Fig. 6E], an embodiment is illustrated featuring three transfer grids for collecting three samples. This has a configuration similar to that of [Fig. 6A], for which a third vertical bar-shaped grid 113 and a third detection node 123 have been added. The third vertical grid 113 is identical to the first and second vertical grids 111, 112. The third detection node 123 is identical to the first and second detection nodes 121, 122.

[0125] In top view, the first, second, and third vertical grids 111, 112, 113 are centered on three consecutive sides of a fictitious square, itself centered on the pixel. The readout circuit further includes a third grid contact 173 in physical contact with the grid electrode 115 of the third vertical grid 113, and a third contact 168 in physical contact with the third detection node 123.

[0126] In an alternative embodiment, the three vertical grids can together be rotated by 45°. The initialization contact 163 can be relocated to the periphery of the pixel.

[0127] In [Fig. 6F], an embodiment is shown featuring four vertical transfer grids for collecting four samples. This embodiment has a configuration similar to that of [Fig. 6E], in which a fourth vertical bar-shaped grid 114 and a fourth detection node 124 have been added. The fourth vertical grid 114 is identical to the other vertical grids. The fourth detection node 124 is identical to the other detection nodes.

[0128] In top view, the four vertical grids are centered on four sides of a fictitious square centered on the pixel. The read circuit further includes a fourth grid contact 174 in physical contact with the grid electrode 115 of the fourth vertical grid 114, and a fourth contact 169 in physical contact with the fourth sensing node 124.

[0129] Figure 6G represents another embodiment comprising four vertical transfer grids. In this embodiment, the vertical grids each have an L-shape in top view.

[0130] Specific embodiments have just been described. Various variants and modifications will be apparent to those skilled in the art.

Claims

Demands

1. A depth image sensor comprising a readout circuit and a plurality of pixels formed in and on a substrate (100) of the sensor, each pixel comprising: • a photosensitive region (120) formed in the substrate (100) and configured to convert photons into electrical charges, • a first detection node (121), a second detection node (122) and a collection zone (130) located above the photosensitive region (120) and doped with a first type of conductivity, • a first transfer transistor (51.1) comprising a first vertical gate (111) and a first channel controllable by the first vertical gate (111), • a second transfer transistor (51.2) comprising a second vertical gate (112) and a second channel controllable by the second vertical gate (112), • an initialization transistor (50) for the multi-gate photosensitive region,comprising the first and second vertical grids (111, 112) and a collection channel controllable by the first and second vertical grids (111, 112), the pixel being such that the first channel, the second channel and the collection channel extend in the substrate (100) between the photosensitive region (120) and, respectively, the first detection node (121), the second detection node (122) and the collection area (130); the readout circuit being configured to apply a first electrical signal (TGZ1) to the first vertical grid (111) and a second electrical signal (TGZ2) to the second vertical grid (112) so as to alternately conduct each of the first channel, the second channel and the collection channel, independently of the other two channels.

2. Sensor according to claim 1, wherein the collection area (130) extends vertically into the substrate (100) deeper than the first and second sensing nodes (121, 122).

3. Sensor according to claim 1 or 2, wherein each pixel further comprises a peripheral isolation trench (105) extending vertically into the substrate (100) from an upper face (100.1) of the substrate (100) and laterally delimiting the photosensitive region (120).

4. Sensor according to claim 3 further comprising a housing (141) doped with a second type of conductivity opposite to the first type of conductivity, in which the housing (141) is in contact with the peripheral insulation trench (105) and is flush with the upper face (100.1) of the substrate (100).

5. Sensor according to claim 4, wherein the peripheral insulation trench (105) comprises a vertical electrode (106) made of a doped semiconductor material of the second type of conductivity.

6. Sensor according to any one of the preceding claims, wherein the first and second vertical grids (111, 112) have respective principal portions opposite each other, symmetrical to each other with respect to a vertical axis of symmetry passing through the center of the pixel and wherein the collection area (130) extends from one principal portion to the other.

7. Sensor according to claim 6 wherein the first and second vertical grids (111, 112) each have a U shape in top view, and wherein the first sensing node (121) and the second sensing node (122) each extend between two opposite branches of the U formed by, respectively, the first vertical grid (111) and the second vertical grid (112).

8. Sensor according to claim 6 or 7, wherein the reading circuit includes an initialization contact (163) and the pixel further includes a peripheral contact area (130.1) of the first type of conductivity, extending the collection area (130) into a peripheral region of the pixel on which the initialization contact (163) rests.

9. Sensor according to any one of the preceding claims, wherein the readout circuit is configured to switch in opposite phase, the first electrical signal (TGZ1) and the second electrical signal (TGZ2) between a first value and a second value so as to alternately make the first channel and the second channel pass during a sampling phase (T2), while keeping the collection channel blocked.

10. Sensor according to claim 9, wherein the readout circuit is configured to assign a third value to the first electrical signal (TGZ1) and the second electrical signal (TGZ2) so as to make the collection channel passable during an initialization phase (T1) of the photosensitive region (120) preceding the sampling phase (T2).

11. Sensor according to claim 10, wherein the plurality of pixels is arranged in a matrix, and wherein the readout circuit is configured to assign an electrical potential equal to an intermediate value to the first and second vertical grids (111, 112) so as to prevent a transfer of photo-generated electrical charges in the photosensitive region (120) to the first and second sensing nodes (121, 122) during a matrix readout phase (T3), the intermediate value being different from the third value.

Images