Dual-port FeRAM cell memory circuit

Abstract

Dual-port FeRAM cell memory circuit. Dual-access memory circuit (100) comprising: - FeRAM cells (102) arranged in rows and columns, each coupled to plate (106) and bit (112A, 112B) lines common to a column; and applying, during a dual access to cells (102.1 - 102.4) belonging to different column groups: - when the cells belong to the same row, electrical potentials of the same values ​​on the bit lines coupled to other cells in the column groups to which the cells belong, or - when the cells belong to different rows, and on the bit lines coupled to other cells belonging to the same rows and columns as the cells, electrical potentials of the same values ​​as those applied to the plate lines coupled to the cells. Figure for the abbreviation: Fig. 1

Description

Title of the invention: Dual-port FeRAM cell memory circuit technical field

[0001] This description relates generally to the field of memory circuits, or memory devices, with dual-port FeRAM cells adapted to implement dual read and / or write access. Previous technique

[0002] Multi-banking of a memory circuit consists of segmenting the memory address space into several distinct banks. These memory banks often have identical capacities to facilitate their design and programming. This memory architecture has the advantage of reducing memory latency while increasing energy efficiency. However, in the case of a memory circuit with multiple (two or more) simultaneous accesses, this architecture does not allow multiple accesses within the same bank, and therefore restricts the flexibility of memory space partitioning to a granularity corresponding to that of the memory circuit's banks. In this case, it is therefore necessary to know the memory architecture to optimize the distribution of the code and / or data to be processed and to avoid simultaneous addressing conflicts.

[0003] Another possible design is that of dual-port memories, which allows simultaneous access to any area of ​​a memory's address space without restrictions on multiple accesses to the same bank, i.e., parallel access to two different memory cells. This design also has the advantage that it is not necessary to know the internal architecture of the memory to program it. It also allows for better scalability of memory space partitioning over the memory's lifetime, particularly between data regions and code or instruction regions. However, this memory architecture may require increasing the area occupied by each memory cell in order to add the extra access port compared to single-port memory cells.It also requires the addition of an address decoder as well as additional read / write input / output ports to manage this second port, thus impacting the total area occupied by memory.

[0004] A dual-port DRAM memory cell can be of type 2T1C, that is, comprising two access transistors coupled to a storage capacitor. The gates of the two access transistors are coupled to separate word lines, one of the source / drain electrodes of each access transistor is One is coupled to the storage capacity, while the other is coupled to a bit line specific to each of the access transistors. The access transistors have identical dimensions. However, a DRAM memory cell, whether single-port or dual-port, has the disadvantage of being volatile. Current leakage that occurs in such a cell necessitates periodically refreshing the data stored within it.

[0005] A dual-port FeRAM memory cell has an architecture similar to that of a dual-port DRAM memory cell, but with a variable-bias memory element made of a ferroelectric material, which renders this type of memory cell non-volatile. Unlike a DRAM memory cell, a FeRAM memory cell therefore does not require refreshing the data stored in the cell. In this type of memory cell, a first electrode of the memory element is coupled to the access transistors, and a second electrode of the memory element is coupled to a plate line to which an electrical potential is applied, the value of which depends on the operation being performed.

[0006] During a read operation of a FeRAM memory cell, the bit line is pre-charged to a low state, or state '0', and its potential is then left floating, while the potential of the plate line transitions from a low state to a high state, or state '1'. This corresponds to the application of a pulse, or "punch," to the plate line. The capacitive coupling of the memory element in the cell will then generate a voltage on the bit line, the magnitude of which depends on whether the '1' or '0' state is stored in that memory element. When writing a '0' state to such a cell, a '0' potential is applied to the bit line, and the '1' potential is applied to the plate line. Writing a '1' state in the cell corresponds to an inverted polarization compared to writing a '0' state: the potential applied to the bit line is in the '1' state and that applied to the plate line is in the '0' state.

[0007] Reading a FeRAM memory cell, like reading a DRAM memory cell, is destructive; that is, the stored data is erased as a result of the reading. It is therefore necessary to implement a "write back" step, i.e., rewriting the read data, when a '1' state is read. This rewriting in the memory cell is implemented immediately after it is read.

[0008] When memory operates in sequential access mode, to perform read or write operations in memory cells with consecutive addresses (as opposed to random access), the access time to the memory cells to perform these read or write operations can be advantageously reduced compared to random access to the same cells Memory is more efficient because the word line(s) coupled to these memory cells do not need to be deactivated and reactivated between successive read or write operations, particularly during burst access. Furthermore, address decoding is not required to determine which memory cells should be used for read or write operations. Sequential memory access also has the advantage of being more robust against side-channel attacks because it eliminates the current surges caused by activating and deactivating word lines and certain address decoding blocks.

[0009] However, during multiple accesses to FeRAM memory cells, address conflicts can occur when word lines associated with different memory cell lines are activated simultaneously. Unselected memory cells connected to these activated word lines, as well as to the same bit lines as the accessed memory cells, may have one of their access transistors disrupted because their VGs voltage becomes greater than their threshold voltage Vt and their VDs voltage becomes greater than the difference (VGS - Vt), which can lead to an undesired change in the values ​​stored in these memory cells. Summary of the invention

[0010] There is a need to propose a dual-access memory circuit that does not have the disadvantages described above, and includes in particular dual-port memory cells that can access two memory cells simultaneously while avoiding address conflicts.

[0011] To this end, one embodiment provides a dual-access memory circuit, comprising at least:

[0012] - FeRAM-type memory cells arranged in rows and columns, each memory cell comprising at least one memory element, a first electrode of which is coupled to a plate line common to a column of memory cells, and at least one first and one second access transistor, each coupled to one of a first and second bit line common to said column of memory cells, and a gate of which is coupled to one of a first and second word line common to a row of memory cells;

[0013] - read amplifiers and write control circuits;

[0014] - interconnection circuits each configured to couple the first and second bit lines and plate lines of a group of memory cell columns to one of the write driver circuits and to at least one of the read amplifiers;

[0015] in which the memory circuit is configured to apply, during a double read and / or write access to first and second memory cells belonging to different memory cell column groups:

[0016] - when the first and second memory cells belong to a same row of memory cells, electrical potentials of the same values ​​on the first and second bit rows coupled to the access transistors of the other memory cells in the groups of memory cell columns to which the first and second memory cells belong, or

[0017] - when the first and second memory cells belong to rows of different memory cells, and on the bit lines coupled to the access transistors in the conducting state of the other memory cells belonging to the same rows and columns of memory cells as the first and second memory cells, electrical potentials of the same values ​​as those applied on the plate lines coupled to the memory elements of the first and second memory cells.

[0018] According to a particular embodiment, the double access is carried out during sequential read and / or write access to at least a part of the memory cells including the first and second memory cells.

[0019] According to a particular embodiment, the memory circuit is configured to apply, during a sequential read and / or write access to memory cells belonging to at least one of the same row of memory cells, electrical potentials of constant values ​​on the first and second word lines common to said at least one of the memory cell lines, for the entire duration of said accesses so as to maintain in the conducting state, for the total duration of said accesses, the access transistors to which the first and second word lines are coupled.

[0020] According to a particular embodiment, each of the interconnection circuits comprises first inputs coupled to the first bit lines of a group of memory cell columns, second inputs coupled to the second bit lines of the group of memory cell columns, third inputs coupled to the plate lines of the group of memory cell columns, a first output configured to be coupled to at least one of the first inputs, a second output configured to be coupled to at least one of the second inputs, and a third output configured to be coupled to at least one of the third inputs.

[0021] According to a particular embodiment:

[0022] - during a read operation of one of the memory cells, the memory circuit is configured to apply to one of the first and second bit lines coupled to said memory cell an electrical potential corresponding to a first state and then a floating electrical potential, and to apply to the plate line coupled to said memory cell an electrical potential corresponding to a second state different from the first state;

[0023] - during an operation to write the first state into one of the memory cells, the memory circuit is configured to apply to one of the first and second bit lines coupled to said memory cell an electrical potential corresponding to the first state, and to apply to the plate line coupled to said memory cell an electrical potential corresponding to the second state;

[0024] - during an operation to write the second state into one of the memory cells, the memory circuit is configured to apply to one of the first and second bit lines coupled to said memory cell an electrical potential corresponding to the second state, and to apply to the plate line coupled to said memory cell an electrical potential corresponding to the first state.

[0025] According to a particular embodiment, the memory circuit is configured to apply, for each of the memory cell columns, the same electrical potential on the first and second bit lines and the plate line of said memory cell column during a preload phase implemented at the beginning or end of an operation cycle including a read operation.

[0026] According to a particular embodiment, the memory cells are configured to store words in the memory cells such that the bits of each word are stored in several groups of memory cell columns.

[0027] According to a particular embodiment, each group of memory cell columns is coupled to two read amplifiers, and the memory circuit is configured to implement dual read access in first and second memory cells belonging to the same memory cell column.

[0028] According to a particular embodiment, all interconnection circuits are controlled by the same control circuit.

[0029] According to a particular embodiment, the gate of each access transistor of each memory cell comprises a single electrically conductive portion.

[0030] According to a particular embodiment, the word lines comprise portions of polysilicon extending into a beginning part of a line of an integrated circuit and metallic portions extending into an end part of a line of the integrated circuit.

[0031] A method for implementing a dual-access memory circuit is also proposed, comprising at least:

[0032] - realization of FeRAM type memory cells arranged in rows and columns, each memory cell comprising at least one memory element, the first electrode of which is coupled to a plate row common to a column of memory cells, and at least one first and one second access transistor, each coupled to one of a first and a second bit row common to said column of memory cells and of which a grid is coupled to one of a first and second word lines common to a line of memory cells;

[0033] - realization of reading amplifiers and writing control circuits;

[0034] - realization of interconnection circuits each configured to couple the first and second bit lines and plate lines of a group of memory cell columns to one of the write driver circuits and to at least one of the read amplifiers;

[0035] in which the memory circuit is configured to apply, during a double read or write access to first and second memory cells belonging to different groups of memory cell columns:

[0036] - when the first and second memory cells belong to a same row of memory cells, electrical potentials of the same values ​​on the first and second bit rows coupled to the access transistors of the other memory cells in the groups of memory cell columns to which the first and second memory cells belong, or

[0037] - when the first and second memory cells belong to rows of different memory cells, and on the bit lines coupled to the access transistors in the conducting state of the other memory cells belonging to the same rows and columns of memory cells as the first and second memory cells, electrical potentials of the same values ​​as those applied on the plate lines coupled to the memory elements of the first and second memory cells.

[0038] According to a particular embodiment, the memory circuit is made in the form of an integrated circuit, and the method comprises a realization of polysilicon portions extending in a beginning part of the line of the integrated circuit and metallic portions extending in an end part of the line of the integrated circuit together forming the word lines.

[0039] A method for controlling memory cells in a memory circuit is also proposed, comprising at least:

[0040] - FeRAM-type memory cells arranged in rows and columns, each memory cell comprising at least one memory element, a first electrode of which is coupled to a plate line common to a column of memory cells, and at least one first and one second access transistor, each coupled to one of a first and second bit line common to said column of memory cells, and a gate of which is coupled to one of a first and second word line common to a row of memory cells;

[0041] - read amplifiers and write control circuits;

[0042] - interconnection circuits each configured to couple the first and second lines of bits and plate lines of a group of columns of memory cells to one of the write control circuits and to at least one of the read amplifiers;

[0043] the method comprising applying, during a double read and / or write access to first and second memory cells belonging to different groups of memory cell columns:

[0044] - when the first and second memory cells belong to a same row of memory cells, electrical potentials of the same values ​​on the first and second bit rows coupled to the access transistors of the other memory cells in the groups of memory cell columns to which the first and second memory cells belong, or

[0045] - when the first and second memory cells belong to rows of different memory cells, and on the bit lines coupled to the access transistors in the conducting state of the other memory cells belonging to the same rows and columns of memory cells as the first and second memory cells, electrical potentials of the same values ​​as those applied on the plate lines coupled to the memory elements of the first and second memory cells.

[0046] According to a particular embodiment, the method further comprises:

[0047] - during a read operation of one of the memory cells, an application of a electrical potential corresponding to a high state on one of the first and second word lines coupled to said memory cell, and an application, on one of the first and second bit lines coupled to said memory cell, of an electrical potential corresponding to a low state then of a floating electrical potential, and an application, on the plate line coupled to said memory cell, of an electrical potential going from a low state to a high state;

[0048] - during an operation to write a low state to one of the memory cells, an application of an electrical potential corresponding to a high state on one of the first and second word lines coupled to said memory cell, and an application, on one of the first and second bit lines coupled to said memory cell, of an electrical potential corresponding to a low state, and an application, on the plate line coupled to said memory cell, of an electrical potential corresponding to a high state;

[0049] - during an operation to write a high state to one of the memory cells, an application of an electrical potential corresponding to a high state on one of the first and second word lines coupled to said memory cell, and an application, on one of the first and second bit lines coupled to said memory cell, of an electrical potential corresponding to a high state, and an application, on the plate line coupled to said memory cell, of an electrical potential corresponding to a low state. Brief description of the drawings

[0050] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0051] - Figure 1 schematically represents memory cells of a memory circuit according to a particular embodiment;

[0052] - Figure 2 schematically represents part of a memory circuit according to a particular embodiment;

[0053] - Figure 3 schematically represents part of a memory circuit according to a particular embodiment;

[0054] - Figure 4 schematically represents polarization signals applied to bit lines and plate lines during sequential access to memory cells of a memory circuit according to a particular embodiment;

[0055] - [Fig. 5] schematically represents an example of the implementation of a circuit interconnection present in a memory circuit according to a particular embodiment;

[0056] - Figures [Fig. 6] and [Fig. 7] schematically represent examples of embodiment of a read amplifier present in a memory circuit according to a particular embodiment;

[0057] - Figures 8, 9 and 10 schematically represent cells memories of a memory circuit according to a particular embodiment, in which operations are carried out simultaneously in two memory cells of the memory circuit. Description of the implementation methods

[0058] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0059] For the sake of clarity, only the steps and elements necessary for understanding the described embodiments have been shown and are detailed. In particular, various elements of the memory circuit (line decoder, control circuit, registers, etc.) and the steps involved in their implementation are not detailed. A person skilled in the art will be able to implement these elements in detail from the functional description given here.

[0060] Unless otherwise specified, when referring to two interconnected elements, this means directly connected without intermediate elements other than conductors, and when referring to two linked or coupled elements (in English "coupled") between them, this means that these two elements can be connected or linked via one or more other elements.

[0061] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures in a normal position of use.

[0062] The terms "row" and "column" are also used in connection with an orientation corresponding to a normal position of use of the memory circuit, although this orientation may be different.

[0063] Unless otherwise specified, the expressions "approximately", "roughly", and "in the order of" mean within 10%, preferably within 5%.

[0064] A memory circuit 100 according to a particular embodiment is described below. The memory circuit 100 comprises at least one matrix of FeRAM memory cells 102. The memory cells 102 are arranged in rows and columns. According to one embodiment, the memory circuit 100 may have between 16 and 1024 rows of memory cells 102 and between 16 and 1024 columns of memory cells 102.

[0065] In the memory circuit 100, a low state or '0' state can correspond to an electrical potential equal to the electrical reference potential of the memory circuit 100, for example the electrical potential of the ground of the memory circuit 100. In addition, a high state or '1' state can correspond to an electrical potential equal to the electrical supply potential of the memory circuit 100.

[0066] A portion of the memory cell matrix 102 is shown in [Fig. 1], this portion comprising here four memory cells 102 belonging to two distinct groups of memory cell columns and to two different rows (adjacent or not) of memory cell 102. In the example of [Fig. 1], the four memory cells 102 shown are designated by the references 102.1 to 102.4.

[0067] Each memory cell 102 comprises at least one FeRAM-type memory element 104, forming a non-volatile storage capacity. Each memory element 104 has a first of its electrodes coupled to a plate line 106 common to the memory cells 102 of the same column of memory cells 102. In the example of [Fig. 1], a first plate line 106 is coupled to the memory elements 104 of the memory cells 102 in the column to which memory cells 102.1 and 102.3 belong, and a second plate line 106 is coupled to the memory elements 104 of the memory cells 102 in the column to which memory cells 102.2 and 102.4 belong.

[0068] Memory cells 102 correspond to dual port memory cells. Each memory cell 102 comprises at least two access transistors 108A, 108B each coupled to one of two word lines 110A, 110B common to the memory cells 102 of the same row of memory cells 102 and to one of two bit lines 112A, 112B common to the memory cells 102 of the same column of memory cells 102. In the example of [Fig.1], in each memory cell 102, the memory element 104 has a second of its electrodes coupled to one of the source or drain electrodes of each of the access transistors 108A, 108B of the memory cell 102.In this particular example, in each memory cell 102, the other source or drain electrode of the access transistor 108A is coupled to the first of the two bit lines 112A associated with the column of memory cells 102 to which that memory cell 102 belongs, and the other source or drain electrode of the access transistor 108B is coupled to the second of the two bit lines 112B associated with the column of memory cells 102 to which that memory cell 102 belongs. Furthermore, in each memory cell 102, the gate of the access transistor 108A is coupled to the first of the two word lines 110A associated with the row of memory cells 102 to which that memory cell 102 belongs, and the gate of the access transistor 108B is coupled to the second of the two word lines 110B associated with the row of memory cells 102 to which that memory cell 102 belongs. .

[0069] The memory cells 102 of the matrix are arranged in groups of columns of memory cells 102, called "Data column", arranged side by side parallel to the word lines 110A, 110B. Each group of columns of memory cells 102 comprises n columns of memory cells 102, with n for example between 2 and 1024 (or even more in some cases), and generally equal to a number that is a power of 2. In addition, the matrix of memory cells 102 may have a number of column groups equal to the sum of the number of bits of the data bus of the memory circuit 100 which is for example 8, 16, 32 or 64, and the number of check bits used to encode parity.

[0070] Figure 2 schematically represents a portion of the memory circuit 100 according to a particular embodiment. To facilitate understanding of the memory circuit 100, it is represented and described, in conjunction with Figure 2, with a limited number of memory cells 102, the actual number of memory cells 102 in the memory circuit 100 being potentially much greater than the number of memory cells 102 shown in Figure 2.

[0071] As shown in [Fig. 2], the memory cells 102 are arranged in four groups of memory cell columns, each group comprising four memory cell columns. Furthermore, only two rows of memory cells 102 are represented. On [Fig.2], the memory cells 102 of a first group of columns are designated by the references "A1" to "H1", the memory cells 102 of a second group of columns are designated by the references "A2" to "H2", the memory cells 102 of a third group of columns are designated by the references "A3" to "H3", and the memory cells 102 of a fourth group of columns are designated by the references "A4" to "H4".

[0072] An arrangement of the memory cells 102 in several groups of columns arranged next to each other parallel to the word lines 110 can be advantageous because it can allow, at the level of an integrated circuit forming the memory circuit 100, a shape well adapted to the space and geometry constraints encountered for this type of circuit.

[0073] According to a particular embodiment, the memory circuit 100 is configured to store words in the memory cell matrix 102 such that the bits of each word stored in the memory cell matrix 102 are stored and distributed in different groups of memory cell columns 102. In the example of [Fig.2], a first 4-bit word is intended to be stored in memory cells A1, A2, A3 and A4, a second 4-bit word is intended to be stored in memory cells B1 to B4, etc., up to an eighth 4-bit word intended to be stored in memory cells H1 to H4.

[0074] In the described embodiment, the memory circuit 100 is configured to perform simultaneous read and / or write access to different memory cells belonging to different column groups. Furthermore, the memory circuit 100 is configured here to operate, in at least one of its operating modes, by sequentially accessing the memory cells 102 column by column for the memory cells 102 in the same row, this access being repeated, for example, for each row of memory cells 102 in the memory circuit 100.

[0075] In the described embodiment, the memory circuit 100 further includes elements for managing access to word lines 110A, 110B. In the described example, this management of access to word lines 110A, 110B is carried out in particular by a line decoder 114 configured to apply electrical potentials to the word lines 110A, 110B in order to turn on access transistors 108A, 108B of the line(s) of memory cells 102 during read and / or write operations in the desired memory cells 102.

[0076] As in the example of [Fig. 2], the memory circuit 100 further includes a control circuit 116 configured to drive, in particular, the line decoder 114. In the example described, during a sequential access to at least one row of memory cells 102, the line decoder 114 is configured to apply electrical potentials of values ​​to the word lines 110A, 110B involved in this sequential access. constants throughout the duration of the access to the memory cell line(s) 102. This allows the access transistors 108A, 108B to which the first and second word lines 110A, 110B are coupled to remain in the conducting state for the total duration of said accesses.

[0077] In the example of [Fig.2], the memory circuit 100 includes one or more pre-charge circuits 118 coupled to the bit lines 112A, 112B and the plate lines 106. In the example of [Fig.2], the memory circuit 100 includes several pre-charge circuits 118, each coupled to the bit lines 112A, 112B and the plate lines 106 of one of the memory cell column groups 102. The pre-charge circuit(s) 118 are configured in particular to apply electrical pre-charge potentials to the bit lines 112A, 112B and the plate lines 106 between the read and / or write operations that will be implemented, and thus have the desired electrical potentials on the bit lines 112A, 112B and the plate lines 106 prior to the implementation of these operations.

[0078] The memory circuit 100 further includes interconnection circuits 120. Each of the interconnection circuits 120 comprises first inputs / outputs coupled to the bit lines 112A, 112B and the plate lines 106 of a group of memory cell columns 102, as well as second inputs / outputs coupled to a common first and second bit line and a common plate line. Each of the interconnection circuits 120 is configured to couple several first bit lines 112A to the first common bit line, several second bit lines 112B to the second common bit line, and several plate lines 106 to the common plate line. In the example described, each group of memory cell columns 102 is coupled to an interconnection circuit 120 distinct from those to which the other group(s) of memory cell columns 102 are coupled.

[0079] An example of an embodiment of such an interconnection circuit 120 is shown schematically in [Fig. 5]. In this example, the circuit 120 includes first transmission gates 130A, 130B, for example of the CMOS type, each connected between one of the bit lines 112A, 112B and the plate line 106 of each of the n columns (designated "COL0" to "COLn1" in [Fig. 5]) of the group of memory cell columns 102 to which the interconnection circuit 120 is coupled. In this example, the interconnection circuit 120 also includes MOS transistors 132A, 132B, each connected between one of the bit lines 112A, 112B and a reference electrical potential such as ground.In this example, the interconnection circuit 120 also includes second transmission gates 134A each connected between one of the first bit lines 112A and a first common bit line 138, second transmission gates 134B each connected between one of the second bit lines 112B and a second. common bit line 140, and second transmission gates 136 each connected between one of the plate lines 106 and a common plate line 142. The common bit lines 138, 140 and the common plate line 142 are coupled to at least one read amplifier 124 ("sense amplifier") and a write driver circuit 122 associated with this interconnection circuit 120.

[0080] In the embodiment shown in [Fig. 5], each of the first transmission gates 130A, 130B is used to couple one of the bit lines 112A, 112B to the plate line 106. Each of the MOS transistors 132A, 132B is used to couple one of the bit lines 112A, 112B to the electrical reference potential, for example during a pre-charge phase of the bit lines 112A, 112B. Each of the second transmission gates 134A, 134B, 136 is used to couple one of the bit lines 112A, 112B or one of the plate lines 106 to one of the common bit or plate lines 138, 140, 142.

[0081] Alternatively, the memory circuit 100 may include interconnection circuits 120 different from the example circuit 120 shown in [Fig.5].

[0082] Fig. 3 represents in more detail components and circuits located at the base of one of the groups of memory cell columns 102 of the memory circuit 100 according to the example described.

[0083] In the example described, all the interconnection circuits 120 are controlled, or driven, by the control circuit 116. In addition, in the example of [Fig.3], the interconnection circuit 120 is represented in the form of n interconnected multiplexers.

[0084] In the example of Figures 2 and 3, the memory circuit 100 further comprises write control circuits 122 coupled to the common bit lines 138, 140 and the common plate lines 142. These write control circuits 122 make it possible to apply, via the interconnection circuits 120, the desired electrical potentials to the bit lines 112A, 112B and the plate lines 106. In the written example, each write control circuit 122 is coupled to a group of memory cell columns 102.

[0085] In the example of Figures 2 and 3, the memory circuit 100 includes several read amplifiers 124 each associated with the common bit lines 138, 140 of one of the groups of memory cell columns 102.

[0086] A first example of an embodiment of a readout amplifier 124 is shown in [Fig. 6]. In this example, the readout amplification is based on the use of two inverters 144 coupled back-to-back. A second example of an embodiment of a readout amplifier 124 is shown in [Fig. 7]. In this example, the readout amplification is based on the use of an operational amplifier 146 configured as an integrator. In both examples, a preload is applied, then a readout current is read and amplified. The readouts The implementations in these two examples empty the charges present in the storage element 104 which is read. Details of the operation of the first and second examples of read amplifier 124 indicated above are described for example in the document by O. Billoint et al., "Charge-based Sense Demonstration in 1T-1C HZO FeRAM Arrays to Overcome CBL-induced Bank Size Limitations", 2024 IEEE International Memory Workshop (IMW), Seoul, Korea, Republic of, 2024, pp. 1-4.

[0087] In the embodiment described here, each group of memory cell columns 102 is coupled to a read amplifier 124. Coupling a single read amplifier 124 to each group of memory cell columns 102 allows simultaneous reading of two memory cells 102 located in different column groups. According to another example, each group of memory cell columns 102 can be coupled to two read amplifiers 124, allowing reading of two different memory cells 102 that may be located in the same column of memory cells 102.

[0088] In the example shown in Figures 2 and 3, the memory circuit 100 further includes SIPO 126 registers (Serial In / Parallel Out). In the example shown in Figures 2 and 3, the memory circuit 100 includes several registers 126, each associated with the bit lines 112A, 112B of one of the memory cell column groups 102, and each having a storage capacity of A bits when the memory cell column groups 102 each have A memory cell columns 102. The use of such SIPO 126 registers allows the memory circuit 100 to be compatible with systems operating at higher frequencies than that of the memory circuit 100, such as when the memory circuit 100 is used in a data logger where write operations are much more frequent than read operations.

[0089] In the example of Figures 2 and 3, the memory circuit 100 further includes D 128 flip-flops such that one or more D 128 flip-flops are associated with each group of memory cell columns 102. The D 128 flip-flops allow the output data to be stored before this data is retrieved and used.

[0090] When the memory circuit 100 performs a sequential access to a row of memory cells 102, the potential applied to one of the two word lines 110 of this row of memory cells 102 is in the state '1' and that applied to the other word line 110 of this row of memory cells 102 is in the state '0'. Figure 4 schematically represents bias signals applied to bit lines 112A, 112B and plate lines 106 during such a sequential access. The PL signal is applied successively to plate lines 106 coupled to the memory cells 102 in which the read and / or write operations are performed. These plate lines 106 are physically distinct from each other so as to sequentially address words whose bits are arranged one after the other as shown in [Fig.2]. Similarly, the BL signal is successively applied to one of the bit lines 112 (the one coupled to the access transistor 108 which is in the conducting state) coupled to the memory cells 102 in which the read and / or write operations are carried out.

[0091] In [Fig. 4], the BL and PL signals correspond to the signals applied to access the memory cells 102 in order to sequentially read or write four words in the memory cell matrix 102. Depending on whether it is a read operation, a write operation to a state '0', or a write operation to a state '1' in one of the memory cells, the BL and PL signals differ. Setting one of the bit lines 112A, 112B or plate line 106 to state '0' or '1' is achieved by connecting an active bias circuit to that bit line 112A, 112B or plate line 106 in order to apply a desired bias voltage value to that line. These biasing circuits correspond, for example, to MOS transistors connecting the desired node to the electrical reference potential or to the electrical supply potential as a function of a control signal emitted by the control circuit 116.This biasing of bit lines 112A, 112B and plate lines 106 is distinct from the high impedance state of these lines in which no active biasing is performed.

[0092] In the example described:

[0093] - during a read operation of one of the memory cells 102, one of the first and the second word line 110A, 110B connected to this memory cell 102 is set to the state '1' so as to make one of the access transistors 108A, 108B conducting, the bit line 112A, 112B coupled to the access transistor 108A, 108B set to the conducting state of the memory cell 102 to be read is pre-charged to the state '0' then its potential is left in the floating state, while the potential applied to the plate line 106 coupled to the memory cell 102 goes from the state '0' to the state '1'. The potential read on the bit line 112A, 112B coupled to the access transistor 108A, 108B in the conducting state is then representative of the state stored in the memory cell 102;

[0094] - during an operation to write a state '0' to one of the memory cells 102, one of the word lines 110A, 110B connected to this memory cell 102 is set to the state '1' so as to make one of the access transistors 108A, 108B conducting, the potential applied to the bit line 112A, 112B coupled to the access transistor 108A, 108B set to the conducting state of the memory cell 102 is in the state '0', while the potential applied to the plate line 106 coupled to the memory cell 102 is in the state '1';

[0095] - during an operation to write a state '1' to one of the memory cells 102, one of the word lines 110A, 110B connected to this memory cell 102 is set to the state '1' so as to make one of the access transistors 108A, 108B conducting, the potential applied on the bit line 112A, 112B coupled to the access transistor 108A, 108B which is turned on by the memory cell 102 is in the state '1', while the potential applied on the plate line 106 coupled to the memory cell 102 is in the state '0'.

[0096] The BL and PL signals shown in [Fig. 4] correspond, during the access performed for each read or write of a word, to a first phase of reading or writing a state '0' (phase 1 called "RD / WR0" in [Fig. 4]), followed by a second phase of writing a state '1' (phase 2 called "WRi" in [Fig. 4]). When a read operation is performed, writing state '1' is only carried out if the value read corresponds to state '1'. In the case of a '0' state write, the value of the BL signal is maintained in the '0' state for the duration of the PL signal pulse (phase 1), and no pulse in the '1' state is then applied to the BL signal during phase 2. In the case of a '1' state write, the value of the BL signal is maintained in the '0' state for the duration of the PL signal pulse (phase 1), and a pulse transitioning from the '0' state to the '1' state is then applied to the BL signal during phase 2.Regardless of the operation implemented, the sequence applied to the PL signal is identical, i.e. a pulse going from state '0' to state '1' during phase 1, and a hold in state '0' during phase 2. Alternatively, when implementing a write operation, phase 2 can be implemented before phase 1.

[0097] In a particular configuration, the memory circuit 100 is configured to apply, for each of the memory cell columns 102, the same electrical potential to the bit lines 112A, 112B and the plate line 106 of said memory cell column 102 during a preload phase implemented between two read and / or write operations. This equality of electrical potential between the bit lines 112A, 112B and the plate lines 106 can be ensured by transmission gates (or "pass gates") such as those previously described for the interconnection circuit 120 in [Fig. 5]. This same potential will be ground in the example described. The preload phases are not shown in the signals in [Fig. 4].

[0098] To avoid address conflicts during dual access to memory cells 102 belonging to different rows and different column groups, the memory circuit 100 is configured to apply, during such multiple read and / or write access, to the bit lines 112A, 112B coupled to the access transistors 108A, 108B, to the on-state of the other memory cells 102 belonging to the same rows and columns as the first and second memory cells 102, biasing electrical potentials of the same values ​​as those applied to the plate lines 106 coupled to the memory elements 104 of the first and second memory cells 102. Thus, the memory cells 102 do not not being accessed for reading and / or writing but being located on the same rows and columns as the memory cells 102 being accessed for such purposes are thus protected from unwanted reading or writing.

[0099] By way of illustration, considering the memory cells 102.1 - 102.4 shown in [Fig. 1], we describe below an operation of writing a state '0' in memory cell 102.1 carried out simultaneously with an operation of writing a state '1' in memory cell 102.4. The values ​​of the potentials applied on the word lines 110A, 110B, the bit lines 112A, 112B and the plate lines 106 of these memory cells 102.1 - 102.4 are shown in the diagram in [Fig. 8].

[0100] With such a biasing of the plate lines 106, the word lines 110A, 110B, and the bit lines 112A, 112B, the voltage VGs of one of the access transistors 108A, 108B of each of the memory cells 102.1 and 102.4 is greater than the threshold voltage Vt of these access transistors 108A, 108B, and their voltage VDs becomes greater than the difference (VGs - Vt). Currents then flow in these transistors, represented by arrows in [Fig. 8], resulting in the writing of a state '0' in memory cell 102.1 and a state '1' in memory cell 102.4.

[0101] To prevent a '1' state from being written to memory cell 102.2, the potential of bit line 112A coupled to access transistor 108A in the on state of memory cell 102.2 is defined as being equal to that of plate line 106 coupled to memory cell 102.2, i.e., set to the '0' state. Similarly, to prevent a '0' state from being written to memory cell 102.3, the potential of bit line 112B coupled to access transistor 108B in the on state of memory cell 102.3 is defined as being equal to that of plate line 106 coupled to memory cell 102.3, i.e., set to the '1' state. By applying such potentials, the VDs voltages of the access transistors 108A, 108B, being in the conducting state, memory cells 102 located in the same rows and columns as the memory cells 102 being read and / or written to are maintained at 0V, thus preventing a write to these memory cells 102..

[0102] In general, the memory circuit 100 can operate in different configurations to perform simultaneous access to two memory cells 102 belonging to different column groups. Thus, when the first and second memory cells 102 belong to the same row of memory cells 102, electrical potentials of the same value can be applied to the first and second bit lines 112A, 112B coupled to the access transistors 108A, 108B of the other memory cells 102 in the column groups of memory cells 102 to which the first and second memory cells belong. Such a configuration is shown schematically in [Fig. 9], on which examples of The electrical potentials applied to word lines 110A, 110B, bit lines 112A, 112B and plate lines 106 are indicated.

[0103] As previously stated, each group of memory cell columns 102 can be coupled to two read amplifiers 124 to perform a read of two different memory cells 102 located in the same column of memory cells 102, thus using two different word lines 110 coupled to the same group of memory cell columns 102, the data being read on each of the first and second bit lines 112A, 112B of this memory cell column 102. Such a configuration is shown schematically in [Fig. 10], on which examples of electrical potentials applied to the word lines 110A, 110B, the bit lines 112A, 112B and the plate lines 106 are indicated.

[0104] Alternatively, it is possible to implement any type of operation (read and / or write) simultaneously within two memory cells belonging to the same column group. In this case, the interconnection circuits 120 are such that the potentials applied to each of the bit lines 112A, 112B of the different columns within the same column group can be controlled independently of each other.

[0105] In the various embodiments described above, the values ​​of the electrical potentials applied to the bit lines 112A, 112B and the plate lines 106 are given considering the connection direction of the electrodes of the memory elements 104 to the access transistors 108A, 108B and to the plate lines 106. Alternatively, similar operations can be performed for memory elements 104 whose connection direction is reversed compared to the examples described above, by applying complementary electrical potentials (high state when a low state is described, and low state when a high state is described) to the bit lines 112A, 112B and the plate lines 106 compared to the examples described above.

[0106] In one embodiment of the memory circuit 100, each of the dual-port memory cells 102 can occupy a semiconductor area substantially equal to that of a single-port 1T1C memory cell. Indeed, in a 1T1C memory cell, the gate of the single transistor is generally made in the form of two separate fingers, for reasons of integration and continuity of the active area throughout an entire memory matrix, particularly in sub-22nm technology. To avoid occupying a larger semiconductor area, in each of the 2T1C type memory cells 102, each of the access transistors 108 can have a gate made in the form of a single finger. For example, in 22 nm technology, a 102 memory cell can occupy a semiconductor surface with a width of 400 nm and a height of 250 nm, or an area of ​​0.1 pm2.

[0107] In an example embodiment of the memory circuit 100, the word lines 110A, 110B comprise electrically conductive portions of polysilicon extending into a part of the FEOL (Front-End Of Line) of the integrated circuit forming the memory circuit 100. In order to minimize the propagation time of electrical signals in the word lines 110A, 110B, it is possible to couple, at regular intervals, these portions of polysilicon to other conductive portions located in a higher metal level belonging to the BEOL (Back-End Of Line) of the integrated circuit, for example in metal level 2.Advantageously, these connections between the polysilicon portions and the conductive portions in a higher metal level are made by spacing these connections from each other such that at least 16 memory cells 102 are interposed between two neighboring connections, and for example such that at most 256 memory cells 102 are interposed between two neighboring connections, which makes it possible to minimize the propagation time of the signals in the word lines 110 while limiting the semiconductor surface occupied by these connections.

[0108] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.

[0109] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.

Claims

1. Demands Dual-access memory circuit (100), comprising at least: - FeRAM type memory cells (102) arranged in rows and columns, each memory cell comprising at least one memory element (104) of which a first electrode is coupled to a plate row (106) common to a column of memory cells, and at least one first and one second access transistor (108A, 108B) each coupled to one of a first and a second bit row (112A, 112B) common to said column of memory cells and of which a gate is coupled to one of a first and a second word row (110A, 110B) common to a row of memory cells; - read amplifiers (124) and write control circuits (122); - interconnection circuits (120) each configured to couple the first and second bit lines and plate lines of a group of memory cell columns to one of the write driver circuits and to at least one of the read amplifiers; in which the memory circuit is configured to apply, during a double read and / or write access to first and second memory cells (102.1 - 102.4) belonging to different memory cell column groups: - when the first and second memory cells belong to the same row of memory cells, electrical potentials of the same values ​​on the first and second bit lines coupled to the access transistors of the other memory cells in the groups of memory cell columns to which the first and second memory cells belong, or - when the first and second memory cells belong to different memory cell rows, and on the bit lines coupled to the access transistors in the conducting state of the other memory cells belonging to the same rows and columns of cells memories than the first and second memory cells, electrical potentials of the same values ​​as those applied to the plate lines coupled to the memory elements of the first and second memory cells.

2. Memory circuit (100) according to claim 1, wherein the dual access is performed during sequential read and / or write access to at least a portion of the memory cells (102) including the first and second memory cells (102.1 - 102.4).

3. Memory circuit (100) according to claim 2, configured to apply, during a sequential read and / or write access to memory cells (102) belonging to at least one of the same row of memory cells (102), electrical potentials of constant values ​​on the first and second word lines (110A, 110B) common to said at least one of the rows of memory cells (102), for a whole duration of said accesses so as to maintain in the conducting state, for the total duration of said accesses, the access transistors (108A, 108B) to which the first and second word lines (110A, 110B) are coupled.

4. Memory circuit (100) according to any one of the preceding claims, wherein each of the interconnection circuits (120) comprises first inputs coupled to the first bit lines (112A) of a group of memory cell columns (102), second inputs coupled to the second bit lines (112B) of the group of memory cell columns (102), third inputs coupled to the plate lines (106) of the group of memory cell columns (102), a first output configured to be coupled to at least one of the first inputs, a second output configured to be coupled to at least one of the second inputs, and a third output configured to be coupled to at least one of the third inputs.

5. Memory circuit (100) according to any one of the preceding claims, wherein: - during a read operation of one of the memory cells (102), the memory circuit (100) is configured to apply to one of the first and second bit lines (112A, 112B) coupled to said memory cell (102) an electrical potential corresponding to a first state and then a potential floating electrical potential, and to apply to the plate line (106) coupled to said memory cell (102) an electrical potential corresponding to a second state different from the first state; - during a write operation of the first state in one of the memory cells (102), the memory circuit (100) is configured to apply to one of the first and second bit lines (112A, 112B) coupled to said memory cell (102) an electrical potential corresponding to the first state, and to apply to the plate line (106) coupled to said memory cell (102) an electrical potential corresponding to the second state;- during a write operation of the second state in one of the memory cells (102), the memory circuit (100) is configured to apply to one of the first and second bit lines (112A, 112B) coupled to said memory cell (102) an electrical potential corresponding to the second state, and to apply to the plate line (106) coupled to said memory cell (102) an electrical potential corresponding to the first state.;

6. Memory circuit (100) according to any one of the preceding claims, configured to apply, for each of the memory cell columns (102), the same electrical potential on the first and second bit lines (112A, 112B) and the plate line (106) of said memory cell column (102) during a preload phase implemented at the beginning or end of an operation cycle including a read operation.

7. Memory circuit (100) according to any one of the preceding claims, wherein the memory cells (102) are configured to store words in the memory cells (102) such that the bits of each word are stored in several groups of columns of memory cells (102).

8. A memory circuit (100) according to any one of the preceding claims, wherein each group of memory cell columns (102) is coupled to two read amplifiers (124), and wherein the memory circuit (100) is configured to implement dual read access in the first and second memory cells (102.1 - 102.4) belonging to the same column of memory cells (102).

9. Memory circuit (100) according to any one of the preceding claims, wherein all interconnection circuits (120) are driven by the same control circuit (116).

10. Memory circuit (100) according to any one of the preceding claims, wherein the gate of each access transistor (108) of each memory cell (102) has a single electrically conductive portion.

11. Memory circuit (100) according to any one of the preceding claims, wherein the word lines (110) comprise polysilicon portions extending into a beginning-of-line portion of an integrated circuit and metallic portions extending into an end-of-line portion of the integrated circuit.

12. Method of making a dual-access memory circuit (100), comprising at least: - making FeRAM-type memory cells (102) arranged in rows and columns, each memory cell comprising at least one memory element (104) of which a first electrode is coupled to a plate row (106) common to a column of memory cells, and at least one first and one second access transistor (108A, 108B) each coupled to one of a first and a second bit row (112A, 112B) common to said column of memory cells and of which a gate is coupled to one of a first and a second word row (110A, 110B) common to a row of memory cells; - making read amplifiers (124) and write control circuits (122);- realization of interconnection circuits (120) each configured to couple the first and second bit lines and plate lines of a group of memory cell columns to one of the write driver circuits and to at least one of the read amplifiers; wherein the memory circuit is configured to apply, during a double read or write access to the first and second;

13.

14. memory cells (102.1 - 102.4) belonging to different memory cell column groups: - when the first and second memory cells belong to the same row of memory cells, electrical potentials of the same values ​​on the first and second bit lines coupled to the access transistors of the other memory cells in the groups of memory cell columns to which the first and second memory cells belong, or - when the first and second memory cells belong to different memory cell rows, and on the bit lines coupled to the access transistors in the conducting state of the other memory cells belonging to the same memory cell rows and columns as the first and second memory cells, electrical potentials of the same values ​​as those applied on the plate lines coupled to the memory elements of the first and second memory cells. Method according to claim 12, wherein the memory circuit (100) is made in the form of an integrated circuit, and comprising an embodiment of polysilicon portions extending in a beginning part of the line of the integrated circuit and metallic portions extending in an end part of the line of the integrated circuit together forming the word lines (110). Method for controlling memory cells (102) of a memory circuit (100) comprising at least: - FeRAM type memory cells (102) arranged in rows and columns, each memory cell comprising at least one memory element (104) of which a first electrode is coupled to a plate row (106) common to a column of memory cells, and at least one first and one second access transistor (108A, 108B) each coupled to one of a first and a second bit row (112) common to said column of memory cells and of which a gate is coupled to one of a first and a second word row (110A, 110B) common to a row of memory cells;

15. - read amplifiers (124) and write control circuits (122); - interconnection circuits (120) each configured to couple the first and second bit lines and plate lines of a group of memory cell columns to one of the write driver circuits and to at least one of the read amplifiers; the method comprising the application, during a double read and / or write access to first and second memory cells (102.1, 102.4) belonging to different memory cell column groups: - when the first and second memory cells belong to the same row of memory cells, electrical potentials of the same values ​​on the first and second bit lines coupled to the access transistors of the other memory cells in the groups of memory cell columns to which the first and second memory cells belong, or - when the first and second memory cells belong to different memory cell rows, and on the bit lines coupled to the access transistors in the conducting state of the other memory cells belonging to the same memory cell rows and columns as the first and second memory cells, electrical potentials of the same values ​​as those applied on the plate lines coupled to the memory elements of the first and second memory cells. The method according to claim 14, further comprising: - during a read operation of one of the memory cells (102), an electrical potential corresponding to a high state is applied to one of the first and second word lines (110A, 110B) coupled to said memory cell (102), and an electrical potential corresponding to a low state is applied to one of the first and second bit lines (112A, 112B) coupled to said memory cell (102), followed by an electrical potential floating, and an application, on the plate line (106) coupled to said memory cell (102), of an electrical potential passing from a low state to a high state; during an operation of writing a low state in one of the memory cells (102), an application of an electrical potential corresponding to a high state on one of the first and second word lines (110A, 110B) coupled to said memory cell (102), and an application, on one of the first and second bit lines (112A, 112B) coupled to said memory cell (102), of an electrical potential corresponding to a low state, and an application, on the plate line (106) coupled to said memory cell (102), of an electrical potential corresponding to a high state; during an operation of writing a high state into one of the memory cells (102), an application of an electrical potential corresponding to a high state on one of the first and second word lines (110A, 110B) coupled to said memory cell (102), and an application, on one of the first and second bit lines (112A, 112B) coupled to said memory cell (102) of an electrical potential corresponding to a high state, and an application, on the plate line (106) coupled to said memory cell (102), of an electrical potential corresponding to a low state.

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