Method for measuring the phase of a complex impedance and measuring apparatus

Abstract

The invention relates to a method for measuring the phase of a complex impedance of an electrical element (EL), comprising the following steps: applying an excitation signal (Sex) to the electrical element; acquiring a first analog signal (uV); acquiring a second analog signal (uI); digitizing the first analog signal into a first digital signal (μ) and the second analog signal into a second digital signal (μ); injecting the first digital signal into the turn-on input of a first time-to-digital converter and into the turn-off input of a second time-to-digital converter; injecting the second digital signal into the turn-off input of the first time-to-digital converter and into the turn-on input of the second time-to-digital converter; determining a first delay value t1 and a second delay value t2; calculating the phase value of the complex impedance of the electrical element. Figure for the abstract: Fig. 5

Description

Title of the invention: Method for measuring phase of a complex impedance and measuring device

[0001] The invention lies in the field of electronic instrumentation. It relates to more specifically on a method and apparatus for measuring impedance complex of an electrical element.

[0002] The notion of complex impedance generalizes that of resistance for signals sinusoidal at a given frequency f. In the case of an electrical dipole, the impedance The complex number Z is defined by Z - j- where U is the phasor (complex number) representing the amplitude and phase of the voltage across the dipole and I the phasor representing the amplitude and phase of the current flowing through it. More generally, in the case of an N-port circuit (the dipole corresponding to the case N=1) we can define an impedance 7 1 . In other words, the impedance Zÿ- is the (complex) ratio between the lJ~ The phasor represents the voltage across port "i" and the phasor represents the current entering (or leaving, depending on the convention adopted) port "j" when the current entering all other ports is zero. The various Zy terms form the impedance matrix of the multiport element. In the following, the term impedance and the symbol "Z" will be used to refer to both the impedance of a two-terminal device and a Zy term in the impedance matrix of a multiport.

[0003] Being a complex number, the impedance Z of an electrical element can be decomposed into a real part and an imaginary part – Z = R + jX, where “j” here denotes the imaginary unit – or into magnitude and phase: Z = IZIe^, where IZI is the ratio between the RMS values ​​of the voltage and the current, and θ is their phase shift. The phase of the impedance corresponds to the time lag between the voltage across the electrical element and the current flowing through the electrical element.

[0004] In general, impedance varies with the frequency of the electrical signals considered. To characterize an electrical element, it is therefore necessary to measure its impedance(s) over a more or less wide frequency band. We therefore write Z(f), IZ(f)l and <p(f) pour désigner, respectivement, une impédance complexe, son module et sa phase en fonction de la fréquence f (ou de manière équivalente en fonction de sa période T=l / f).

[0005] Several techniques have been developed to measure the phase of the impedance, <p(f), d’un élément électrique en fonction de la fréquence.

[0006] Among the methods known in the prior art, the delay / (y) (or the phase shift) <p(f), si multiplié par 2r / T) entre les signaux numérisés Üy et Üj de la tension uv aux terminals of the electrical element and current u; the current through is measured from a time-to-digital converter (TDC or "Time-to-Digital Converter" according to the commonly used Anglo-Saxon name) comprising N delay element, where each delay element has a transition time T.

[0007] This TDC architecture is a conventional architecture that can be easily implemented, particularly in systems based on field-programmable gate arrays (FPGA or "Field-Programmable Gate Array" according to the commonly used Anglo-Saxon term).

[0008] The complexity of integrating TDC into an FPGA depends on multiple factors:

[0009] - The transition time r of the logical element of the delay line. A value A small T allows for very precise time measurements, but can lead to overly complex TDC integration if the time dynamics to be measured are much larger than T. The minimum value of T is defined by the targeted FPGA technology.

[0010]

[0011]

[0012]

[0013] - The maximum frequency to be generated to perform the frequency sweep for the impedance phase measurement. A high frequency results in short period values, and therefore, small delays to be measured, which requires a very small value for accurate measurements. The accuracy in estimating <p(f) sera donc déterminée par le FPGA utilisé. - the minimum frequency f to be generated to perform the frequency sweep for the impedance phase measurement. A low frequency is associated with high periods and therefore, for a full dynamic phase measurement (0-2ir), with a very complex TDC in terms of the number of delay elements and flip-flops. It is therefore necessary to find a compromise between the measurement dynamics ( / f ) and the resolution of the TDC determined by the value T. J min To measure a phase range from 0 to 2Φ, it is necessary to design a delay line comprising a large number of delay elements. Consequently, FPGA integration exhibits significant dispersion phenomena due to the non-uniformity of the logic cells and the internal routing of signals and blocks within the FPGA.

[0014] The error Aq>(f) on the phase estimation also exhibits a strong asymmetry with respect to the estimated phase (see [Fig.4]), which is a handicap for post-processing algorithms.

[0015] (Mattada et al. 2021) proposes a system to reduce the error in phase estimation by using complex TDCs, designed from multiple phase-locked loop (PLL) counters. (according to the commonly used Anglo-Saxon term) and delay lock loop counters (DLL or "Delay Locked Loop" according to the commonly used Anglo-Saxon term).

[0016] Moreover, no prior art document deals with imperfections giving an asymmetry in the phase estimation error.

[0017] There is therefore a need to make the phase estimation error symmetrical and low in the context of an integration of conventional TDCs in an FPGA.

[0018] Other features, details and advantages of the invention will become apparent from the description given with reference to the accompanying drawings provided by way of example, which represent, respectively:

[0019] [Fig. 1], the functional diagram of a measuring device not falling within the scope of the invention;

[0020] [Fig.2], an illustration of the operating principle of the device in [Fig.1];

[0021] [Fig.3] is a functional diagram of a phase measurement device from a TDC based on a delay line;

[0022] [Fig.4] is a graph illustrating the dependence of said phase measurement error on the phase of the measured complex impedance.

[0023] [Fig.5] is a functional diagram of a measuring device according to an embodiment of the invention;

[0024] [Fig.6] is a functional diagram of a measuring device according to another embodiment of the invention;

[0025] In the algorithms presented in the following description, the symbol “&” is equivalent to the logical operator “AND”, the symbol “I” is equivalent to the logical operator “OR”.

[0026] Fig. 1 is the functional diagram of a hypothetical measuring device which, in principle, allows the phase shift between two sinusoidal analog signals uv and u to be measured. If these two signals are representative, respectively, of the voltage across an electrical element and the current flowing through it, this phase shift measurement makes it possible to determine the phase of the complex impedance of the element.

[0027] The device in [Fig. 1] comprises two Schmitt flip-flops BS1, BS2 having two threshold voltages VLh>0 V and VHl<0 V. The output of a Schmitt flip-flop goes high when the signal at its input exceeds VLh, and then remains high as long as said signal falls below VHl. For VLh0 V and VHl0 V, the Schmitt flip-flop becomes a simple zero comparator. If such a comparator were used, electronic noise would induce multiple and random switching operations when the input signal crosses zero; for this reason, it is generally preferable to use flip-flops. Schmitt flip-flops - also called hysteresis comparators - with a hysteresis AV = VLH - VHl of the same order of magnitude as the peak amplitude of the noise affecting the input signal.

[0028] The Schmitt flip-flops convert the sinusoidal input signals uv and u; two square wave signals Ûy and Ûj respectively. A time-to-digital converter (TDC) receives these signals as input and provides at its output a digital value aT, which constitutes an estimate of the time shift AT between the rising (or, equivalently, falling) edges of these signals. As can be seen in [Fig. 2], this time shift is in turn proportional to the phase shift q between the two analog input signals uv and u;. Thus, the digital output of the TDC constitutes (up to a multiplicative factor equal to the frequency f of the input signals) an estimate of this phase shift.

[0029] The operating principle of a time delay converter (TDC) is to measure, in multiples of time units T, the delay between the signals Üy and Ûj. To do this, the signal Üy is injected into a delay line comprising N delay elements, where each delay element has a transition time r, as can be seen in [Fig. 3]. This delay element can be implemented from a logic gate (e.g., NOT, OR, AND) or an arithmetic block (e.g., adder, multiplier), or any other asynchronous logic block with a fixed delay. The time measurement is performed at the instant of the rising edge of Üj. At this instant, the output state of each delay element is recorded at the output of the flip-flops. The delay ï between the rising edges of Üy and Üj is approximated by t = Nt, with N the position of the flip-flop where an output value transition from logic '1' to logic '0' occurs.The frequency <p(f) est estimée grâce à la connaissance à priori de la fréquence (et la période) du signal uv, qui est généré par le système de mesure. .

[0030] For a TDC integrated into a Xilinx ZYNQ 7010 type FPGA, the delay element is a 2-bit adder with carry, with a transition time r = 585 ps. The TDC is designed to operate at frequencies ranging from 6 MHz to 10 MHz. With a minimum frequency around 6 MHz (period T = 166 ns), it is necessary to integrate a delay line of approximately 300 elements to be able to measure a phase range from 0 to 2 ir. As explained above, such FPGA integration is subject to significant dispersion phenomena due to the non-uniformity of the logic cells and the internal routing of signals and blocks within the FPGA.

[0031] For a transition time T = 585 ps and an injected signal Üy at a frequency λ = 8.5 MHz, the resolution given by the transition time T represents a phase of 1.8°. As shown in [Fig. 4], in this configuration, the error is less than the resolution for the measurement interval over the interval [0°-40°]. Subsequently, the Dispersion generates an error of 2 times the resolution over the interval [40°-250°]. Over the interval [250°-360°], the error is greater than 3 times the resolution.

[0032] One idea underlying the invention is that a different TDC for each phase interval can be used to reduce the error in the phase estimation.

[0033] Fig. 5 illustrates the functional diagram of a device according to a first embodiment of the invention, implementing this principle.

[0034] In [Fig. 5], the reference EL represents an electrical element (more particularly, a dipole, comprising two terminals forming a single port) whose complex impedance phase is to be determined. A generator GS applies a sinusoidal excitation signal sext(t), of frequency θ possibly variable, to the terminals of the element EL. The signal sext(t) can be a current or voltage signal. The generator GS also provides at its output a numerical value representative of the frequency f. The generator GS can, for example, be driven such that f sweeps, continuously or discretely, a spectral band of interest.

[0035] The device in [Fig. 5] receives, at a first input port, the first analog signal uv(t) representing the voltage across element EL, and at a second input port, the second analog signal ut(t) representing the current flowing through it. For example, the signal uv(t) can be directly the voltage across element EL, and ut(t) a voltage across a resistor connected in series with EL. The signals uv(t) and ut(t) are fed into respective Schmitt flip-flops BS1 and BS2, which output square wave signals Ûv and Ûr.

[0036] The output of the first Schmitt flip-flop BS1 is connected to the turn-on input (the "START" input, according to the commonly used Anglo-Saxon terminology) of a first time-to-digital converter TDC1 and to the turn-off input (the "STOP" input, according to the commonly used Anglo-Saxon terminology) of a second time-to-digital converter TDC2 of the device in [Fig. 5]. Preferably, the output of the first Schmitt flip-flop BS1 is connected directly to the turn-on input of TDC1 and to the turn-off input of TDC2, such that no other component is connected in series between BS1 and the turn-on input of TDC1, nor between BS1 and the turn-off input of TDC2. Alternatively, a dipole is connected in series between BS1 and the switch-on input of TDC1 or between BS1 and the switch-off input of TDC2. The dipole is, for example, a current sensor.

[0037] The output of the second Schmitt flip-flop BS2 is connected to the trigger input of the first time-to-digital converter TDC1 and to the turn-on input of the second time-to-digital converter TDC2. Preferably, the output of the second Schmitt flip-flop BS1 is connected directly to the trigger input of TDC1 and the turn-on input of TDC2. of TDC2 in the sense that no other dipole is connected in series between BS2 and the trigger input of TDC1, nor between BS2 and the energizing input of TDC2. Alternatively, a dipole is connected in series between BS2 and the trigger input of TDC1 or between BS2 and the energizing input of TDC2. The dipole is, for example, a current sensor.

[0038] The first time-to-digital converter TDC1 is configured to measure a delay value ti between the rising edge of the digital signal injected at the on input and the rising edge of the digital signal injected at the trigger input. Equivalently, the first time-to-digital converter TDC1 is configured to measure a delay value ti between the falling edge of the digital signal injected at the on input and the falling edge of the digital signal injected at the trigger input.

[0039] The second time-to-digital converter TDC2 is configured to measure a delay value t2 between the rising edge of the digital signal injected at the trigger input and the rising edge of the digital signal injected at the turn-on input. Equivalently, the second time-to-digital converter TDC2 is configured to measure a delay value ti between the falling edge of the digital signal injected at the trigger input and the falling edge of the digital signal injected at the turn-on input.

[0040] The device in [Fig. 5] also includes a calculation unit UC configured to calculate the phase value of the complex impedance of the electrical element EL, either as a function of ti for ti <S0, soit en fonction de t2 pour Si<ti<S2, dans lequel So, Si et S2 sont trois valeurs seuil, avec S0<Si<S2.

[0041] As explained above, the delay is estimated by the formula / = Nt- When ti <S0, le retard t est égal au temps tb 0 étant calculé à partir du premier convertisseur temps-numérique TDC1, qui est dans une configuration conventionnelle, celui-ci mesurant une valeur de retard entre le front montant de Ûj et le front montant {Jy-

[0042] When If <ti<S2, le retard t est égal à (S2-12), t2 étant calculé à partir du deuxième TDC2 is a digital-time converter, which is in a configuration opposite to that of the first digital-time converter TDC1. In this configuration, the second digital-time converter TDC2 measures a delay value between the rising edge of Ûy and the rising edge of Ûj-. Consequently, the value Nt measured by the second digital-time converter TDC2 corresponds to the value (S2-i).

[0043] Preferably, S0=Si=T / 2 and S2=T. For ti <T / 2, le retard t est égal au temps tb Pour T / 2<ti<T ou ti=0, la valeur de retard t est égale à (T-t2). Pour les phases inférieures à 180°, le retard t est évalué par le premier convertisseur temps-numérique TDC1 qui mesure le retard du front montant de Ûy par rapport au front montant Üj- For phases greater than 180°, the delay î is evaluated by the second time-to-digital converter TDC2, which measures the delay of the rising edge relative to the rising edge Ûy-

[0044] The time-to-digital converter TDC1 is configured to return a zero value (0=0) when the measured delay value is greater than half the period of the first digital signal Ûy-

[0045] According to the first embodiment of the invention, the measurement algorithm for estimating the delay t is as follows:

[0046] (Zl<f)^ = ï|(tl> T)[ti==0)^ = T_t2

[0047] According to the first embodiment, all TDCs only need to be able to measure a delay value up to Tmax / 2.

[0048] Advantageously, the delay ti or t2 used for evaluating the delay t is always less than 180° for a frequency of the first digital signal Vy equal to f. The measured delay t can be greater than 180° if the frequency of the first digital signal LTy is greater than f. This makes it possible to limit the complexity of the TDCs used, particularly in terms of the number of delay elements, and to reduce the error in estimating the phase of the impedance of the electrical element EL. The invention also makes the error in estimating the phase of the impedance of the electrical element EL more phase-symmetrical.

[0049] Figure 6 illustrates the functional diagram of a device according to a second embodiment of the invention, implementing this principle.

[0050] According to this embodiment, the device also includes, compared to the first embodiment, a third time-to-digital converter TDC3 and a fourth time-to-digital converter TDC4.

[0051] The output of the first Schmitt flip-flop BS1 is connected to the turn-on input of the fourth time-to-digital converter TDC4 and to the turn-off input of the third time-to-digital converter TDC3 of the device in [Fig. 5]. Preferably, the output of the first Schmitt flip-flop BS1 is connected directly to the turn-on input of TDC4 and to the turn-off input of TDC3, such that no other component is connected in series between BS1 and the turn-on input of TDC4, nor between BS1 and the turn-off input of TDC3. Alternatively, a component is connected in series between BS1 and the turn-on input of TDC4 or between BS1 and the turn-off input of TDC3. The component is, for example, a current sensor.

[0052] The output of the second Schmitt flip-flop BS2 is connected to the trigger input of the fourth time-to-digital converter TDC4 and to The turn-on input of the third time-to-digital converter, TDC3. Preferably, the output of the second Schmitt flip-flop, BS1, is connected directly to the turn-on input of TDC4 and the turn-on input of TDC3, such that no other component is connected in series between BS2 and the turn-on input of TDC4, nor between BS2 and the turn-on input of TDC3. Alternatively, a component is connected in series between BS2 and the turn-on input of TDC4 or between BS2 and the turn-on input of TDC3. This component could be, for example, a current sensor.

[0053] The third time-to-digital converter TDC3 is configured to measure a delay value t3 between the rising edge of the digital signal injected at the switch input and the falling edge of the digital signal injected at the trigger input. Equivalently, the third time-to-digital converter TDC3 is configured to measure a delay value t3 between the falling edge of the digital signal injected at the switch input and the rising edge of the digital signal injected at the trigger input.

[0054] The fourth time-to-digital converter TDC4 is configured to measure a delay value t4 between the falling edge of the digital signal injected at the trigger input and the rising edge of the digital signal injected at the energize input. Equivalently, the fourth time-to-digital converter TDC4 is configured to measure a delay value t4 between the rising edge of the digital signal injected at the trigger input and the falling edge of the digital signal injected at the energize input.

[0055] As described above, for TDCs 1, 2, and 4, the delay t between the rising or falling edges of Ûy and Ûj is approximated by t = AV, where N is the position of the flip-flop where an output value transition from logic '1' to logic '0' occurs. For TDC3, the delay î between the falling edge of the digital signal Ûy injected at the turn-on input (Uy) and the rising edge of the digital signal Ûj injected at the turn-off input is approximated by t = Nt, where N is the position of the flip-flop where an output value transition from logic '0' to logic '1' occurs.

[0056] In this embodiment, the calculation unit UC is configured to calculate the phase value of the complex impedance of the electrical element EL, either as a function of ti for ti <S0, soit en fonction de t2 pour Si<ti<S2, soit en fonction de t3 pour So< 0< Sœ, soit en fonction de t4 pour S0 <ti<Si, dans lequel So, S0’ Si et S2 sont quatre valeurs seuil, avec So<So <Si<S2.

[0057] Preferably, S0=T / 4, S0 =T / 2, Si=3T / 4 and S2=T. For ti <T / 4, le retard t est égal au temps tb Pour T / 4<ti<T / 2, la valeur de retard t est égale à (T / 2-t3). Pour For T / 2 < 0 < 3T / 4, the delay value t is equal to (T / 2 + t4). For 3T / 4 <ti<T, la valeur de retard t est égale à (T-t2).

[0058] According to a first variant of the second embodiment, the measurement algorithm for estimating the delay t is as follows: ( / l>f)&( / l<4)- / = f+ / 4( / ,>?)- / = r- / 2

[0059] According to the first variant of the second embodiment, TDC 1 must be able to measure a delay value up to Tmax while TDC 2, 3 and 4 must be able to measure a delay value up to Tmax / 4.

[0060] Advantageously, the delay 0, t2, t3, or t4 used for evaluating the delay t is always less than 90° for a frequency of the first digital signal Ûy equal to f. The measured delay t can be greater than 90° if the frequency of the first digital signal Ûy is greater than f. This makes it possible to limit the complexity of the TDCs used, particularly in terms of the number of delay elements, and to reduce the error in estimating the phase of the impedance of the electrical element EL. The invention also makes the error in estimating the phase of the impedance of the electrical element EL more phase-symmetrical.

[0061] According to a second variant of the second embodiment, the time-to-digital converter TDC1 (respectively TDC2, TDC3) is configured to return a zero value when the measured delay value ti (respectively t2, t3) is greater than one-quarter of the period of the first digital signal Ûy. The phase value of the complex impedance of the electrical element is determined, either as a function of the delay value ti for ti<T / 4, soit en fonction de t3 pour (ti> T / 4 or 0=0) and t3<T / 4, soit en fonction de t4 pour (ti> T / 4 or 0=0), (t3>T / 4 or t3=0) and t4<T / 4, soit en fonction de t2 pour (0> (t / 4 or 0=0), (t3>T / 4 or t3=0), (t4>T / 4 or t4=0) and t2 <T / 4.

[0062] According to the second variant of the second embodiment, the measurement algorithm for estimating the delay t is as follows:

[0063] = (Mfc==0))*MH = L3 (( / |>DK / 1==0))&(( / 3>DI( / 3==0))&( / 4<t)- / = ;+ / 4 (( / p?)^ = 0)) )1(6 = =0))&(( / 4> J )1( / ==0) )- / = 7- / ,

[0064] According to the second variant of the second embodiment, all TDCs only need to be able to measure a delay value up to Tmax / 4. Advantageously, this reduces the complexity of the TDCs used.

[0065] The time-to-digital converters TDC1, TDC2, TDC3 are thus of less complexity because their measurement range is from 0° to 90°.

[0066] The invention also relates to a method for measuring the phase of a complex impedance of an electrical element EL. The method can be implemented by an apparatus according to one of the embodiments described above.

[0067] According to a first embodiment of the invention, the process comprises the following steps:

[0068] an excitation step SI 1 during which an excitation signal Sex oscillating at a known period T is applied to the electrical element EL;

[0069] a first acquisition step S21 during which a first analog signal uv, variable over time, and representative of a voltage across the terminals of the electrical element EL is acquired;

[0070] a second acquisition step S22 during which a second analog signal U;, variable over time, and representative of a current through the electrical element EL is acquired;

[0071] a digitization step S31 during which the first analog signal uv is digitized into a first digital signal Ûv and the second analog signal (u;) is digitized into a second digital signal Ûj;

[0072] a first injection step S41 during which the first digital signal [jv] is injected into the switch-on input of a first time-to-digital converter and into the switch-off input of a second time-to-digital converter;

[0073] a second injection step S42 during which the second digital signal Ûf is injected into the trigger input of the first time-to-digital converter and into the switch-on input of the second time-to-digital converter;

[0074] a first determination step S51 during which a first delay value ti between the rising edge, respectively falling edge, of the digital signal injected into the switch-on input and the rising edge, respectively falling edge, of the digital signal injected into the switch-off input of the first digital delay converter is determined, and a second delay value t2 between the rising edge, respectively falling edge, of the digital signal injected into the switch-on input and the rising edge, respectively falling edge, of the digital signal injected into the switch-off input of the second time-digital converter is determined;

[0075] a first calculation step S61 during which the value of the phase of the complex impedance of the electrical element is calculated, either as a function of ti for ti <S0, soit en fonction de t2 pour Si<ti<S2, dans lequel So, Siet S2 sont trois valeurs seuil, avec So Si S2.

[0076] Preferably, S0=Si=T / 2 and S2=T.

[0077] Preferably, the delay value ti is assigned a value of zero when the measured delay value ti is greater than half the period of the first digital signal Ûv-

[0078] According to the first embodiment of the invention, the measurement algorithm for estimating the delay t is as follows:

[0079] (^7)^ = ,,(^1)^0)^1-^

[0080] According to a second embodiment of the invention, the measurement method also comprises:

[0081] a third injection step S43 during which the second digital signal Ûj is injected into the turn-on input of a third time-to-digital converter and into the turn-off input of a fourth time-to-digital converter. The third injection step S43 is located after the second injection step S42 and before the first determination step S51;

[0082] a fourth injection step S44 during which the first digital signal Ûy is injected into the trigger input of the third time-to-digital converter and into the turn-on input of the fourth time-to-digital converter. The fourth injection step S44 is located after the third injection step S43 and before the first determination step S51;

[0083] A second determination step S52 during which a third delay value t3 between the rising edge, respectively falling edge, of the digital signal injected into the switch input and the falling edge, respectively rising edge, of the digital signal injected into the switch input of the third time-to-digital converter is determined, and a fourth delay value t4 between the falling edge, respectively rising edge, of the digital signal injected into the switch input and the rising edge, respectively falling edge, of the digital signal injected into the switch input of the fourth time-to-digital converter is determined;

[0084] A second calculation step S62 during which the value of the phase of the complex impedance of the electrical element is calculated, either as a function of t3 for S0 <ti<Sœ, soit en fonction de t4 pour S0 <ti<Si, dans lequel So- est une valeur seuil, avec So<So’<Si<S2.

[0085] Preferably, S0=T / 4, S0 =T / 2 and Si=3T / 4 and S2=T.

[0086] According to a first variant of the second embodiment, the measurement algorithm for estimating the delay t is as follows: 1 4 / ~ 2 4 / — 2 ^4 4 / t — 1 -t 2

[0087] According to a second variant of the second embodiment, the delay values ​​are assigned a value of zero when they are greater than T / 4, and wherein the value of the phase of the complex impedance of the electrical element is calculated, either as a function of the delay value ti for ti<T / 4, soit en fonction de t3 pour (ti> T / 4 or ti=0) and t3<T / 4, soit en fonction de t4 pour (ti> T / 4 or 0=0), (t3>T / 4 or t3=0) and t4<T / 4, soit en fonction de t2 pour (ti> (t / 4 or 0=0), (t3>T / 4 or t3=0), (t4>T / 4 or t4=0) and t2 <T / 4.

[0088] According to the second variant of the second embodiment, the measurement algorithm for estimating the delay t is as follows: (( / .>?)&,= =0))&(z,<n-M-z, (((pHt,= =0))&((r3> ?)|(r3==0))&(^ ( (»>>1)1 / ,= =<>)) & ( (»3>ï)|«3= -0) ) & ( ( / 4>$ )k»= =0) ) '' ''

[0090] The invention has been described with reference to particular embodiments, but variations are possible. For example:

[0091] The threshold values ​​can be S0=T / 3, S0 =T / 2 and Si=2T / 3 and S2=T.

[0092] Advantageously, such a configuration with asymmetrical measurement ranges between each TDC (in this variant, the measurement ranges of TDC3 and TDC4 would be smaller than the measurement ranges of TDC1 and TDC2) would allow the use of TDCs with a greater number of delay elements (or a smaller transition time T) for a smaller measurement range. This would allow the measurement elements (or the use of measurement elements with the smallest transition times T) to be concentrated at the most relevant intervals and would more effectively account for the asymmetry of the phase measurement error as a function of phase described above and shown in [Fig. 4], while limiting the total number of measurement elements over the [0°-360°] interval. Other threshold values ​​can be chosen to better account for the behavior of the TDCs used and the frequency bands used for impedance measurement.

[0093] The device can be integrated into an ASIC system (or "Application-Specific Integrated Circuit" according to the commonly used Anglo-Saxon term). References

[0094] (Mattada et al. 2021): M. Mattada, H. Guhilot, 62.5 ps LSB resolution multiphase clock Time to Digital Converter (TDC) implemented on FPGA, Journal of King Saud University - Engineering Sciences, Volume 34, Issue 6, 2022, Pages 418-424.

Claims

1. Demands A phase measuring device for a complex impedance of an electrical element (EL) comprising: - a first Schmitt flip-flop (BS1) configured to receive as input a first analog signal (uv), variable over time, of period T, representative of a voltage between two terminals of the electrical element, and convert it into a first digital signal (Üv); - a second Schmitt flip-flop (BS2) configured to receive a second analog signal (u^, variable over time, representing a current through the electrical element, and convert it into a second digital signal ({ / p ; - a first time-to-digital converter (TDC1); - a second time-to-digital converter (TDC2); - a computing unit (CU); the output of the first Schmitt flip-flop (BS1) being connected, directly or indirectly, to the turn-on input of the first time-to-digital converter (TDC1) and to the turn-off input of the second time-to-digital converter (TDC2), the output of the second Schmitt flip-flop (BS2) being connected, directly or indirectly, to the turn-off input of the first time-to-digital converter (TDC1) and to the turn-on input of the second time-to-digital converter (TDC2), the first time-to-digital converter (TDC1) being configured to measure a delay value ti between the rising edge, respectively falling edge, of the digital signal injected at the switch input and the rising edge, respectively falling edge, of the digital signal injected at the switch input, the second time-to-digital converter (TDC2) being configured to measure a delay value t2 between the rising edge, respectively falling edge, of the digital signal injected at the switch input and the rising edge, respectively falling edge, of the digital signal injected at the switch input, the processing unit (PU) being configured to calculate the phase value of the complex impedance of the electrical element, either in function of ti for ti <S0, soit en fonction de t2 pour Si<ti<S2, dans lequel So, Si et S2 sont trois valeurs seuil, avec S0<Si<S2.

2.

3. Apparatus according to claim 1, wherein S0=Si=T / 2 and S2=T. Apparatus for measuring the phase of a complex impedance of an electrical element (EL) according to claim 2, further comprising: - a third time-to-digital converter (TDC3); - a fourth time-to-digital converter (TDC4); the output of the first Schmitt flip-flop (BS1) being connected, directly or indirectly, to the turn-on input of the fourth time-to-digital converter (TDC4) and to the turn-off input of the third time-to-digital converter (TDC3), the output of the second Schmitt flip-flop (BS2) being connected, directly or indirectly, to the turn-on input of the third time-to-digital converter (TDC3) and to the turn-off input of the fourth time-to-digital converter (TDC4), the third time-to-digital converter (TDC3) being configured to measure a delay value t3 between the rising edge, respectively, falling edge,of the digital signal injected at the switch input and the falling edge, respectively rising edge, of the digital signal injected at the switch input, the fourth time-to-digital converter (TDC4) being configured to measure a delay value t4 between the falling edge, respectively rising edge, of the digital signal injected at the switch input and the rising edge, respectively falling edge, of the digital signal injected at the switch input, the processing unit (PU) being configured to calculate the phase value of the complex impedance of the electrical element, either as a function of t3 for So < t1 < S0, or as a function of t4 for S0 <ti<Si, dans lequel S0’ est une valeur seuil, avec So<So <Si<S2.,

4. Apparatus according to claim 3, wherein S0=T / 4, S0 =T / 2, Si =3174 and S2=T.

5. Apparatus according to claim 4, wherein the time-to-digital converters are configured to return a zero value when the measured delay value is greater than T / 4, and wherein the phase value of the complex impedance of the element electrical is determined, either as a function of the delay value ti for ti<T / 4, soit en fonction de t3 pour (ti> T / 4 or ti=0) and t3<T / 4, soit en fonction de t4 pour (ti> T / 4 or t1=0), (t3>T / 4 or t3=0) and t4<T / 4, soit en fonction de t2 pour (ti> (t / 4 or t1=0), (t3>T / 4 or t3=0), (t4>T / 4 or t4=0) and t2 <T / 4.

6. Device according to any one of claims 1 to 5, wherein the device is integrated into an FPGA system.

7. A method for measuring the phase of a complex impedance of an electrical element (EL) comprising the following steps: a) applying to the electrical element (EL) an excitation signal (Sex) oscillating at a known period T; b) acquiring a first analog signal (uv), varying over time, representative of a voltage across the terminals of the electrical element; c) acquiring a second analog signal (u^), varying over time, representative of a current through the electrical element; d) digitizing the first analog signal (uv) into a first digital signal (Üy) and the second analog signal (u^) into a second digital signal (Ûj); e) injecting the first digital signal (Üv) into the turn-on input of a first time-to-digital converter and into the turn-off input of a second time-to-digital converter;f) inject the second digital signal (Ûj) at the trigger input of the first time-to-digital converter and at the turn-on input of the second time-to-digital converter; g) determine a first delay value ti between the rising and falling edges of the digital signal injected at the turn-on input and the rising and falling edges of the digital signal injected at the trigger input of the first time-to-digital converter, and a second delay value t2 between the rising and falling edges of the digital signal injected at the turn-on input and the rising and falling edges of the digital signal injected at the trigger input of the second time-to-digital converter; h) calculate the phase value of the complex impedance of the electrical element, i.e., as a function of ti for ti <S0, soit en fonction; of t2 for Si<0 <S2, dans lequel So, Siet S2 sont trois valeurs seuil, avec So - Si - S2.

8.

9. A method according to claim 7, wherein S0=Si=T / 2 and S2=T. A method according to claim 7, further comprising the following steps: i) injecting the second digital signal (Üj) into the turn-on input of a third time-to-digital converter and into the turn-off input of a fourth time-to-digital converter; j) injecting the first digital signal (Üy) into the turn-off input of the third time-to-digital converter and into the turn-on input of the fourth time-to-digital converter;k) determine a third delay value t3 between the rising edge, respectively falling edge, of the digital signal injected at the switch input and the falling edge, respectively rising edge, of the digital signal injected at the switch input of the third time-to-digital converter, and a fourth delay value t4 between the falling edge, respectively rising edge, of the digital signal injected at the switch input and the rising edge, respectively falling edge, of the digital signal injected at the switch input of the fourth time-to-digital converter; 1) calculate the value of the phase of the complex impedance of the electrical element, either as a function of t3 for S0 <ti<S0’, soit en fonction de t4 pour S0 <ti<Si, dans lequel Sœ est une valeur seuil, avec So<SO’<Si<S2.;

10. Method according to claim 9, wherein, S0=T / 4, S0 =T / 2 and Si =3174 and S2=T.

11. A method according to claim 10, wherein the delay values ​​are assigned a value of zero when they are greater than T / 4, and wherein the phase value of the complex impedance of the electrical element is determined either as a function of the delay value ti for ti<T / 4, soit en fonction de t3 pour (ti> T / 4 or 0=0) and t3<T / 4, soit en fonction de t4 pour (ti> T / 4 or 0=0), (t3>T / 4 or t3=0) and t4<T / 4, soit en fonction de t2 pour (0> (t / 4 or 0=0), (t3>T / 4 or t3=0), (t4>T / 4 or t4=0) and t2

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