Method and system for processing analog signals delivered by pixels

Abstract

The process for processing an analog signal from a pixel uses a method called correlated double sampling, which involves two successive measurements of the time between the start of a ramp signal and the moment the pixel signal crosses the ramp. A single counting circuit (CCPT) is used for both measurements, and in particular a single counter (CPT1) which provides the two count values ​​used to generate the least significant bits of the output digital word representing the amount of light captured by the pixel. (See Figure 3 for abbreviations.)

Description

Title of the invention: Method and system for processing analog signals delivered by pixels

[0001] Some embodiments and implementations relate to the processing of analog signals, in particular the processing of analog signals delivered by pixels using a method called correlated double sampling, known to those skilled in the art under the Anglo-Saxon acronym CDS (“Correlated Double Sampling”), and in particular the reduction or even the elimination of vertical fixed pattern noise, known to those skilled in the art under the Anglo-Saxon acronym VFPN (“Vertical Fixed Pattern Noise”), which results in vertical bands in images.

[0002] The processing of an analog signal from a pixel using the so-called correlated double sampling method comprises two consecutive steps, namely: - a comparison of the signal delivered by the pixel, in this case a voltage, with a reference ramp signal, -a measurement of the duration between the start of the ramp and the moment of crossing the ramp with the signal delivered by the pixel.

[0003] These two steps are performed twice: -first time with the unilluminated pixel having a reference state, typically its black level, -a second time with the pixel illuminated.

[0004] The difference between the two measurement durations is representative of the amount of light captured by the pixel.

[0005] The determination of the two measurement durations classically involves the use of different counters to count periods of a clock signal.

[0006] However, even if these different meters are structurally identical, the components present in these meters exhibit mismatches resulting from their manufacturing process.

[0007] Furthermore, the use of different counters requires the use of physical paths for the propagation of signals to these counters, which induces different propagation delays between the same signals carried during the two measurements, even though they are initiated at the same instant during these two measurements.

[0008] These mismatches and different propagation delays induce measurement errors in the amount of light captured by the pixel.

[0009] In general, an image sensor comprises a matrix of pixels arranged in rows and columns.

[0010] The matrix is ​​read line by line, all the pixels of the same line being read simultaneously from reading devices having these different counters and respectively arranged at the bottom of each column.

[0011] The measurement errors mentioned above may vary from one pixel to another along a line, which produces the VFPN noise mentioned above.

[0012] There is therefore a need to provide a solution aimed at reducing or even eliminating this VFPN noise.

[0013] According to one embodiment, it is proposed to use a single counting circuit to perform the two measurements mentioned above, and in particular a single counter to determine the least significant bits of the digital output word representing the amount of light captured by a pixel.

[0014] According to one aspect, a method for processing an analog signal from a pixel is proposed using a method called correlated double sampling.

[0015] This method includes a first comparison of the signal corresponding to a reference state, for example a black level, of the unilluminated pixel, with a ramp-type signal and a first measurement of a first duration between the start of the ramp signal and a first instant where the signal crosses the ramp signal.

[0016] This first measurement is followed by a second comparison of the analog signal corresponding to the illuminated pixel, with said ramp signal and a second measurement of a second duration between the start of the ramp signal and a second instant when the signal crosses the ramp signal.

[0017] The method also includes the development of a digital output word corresponding to a subtraction of the second duration and the first duration.

[0018] This digital output word is representative of the amount of light captured by the pixel.

[0019] In the method according to this aspect, the first measurement, the second measurement and the development of the output digital word include counting in the same counting circuit the number of periods of a basic clock signal between the start of the ramp signal and each of the first and second instants.

[0020] Thus instead of using different counting circuits for the two measurements (unlit pixel and lit pixel) and in particular two different counters for the development of the least significant bits which involves in particular a subtraction between the two count values), here we use a single counting circuit for the two measurements and in particular a single counter which will provide the two count values ​​used for the development of the least significant bits of the output digital word.

[0021] This eliminates any measurement error by using a single counting circuit.

[0022] More specifically, and according to one embodiment, the metering circuit comprises -a first counter successively delivering a first digital word after a first count between the start of the ramp signal and the first instant, and a second digital word after a second count between the start of the ramp signal and the second instant, and -a second counter controlled by the first counter during the first count and during the second count and delivering a third digital word at the end of the second count.

[0023] The generation of the output digital word then involves - an elaboration of at least one least significant bit of the output digital word from the first and second digital words, and -a processing of the other bits of the output digital word (the most significant bits) from the third digital word.

[0024] Although it would be possible to process only one least significant bit of the output digital word, processing the output digital word involves processing several least significant bits of the output digital word from the first and second digital words.

[0025] Although it would be possible to subtract the second and first numeric words, for example if they were coded in binary, it is advantageous to use a thermometric code to encode the first and second numeric words.

[0026] In this case, the processing of the least significant bit(s) of the output digital word involves, for example, the processing of a first intermediate word (advantageously coded in binary) from the first digital word (advantageously coded in thermometric code) and a second intermediate word (advantageously coded in binary) from the second digital word (advantageously coded in thermometric code), and -a subtraction of the second and first intermediate digital words in order to obtain the least significant bit(s) of the output digital word.

[0027] The use of a thermometric code is advantageous because one goes from one value to another by changing only one bit.

[0028] Also as indicated above, when the first digital word and the second digital word are coded according to a thermometric code, the first intermediate digital word and the second intermediate digital word are coded according to a binary code and the elaboration of the first and second intermediate words then involves a conversion of the thermometric code into a binary code.

[0029] According to one embodiment, the first digital word and the second digital word are N-bit coded words according to a thermometric code corresponding to 2N decimal values.

[0030] The first counter then comprises N first flip-flops, for example D flip-flops.

[0031] The method then comprises, according to one embodiment, a generation of N additional clock signals mutually out of phase by one base period of the base clock signal and each having a period equal to 2N times the base period.

[0032] The first count (with the unilluminated pixel) comprises: - the input output to the first N flip-flops of successive groups of N binary data corresponding respectively to the logic states (high or low) of the N additional clock signals present at the input of these first N flip-flops, - the extraction of the first N binary data contained in these first N flip-flops at the expiration of said first duration (i.e., when the pixel signal crosses the ramp signal), and -a backup of these first N binary data in respectively N second flip-flops, for example also D flip-flops.

[0033] The second count (with the illuminated pixel) includes: -the output at the input of the first N flip-flops of successive groups of N binary data corresponding respectively to the logic states of the N additional clock signals present at the input of these first N flip-flops, and -a backup of the N second binary data contained in these first N flip-flops at the expiration of said second duration (this backup is advantageously carried out in the first N flip-flops).

[0034] The process then includes a delivery at the end of the second counting, -the first N binary data outputs from the second N flip-flops, so as to form the first digital word, and -N second binary data outputs from the first N flip-flops, so as to form the second digital word.

[0035] According to one embodiment, the first count includes an increment of the second counter each time the N binary data contained in the first N flip-flops correspond to a maximum logical value, and -the second counting involves decrementing the second counter each time the N binary data contained in the first N flip-flops correspond to a maximum logical value, - the binary data delivered by the second counter at the end of the second count forming the bits of the third digital word.

[0036] In other words, the subtraction of the count values ​​between the two measurements is directly carried out in the second counter by means of successive increment and decrement operations.

[0037] According to another aspect, a system for processing an analog signal from a pixel is proposed using a method called correlated double sampling.

[0038] This system comprises: -a signal input to receive the analog signal from the pixel, -a ramp generator to deliver a ramp-type signal, and -methods of treatment.

[0039] These processing means are configured to -perform a first comparison of the signal corresponding to a reference state of the unilluminated pixel with the ramp signal and a first measurement of a first duration between the start of the ramp signal and a first instant where the signal crosses the ramp signal, followed by a second comparison of the signal corresponding to the illuminated pixel with said ramp signal and a second measurement of a second duration between the start of the ramp signal and a second instant where the signal crosses the ramp signal, and -develop a numerical output word corresponding to a subtraction of the second duration and the first duration.

[0040] In the system according to this aspect, the processing means are configured to perform the first measurement, the second measurement and the development of the digital output word from counts in the same counting circuit, of the number of periods of a basic clock signal between the start of the ramp signal and each of the first and second instants.

[0041] According to one embodiment, the counting circuit comprises -a first counter configured to successively deliver a first digital word after a first count between the start of the ramp signal and the first instant, then a second digital word after a second count between the start of the ramp signal and the second instant, and -a second counter controlled by the first counter during the first count and during the second count and configured to deliver a third digital word at the end of the second count.

[0042] The processing means include -first processing means configured to process at least one least significant bit of the output digital word from the first and second digital words, and -second processing means configured to process the remaining bits of the output digital word from the third digital word.

[0043] According to one embodiment, the first processing means are configured to process several least significant bits of the output digital word from the first digital word and the second digital word.

[0044] According to one embodiment, the first processing means comprise - a module configured to process a first intermediate word from the first digital word and a second intermediate word from the second digital word, and -a subtractor configured to perform a subtraction of the second and first intermediate numeric words in order to obtain the least significant bit(s) of the output numeric word.

[0045] When the first digital word and the second digital word are coded according to a thermometric code, the first intermediate digital word and the second intermediate digital word are coded according to a binary code and said module is configured to perform a conversion of the thermometric code into a binary code.

[0046] According to one embodiment, the first digital word and the second digital word are words coded according to a thermometric code on N bits corresponding to 2N, decimal values.

[0047] The processing means further include a control block configured to deliver -a first control signal at the first instant, -a second control signal at the second instant, -a third control signal between the first instant and the delivery of the trigger signal.

[0048] The processing means further include a generation circuit configured to generate -N additional clock signals, each mutually out of phase by one base period of the base clock signal and each having a period equal to 2N times the base period, and

[0049] -a trigger signal intended to trigger the ramp generator.

[0050] The first counter advantageously comprises N counting inputs respectively capable of receiving successive groups of N binary data corresponding respectively to the logic states of the N additional clock signals present at the N counting inputs and N first flip-flops having their inputs respectively connected to the N counting inputs, and configured to freeze in the presence of the first control signal (i.e. at the first instant when the unlit pixel signal crosses the ramp signal), the first N binary data received on their respective inputs.

[0051] The processing means also advantageously comprise N second flip-flops having their inputs respectively connected to the outputs of the first N flip-flops and configured to store said first N binary data, in the presence of the third control signal.

[0052] In other words, there is then a transfer of the first N data from the first N flip-flops to the second N flip-flops and the first n flip-flops are again available for the second counting with the illuminated pixel.

[0053] Thus, according to one embodiment, during the second count, the N counting inputs are respectively able to receive again successive groups of N binary data corresponding respectively to the logic states of the N additional clock signals present at the N counting inputs, and the first N flip-flops of the first counter are then configured to freeze in the presence of the second control signal (i.e. at the second instant when the illuminated pixel signal crosses the ramp signal), the second N binary data received on their respective inputs.

[0054] The control block is configured to deliver control information -to the first flip-flops to extract the N second binary data points frozen in the first N flip-flops, so as to form the second digital word, and -to the second flip-flops to extract the first N stored binary data, in order to form the first digital word.

[0055] According to one embodiment, the generation circuit is configured to deliver the ramp trigger signal when the N binary data present at the N counting inputs of the first counter correspond to a maximum logic value.

[0056] According to one embodiment: -during the first count by the first counter, the second counter is configured to be incremented each time the N binary data contained in the first N flip-flops correspond to a maximum logic value, and -during the second count by the first counter, the second counter is configured to be decremented each time the N binary data contained in the first N flip-flops correspond to a maximum logic value.

[0057] The binary data delivered by the second counter at the end of the second counting form the bits of the third digital word.

[0058] According to another aspect, a sensor is proposed comprising a pixel matrix organized in rows and columns, and comprising respectively at the foot of each column, a system as defined above.

[0059] Other advantages and features of the invention will become apparent upon examination of the detailed description of implementations and embodiments, which are by no means limiting, and the accompanying drawings in which: [Fig.l], [Fig.2], [Fig.3], [Fig.4] [Fig.5] [Fig. 6], and [Fig.7]

[0060] illustrate methods of implementation and realization of the invention.

[0061] In [Fig.1], the reference SYS designates a system for processing an analog signal VX from a pixel PX using a method called correlated double sampling.

[0062] The PX pixel has a classic and known structure in itself which will not be detailed here.

[0063] The reference VX designates the signal or voltage delivered by the pixel when it is read.

[0064] The SYS system comprises: -an ESP signal input to receive the analog VX signal from the pixel, and -a GENR ramp generator to deliver a VRAMP ramp type signal with predetermined characteristics.

[0065] This VRAMP ramp signal is used in a conventional way to determine the value of the pixel signal PX.

[0066] The SYS system also includes MTR processing means.

[0067] In general, these MTR processing means are configured to, in a first step STP1 ([Fig.2]), called calibration step, perform a first comparison of the VX signal corresponding to a reference state of the unilluminated pixel, for example a black level, with the VRAMP ramp type signal and a first measurement of a first duration between the start T0 of the ramp signal and a first instant Tl where the signal crosses the ramp signal.

[0068] This first step STP1 is followed by a second step STP2, in which the processing means are configured to perform a second comparison of the VX signal corresponding to the illuminated pixel, with said VRAMP ramp signal and a second measurement of a second duration between the start T0 of the ramp signal and a second instant T2 where the signal crosses the ramp signal.

[0069] The processing means are then configured to generate a digital output word MNS corresponding to a subtraction of the second duration and the first duration.

[0070] This MNS output digital word is representative of the amount of light captured by the pixel.

[0071] It can already be noted that the MTR processing means are configured to perform the first measurement, the second measurement and the development of the digital output word from counts in a single CCPT counting circuit, of the number of periods of a basic clock signal CLK (having a basic period) between the start T0 of the ramp signal and each of the first and second instants T1, T2.

[0072] As will be seen in more detail below, these counts of the number of periods of the basic clock signal CLK are carried out using additional mutually out-of-phase clock signals, each having a period equal to a multiple of the basic period.

[0073] To perform the various operations mentioned above, the processing means include ([Fig.1]) -a CMP comparator configured to perform the comparison between the VRAMP ramp signal and the VX pixel signal and deliver an OUTCOMPB comparison signal, -a GENH clock generator configured to generate a CLK base clock signal, typically having a high frequency, -a CGEN generation circuit configured to generate the additional CLKPATH clock signals (here N additional clock signals CLKPATH) with i varying from 1 to N) as well as an SDCL signal for triggering the GENR ramp generator, -a CCPT counting circuit, -initial MLB1 processing methods configured to process several least significant bits of the MNS output digital word, -second processing means MLB2 configured to process the remaining output bits, the most significant bits, of the MNS output digital word, -a BCTRL control block configured to deliver multiple control signals.

[0074] We will return in more detail below to the structure and / or functionality of some of these means.

[0075] We now refer more particularly to [Fig.2] and [Fig.3].

[0076] The method comprises ([Fig.2]) a first STPC1 counting between the beginning T0 of the VRAMP ramp signal and the first instant T1 and a second STPC2 count between the start T0 of the VRAMP ramp signal and the second instant T2.

[0077] A control signal SC3, in the form of a pulse, is delivered by the BCTRL control block between the first instant Tl and the occurrence of the signal of SDCL triggering marks the start of the second STPC2 count and the triggering of the GENR ramp signal.

[0078] The comparator's OUTCOMPB signal is in the high state (logic value 1) during counting and goes to the low state (logic value 0) when the VRAMP ramp signal crosses the VX pixel signal, marking the end of counting.

[0079] As schematically illustrated in [Fig. 3], the CCPT counting circuit comprises a first counter CPT1 which successively delivers a first digital word QLSB0<N :1> following the first count STPC1 and a second numeric word QLSB1<N :1> following the second STPC2 count.

[0080] The least significant bits of the output digital word are derived from the first digital word QLSB0<N :1> and the second numeric word QLSB1<N :1> .

[0081] The CCPT counting circuit also includes a second counter CPT2, controlled by the first counter CPT1 during the first count and during the second count, and delivering a third digital word MSB<M :1> at the end of the second count.

[0082] The other bits of the output digital word (the most significant bits) are generated from the third digital word.

[0083] The first QLSB0 numeric word<N : 1> and the second numeric word QLSB1<N :1> are made up of N bits and are coded according to a digital thermometric code corresponding to 2N decimal values.

[0084] This is why N additional CLKPATH clock signals are used<N :1> each having a period equal to 2N basic periods of the CLK basic clock signal, to perform the two successive counts.

[0085] Referring more specifically to [Fig. 3], we see that the first counter CPT1 has N counting inputs EC1, EC1, EC2, ECN respectively capable of receiving successive groups of N binary data corresponding respectively to the logical states of the N additional clock signals CLKPATH <1> CLKPATH <2> CLKPATH <n>present at the N counting inputs.

[0086] The first counter CPT1 also includes N first flip-flops BSC11, BSC21, ..., BSCN1 having their EDI, ED2, ..., EDN data inputs respectively connected to the N counting inputs.

[0087] These first flip-flops are here synchronized flip-flops on the low level of the first SCI signal (during the first count) and on the low level of the second SC2 signal (during the second count).

[0088] These SCI and SC2 signals are the opposites of the OUTCOMPB signal.

[0089] In other words, as long as the OUTCOMPB signal is high (SCI or SC2 signal low), each first BSC1 flip-flop is "transparent", that is, it copies its CLKPATH input on his QLSB exit .

[0090] On the other hand, when the OUTCOMPB signal goes low (SCI or SC2 signal high), each first flip-flop "closes", leading to the last input value of that first flip-flop being stored at the output.

[0091] In other words, the transition to the high state of the SCI signal, during the first count, corresponds to a first control signal freezing the first N binary data received on the respective data inputs of the first flip-flops.

[0092] These first N binary data are referenced QLSB0<N :1> and form the first numerical word.

[0093] The transition to the high state of the SC2 signal, during the second count, corresponds to a second control signal freezing the N second binary data received on the respective data inputs of the first flip-flops.

[0094] These N second binary data are referenced QLSB1<N :1> and form the second numerical word.

[0095] The processing means also include N second flip-flops D referenced BSC12, BSC22, ...., BSCN2, having their data inputs respectively connected to the outputs of the first N flip-flops BSC11, BSC21, ..., BSCN1.

[0096] These N second flip-flops are synchronized to the low level of the third signal SC3.

[0097] When this SC3 impulse signal goes high, it acts as a third control signal and these second N flip-flops then store the said first N binary data QLSB0<N :1>

[0098] In other words, there is then a transfer of the first N binary data QLSB0<N :1> from the first N BSCil flip-flops to the second N BSCi2 flip-flops and the first N BSCil flip-flops are again available for the second counting with the illuminated pixel.

[0099] The second counter CPT2 is a counter of classic and known structure and includes looped FF flip-flops of the "Flip Flop" type connected in series.

[0100] This second counter CPT2 is controlled by the output of the first flip-flop BSCN1 of the first counter CPT1.

[0101] When the QLSB data <n>of this first flip-flop is equal to 1, which corresponds to a maximum value for the N data received by these first N flip-flops, the second counter CPT2 is incremented during the first count and decremented during the second count.

[0102] Therefore, it delivers the MSB bits at the end of the second count<M : 1> of the third numerical word.

[0103] Reference is now made more particularly to [Fig.4] which illustrates a partial chronogram relating to the first count or the second count.

[0104] The SDCL trigger signal triggers the GENR generator of the ramp signal on the falling edge of the CLKPATH supplementary clock signal <1> that is, just after the N CLKPATH signals<N :1> all had their high state.

[0105] CLKPATH signals<N :1> are then delivered to the counting inputs of the first CPTL meter

[0106] The successive values ​​of the N QLSB binary data<N :1> then correspond to the successive states of the CLKPATH signals<N :1> .

[0107] Each time CLKPATHN goes to the high state, the second counter CPT2 is incremented in the STP1 step (during the first count) while it is decremented in the STP2 step (during the second count).

[0108] This continues until the descending front of OUTCOMPB.

[0109] At the falling edge of OUTCOMPB, the first BSCil flip-flops (during the first count) close and the first QLSB0 binary data<N :1> (at the end of the first counting) are stored and transferred into the N second flip-flops in response to the third SC3 control signal.

[0110] Then what has just been described is repeated during the second count until the falling edge of OUTCOMPB.

[0111] On the falling edge of OUTCOMPB, the first BSCil flip-flops (during the second count) close and the second QLSB1 binary data<N :1> (at the end of the second counting) are stored in these first flip-flops.

[0112] Of course, the values ​​of the first and second stored binary data are generally different.

[0113] We now refer more specifically to [Fig. 5] to describe a mode realization of the first processing means MLB1 and the second processing means MLB2, which are incorporated within a DSP processing unit, for example a signal processing processor.

[0114] In response to an INFC command information delivered by the control block, the first numeric word QLSB<N :1> and the second numeric word QLSB1<N :1> are extracted from the corresponding flip-flops and the third digital word MSB<M :1> is delivered by the second CPT2 meter.

[0115] The first MLB1 processing means receive the first QLSB digital word<N :1> and the second numeric word QLSB1<N :1> , coded according to a thermometric code.

[0116] They include an MDCV module configured to generate a first intermediate word LSB0 from the first numeric word and a second intermediate word LSB1 from the second numeric word.

[0117] These two intermediate words are coded in binary.

[0118] Said module is therefore configured to perform a conversion of the thermometric code into a binary code, according to the classic conversion table illustrated in [Fig.6].

[0119] In this table, T1, T2, ..., TN denote the N bits of the thermometric code.

[0120] S1, S2, ..., SN denote the corresponding N bits of the binary code and VD denotes the corresponding decimal value.

[0121] The first processing means also include a subtractor STR configured to perform an LSB1-LSB0 subtraction of the second LSB1 and the first LSB0 intermediate digital words so as to obtain the ALSB least significant bit(s) of the output digital word MNS.

[0122] The second processing means here comprise a second MD2 module optionally multiplying the MSB bits<M :1> by an integer depending on the desired resolution.

[0123] The bits of the digital output word MNS delivered by the second module MD2 include the least significant bits ALSB and the most significant bits MSB<M :1> possibly multiplied by said integer.

[0124] Fig. 7 schematically illustrates an SNS sensor comprising an MPX matrix of PXi,j pixels having q rows and p columns.

[0125] The pixels of a line are read simultaneously using the method just described.

[0126] Then we move to the next line until we have read the entire matrix.

[0127] Consequently, the SNS sensor comprises, respectively at the foot of the p columns, p SYSl-SYSp systems identical to the SYS system described with reference to figures 1 to 6.< / n> < / n>

Claims

Demands

1. A method for processing an analog signal from a pixel using a so-called correlated double sampling method, comprising: - a first comparison of the signal (VX) corresponding to a reference state of the unilluminated pixel with a ramp signal (VRAMP) and a first measurement of a first duration between the start (TO) of the ramp signal and a first instant (T1) where the signal crosses the ramp signal, followed by a second comparison of the signal corresponding to the illuminated pixel with said ramp signal and a second measurement of a second duration between the start (TO) of the ramp signal and a second instant (T2) where the signal crosses the ramp signal; - the generation of a digital output word (MNS) corresponding to a subtraction of the second duration and the first duration, wherein the first measurement,The second measurement and the generation of the digital output word include counting, within a single counting circuit (CCPT), the number of periods of a basic clock signal between the start of the ramp signal and each of the first and second instants.

2. A method according to claim 1, wherein the counting circuit (CCPT) comprises - a first counter (CPT1) successively delivering a first digital word (QLSB0<N :1> ) following a first count between the start of the ramp signal and the first instant and a second digital word (QLSB1<N :1> ) following a second count between the start of the ramp signal and the second instant, and -a second counter (CPT2) controlled by the first counter during the first count and during the second count and delivering a third digital word (MSB<M :1> ) at the end of the second counting, a process in which the development of the output digital word involves -development of at least one least significant bit of the output digital word from the first digital word and the second digital word, and -development of the other bits of the output digital word from the third digital word.

3. Method according to claim 2, wherein the processing of the output digital word (DDN) comprises processing several least significant bits of the output digital word from the first digital word and the second digital word.

4. A method according to claim 2 or 3, wherein the processing of the least significant bit(s) of the output digital word comprises processing a first intermediate word (LSBO) from the first digital word and a second intermediate word (LSB1) from the second digital word, and subtracting the second and first intermediate digital words to obtain the least significant bit(s) of the output digital word.

5. A method according to claim 4, wherein the first digital word and the second digital word are encoded according to a thermometric code, the first intermediate digital word and the second intermediate digital word are encoded according to a binary code and the development of the first and second intermediate words comprises a conversion (MDCV) of the thermometric code into a binary code.

6. A method according to claims 3 and 5, wherein: - the first digital word and the second digital word are N-bit coded words corresponding to 2N decimal values, - the first counter (CPT1) comprises N first flip-flops (BSC1), - the method includes the generation of N additional clock signals (CLKPATH).<N :1> ) mutually out of phase by one base period of the base clock signal (CLK) and each having a period equal to 2N times the base period, -the first count involves outputs to the input of the first N flip-flops, of successive groups of N binary data corresponding respectively to the logic states of the N additional clock signals present at the input of these first N flip-flops,an extraction of the first N binary data (QLSB0<N :1> ) contained in these first N flip-flops at the expiration of said first duration and a backup of these first N binary data in respectively N second flip-flops (BSCi2),

7.

8. -the second counting involves outputting successive groups of N binary data to the input of the first N flip-flops, corresponding respectively to the logic states of the N additional clock signals present at the input of these first N flip-flops, and saving the second N binary data (QLSB1).<N :1> ) contained in these first N flip-flops (BSCil) at the expiration of said second duration, and -the process includes delivering, at the end of the second counting, the first N binary data and the second N binary data respectively at the output of the second N flip-flops and the first N flip-flops, so as to form respectively the first digital word and the second digital word. A method according to claims 2 and 6, in which -the first count involves incrementing the second counter (CPT2) each time the N binary data contained in the first N flip-flops correspond to a maximum logical value, and -the second count involves a decrement (CPT2) of the second counter each time the N binary data contained in the first N flip-flops correspond to a maximum logical value, - the binary data delivered by the second counter at the end of the second count, forming the bits of the third digital word. A system for processing an analog signal from a pixel using a method called correlated double sampling, comprising: - a signal input (ESP) to receive the signal (VX), -a ramp generator (GENR) to deliver a ramp-type signal (VRAMP), -processing means (MTR) configured for perform a first comparison of the signal corresponding to a reference state of the unilluminated pixel with the ramp signal and a first measurement of a first duration between the start of the ramp signal and a first instant where the signal crosses the ramp signal, followed by a second comparison of the signal corresponding to the illuminated pixel with said ramp signal and a second measurement of a second duration between the start of the ramp signal and a second instant where the signal crosses the ramp signal, and to construct a digital output word corresponding to a subtraction of the second duration and the first duration, wherein the processing means are configured to perform the first measurement, the second measurement and the construction of the digital output word from counts in a single counting circuit (CCPT) of the number of periods of a basic clock signal between the beginning of the ramp signal and each of the first and second instants.

9. System according to claim 8, wherein the counting circuit (CCPT) comprises -a first counter (CPT1) configured to successively deliver a first digital word at the end of a first count between the start of the ramp signal and the first instant and then a second digital word at the end of a second count between the start of the ramp signal and the second instant, and -a second counter (CPT2) controlled by the first counter during the first count and during the second count and configured to deliver a third digital word at the end of the second count, and the processing means (MTR) comprise -first processing means configured to process at least one least significant bit of the output digital word from the first digital word and the second digital word, and -second processing means configured to process the other bits of the output digital word from the third digital word.

10. System according to claim 9, wherein the first processing means (MLB1) are configured to process several least significant bits of the output digital word from the first digital word and the second digital word.

11. A system according to claim 9 or 10, wherein the first processing means (MLB1) comprise a module configured to process a first intermediate word from the first digital word and a second intermediate word from the second digital word, and -a subtractor configured to perform a subtraction of the second and first intermediate numeric words in order to obtain the least significant bit(s) of the output numeric word.

12. System according to claim 11, wherein the first digital word and the second digital word are encoded according to a thermometric code, the first intermediate digital word and the second intermediate digital word are encoded according to a binary code and said module (MDCV) is configured to perform a conversion of the thermometric code into a binary code.

13. System according to claims 10 and 12, wherein the first digital word and the second digital word are N-bit coded words corresponding to 2N decimal values, wherein the processing means (MTR) further comprise a control block configured to deliver -a first control signal at the first instant, -a second control signal at the second instant, -a third control signal between the first instant and the delivery of the trigger signal, wherein the processing means further comprise a generation circuit configured to generate -N additional clock signals mutually out of phase by one base period of the base clock signal and each having a period equal to 2N times the base period, and -a trigger signal for triggering the ramp generator.

14. A system according to claim 13, wherein - the first counter (CPT1) comprises N counting inputs respectively capable of receiving successive groups of N binary data corresponding respectively to the logic states of the N additional clock signals present at the N counting inputs, and N first flip-flops having their inputs respectively connected to the N counting inputs and configured to freeze, upon the presence of the first control signal, the first N binary data received at their respective inputs, - and the processing means (MTR) also comprise N second flip-flops having their inputs respectively connected to the outputs of the first N flip-flops and configured to store the said first N binary data, in the presence of the third control signal.

15. System according to claim 14, wherein the first N flip-flops of the first counter (CPT1) are configured to freeze, in the presence of the second control signal, the second N binary data received on their respective inputs, and the control block is configured to deliver control information -to the first flip-flops to extract the second N binary data frozen in the first N flip-flops, so as to form the second digital word, and -to the second flip-flops to extract the first N stored binary data, so as to form the first digital word.

16. System according to any one of claims 13 to 15, wherein the generation circuit is configured to deliver the trigger signal (SDCL) when the N binary data present at the N counting inputs of the first counter correspond to a maximum logic value.

17. A system according to claims 9 and any one of claims 14 to 16, wherein - during the first count by the first counter, the second counter (CPT2) is configured to be incremented each time the N binary data contained in the first N flip-flops correspond to a maximum logic value, and - during the second count by the first counter, the second counter (CPT2) is configured to be decremented each time the N binary data contained in the first N flip-flops correspond to a maximum logic value, - the binary data delivered by the second counter at the end of the second count forming the bits of the third digital word.

18. Sensor, comprising a pixel matrix (MPX) arranged in rows and columns, and comprising respectively at the foot of each column, a system (SYSj) according to any one of claims 8 to 17.

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