DEVICE AND METHOD OF INTERLACE
By employing multiple processor cores with local memory portions smaller than the interleaving length, the method addresses the limited local memory issue in DSP cores, achieving longer interleaving lengths and maintaining real-time performance in radio modems.
Patent Information
- Authority / Receiving Office
- FR · FR
- Patent Type
- Applications
- Current Assignee / Owner
- THALES SA
- Filing Date
- 2024-12-18
- Publication Date
- 2026-06-19
AI Technical Summary
The limited size of the local memory in a DSP core restricts the interleaving length, which is crucial for improving Bit Error Rate (BER) performance in radio modems, and using external memory increases data access time.
Implement an interleaving method using multiple processor cores, each with a local memory portion smaller than the interleaving length, to perform interleaving in parts, storing each part in local memory, and transferring it to external memory for the complete interleaved sequence, allowing longer interleaving lengths without increasing data access time.
The method achieves longer interleaving lengths than conventional methods, maintaining real-time processing performance and reducing data access time by utilizing multiple processor cores effectively.
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Abstract
Description
Title of the invention: DEVICE AND METHOD FOR INTERLACED Technical field
[0001] The invention is in the field of computer science and telecommunications and relates more particularly to interlacer and deinterlacer type modules.
[0002] These modules are primarily used in data communication, multimedia files, and radio transmissions (e.g., satellite, digital TV, or ADSL). Historically, they have also been used for storing sorted data on hard drives or optical media (CD-ROM, DVD, etc.) to protect data from scratches and damage to the storage medium. Prior art
[0003] An interleaver is adapted to perform interleaving, i.e., to process a digital signal to rearrange contiguous data into a non-contiguous form. Particularly in the physical layer of a radio modem, an interleaver is implemented to separate consecutive bits to be transmitted as far apart as possible along the length of the interleaver. As a result, the bits to be transmitted, which were originally consecutive, are spaced apart.
[0004] Interleaving improves performance, for example in terms of error detection and correction, in subsequent signal processing, such as following a transmission affected by consecutive error packets. The aim is to standardize the bit errors at the receiver, thus preventing error decoder resonance. A classic method consists of constructing a rectangular array in which each row represents a vector of transmitted bits. The array is then read column by column. The greater the spacing between consecutive bits, the better the signal's resistance to interference.
[0005] The reverse operation is called deinterlacing and is performed in a deinterlacer; its purpose is to reconstruct the original order of the data. Deinterlacing is therefore also a form of interlacing.
[0006] The greater the length of the interleaver, the better the performance of the modem in terms of Bit Error Rate (BER).
[0007] The interleaver length (or interleaving length) is the amount of information involved in an execution of the interleaving operation. This amount corresponds to the number of input and output data points of the interleaving process.
[0008] When the interleaver is implemented (embedded) on a digital signal processor, also called a DSP (Digital Signal Processor), of a real-time radio modem, the length of the interleaver may be limited by the size of the local memory of a DSP core. If external memory is associated with the DSP, it can be used, but the data access time is longer.
[0009] The local memory of a DSP core is rather small, whereas it would be preferable for an interleaver if it were larger.
[0010] Figure 3 schematically illustrates the operating principle of an interleaver in the prior art: the positions of consecutive bits in a sequence 41 of M consecutive bits supplied as input to the interleaver are redefined by the implementation, in a DSP core, of an interleaving algorithm and are found, at the output of the interleaver, to be organized according to a sequence 42, in a different order, in the local memory of the DSP core. This local memory is of a size greater than or equal to 2M bits (containing the M bits of the input sequence 41 and the M bits of the output sequence 42); in the example considered, the size of the local memory is 130 KB (kilobytes), which limits the interleaving length L (= M).
[0011] Fig. 4 illustrates a prior art in which, compared to the example in Fig. 3, one or more registers, here two DMA registers 43 and 44, in the interleaver implemented on a DSP core, successively extract bits from a sequence to be interleaved which is stored in a memory external to the DSP.
[0012] There is therefore a need to improve the performance of devices including an interlacer. Summary of the invention
[0013] To this end, according to a first aspect, the present invention describes an interleaving method comprising a set of ncore processor core(s), each core being associated with a local processor memory whose portion dedicated to the interleaving output is of size T strictly less than the interleaving length L and being adapted to implement an interleaving algorithm of length L, and ncore being an integer greater than or equal to 1, said device being adapted to implement the following steps to perform interleaving on a sequence of data to be interleaved: - implementation, N times, of the interleaving algorithm of length L on at least a respective part of said input sequence, the interleaved input sequence being equal to the union of several distinct consecutive subsequences S_l, ..., S_N and N >1; - the i-th implementation, i = 1 to N, of interleaving on at least a part of said input sequence being performed by a core of the set of ncore cores, said implementation being followed by the storage in said local memory part of said core of, among the subsequences S_l, ..., S_N, only the subsequence S_i; - then transfer of each sub-sequence S_i into a predefined memory, external to the processor core; at the end of the N transfers, said external memory thus contains the interlaced input sequence.
[0014] The invention therefore makes it possible to obtain an output result from the interlacer which is longer than the portion of the local memory of a DSP core which was available in the prior art to accommodate the result of the interlacing.
[0015] In embodiments, such a method will further comprise at least one of the following features:
[0016] - ncore = N, and the i-th implementation, i = 1 to N, of the interleaving is carried out by the i-th processor core, i = 1 to N;
[0017] - ncore < N and at least one of the same cores among the ncores successively performs:
[0018] - the ith implementation, i between 1 and Nl, of the interleaving on at least a part of said input sequence followed by the storage in the local memory of said core of only the subsequence S_i, then the transfer of the subsequence S_i into the predefined external memory;
[0019] - the jth implementation, j between 2 and N and strictly greater than i, of interleaving on at least a part of said input sequence followed by storing in the local memory of said core only the subsequence Sj, then transferring the subsequence Sj to the predefined external memory;
[0020] - the index of the input bits that are in the subsequence S_i is precalculated, thus that their respective associated positions in the subsequence S_i, and the i-th implementation, i = 1 to N, of the interleaving on at least a part of said input sequence performed by a core is carried out according to the pre-calculated index of the input bits in the subsequence S_i and their respective associated positions in the subsequence S_i.
[0021] According to another aspect, the invention describes an interleaving device comprising a set of ncore processor core(s), each core being associated with a local processor memory whose portion dedicated to the interleaving output is of size T strictly less than the interleaving length L, said interleaving device being adapted to implement an interleaving algorithm of length L, and ncore being an integer greater than or equal to 1, said device being adapted to implement N times the interleaving algorithm of length L on at least a respective portion of an input data sequence to be interleaved, the interleaved input sequence being equal to the union of several distinct consecutive subsequences S_l, S_N and N> 1;
[0022] in which the ith implementation, i = 1 to N, of the interleaving on at least a part of said input sequence is carried out by a core of the set of ncore cores, said device being adapted to, following said implementation, store in said part of local memory of said core, among the subsequences S_1, ..., S_N, only the subsequence S_i;
[0023] said device being adapted to then transfer each sub-sequence S_i into a predefined memory, external to the processor core so that at the end of the N transfers, said external memory thus contains the interleaved input sequence.
[0024] In embodiments, such a device will further comprise at least one of the following features:
[0025] - ncore = N, and in which the i-th implementation, i = 1 to N, of the interleaving is performed by the i-th processor core, i = 1 to N;
[0026] - ncore < N and at least one of the ncore cores is suitable to perform successively:
[0027] - the ith implementation, i between 1 and N-1, of the interleaving on at least a part of said input sequence followed by the storage in the local memory of said core of only the subsequence S_i, then the transfer of the subsequence S_i into the predefined external memory;
[0028] - the jth implementation, j between 2 and N and strictly greater than i, of interleaving on at least a part of said input sequence followed by storing in the local memory of said core only the subsequence Sj, then transferring the subsequence Sj to the predefined external memory;
[0029] - the index of the input bits that are in the subsequence S_i is precalculated, thus that their respective associated positions in the subsequence S_i, and the device is adapted to perform the ith implementation, i = 1 to N, of the interleaving on at least a part of said input sequence performed by a core as a function of the precalculated index of the input bits in the subsequence S_i and their respective associated positions in the subsequence S_i.
[0030] According to another aspect, the invention describes a computer program intended to be stored in the memory of an interleaving device comprising a DSP having an array of ncore processor core(s), each core being associated with a local processor memory whose portion (42) dedicated to the interleaving output is of size T strictly less than the interleaving length L and being adapted to implement an interleaving algorithm of length L, and ncore being an integer greater than or equal to 1, said interleaving device comprising a microcomputer, said computer program comprising instructions which, when executed on the microcomputer, implement the steps of a process according to the invention.
[0031] The invention also describes a non-transient, computer-readable medium storing such a computer program. Brief description of the drawings
[0032] The invention will be better understood and other features, details and advantages will become clearer from the following description, given by way of non-limiting reason, and from the accompanying figures, given by way of example.
[0033] [Fig-1] Fig. 1 is a diagram of a radio communication system in a mode realization of the invention;
[0034] [Fig.2] Fig.2 represents the steps of an interlacing process in one embodiment of the invention;
[0035] [Fig.3] The [Fig.3] schematically illustrates the operating principle of a prior art interlacer;
[0036] [Fig.4] The [Fig.4] schematically illustrates the operating principle of a prior art interlacer;
[0037] [Fig.5] Fig.5 schematically illustrates the operating principle of an interlacer in one embodiment of the invention;
[0038] [Fig.6] The [Fig.6] is a comparison of interlacing characteristics;
[0039] [Fig.7] Fig.7 schematically illustrates the operation of a process in an embodiment of the invention using 4 cores of a DSP.
[0040] Identical references may be used in different figures when they refer to identical or comparable elements. Description of the implementation methods
[0041] A radio communication system 1 in one embodiment of the invention is schematically represented in [Fig. 1]. It comprises a radio communication transmitter device 10, named EM 10, and a radio communication receiver device 25, named REC 25, adapted to communicate with each other.
[0042] Of course, in one embodiment, the device 10 (similarly the device 25) is adapted to function as a transmitter and receiver and further comprises, in this case, a module similar to the receiver device 25 for reception.
[0043] The EM 10 device includes a radio modem 11 adapted to receive binary data to be transmitted, to process and format it, in particular by interleaving the data using an interleaver, and then to modulate it. The EM 10 device is adapted to, after processing by a digital-to-analog converter 20 and a stage radio frequency 21, transmit the resulting radio frequency signal on one or more radio frequency (RF) channels via an RF antenna.
[0044] Symmetrically, the REC 25 device is adapted to receive a radio frequency signal transmitted by EM 10. The REC 25 device includes in particular a radio frequency receiver stage 27, an analog-to-digital converter (ADC) 28 and a modem 23 adapted to demodulate the received radio frequency signal once digitized, to extract binary data from the signal output from ADC 28 and to process them including deinterlacing them using a deinterlacer 26.
[0045] The part relating to the modem 11 of the EM device 10 is more particularly represented in [Fig. 1]. The modem 11 includes, for example in the present case, as is known, an FEC block 12 (FEC being an acronym for the English expression Forward Error Correction), an interlacer block 13, a symbol formation block 14, a scrambling block 15, a framing block 16, a modulation block 17, an oversampler 18 and a shaping filter (for example of the half-Nyquist type) 19.
[0046] Blocks 12 to 19 (or at least some of these blocks) are for example implemented on a digital signal processor 24, named DSP 24.
[0047] In one embodiment, at least some of the blocks of the modem 11, including the interleaver 13, are digital data processing blocks. Typically, the functions of the interleaver 13 (or at least some of these functions) are implemented via the execution, on the DSP 24, of software instructions stored in a memory of the EM device 10 (the local memory of the DSP 24, for example).
[0048] The DSP 24 comprises ncore processor core(s) each associated with a respective local memory, with ncore equal to 1 or strictly greater than 1. A part, named 42_k, of size T, of the local memory respectively associated with the keme core (k = 1 to ncore) is dedicated to the output of the interleaver 13.
[0049] The local memory of a processor core is defined as the memory associated with (the closest to) each core and directly accessible from the CPU (Central Processing Unit) of that core via a local bus. This is the memory that allows the CPU the fastest access to data. Other memories accessible by the core are accessed indirectly via a DMA (Direct Memory Access) transfer to (from) the local memory or via a cache system residing in local memory.
[0050] The interleaving length, L, is strictly greater than T (i.e., the size of the 42_k portion of the local memory of the keme core (k = 1 to ncore) is insufficient to contain the input sequence data once the latter has been interleaved by the interleaving algorithm of interleaving length L). L is, for example greater than (Nl)xT and less than or equal to NxT, with N an integer strictly greater than 1. In the case considered, L is for example equal to NxT.
[0051] In one embodiment, the size of the local memory of a core is thus equal to the sum of the size of the 2 DMA registers, of T, of the size of the software program and of the size of the cache (Data, Program).
[0052] The technical solution proposed according to the invention makes it possible to compensate for the small size of the local memory of a core of a multicore DSP.
[0053] The interlacer 13 is adapted to implement an interlacing process in an embodiment of the invention, comprising the set of steps 200 represented in [Fig.2].
[0054] In a step 201, the interleaver 13 obtains as input a sequence of binary data to be interleaved (in the case considered, from the FEC block 12).
[0055] It then carries out the steps 202_i, i = 1 to N, thus implementing N times (with N an integer strictly greater than 1) the same interleaving algorithm on the entirety of this same input sequence.
[0056] Each step 202_i comprises a substep 2021_i, followed by a substep 2022_i.
[0057] In step 2021_i, a processor core of the DSP 24, for example the keme core, obtains as input the binary data sequence to be interlaced, then implements the interlacing algorithm of size L, here L= NxT, which generates as a result a sequence occupying a length of size L, composed of successive sub-sequences S_1, S_2, ..., S_N, each of size T.
[0058] The size of the data sequence to be interlaced provided as input to the interlacer is L and L = NxT is the size of the interlacing result.
[0059] In step 2022_i, after the interleaving calculation of step 2021_i, only the subsequence S_i is stored in the 42_k part of the local memory of the keme processor core used in step 2021_i. Then this subsequence S_i is extracted from this part of the local memory and is provided to an external memory (for example the one from which the input sequence provided in step 201 comes) to the processor core (and external to the DSP 24), of a size greater than NT, in which all the subsequences S_i, i = 1 to N, will be stored in a consecutive manner thus reconstituting the input sequence in its interleaved form, with the interleaving length L.
[0060] Next, the processing corresponding to blocks 14 to 21 is carried out on this interlaced sequence, the corresponding signal then being sent to the receiver 25.
[0061] In the particular example now considered, the DSP 24 has ncore = N processor cores referenced 102_l, 102_N, as shown in [Fig.5].
[0062] Each processor core 102_i, i = 1 to N, is associated with the part 42_i, of the local memory; this part is of size T; here T is equal to 130 kB.
[0063] In the case considered, for i = 1 to N, step 202_i is implemented by processor core 102_i. For example, it takes place in parallel with step 202j implemented in processor core 102j, with i, j distinct and taking any value from 1 to N. This makes it possible to satisfy real-time interleaver processing performance constraints.
[0064] Each processor core 102_i calculates the entire result; but only the subsequence S_i is stored in local memory 42_i (the rest of the subsequences, represented by dotted lines, are not saved in local memory 42_i in step 202_i).
[0065] In such a case of implementation on N processors (cores) of a multicore DSP:
[0066] - each processor core reads the entire input sequence (i.e., RX = 1),
[0067] - each processor core processes (calculates the interleaving of) the entire input sequence and only saves in local memory a part out of N of the interleaver output (selectively the subsequence S_i),
[0068] - the output data (the subsequence S_i) of a processor remain local before to be transferred in a block into external memory (DRAM, from the English "Dynamic Random Access Memory") at the end of the processing of the entire input sequence of a processor (i.e. TX = 1 for all sub-sequences S_i).
[0069] For N = 4, corresponding to the schematic illustration in [Fig.7]:
[0070] - the CPU cost is multiplied by 4;
[0071] - bandwidth = data rate required (bits / sec) for the information exchanged The ratio between cores and external memory is multiplied by 2.5: it goes from (RX = 1) + (TX = 1) to (RX = 4) + (TX = 1).
[0072] In another embodiment, the N steps 202_l to 202_N are performed by an interleaver implemented with a number ncore of processors strictly less than N. At least one of the same processor cores is then used to serially perform several steps 202_i out of the N steps 202_i, i = 1 to N. Such an implementation of the invention is satisfactory if the timing constraints of the application using this interleaving allow it. For example, ncore = 1 and the N steps 202_l to 202_N are then performed serially by the single processor core. Or, if ncore = N / 2, each processor core performs 2 steps 202_i out of the N.
[0073] In one embodiment, on the first pass, on the first input sequence processed by the interleaver, each processor core saves an array Information (e.g., 0 or 1) indicates whether the interleaver's output (for each input bit) should be stored in its local memory during a step 202_i for which it is responsible. This consumes more time the first time, but at the cost of a gain for subsequent input sequences, by using this table of intermediate calculations (for implementing the subsequent input sequences of the step 202_i for which it is responsible) and the processor's cache memory (in local memory). The position must always be recalculated, and a test must be performed. During the test, either the position's position relative to the interval to be processed (i.e., the subsequence S_i to be stored) is checked, or binary information is read indicating whether the position should be stored.
[0074] In one embodiment, each processor core number k, k = 1 to ncore, pre-calculates the index of the input bits to be stored in its local memory and their associated positions (subsequence S_i). This pre-calculation results in significant computational savings because not all positions are subsequently calculated, only a portion is used (only the relevant part is calculated). Pre-calculation is particularly advantageous for a modem where there are no random changes to the interleaver parameters that need to be considered with each new input sequence.
[0075] The proposed technical solution thus consists of performing N times the interleaving function in transmission (respectively deinterleaving in reception) and saving each time only a sub-sequence (on AO of the result (the sub-sequences s each time being distinct, or even disjoint, for example consecutive): CPU x ~A(in the last two embodiments described above); Bandwidth (BP) x ~N.
[0076] In the end, we obtain the (complete) result with an interleaving length of N times the conventional interleaving length (i.e., on a single core). The calculations of the interleaving algorithm are duplicated N times (and therefore independent): more operations (more calculations and read memory accesses) than necessary are therefore performed (the calculations of (Nl) subsequences S_i are aborted); this is the price to pay to obtain a solution to the hardware technical problem of compensating for the small size of the local memory of a DSP core, i.e., of increasing the interleaving length.
[0077] The unit data to be interleaved together are, according to embodiments of the invention, bits or weighted bits (for example quantized on 8 bits).
[0078] The invention can of course be implemented with variable interleaving lengths and is of interest when the interleaving length is strictly greater than the size T of part 42 of the local memory of a core dedicated to the interleaver.
[0079] The invention can be implemented with local core memories having non-equal sizes between them.
[0080] A device, or a method according to the invention, thus makes it possible to increase the conventional length of the interlacer used.
[0081] Figure 6 represents the comparative use of CPU resources, bandwidth, local memory of a processor and external memory for the interleaving methods respectively classical (for example of HF modem type STANAG 4539® on one core) and finally according to the invention.
[0082] The invention can be implemented in various other applications such as: LDPC, convolutional encoder, cryptography.
[0083] The invention implemented with respect to an interleaver has been described above. Of course, the invention applies similarly with respect to a deinterleaver (typically that of the receiving device 25, which is in fact also an interleaver but applying an inverse interleaving algorithm to that which was performed on the data supplied to the input of the interleaver).
[0084] The described method can be implemented by executing software instructions on a processor. Alternatively, it can be implemented by dedicated hardware, typically a digital integrated circuit, either application-specific (ASIC) or based on programmable logic (e.g., FPGA).
Claims
Demands
1. A method for interleaving data of interleaving length L by an interleaving device (10) comprising a set (24) of ncore processor core(s), each core being associated with a local processor memory whose interleaving output portion (42) is of size T strictly less than the interleaving length L and being adapted to implement an interleaving algorithm of length L, and ncore being an integer greater than or equal to 1, said device (10) being adapted to implement the following steps to perform interleaving on a sequence of data to be interleaved: - implementation, N times, of the interleaving algorithm of length L on at least a respective portion of said input sequence, the interleaved input sequence being equal to the union of several distinct consecutive subsequences S_l, ..., S_N and N >1 ; - the ith implementation, i = 1 to N, of the interleaving on at least a part of said input sequence being carried out by a core of the set of n core cores, said implementation being followed by the storage in said part of local memory of said core of, among the sub-sequences S_1, ..., S_N, only the sub-sequence S_i ; - then transfer of each sub-sequence S_i into a predefined memory, external to the processor core ; at the end of the N transfers, said external memory thus containing the interleaved input sequence.
2. Data interleaving method according to claim 1, wherein ncore = N, and the i-th implementation, i = 1 to N, of the interleaving is carried out by the i-th processor core, i = 1 to N.
3. A data interleaving method according to claim 1, wherein ncore < N and at least one of the ncores successively performs: - the ith implementation, i between 1 and N-1, of the interleaving on at least a portion of said input sequence followed by the storage in the local memory (42) of said core of only the subsequence SJ, then the transfer of the subsequence S_i into the predefined external memory; - the jth implementation, j between 2 and N and strictly greater than i, of the interleaving on at least a part of said input sequence followed by the storage in the local memory (42) of said core of only the subsequence SJ, then the transfer of the subsequence SJ into the predefined external memory.
4. A data interleaving method according to any one of the preceding claims, wherein the index of the input bits in the subsequence SJ is precalculated, as well as their respective associated positions in the subsequence SJ, and the i-th implementation, i = 1 to N, of the interleaving on at least a portion of said input sequence performed by a core is carried out according to the precalculated index of the input bits in the subsequence SJ and their respective associated positions in the subsequence S i
5. A computer program, intended to be stored in memory, of an interleaving device (10) comprising a DSP (24) having a set of ncore processor core(s), each core being associated with a local processor memory having the portion (42) dedicated to the interleaving output of size T strictly less than the interleaving length L and being adapted to implement an interleaving algorithm of length L, and ncore being an integer greater than or equal to 1, said interleaving device (10) comprising a microcomputer, said computer program comprising instructions which, when executed on the microcomputer, implement the steps of a method according to any one of the preceding claims.
6. An interleaving device (10) comprising a set (24) of ncore processor core(s), each core being associated with a processor local memory whose interleaving output portion (42) is of size T strictly less than the interleaving length L, said interleaving device being adapted to implement an interleaving algorithm of length L, and ncore being an integer greater than or equal to 1, said device being adapted to implement the L-length interleaving algorithm N times on at least a respective portion of an input sequence of data to be interlaced, the interlaced input sequence being equal to the union of several distinct consecutive sub-sequences S_l, S_N and N > 1; in which the ith implementation, i = 1 to N, of the interlacing on at least a part of said input sequence is carried out by a core of the set of n core cores, said device being adapted to, following said implementation, store in said part of local memory of said core, among the sub-sequences S_l, ..., S_N, only the sub-sequence S_i; said device (10) being adapted to then transfer each sub-sequence S_i into a predefined memory, external to the processor core so that at the end of the N transfers, said external memory thus contains the interlaced input sequence.
7. Data interleaving device (10) according to claim 6, wherein ncore = N, and wherein the ith implementation, i = 1 to N, of the interleaving is performed by the ith processor core, i = 1 to N
8. Data interleaving device (10) according to claim 6, wherein ncore < N and at least one of the same core among the ncore cores is adapted to perform successively: - the ith implementation, i between 1 and N-1, of interleaving on at least a part of said input sequence followed by storing in the local memory of said core only the subsequence S_i, then transferring the subsequence S_i into the predefined external memory; - the jth implementation, j between 2 and N and strictly greater than i, of interleaving on at least a part of said input sequence followed by storing in the local memory of said core only the subsequence SJ, then transferring the subsequence SJ into the predefined external memory.
9. A data interleaving device (10) according to any one of claims 6 to 8, wherein the index of the input bits that are in the subsequence SJ is precalculated, as well as their respective associated positions in the subsequence SJ, and the device is adapted to perform the i-th implementation, i = 1 to N, of the interleaving on at least a portion of said input sequence performed by a core as a function of the precalculated index of the input bits in the subsequence S_i and their respective associated positions in the subsequence S_i.