A semiconductor device

Abstract

The device comprises a cathode contact having first and second arrays of cathode cells 150. The cathode cells are disposed in a p-base region 160 proximate the cathode surface. The device further comp

Description

Background of the Invention This invention relates to a semiconductor device and particularly, but not exclusively, to a trench clustered insulated gate bipolar transistor (TCIGBT) device. Traditionally, power Metal Oxide Field Effect Transistors (MOSFETs) have been used in low to medium power applications. However, it has been found that Insulated Gate Bipolar Transistors (IGBTs) enable better performance in such applications due to their lower on-state power loss and higher current densities. The power ratings of IGBTs are slowly increasing and they are envisaged to replace thyristors in medium power applications such as High Voltage Direct Current (HDVC) inverter systems and traction drive controls. MOS Gated Thyristor (MGT) devices have been identified as a promising alternative to transistor-based devices as they exhibit a lower forward voltage drop and improved current densities. The clustered IGBT (CIGBT) described in International Patent Application No. WO01 / 18876 is a MOS gated thyristor device that exhibits a unique self-clamping feature that protects cathode cells from high anode voltages under all operating conditions. The self-clamping feature also enables current saturation at high gate biases and provides low switching losses. The CIGBT low on-state voltage and high voltage blocking capabilities make the CIGBT highly suitable as an alternative to the IGBT. WO2015 / 011440 discloses a CIGBT. Specifically, the document discloses a cathode cell structure array and method of fabricating the same, using CIGBT technology. However, the intra-cell structure is found to present a significant gate capacitance which can affect the performance of the transistor. It is an object of the present invention to provide a semiconductor device which alleviates at least some of the above limitations. Summary of the Invention In accordance with the present invention, there is provided a semiconductor device comprising a body having a cathode contact surface and an anode contact surface separated along a first direction, the body further comprising at least one first array of MOS gated thyristor cells and second array of MOSgated thyristor cells formed therein separated along a second direction, the first and second array of cells comprising: - a base region of a first conductivity type disposed proximate the cathode contact surface and having disposed therein at least one cathode region of a second conductivity type, the cathode regions of each cell being connected by the cathode contact surface; - a first well region of the second conductivity type; - a second well region of the first conductivity type which extends to the cathode contact surface; - a drift region of the second conductivity type; and - an anode region of the first conductivity type disposed proximate the anode contact surface; each cell of the first and second array of cells being disposed within the first well region of the respective array, the first well region of each array being disposed within the second well region of the respective array; the device further comprising an elongate trench comprising a gate disposed therein, the trench intersecting the second well region and the drift region of the first and second array of cells at a region disposed between the at least one first and second array of cells; the drift region of the first and second array of cells being common to both the first and second array, and wherein the semiconductor device further comprises a buffer region of the first conductivity type which connects the second well region of the first and second array, and which extends between the drift region and the cathode contact surface, at the cathode contact surface, at the region disposed between the at least one first and second array of cells, the buffer region being arranged to adjust the charge in the region between the anode contact surface and the gate. The presence of the buffer region serves to reduce the charge build up at the gate by providing a conduit between neighbouring arrays of cells, so that excess charges can distribute evenly throughout the body. The gate capacitance affects the switching behaviour of the circuit. Unbalanced gate capacitances can cause oscillatory behaviour in switching, as well as affect switching speed and energy, so it is important to carefully manage gate capacitance. The buffer region serves to reduce gate capacitance in the intercell portion of the device, without affecting the operation of the intra-cell portions. In an embodiment, the device comprises a plurality of trenches, each comprising a respective gate disposed therein. In an embodiment, the cathode surface and anode surface are disposed on opposite sides of the body. An insulating film is provided to substantially cover an inner surface of the trench and a gate is formed on the insulating film so as to substantially fill the trench. The trench extends all the way through the base region and is configured to allow electron conduction through the base region. In an embodiment, the trench and gate extend along the first direction through the base region and terminate within the first well region. Alternatively, the trench and gate may extend along the first direction through the base region and the first well region and terminate in the second well region. The extent to which the gate and trench extend into the body is dependent on, for example, required device characteristics and processing constraints. In an embodiment, the trench is configured to extend along the second direction and intersect the drift region and the first and second well regions of the at least one first and second array. In an embodiment, the or each trench is configured to extend along the first direction, and intersect the base region and terminate in the first well region or the second well region. In an embodiment, each cell of the first and / or second array of cells comprise a cathode region having a first and second conductivity type, the first and second conductivity types of the cathode region of each cell being connected together through conductive contacts to configure the cells operative. In an embodiment, the device comprises a plurality of gates and at least one gate of the plurality of gates is maintained at a separate voltage to the other gates, to render a proportion of the cells of inactive or inoperative, namely dummy cells. In an alternative embodiment, a proportion of cells of the first and / or second array of cells comprise a cathode region having a first and second conductivity type, the first and second conductivity types of the cathode region of the proportion of cells being connected together through conductive contacts to configure the proportion of cells operative, with the remaining cells being inoperative, dummy cells. In a further alternative, a proportion of the cells of the first and / or second array of cells to not comprise a cathode region. In an embodiment, the semiconductor device further comprises a least one pillar which extends within the drift region of the at least one first and / or second array of cells, the pillar comprising the same material composition as the second well region, having the first conductivity type. The pillar may extend from the second well region into the drift region and terminate within the drift region. Alternatively, the pillar may extend from the anode region into the drift region and terminate in the drift region. In a further alternative, the pillar connects, effectively bridges, the second well region with the anode region. In yet a further alternative, the pillar comprises an isolated region within the drift region, and is unconnected with the second well region and the anode region. In an embodiment, the semiconductor device further comprises at least one further pillar which extends within the drift region of the at least one first and / or second array of cells, the at least one further pillar being formed of the same material composition as the second well region, having the first conductivity type, the at least one further pillar extending between the buffer region and the anode region. Brief Description of the Drawings An exemplary embodiment of this invention will now be described by way of example only and with reference to the accompanying drawings, in which: Figure 1 is a perspective view of cutaway section through a body of a semiconductor device according to an exemplary embodiment of the present invention; Figure 2 is a sectional view through the device illustrated in figure 1, taken along the y-axis; Figure 3 is a sectional view through the device illustrated in figure 1, with the left hand portion illustrating the view along the y-axis and the right hand portion illustrating the view along a trench (with the p-well and part of the n-drift region removed) so that the extent of the trench and gate into the body along the z-axis can be seen; Figure 4 is an end view of the device illustrated in figure 1; Figure 5 is a sectional view through the device illustrated in figure 1, taken along an axis through a centre of the device, parallel to the x-axis; Figure 6 is plan view of the device illustrated in figure 1, with (a) the p+ cathode regions disposed above the n+ cathode regions, and (b) the p+ cathode regions disposed below the n+ cathode regions; Figure 7 is an extension to the plan view of the device illustrated in figure 6 with multiple cells illustrated, and with (a) the p+ cathode regions disposed above the n+ cathode regions, and (b) the p+ cathode regions disposed below the n+ cathode regions; Figure 8 is a perspective view of a semiconductor device according to an embodiment of the present invention, comprising a pillar which extends between the second well region and the drift region; and, Figure 9 is a perspective view of a semiconductor device according to an embodiment of the present invention comprising a plurality of pillars which extend between the second well region and the drift region Detailed Description of Embodiments of the Invention Referring to Figure 1 of the drawings, there is illustrated a perspective view of a section of a semiconductor device 100 according to an embodiment of the present invention. The device comprises a planar body 110 (only a section of which is illustrated) which is typically, but not necessarily exclusively, formed of monocrystalline silicon, and which comprises a cathode contact surface 200 on one side of the planar body (the upper side of the device illustrated in figure 1) and an anode contact surface 300 on an opposite side of the planar body (namely the lower side of the device illustrated in figure 1). The cathode and anode surfaces 200, 300 are thus separated along a first, namely z-direction and provide the external connection points to cathodes and anodes, which have been omitted for clarity in order to better illustrate the internal structure of the semiconductor device 100. The device is an NPT (non-punch through) device, through which diffusions are made to provide a pattern of cathode cells at the cathode surface. Punch through (PT) and / or Field Stop (FS) technologies are also within the scope of the invention. Specifically, and referring to figures 1 and 2 of the drawings, the body 110 of the device comprises a plurality of arrays of cathode cells. In the following description, the device 100 will be described with respect to a first and second array A1, A2 of cathode cells only separated along a second direction (namely the y-direction), although the skilled reader will recognise that a real device will comprise multiple arrays disposed within the body 110 which extend both longitudinally (namely, along the y-direction) and laterally (namely, along the x-direction) of the body 110, and which may be configured to a particular pattern, such as a square pattern within the body. This technique can be used in Reverse Conducting devices as well as conventional devices. The body 110 comprises a drift region 120 having a second conductivity type, namely an N-type in the present embodiment, which is common to each array of the device. The cathode cells are localised to a given array and each array is formed by diffusing a respective second well 130 having a first conductivity type, namely a P-type well in the present embodiment, into the N drift region 120. Each array further includes a first well 140 having a second conductivity type, namely an N-type well, diffused into the P well 130, so as to lie within the P well 130 both vertically (along z-direction), longitudinally (along y-direction) and laterally (along the x-direction). Within the N well 140 a cluster of cathode cells 150 are formed (see figures 6 and 7), separated by trenches 152 and each cell is identical in structure so that only one of them will be described in detail. Thus, each cell 150 comprises a shallow base region 160 formed adjacent the cathode surface 200 and having a first conductivity type, namely a P-type in the present embodiment, diffused into N well 140. The skilled reader will recognise however, that the arrangement of conductivity types within each array, may be opposite to that described above (and below) and as such a complementary device may be formed by reversing the conductivity types. In any event, it will be appreciated that the P base region, N well, P well, N drift region effectively form a four layer semiconductor device, akin to a thyristor. All the diffusions are made through the surface 112 of the body 110 using, for example, a plurality of conventional lithography stages. The particular process used to achieve these diffusions is not critical to the invention; any known process for effecting diffusion regions may be used, and this process will, therefore, not be described further in any detail. However, it will be appreciated by a person skilled in the art that it may be possible to form the structure with growth processes involving those regions selectively or otherwise, such as epitaxy, and this is applicable, particularly, but not exclusively, to wide bandgap devices such as Silicon Carbide devices. Referring now to figures 3-5 of the drawings, and as stated previously, the N well 140 contains a cluster of cathode cells 150, each cell being of the same symmetric construction (although the skilled reader will recognise that the cells do not need to be symmetric). The cells 150 are formed in the P base region 160 which is intersected by a gate structure 154 of each cell 150. The gate structure 154 comprises a trench 152 (two of which are illustrated, although in reality, the device can comprise many trenches extending across the body of the device), etched from the body surface 112, and extending from that surface through the P base region 160 and N well 140, into the P well region 130. In alternative embodiments, the trench 152 may extend only into the N well region 140. The trenches 152 extend longitudinally of the body 110 (namely along the y-direction) and extend between the first and second array A1, A2 of the device 100. A gate 154, which may be formed of polysilicon, is located in each trench 152 and isolated from the adjacent semiconductor material by a gate insulator, such as a gate oxide (not shown), and the purpose of the gate 154 is to allow conduction of charge carriers through the P base 160, such that current can flow between the cathode 200 and anode 300. In an exemplary embodiment of the present invention, after the trench gates 154 have been formed, a plurality of N+ cathode regions 156 are selectively diffused into the P base region 160, and which extend across the P base 160 region substantially transverse to the trenches 152. Each N+ region 156 separately defines a cathode cell 150 and these cathode cells 150 are separated along a longitudinal axis, within the P base region 160. The width (i.e. in the y-direction in figures 6 and 7) of the N+ cathode regions 156 is not fixed and can vary. Once the N+ cathode regions 156 have been formed, a P+ cathode region 158 is then diffused into the P base region 160. The P+ cathode region 158 extends along the array between the trenches 152 and the width (i.e. in the x-direction in figures 6 and 7) can be varied. The P+ cathode region 158 extends between the N+ cathode regions 156, substantially parallel to the longitudinal axis of the trenches 152. As illustrated in figure 6 of the drawings, the P+ region 158 extends over the N+ region 156, however, in an alternative embodiment, as illustrated in figure 7 of the drawings, the P+ cathode regions 158 may instead be formed below the N+ cathode regions 156. The cathode regions 158 extend adjacent the cathode surface 200 and a cathode contact, namely an emitter contact 210, is arranged to bridge, namely contact both the N+ and P+ cathode regions 156, 158 to form a non-rectifying junction with the P base region 160. The cathode regions 156, 158 thus provide the “emitter” terminal of the transistor, and the gate 154 controls the conduction from the cathode / emitter 200 to the P well 130. In figure 4, the cathode contacts 156, 158 are provided by metallisation extending to each cathode region of cell. An anode region 310 formed of a first conductivity type, namely a P-type in the present embodiment, is formed on the anode surface 300 of the drift region, to which the anode contact (not shown) is made to form the “collector” terminal of the transistor. In some cases, it may be required to provide so-called “dummy cells” (not shown) within the structure, in order to increase the spacing between the N well 140 of a cathode cell 150 and that of adjacent cells. This may be achieved simply by omitting the N+ cathode regions 156 at positions along the array. These dummy cells (not shown) can be dispersed independently within an array. The number of dummy cells within a structure is dependent upon design, the fabrication process used and the required device characteristics. It has been shown that the use of dummy cells in the cathode cell structure can improve the trade-off between the on-state and turn-off losses, and allow the current density within the device to be varied. Alternatively, in situations where the device 100 comprises a plurality of trenches 152, and a gate 154 disposed in each of the plurality of trenches 152, rather than omitting the N+ cathode regions 156, or in addition thereto, it is envisaged that each gate could be kept at a bespoke potential. For example, in the device illustrated in the drawings, it is envisaged that each gate 154 could be maintained at a different potential, such as -15 V and 15 V, or 0 V and 15 V. This will create a similar effect as incorporating a dummy cell, but will offer the advantage of enabling a “dummy gate” to be turned on through correct wire bonding by selectively applying a voltage to the gate, without requiring a separate wafer fabrication step to convert the dummy gates into active cells. The dummy gates allow the electric field within the device to be adjusted and thus influence the capacitance. The cluster of cathode regions 156, 158 can be built together. For example, a striped configuration comprising a plurality of parallel “stripes” or trenches, between arrays A1, A2 of cathode cells 150, wherein each cell is provided with a set of gate contacts and connected thereby, via trenches, to the power supply. It will be appreciated that these connecting trenches do not need to be configured in simply a parallel longitudinal configuration across the body 110 of the device - a large number of alternative configurations is envisaged, for example, a zig-zag pattern, and the present invention is in no way intended to be limited in this regard. In some configurations the same trench longitudinally intersects (namely, along the y-direction) the P base 160, N well 140 and P well regions 130 of each array 150, and possibly also the N-drift region 120. The same trench may also vertically (namely, along the z -direction) intersect the P base 160, although this is not a requirement. For example, referring to Figure 1, the trench 152 is arranged to intersect the P base 160 along the z -axis and terminate in the N well or P well region so that the gate disposed therein can act as a control gate (once the device is turned on), and intersect the P base 160, N well 140 and P well 130 along the y-axis to turn the device on and allow current conduction. However, in an alternative embodiment, it is envisaged that one trench may intersect the N well region 140, P well region 130 and N drift region 120 along the surface to function as a “turn-on” trench, and a separate “control trench” may be provided proximate the N+ / P+ cathode regions 156, 158. During use, when a positive bias above the threshold voltage is applied to the gate 154, the cathode cells 150 are turned on and the electrons are supplied into the N-drift region 120. When the anode voltage is above the bipolar on-set voltage, holes are injected from the anode. However, there is no path for holes to flow directly into the cathode regions 156, 158. As a result, the potential of the P well region 130 increases. The concentration of the N well 140 plays an important role in the overall performance of the device and is above the critical limit required to create a barrier for holes, as is the case with a charge stored IGBT (CS-IGBT). When the control gates are ON, the N well 140 is tied to the cathode potential through the accumulation region formed in the N well region 140 and inverted channels in the P base region 160. With increase in the potential differences of the P well 130 and N well 140 junction above its built-in potential, results in the firing ON of the cathode cells 150. Once the cathode cells 150 are ON, the N well / P well 140, 130 potential increases with further increase in the anode voltage. This increase in the potential leads to the enhancement of the P base / N well 140, 130 depletion region. As the concentration of the N well 140 is lower than that of the P base 130, the depletion region predominantly moves into the N well region 140. At a certain voltage (determined by the doping concentration, the depth of the N well 140, the depth of the P base 130 and the MOS channel saturation characteristic), the depletion touches the P well / N well junction and at that point the device becomes clamped. The self clamping feature ensures that any further increase in the anode potential is dropped only across the P well / N drift region 130, 120. This self-clamping voltage can be less than, equal to or higher than that of the MOSFET saturation voltages. The device turn-off performance is similar to that of the IGBT. When the control gate is turned off, the potential across the P base / N well 160, 140 increases until self-clamping occurs. Once it is clamped, the wide nature of the P well 130 enables the holes to be collected to the P base region 160 effectively. Referring to figure 1,2 and 5 of the drawings, the device 100 further comprises a buffer region 170 of a first conductivity type, namely a P-type in the present embodiment, localised between the first and second array A1, A2. The P buffer region 170 comprises a layer which extends between the body surface 112 and the N drift region 120 to effectively shield the N drift region 120 from the surface 112 of the body 110. The P buffer region 170 extends to a depth into the body 110 which is less than the depth of the P base region 160 and extends into the P well region 130 of neighbouring arrays to effectively couple the arrays. The P buffer region 170 adjusts the charge between the gate 154 and the collector in the non-active regions, as this area surrounding the gate 154 is charged with the same polarity as the collector. The capacitance between the gate 154 and anode (not shown) is therefore reduced as it is thought the P buffer region 170 reduces the dQ / dV in this portion of the device. In a further embodiment of the present invention, the semiconductor device 100 further comprises at least one pillar region 180 having a second conductivity type which extends into the N drift region 120. In the embodiment illustrated in figure 9 of the drawings, at least one of the first or second arrays A1, A2 comprise three pillars 180a-c (although the number of pillars may be varied) formed of the same material composition as the P well 130 and which extend from the P well 130 into the N drift region 120. However, the pillars 180 may also extend from the P buffer region 170 into the N drift region 120. The pillars 180 may comprise a variety of cross-sectional shapes. In the illustrated embodiment, the pillars 180 comprise a circular cross-section and thus have a cylindrical form, however, the skilled reader will recognise that alternative cross-sectional shapes for the pillars 180 may be used, including square. The pillars 180 extend through the full thickness of the N drift region 120 and terminate at a further buffer region or layer having a first conductivity type, namely an N-type in the present embodiment, which is disposed between the N drift 120 and anode contact surface 300. The pillars 180 extend substantially perpendicular to the anode and cathode surfaces 300, 200 and are separated along a longitudinal axis of the device. In a further embodiment which is not illustrated, the P pillars 180 may alternatively extend from the P well 130 and terminate within the N drift region 120, or in a further alternative, extend from the N buffer region 170 and terminate within the N drift region 120. Moreover, it is also envisaged that the P pillars 180 may comprise islands (not shown), namely isolated regions within the N drift region 120. These p-pillars 180 allow hole conduction during the operation of the device (as the device is bipolar), and in a Super-Junction style embodiment of the device, these pillars 180 form hole-conduction channels, while the n-drift region 120 forms electronconduction channels.

Claims

1. A semiconductor device comprising a body having a cathode contact surface and an anode contact surface separated along a first direction, the body further comprising at least one first array of MOS gated thyristor cells and second array of MOS-gated thyristor cells formed therein separated along a second direction, the first and second array of cells comprising:- a base region of a first conductivity type disposed proximate the cathode contact surface and having disposed therein at least one cathode region of a second conductivity type, the cathode regions of each cell being connected by the cathode contact surface;- a first well region of the second conductivity type;- a second well region of the first conductivity type whichextends to the cathode contact surface;- a drift region of the second conductivity type; and- an anode region of the first conductivity type disposed proximate the anode contact surface;each cell of the first and second array of cells being disposed within the first well region of the respective array, the first well region of each array being disposed within the second well region of the respective array;the device further comprising an elongate trench comprising a gate disposed therein, the trench intersecting the second well region and the drift region of the first and second array of cells at a region disposed between the at least one first and second array of cells;the drift region of the first and second array of cells being common to both the first and second array, and wherein the semiconductor device further comprises a buffer region of the first conductivity type which connects the second well region of the first and second array, and which extends between the drift region and the cathode contact surface, at the cathode contact surface, at the region disposed between the at least onefirst and second array of cells, the buffer region being arranged to adjust the charge in the region between the anode contact surface and the gate.

2. A semiconductor device according to claim 1, comprising a plurality of the elongate trenches, each comprising a respective gate disposed therein.

3. A semiconductor device according to claim 1 or 2, wherein an insulating film is provided to substantially cover an inner surface of the or each trench and wherein a gate is formed on the insulating film so as to substantially fill the trench.

4. A semiconductor device according to any preceding claim, wherein the or each trench is configured to extend along the second direction and intersect the drift region and the first and second well regions of the at least one first and second array.

5. A semiconductor device according to any preceding claim, wherein the or each trench is configured to extend along the first direction and intersect the base region and terminate in the N well region or the P well region.

6. A semiconductor device according to any preceding claim, wherein each cell of the first and / or second array of cells comprise a cathode region having a first and second conductivity type, the first and second conductivity types of the cathode region of each cell being connected together through conductive contacts to configure the cells operative.

7. A semiconductor device according to any of claims 1-5, wherein a proportion of cells of the first and / or second array of cells comprise a cathode region having a first and second conductivity type, the first and second conductivity types of the cathode region of the proportion of cells being connected together through conductive contacts to configure the proportion of cells operative, with the remaining cells being inoperative, dummy cells.

8. A semiconductor device according to claim 7, wherein the dummy cells do not comprise the cathode region having the second conductivity type.

9. A semiconductor device according to any preceding claim, further comprising a least one pillar which extends within the drift region of the at least one first and / or second array of cells, the pillar comprising the same material composition as the second well region, having the first conductivity type.

10. A semiconductor device according to claim 9, wherein the pillar extends from the second well region into the drift region and terminates within the drift region.

11. A semiconductor device according to claim 9, wherein the pillar extends from the anode region into the drift region and terminates in the drift region.

12. A semiconductor device according to claim 9, wherein the pillar connects the second well region with the anode region.

13. A semiconductor device according to claim 9, wherein the pillar comprises an isolated region within the drift region and is unconnected with the second well region and the anode region.

14. A semiconductor device according to any preceding claim, further comprising a least one further pillar which extends within the drift region of the at least one first and / or second array of cells, the at least one further pillar being formed of the same material composition as the second well region, having the first conductivity type, the at least one further pillar extending between the buffer region and the anode region.

Images