Accessing tensors

Abstract

Apparatuses, systems, and techniques to access a multidimensional tensor from memory while minimizing tile quantization is disclosed. In at least one embodiment, a processor includes one or more circu

Description

TECHNIC AL FIELD

[0001] At least one embodiment pertains to processing resources used to perform and facilitate artificial intelligence. For example, at least one embodiment pertains to processors or computing systems used to train and use neural networks according to various novel techniques described herein. BACKGROUND

[0002] A tensor generalizes scalars, vectors and matrices and is represented using a multidimensional array with a uniform data type. In machine learning, data often are multidimensional and can be stored as tensors.

[0003] For example, a picture can be stored as a three-dimensional tensor with dimensions: (H) height, (W) weight, and (C) channel (e.g., 3 for RGB color, 1 for grayscale). An example of a tensor layout format can be NDHWC to store a batch of three-dimensional (3D) images, where storage order is: N - number of pictures in a batch, D - depth of image, H - height of image, W -width of image, C - number of channels. Another example layout format can be NHWC for a batch of two-dimensional (2D) images. SUMMARY OF THE INVENTION

[0004] Aspects and embodiments of the present invention are set out in the appended claims. These and other aspects and embodiments of the invention are also described herein.

[0005] According to various aspects described herein, there may be provided apparatuses, systems, and techniques to access a multidimensional tensor from memory while minimizing tile quantization. In at least one embodiment, a processor may include one or more circuits to cause a first one or more portions of at least one tensor to be accessed from a memory using a first technique and a second one or more portions of the at least one tensor to be accessed from the memory using a second technique based, at least in part, on an input to combine the first and second techniques.

[0006] The disclosure extends to any novel aspects or features described and / or illustrated herein.

[0007] Further features of the disclosure are characterized by the independent and dependent claims.

[0008] Any feature in one aspect of the disclosure may be applied to other aspects of the disclosure, in any appropriate combination. In particular, method aspects may be applied to apparatus or system aspects, and vice versa. (0009] Furthermore, features implemented in hardware may be implemented in software, and vice versa. Any reference to software and hardware features herein should be construed accordingly.

[0010] Any system or apparatus feature as described herein may also be provided as a method feature, and vice versa. System and / or apparatus aspects described functionally (including means plus function features) may be expressed alternatively in terms of their corresponding structure, such as a suitably programmed processor and associated memory. [0011 ] It should also be appreciated that particular combinations of the various features described and defined in any aspects of the disclosure can be implemented and / or supplied and / or used independently.

[0012] The disclosure also provides computer programs and computer program products comprising software code adapted, when executed on a data processing apparatus, to perform any of the methods and / or for embodying any of the apparatus and system features described herein, including any or all of the component steps of any method.

[0013] The disclosure also provides a computer or computing system (including networked or distributed systems) having an operating system which supports a computer program for carrying out any of the methods described herein and / or for embodying any of the apparatus or system features described herein.

[0014] The disclosure also provides a computer readable media having stored thereon any one or more of the computer programs aforesaid.

[0015] The disclosure also provides a signal carrying any one or more of the computer programs aforesaid.

[0016] The disclosure extends to methods and / or apparatus and / or systems as herein described with reference to the accompanying drawings.

[0017] Aspects and embodiments of the disclosure will now be described purely by way of example, with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0018] FIG. 1A illustrates inference and / or training logic, according to at least one embodiment;

[0019] FIG. IB illustrates inference and / or training logic, according to at least one embodiment;

[0020] FIG. 2 illustrates training and deployment of a neural network, according to at least one embodiment;

[0021] FIG. 3 A is a flow diagram of a process to access an input tensor using a combined technique, according to at least one embodiment.

[0022] FIG. 3B is a flow diagram of a process to access an input tensor using a combined technique, according to at least one embodiment.

[0023] FIG. 4 is a block diagram of an input tensor illustrating tile quantization, according to at least one embodiment;

[0024] FIG. 5 illustrates a relationship of a bounding box to parameters: boxBaseCorner{D,H,W] and boxFarCorner{D,H,W}, according to at least one embodiment;

[0025] FIG. 6A illustrates processing for requests in im2col mode with padding, according to at least one embodiment;

[0026] FIG. 6B illustrates processing for requests in im2col mode with without padding, according to at least one embodiment;

[0027] FIG. 6C illustrates processing for requests in tiled mode with paddings, according to at least one embodiment;

[0028] FIG. 6D illustrates processing for requests in tiled mode without paddings, according to at least one embodiment;

[0029] Fig. 7 A is a block diagram of an input tensor used for ti! ed im2col access technique, according to at least one embodiment;

[0030] FIG. 7B is a block diagram of an input tensor used for tiled / im2col access technique, according to at least one embodiment; [0031 ] FIG. 8 is a block diagram of an example input tensor using a tiled access technique, according to at least one embodiment;

[0032] FIG. 9 illustrates an example data center system, according to at least one embodiment; [0033 ] FIG. 10A illustrates an example of an autonomous vehicle, according to at least one embodiment;

[0034] FIG. 10B illustrates an example of camera locations and fields of view for autonomous vehicle of FIG. 10A, according to at least one embodiment;

[0035] FIG. 10C is a block diagram illustrating an example system architecture for autonomous vehicle of FIG. 10A, according to at least one embodiment;

[0036] FIG. 10D is a diagram illustrating a system for communication between cloud-based server(s) and autonomous vehicle of FIG. 10A, according to at least one embodiment;

[0037] FIG. 11 is a block diagram illustrating a computer system, according to at least one embodiment;

[0038] FIG. 12 is a block diagram illustrating a computer system, according to at least one embodiment;

[0039] FIG. 13 illustrates a computer system, according to at least one embodiment;

[0040] FIG. 14 illustrates a computer system, according to at least one embodiment;

[0041] FIG. 15A illustrates a computer system, according to at least one embodiment;

[0042] FIG. 15B illustrates a computer system, according to at least one embodiment;

[0043] FIG. 15C illustrates a computer system, according to at least one embodiment;

[0044] FIG. 15D illustrates a computer system, according to at least one embodiment;

[0045] FIG. 15E and 15F illustrate a shared programming model, according to at least one embodiment;

[0046] FIG. 16 illustrates exemplary integrated circuits and associated graphics processors, according to at least one embodiment;

[0047] FIGS. 17A-17B illustrate exemplary integrated circuits and associated graphics processors, according to at least one embodiment;

[0048] FIGS. 18A-18B illustrate additional exemplary graphics processor logic according to at least one embodiment;

[0049] FIG. 19 illustrates a computer system, according to at least one embodiment;

[0050] FIG. 20A illustrates a parallel processor, according to at least one embodiment; [00511 FIG. 20B illustrates a partition unit, according to at least one embodiment,

[0052] FIG. 20C illustrates a processing cluster, according to at least one embodiment;

[0053] FIG. 20D illustrates a graphics multiprocessor, according to at least one embodiment;

[0054] FIG. 21 illustrates a multi-graphics processing unit (GPU) system, according to at least one embodiment;

[0055] FIG. 22 illustrates a graphics processor, according to at least one embodiment;

[0056] FIG. 23 is a block diagram illustrating a processor micro-architecture for a processor, according to at least one embodiment;

[0057] FIG. 24 illustrates a deep learning application processor, according to at least one embodiment;

[0058] FIG. 25 is a block diagram illustrating an example neuromorphic processor, according to at least one embodiment;

[0059] FIG. 26 illustrates at least portions of a graphics processor, according to one or more embodiments;

[0060] FIG. 27 illustrates at least portions of a graphics processor, according to one or more embodiments;

[0061] FIG. 28 illustrates at least portions of a graphics processor, according to one or more embodiments;

[0062] FIG. 29 is a block diagram of a graphics processing engine of a graphics processor in accordance with at least one embodiment;

[0063] FIG. 30 is a block diagram of at least portions of a graphics processor core, according to at least one embodiment;

[0064] FIGS. 31A-31B illustrate thread execution logic including an array of processing elements of a graphics processor core according to at least one embodiment;

[0065] FIG. 32 illustrates a parallel processing unit (“PPU”), according to at least one embodiment; (0066] FIG. 33 illustrates a general processing cluster (“GPC”), according to at least one embodiment;

[0067] FIG. 34 illustrates a memory partition unit of a parallel processing unit (“PPU”), according to at least one embodiment;

[0068] FIG. 35 illustrates a streaming multi-processor, according to at least one embodiment.

[0069] FIG. 36 is an example data flow diagram for an advanced computing pipeline, in accordance with at least one embodiment;

[0070] FIG. 37 is a system diagram for an example system for training, adapting, instantiating and deploying machine learning models in an advanced computing pipeline, in accordance with at least one embodiment; [ 007 3 ] FIG. 38 includes an example illustration of a deployment pipeline for processing imaging data, in accordance with at least one embodiment;

[0072] FIG. 39A includes an example data flow diagram of a virtual instrument supporting an ultrasound device, in accordance with at least one embodiment; and

[0073] FIG. 39B includes an example data flow diagram of a virtual instrument supporting a CT scanner, in accordance with at least one embodiment. DETAILED DESCRIPTION INFERENCE AND TRAINING LOGIC

[0074] FIG. 1A illustrates inference and / or training logic 115 used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 115 are provided below in conjunction with FIGS. 1A and / or IB.

[0075] In at least one embodiment, inference and / or training logic 115 may include, without limitation, code and / or data storage 101 to store forward and / or output weight and / or input / output data, and / or other parameters to configure neurons or layers of a neural network trained and / or used for inferencing in aspects of one or more embodiments. In at least one embodiment, training logic 115 may include, or be coupled to code and / or data storage 101 to store graph code or other software to control timing and / or order, in which weight and / or other parameter information is to be loaded to configure logic, including integer and / or floating point units (collectively, arithmetic logic units (ALUs) or simply circuits). In at least one embodiment, code, such as graph code, loads weight or other parameter information into processor ALUs based on an architecture of a neural network to which such code corresponds. In at least one embodiment, code and / or data storage 101 stores weight parameters and / or input / output data of each layer of a neural network trained or used in conjunction with one or more embodiments during forward propagation of input / output data and / or weight parameters during training and / or inferencing using aspects of one or more embodiments. In at least one embodiment, any portion of code and / or data storage 101 may be included with other on-chip or off-chip data storage, including a processor’s LI, L2, or L3 cache or system memory. |007€>] In at least one embodiment, any portion of code and / or data storage 101 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 101 may be cache memory, dynamic randomly addressable memory (“DRAM”), static randomly addressable memory (“SRAM”), non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, a choice of whether code and / or data storage 101 is internal or external to a processor, for example, or comprising DRAM, SRAM, flash or some other storage type, may depend on available storage on-chip versus off-chip, latency requirements of training and / or inferencing functions being performed, batch size of data used in inferencing and / or training of a neural network, or some combination of these factors.

[0077] In at least one embodiment, inference and / or training logic 115 may include, without limitation, a code and / or data storage 105 to store backward and / or output weight and / or input / output data corresponding to neurons or layers of a neural network trained and / or used for inferencing in aspects of one or more embodiments. In at least one embodiment, code and / or data storage 105 stores weight parameters and / or input / output data of each layer of a neural network trained or used in conjunction with one or more embodiments during backward propagation of input / output data and / or weight parameters during training and / or inferencing using aspects of one or more embodiments. In at least one embodiment, training logic 115 may include, or be coupled to code and / or data storage 105 to store, graph code or other software to control timing and / or order, in which weight and / or other parameter information is to be loaded to configure, logic, including integer and / or floating point units (collectively, arithmetic logic units (ALUs).

[0078] In at least one embodiment, code, such as graph code, causes loading of weight or other parameter information into processor ALUs based on an architecture of a neural network to which such code corresponds. In at least one embodiment, any portion of code and / or data storage 105 may be included with other on-chip or off-chip data storage, including a processor’s LI, L2, or L3 cache or system memory. In at least one embodiment, any portion of code and / or data storage 105 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 105 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, a choice of whether code and / or data storage 105 is internal or external to a processor, for example, or comprising DRAM, SRAM, flash memory or some other storage type may depend on available storage on-chip versus off-chip, latency requirements of training and / or inferencing functions being performed, batch size of data used in inferencing and / or training of a neural network, or some combination of these factors.

[0079] In at least one embodiment, code and / or data storage 101 and code and / or data storage 105 may be separate storage structures. In at least one embodiment, code and / or data storage 101 and code and / or data storage 105 may be a combined storage structure. In at least one embodiment, code and / or data storage 101 and code and / or data storage 105 may be partially combined and partially separate. In at least one embodiment, any portion of code and / or data storage 101 and code and / or data storage 105 may be included with other on-chip or off-chip data storage, including a processor’s LI, L2, or L3 cache or system memory.

[0080] In at least one embodiment, inference and / or training logic 115 may include, without limitation, one or more arithmetic logic umt(s) (“ALU(s)”) 110, including integer and / or floating point units, to perform logical and / or mathematical operations based, at least in part on, or indicated by, training and / or inference code (e.g., graph code), a result of which may produce activations (e.g., output values from layers or neurons within a neural network) stored in an activation storage 120 that are functions of inputoutput and / or weight parameter data stored in code and / or data storage 101 and / or code and / or data storage 105. In at least one embodiment, activations stored in activation storage 120 are generated according to linear algebraic and or matrix-based mathematics performed by ALU(s) 110 in response to performing instructions or other code, wherein weight values stored in code and / or data storage 105 and / or data storage 101 are used as operands along with other values, such as bias values, gradient information, momentum values, or other parameters or hyperparameters, any or all of which may be stored in code and / or data storage 105 or code and / or data storage 101 or another storage on or off-chip. [0081 ] In at least one embodiment, ALU(s) 110 are included within one or more processors or other hardware logic devices or circuits, whereas in another embodiment, ALU(s) 110 may be external to a processor or other hardware logic device or circuit that uses them (e.g., a coprocessor). In at least one embodiment, ALUs 110 may be included within a processor’s execution units or otherwise within a bank of ALUs accessible by a processor’s execution units either within same processor or distributed between different processors of different types (e.g., central processing units, graphics processing units, fixed function units, etc.). In at least one embodiment, code and / or data storage 101, code and / or data storage 105, and activation storage 120 may share a processor or other hardware logic device or circuit, whereas in another embodiment, they may be in different processors or other hardware logic devices or circuits, or some combination of same and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of activation storage 120 may be included with other on-chip or off-chip data storage, including a processor’s LI, L2, or L3 cache or system memory. Furthermore, inferencing and / or training code may be stored with other code accessible to a processor or other hardware logic or circuit and fetched and / or processed using a processor’s fetch, decode, scheduling, execution, retirement and / or other logical circuits.

[0082] In at least one embodiment, activation storage 120 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, activation storage 120 may be completely or partially within or external to one or more processors or other logical circuits. In at least one embodiment, a choice of whether activation storage 120 is internal or external to a processor, for example, or comprising DRAM, SRAM, flash memory or some other storage type may depend on available storage on-chip versus off-chip, latency requirements of training and / or inferencing functions being performed, batch size of data used in inferencing and / or training of a neural network, or some combination of these factors.

[0083] In at least one embodiment, inference and / or training logic 115 illustrated in FIG. 1A may be used in conjunction with an application-specific integrated circuit (“ASIC”), such as a TensorFlow® Processing Unit from Google, an inference processing unit (IPU) from Graphcore™, or a Nervana® (e.g., “Lake Crest”) processor from Intel Corp. In at least one embodiment, inference and / or training logic 115 illustrated in FIG. 1A may be used in conjunction with central processing unit (“CPU”) hardware, graphics processing unit (“GPU”) hardware or other hardware, such as field programmable gate arrays (“FPGAs”).

[0084] FIG. IB illustrates inference and / or training logic 115, according to at least one embodiment. In at least one embodiment, inference and / or training logic 115 may include, without limitation, hardware logic in which computational resources are dedicated or otherwise exclusively used in conjunction with weight values or other information corresponding to one or more layers of neurons within a neural network. In at least one embodiment, inference and / or training logic 115 illustrated in FIG. IB may be used in conjunction with an application-specific integrated circuit (ASIC), such as TensorFlow® Processing Unit from Google, an inference processing unit (IPU) from Graphcore™, or a Nervana® (e.g., “Lake Crest”) processor from Intel Corp. In at least one embodiment, inference and / or training logic 115 illustrated in FIG. IB may be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware or other hardware, such as field programmable gate arrays (FPGAs). In at least one embodiment, inference and / or training logic 115 includes, without limitation, code and / or data storage 101 and code and / or data storage 105, which may be used to store code (e.g., graph code), weight values and / or other information, including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. In at least one embodiment illustrated in FIG. IB, each of code and / or data storage 101 and code and / or data storage 105 is associated with a dedicated computational resource, such as computational hardware 102 and computational hardware 106, respectively. In at least one embodiment, each of computational hardware 102 and computational hardware 106 comprises one or more ALUs that perform mathematical functions, such as linear algebraic functions, only on information stored in code and / or data storage 101 and code and / or data storage 105, respectively, result of which is stored in activation storage 120. (0085) In at least one embodiment, each of code and / or data storage 101 and 105 and corresponding computational hardware 102 and 106, respectively, correspond to different layers of a neural network, such that resulting activation from one storage / computational pair 101 / 102 of code and / or data storage 101 and computational hardware 102 is provided as an input to a next storage / computational pair 105 / 106 of code and / or data storage 105 and computational hardware 106, in order to mirror a conceptual organization of a neural network. In at least one embodiment, each of storage / computational pairs 101 / 102 and 105 / 106 may correspond to more than one neural network layer. In at least one embodiment, additional storage / computation pairs (not shown) subsequent to or in parallel with storage / computation pairs 101 / 102 and 105 / 106 may be included in inference and / or training logic 115. NEURAL NETWORK TRAINING AND DEPLOYMENT

[0086] FIG. 2 illustrates training and deployment of a deep neural network, according to at least one embodiment. In at least one embodiment, untrained neural network 206 is trained using a training dataset 202. In at least one embodiment, training dataset 202 is generated using techniques set forth hereinbelow. In one embodiment, training dataset 202 is generated using a generative adversarial network (GAN) that generates synthetic images and an associated trained neural network that generates labels for synthetic images generated by a GAN. In at least one embodiment, training framework 204 is a PyTorch framework, whereas in other embodiments, training framework 204 is a TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit CNTK. MXNet, Chainer, Keras, Deeplearning4j, or other training framework. In at least one embodiment, training framework 204 trains an untrained neural network 206 and enables it to be trained using processing resources described herein to generate a trained neural network 208. In at least one embodiment, weights may be chosen randomly or by pre-training using a deep belief network. In at least one embodiment, training may be performed in either a supervised, partially supervised, or unsupervised manner.

[0087] In at least one embodiment, untrained neural network 206 is trained using supervised learning, wherein training dataset 202 includes an input paired with a desired output for an input, or where training dataset 202 includes input having a known output and an output of neural network 206 is manually graded. In at least one embodiment, untrained neural network 206 is trained in a supervised manner and processes inputs from training dataset 202 and compares resulting outputs against a set of expected or desired outputs. In at least one embodiment, errors are then propagated back through untrained neural network 206. In at least one embodiment, training framework 204 adjusts weights that control untrained neural network 206. In at least one embodiment, training framework 204 includes tools to monitor how well untrained neural network 206 is converging towards a model, such as trained neural network 208, suitable to generating correct answers, such as in result 214, based on input data such as a new dataset 212. In at least one embodiment, training framework 204 trains untrained neural network 206 repeatedly while adjusting weights to refine an output of untrained neural network 206 using a loss function and adjustment algorithm, such as stochastic gradient descent. In at least one embodiment, training framework 204 trains untrained neural network 206 until untrained neural network 206 achieves a desired accuracy. In at least one embodiment, trained neural network 208 can then be deployed to implement any number of machine learning operations.

[0088] In at least one embodiment, untrained neural network 206 is trained using unsupervised learning, wherein untrained neural network 206 attempts to train itself using unlabeled data. In at least one embodiment, unsupervised learning training dataset 202 will include input data without any associated output data or “ground truth” data. In at least one embodiment, untrained neural network 206 can learn groupings within training dataset 202 and can determine how individual inputs are related to untrained dataset 202. In at least one embodiment, unsupervised training can be used to generate a self-organizing map in trained neural network 208 capable of performing operations useful in reducing dimensionality of new dataset 212. In at least one embodiment, unsupervised training can also be used to perform anomaly detection, which allows identification of data points in new dataset 212 that deviate from normal patterns of new dataset 212.

[0089] In at least one embodiment, semi-supervised learning may be used, which is a technique in which in training dataset 202 includes a mix of labeled and unlabeled data. In at least one embodiment, training framework 204 may be used to perform incremental learning, such as through transferred learning techniques. In at least one embodiment, incremental learning enables trained neural network 208 to adapt to new dataset 212 without forgetting knowledge instilled within trained neural network 208 during initial training. ACCESSING MULTIDIMENSIONAL TENSORS FOR DEEP LEARNING APPLICATIONS

[0090] Large multi-dimensional tensors are typically loaded in a global memory (e.g.. DRAM memory, or any memory external to a processing unit) for computations but due to a size of tensors, only a small portion of tensors are loaded in a shared / cached memory (e g., local cache or any memory local to a processing unit) for a processing unit to process. Accordingly, a tensor is generally accessed in smaller parts for a processing unit to perform operations on a tensor.

[0091] Currently, there are two techniques to load tensors to local cache, often known as a tiled technique and an image-to-column (or im2col) technique. A tiled technique divides a tensor into one or more tiles of a pre-specified dimension that can fit into a shared / cache memory. Each tile can be loaded, one at a time, from global memory into shared / cache memory for a processing unit to perform a computation to a tile. Tiled technique does not require data replication when used with general matrix multiply (GEMM)-based algorithms. Depending on a size of a tensor, tiled technique can cause significant tile-quantization, which is an effect where dimensions of a tensor do not cleanly divide into tiles of a pre-specified dimension, resulting in a shared / cache memory being only partially filled for such tiles and causing performance degradation. Tile quantization is further illustrated in Figure 4. It also causes less efficient utilization of a math unit since there is not enough input data to process.

[0092] Im2col (sometimes called im2row) technique is often used for convolution operations with general matrix multiply (GEMM)-based algorithms. In these algorithms, convolution operations are implemented on top of GEMM functions. (0093 ] For im2col (or im2row), blocks of a tensor are flattened into one or more columns (or rows), and data from one or more columns (or rows) is loaded into shared / cache memory. Data in shared / cache memory is operated on. Then, for a next compute cycle, new data from one or more columns is loaded into shared / cache memory to be operated on. This is repeated until an entire tensor has been processed. For im2col technique, data is not divided into tiles, so there is no tile quantization. In im2col mode scope of data loading is not limited by tile boundaries. Furthermore, single load can cross multiple image boundaries. Im2col technique, however, adds extra complexity to tensor traversal algorithm and Im2col technique usually requires a much higher memory bandwidth as compared to tiled technique. There is a lot of data loading replication for im2col since for each location within convolution filter a whole set of data is loaded from scratch. As a result, same data could be loaded multiple times. For comparison, in tiled mode each data are loaded just once and could be reused multiple times for different locations within a convolution filter. Im2col technique is further illustrated in Figure 5. ACCESSING TENSORS FOR CONVOLUTION LAYERS

[0094] A tensor can be accessed by a processing unit to perform some operations on tensor. One such operation is a convolution operation in deep learning applications. However, embodiments are not limited to convolution operations. A convolution operation is used in a layer of a convolutional neural network (CNN) to analyze images for machine learning applications, such as image classification, object detection, image segmentation, etc. A convolution operation can be performed for a convolutional layer of a CNN during inference and / or training. For example, a convolutional layer can apply a convolution function of a weight filter to a window of elements (a receptive field location) in an input tensor, where a receptive field corresponds to a location of an input tensor to detect a presence of features at a location. Strides of applications of a filter to different locations in an input tensor generate a map of activations (or a feature map), where a feature map indicates locations strength of a detected feature in an input tensor.

[0095] In at least one embodiment, an arithmetic framework for a convolutional operation can be: n,m,h,w ■ , ^niuv> if u = h + / — - >0 A v = w + k — - >0 where, val = j n’l’u’v' J J LzJ L2I I 0, otherwise. Such that, 0<n<NA0<m<MA0<h<H*0<w<W.

[0096] Here, tensor (I) is input to a program as a 4D tensor of size NxCxH*W, which is a sequence of N images each of height H, and width W, with channel C. Filter tensor (F) is of size MxCxRxS, which is a sequence of M filters each of height R, width S, and channel C. Output tensor (0) is a NxMxHxW tensor, where each element is a weighted average of neighboring elements in input image.

[0097] In at least one embodiment, tensor, I, can be transformed to a 2D matrix, I’, of size (NxHxW) x (CxR S) with some elements replicated (e.g., im2col technique) as follows: ^n,c,u,v> if n 0 v >0 0, otherwise.

[0098] In at least one embodiment, 2D matrix, I’, can be loaded to a cache / shared memory for convolution operations, using GEMM functions. For an im2col technique, in at least one embodiment, processing logic unrolls (or flattens), via an image-to-column (or image-to-row) transformations, blocks (or patches) of tensor I, and loads unrolled blocks into shared memory / cache. In at least one embodiment, unrolling a block includes identifying blocks. For a block, processing logic can unroll said block of elements into a column (or row). Processing logic then generates a 2D matrix (tensor) comprising a plurality of columns (or rows) and loads said 2D matrix into shared memory / cache.

[0099] In at least one embodiment, a method and a system combines both tiled and im2col access techniques to access a tensor in a manner that maximizes benefits of each technique and minimizes their respective negative impacts. In at least one embodiment, system splits a tensor (e.g., pixel data for an image of an input layer or feature map of an inner layer of a CNN) into a first one or more portions (tile portions) and a second one or more portions (im2col portions). In at least one embodiment, system loads first and second one or more portions into a shared memory / cache for processing. In at least one embodiment, a user can input a selection for tiled access technique, im2col access technique, or combined (tiled and im2col) access technique to access a tensor. Advantageously, a combined approach that provides a hybrid of tiled and im2col access techniques reduces or eliminates tile quantization associated with tiled technique, while also minimizing high memory bandwidth utilization associated with im2col technique. Combined approach is further illustrated as detailed below.

[0100] FIG. 3 A is a flow diagram of a process to access an input tensor using a combined technique in accordance with at least one embodiment. Method 300 can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In at least one embodiment, method 300 is performed by inference and / or training logic 115 of FIGS. 1-2. In at least one embodiment, a user input selection triggers processing logic to use a combined access techniques for method 300. Although shown in a particular sequence or order, unless otherwise specified, order of processes can be modified. Thus, illustrated embodiments should be understood only as examples, and illustrated processes can be performed in a different order, and some processes can be performed in parallel. Additionally, one or more processes can be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible. [0101 ] At operation 302, processing logic receives a user selection for a tensor access technique from a first technique, a second technique, or a third technique, wherein third technique is a hybrid of first and second techniques. In at least one embodiment, user selection of a tensor access technique is performed at a time of deploying a trained machine learning model or at a time of setting up hyperparameters for machine learning model. For example, tensor access techniques can be programmed in a library loaded into an instruction cache (such as cache 1802 of Fig. 18A). A user can implement a software module that utilizes these tensor access techniques for machine learning inference or training. In at least one embodiment, a user implements a software module to access third technique, which is a hybrid of first and second techniques.

[0102] At operation 304, processing logic sets tensor access technique to third technique based on a user selection. When a system loads a tensor from memory for machine learning applications, said system can utilize a user selected third tensor access technique. In at least one embodiment, no user input is required and by default, a third technique is selected for a system to load a tensor from memory.

[0103] At operation 310, processing logic determines a first one or more portions (one or more tiles) of at least one tensor and a second one or more portions (one or more im2col portions) of said at least one tensor. A tensor can be an input layer representing an input image or a feature map at a convolutional layer of a convolutional neural network (CNN). In at least one embodiment, a tensor can be an input image or a sequence of images (e.g., a continuous list of images) for inferencing or training a CNN.

[0104] In at least one embodiment, with reference to Fig. 3A and Fig. 7A, processing logic determines a first one or more portions of a tensor by determining a size of a tile and dividing input tensor into one or more tiles. In at least one embodiment, tile size can be of a predetermined dimension, such as 128 * 128 x 3 (width of image x height of image x channel of image) for a two dimensional (2D) tile corresponding to a 2-D image with 3 channels. Although a tensor in WHC format is shown, tensors can be in other formats or orderings, such as NDHWC, NHWC, NCHW, CNHW, etc.

[0105] In at least one embodiment, tile size can be predetermined using a capacity of a shared memory (cache), such as tile size <= shared memory (shared memory 1820 of Fig. 18A, shared memory 2070 of Fig 20D, shared memory 3012 in Fig 30, or shared memory 3518 of Fig. 35). In at least one embodiment, tile size can be selected based on an access bandwidth for a bus between a processing unit and shared memory / cache, such that a processing unit can fetch a tile with a least possible latency. In at least one embodiment, a tile size is selected based on a number of available processing threads to perform a computation. Eg., each available processing thread can compute an output element for an output tensor. In at least one embodiment, a tile size is selected from a combination of shared memory capacity, bandwidth, and / or number of available processing threads.

[0106] With reference to Fig. 3A and Fig. 7A, using a tile size of 128 * 128 x 3 (HWC), dimensions of an input tensor can be used to determine how many tiles are divisible into an input tensor. For example, if an input tensor has a dimension of 256 pixels x 280 pixels x 3 (height x width x channel), processing logic can divide a dimension of an input tensor into a dimension of a tile to determine a number of tiles in an input tensor. For example, 256 divided by 128 = 2 tiles in a height dimension, 280 divided by 128 = 2 tiles in a width dimension, and 3 divided by 3 = 1 in a channel dimension. Therefore, there are 2x2 = 4 full tiles in provided example input tensor (tiles A-B, tiles D-E in Fig. 7A). A determined tile size may not divide evenly into a tensor. For a tiled tensor access method, this would result in tile quantization, as shown in FIG. 4. However, in at least one embodiment tile quantization is avoided by using a tiled method only for full tiles (e.g., tiles full of useful data).

[0107] In at least one embodiment, processing logic determines a second one or more portions (im2col portions) using a remainder operation. In at least one embodiment, with reference to Fig. 3A and Fig. 7A, im2col portions in an input tensor are remainder elements that did not evenly divide into a tile. E.g., (256 x (280 rem 128 = 24) x 3) (HWC) of elements to a right of tiles. To a bottom of tiles, there are ((256 rem 128 = 0) x 280 x 3) (HWC), or no elements remaining. Therefore, there are 256 x 24 x 3 remainder elements (im2col portions) to a right of tiles (im2col portion 703 in Fig. 7A). While a second portion (im2col portion) is only to a right of tiled portion in illustrated example, second portion may additionally or alternatively be above, below and / or to a left of first portion.

[0108] At operation 320, processing logic accesses, from (global) memory, determined first one or more portions using a first technique to obtain a first output. In at least one embodiment, a first technique is a tiled tensor access technique.

[0109] For example, processing logic loads a tile from 4 tiles shown in FIG. 7A, one at a time, from global memory into shared memory / cache. Processing logic can further load boundary elements or paddings for a tile. Processing logic can then process a tile by accessing elements in said tile from cache. For example, for machine learning applications, such as machine vision tasks of an autonomous vehicle, medical imaging, robotics, etc., processing logic can apply a convolution operation to a tile using a convolution filter by strides specified by a machine learning model. At each stride, processing logic accesses a patch of elements (e.g., size of a convolution window) in a tile from shared memory / cache and applies a convolution function between patch and convolution filter to generate an output element. Convolution function can be applied repeatedly for different strides (an amount of movement across a tile between each application of a convolution function) across different patches in a tile, by strides, to generate an output tile. In at least one embodiment, output tile = filter*input tile. In at least one embodiment, processing logic includes a plurality of processing threads for computation, where each thread calculates an output element in an output tile. This way, elements in an output tile can be calculated concurrently.

[0110] At operation 330, processing logic accesses, from (global) memory, a second one or more portions (im2col portions) using a second technique to obtain a second output. In at least one embodiment, second technique is an im2col tensor access technique. [0111 ] In at least one embodiment, processing logic unrolls (or flattens), via an image-to-column transformation, second portion(s) and loads unrolled second portion(s) into shared memory / cache as a tensor. In at least one embodiment, unrolling second portion(s) includes determining a plurality of patches (a convolutional filter window of elements) in second portion(s) for a plurality of strides. For a patch in second portions, processing logic can unroll said patch of elements into a column. Processing logic then generates a plurality of columns (matrix of columns) for a plurality of patches and loads said plurality of columns into shared memory / cache as tensor. In at least one embodiment, each processing thread further performs a convolution function, which may use GEMM functions, between a convolution filter and tensor to generate an output tensor (second output). In at least one embodiment, processing logic includes a plurality of processing threads for processing, where each thread calculates an output element in output tensor. This way, elements in output tensor can be calculated concurrently.

[0112] At operation 340, processing logic generates an output tensor by combining one or more first outputs (output tiles) and one or more second outputs (im2col outputs).

[0113] In at least one embodiment, processing logic can merge together an output from a tiled technique (first output) and an output from an im2col technique (second output) to generate a final output tensor. Here, first and second outputs are intermediary outputs. In at least one embodiment, processing logic merges intermediary (first and second) outputs as they are generated. Merging can include in-place placements, where intermediary outputs are placed within an output tensor corresponding to a position where elements used to generate intermediary outputs are found in an input tensor. For example, an output of tile A is placed in an output tensor at a position of tile A in an input tensor.

[0114] In at least one embodiment, first and second outputs can have a predetermined mapping to an output tensor, such as via an index. In at least one embodiment, each output tiles and / or im2col outputs are assigned an index value (0, 1, 2, 3, etc.) and are mapped to an output tensor in an order specified by index value. In at least one embodiment, an output tensor has intermediate outputs arranged according to some index values (0, 1, 2, etc.) for intermediate outputs, as shown in Fig. 7B.

[0115] In at least one embodiment, tiles are processed first, followed by im2col portions to a right side of tiles (im2col portion 723, 727 of Fig. 7B) (vertical index 0, index 1), followed by im2col portions to a bottom side of tiles (im2col portions 725, 729 of Fig. 7B) (horizontal index 0, index 1).

[0116] In at least one embodiment, a convolution function (via GEMM) with a hybrid tiled and im2col access approach is performed by an autonomous vehicle (such as vehicle 1000 of Fig 10A) and / or a deployment system (such as 3606 of Fig. 37) for inference purposes. Inference can be performed by these systems, in real-time, using a machine learning model, such as a deep learning CNN model, or other machine learning models for image classification, object detection, image segmentation, etc. In at least one embodiment, a convolution function (via GEMM) with a hybrid access approach can be performed by a server (such as server 1078 of Fig. 10D, training system 3604 of Fig. 37) to train a neural network model, such as a deep learning CNN model, or other machine learning models.

[0117] For autonomous vehicle 1000 in Fig. 10, a hybrid tiled and im2col access technique and corresponding machine learning models can be loaded in data store(s) 1028. In at least one embodiment, images streamed by a camera of vehicle 1000 (such as camera(s) 1068-1076, cameras 1098) can be loaded onto data store(s) 1028 for GPUs 1020 or CPUs 1018 to access these images. In at least one embodiment, images streamed by a camera of vehicle 1000 (such as camera(s) 1068-1076, cameras 1098) can be loaded onto data store(s) 1016 for GPUs 1008 or CPUs 1006 or accelerator(s) 1014 to access these images.

[0118] For example, vehicle 1000 can pre-process images and store an image as an input tensor. Vehicle 1000 can apply a CNN model to an input tensor, via hardware structure 115 by a hybrid tiled / im2col technique. In at least one embodiment, an input tensor is divided into a first one or more portions (one or more tiles of predetermined dimensions) and a second one or more portions (im2col portions). One or more tiles are loaded into a cache / shared memory for CPU / GPU / accelerator to process, one tile at a time. Each tile can be convolved with a filter of weight values in a layer of a CNN model to generate an output tile. In at least one embodiment, each element in an output tile can by processed by a separate processing threads for parallel processing. Next, im2col portions are loaded into a cache / shared memory for CPU / GPU / accelerator to process. Im2col portions are unrolled into one or more columns according to dimensions of a convolution filter of CNN model and unrolled columns are loaded into a cache / shared memory for CPU / GPU / accelerator to process. Outputs can be combined into an output tensor (representing feature maps) for a next layer of a CNN model for processing.

[0119] In a next layer, output tensor (feature maps) of a previous layer are fed through a filter of weights for a layer to generate an output (feature maps). A hybrid tiled / im2col tensor access technique can be used to access feature maps for convolution operations for each layers of a neural network.

[0120] FIG. 3B is a flow diagram of a process to access an input tensor using a hybrid tensor access technique, according to at least one embodiment. Method 350 can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In at least one embodiment, method 350 is performed by inference and / or training logic 115 of FIGS. 1-2. In at least one embodiment, a user input selection triggers processing logic to use a combined access techniques for method 350. Although shown in a particular sequence or order, unless otherwise specified, order of processes can be modified. Thus, illustrated embodiments should be understood only as examples, and illustrated processes can be performed in a different order, and some processes can be performed in parallel. Additionally, one or more processes can be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

[0121] At operation 352, processing logic identifies one or more tiles in a tensor. For example, with reference to Fig. 4, tensor 401 with (HWC = 280 x 280 x 3) elements can be divided into one or more (128 x 128 x 3) tiles (A-I) using a division operation.

[0122] At operation 354, processing logic determines which tiles are fully occupied with useful elements, via a division operation. For example, tiles A, B, D, and E are fully occupied with useful elements. An input tensor has height 280 div 128 equals 2, and width has 280 div 128 equals 2. Thus (2 x 2) tiles (or tiles A, B, D, and E) are fully occupied with useful elements.

[0123] At operation 356, processing logic determines a first portion (tiled portion) of said tensor corresponding to tiles that are fully occupied with useful elements. E.g., a first portion corresponds to (2 x 2) tiles (or tiles A, B, D, and E).

[0124] At operation 360, processing logic determines a second portion (im2col portion) of said tensor containing remainder elements that are not in first portion. Second portion is a remainder of elements that is not fully occupied. Remainder elements can be calculated from a remainder operation. For example, for tiles C, F, and I, there are (HWC = 280 x (280 rem 128 = 24) x 3) elements. For tiles G and H, there are (HWC = (280 rem 128 = 24) x 256 x 3) elements. These occupied elements in tiles C, F, G, H, and I, thus, can correspond to a second portion.

[0125] At operation 370, processing logic processes said first portion using a first technique. For example, tiles A, B, D, and E are loaded from global memory to a shared memory using a tiled technique, where tiles are loaded into a shared memory, one tile at a tile, and loaded tiles are processed to derive a first output. Tiled technique is further illustrated below.

[0126] At operation 380, processing logic processes said second portion using a second technique. For example, occupied elements in tiles C, F, G, H, and I are loaded from global memory to a shared memory using an im2col technique, where a second portion of elements are processed to derive a second output. Im2col technique is further illustrated below.

[0127] At operation 390, processing logic combines outputs from processing of said first and second portions. For example, one or more first outputs are combined with one or more second outputs in-place, e.g., according to locations of input tiles / elements used to generate first and second outputs. In at least one embodiment, tiles in first portion and elements in second portion can be assigned an index value, where first and second outputs are merged according to corresponding index values.

[0128] FIG. 4 is a block diagram of an input tensor illustrating tile quantization, according to at least one embodiment. Example 400 shows input tensor 401 with dimensions (HWC = 280 x 280 x 3) being loaded as a plurality of tiles 403 (tiles A-I), where a tile has a predetermined dimension (HWC = 128 x 128 x 3).

[0129] A tile can be loaded in memory in a row major or a column major order. When a tile is loaded in shared memory / cache in row major order, a tile has rows of elements in a sequentially addressable memory space, e.g., row 1, row 2, row 3 and so forth. As shown in Fig. 4, tiles A-B and D-E have useful elements in memory in a continuous manner. Tiles C, F, G, H, and I, when loaded in shared memory / cache, have unused elements. Thus, accessing tiles C, F-H, and I can lead to inefficient memory utilization and / or inefficient arithmetic computations. This effect is termed tile quantization, which occurs when tensor dimensions are not divisible by a tile size.

[0130] When a processing unit accesses a tile for computation, each of tiles A-I leads to performance of a same amount of computation. Thus, due to tile quantization, a processing unit performs a full computational load for tiles C, F, G, H and I, when actually less than 10% of computation load is required, leading to computation inefficiencies. Note that tensor 401 can be accessed as tiles by a processing unit for various computations, including convolution, multiplication, addition, etc. [0131 ] For tiled tensor access technique (mode), a number of elements of a tensor to load depends on parameters of a tile, such as height and width of a tile (e.g., boxSize[] parameters). A value within brackets may represents a dimension. For example, boxsize [1] may represent a box size for a second dimension, and boxsize[0] may represent a box size for a first dimension. Processing logic can specify a bounding box in tensor space that can hold all elements that processing logic would load from global memory to cache / shared memory. In tiled mode a number of elements to load depends on boxSize[] parameters. In at least one embodiment, when processing logic traverses a specific dimension it uses corresponding value from boxSize [] to determine how many elements to load. In at least one embodiment, in tiled mode, instruction coordinates specify boundingBox location (origin) in tensor space.

[0132] Fig. 5 illustrates a relationship of a bounding box to parameters: boxBaseCorner{D,H,W} and boxFarCorner {D,H,W}, according to at least one embodiment. For example, parameter boxBaseCorner can be an upper left corner coordinate and parameter boxFarCorner can be a bottom right corner coordinate, at an opposite corner to upper left corner coordinate. In at least one embodiment, boxBaseCorner coordinates are represented as offsets from an upper left corner of a tensor and boxFarCorner coordinates are represented as offsets from a bottom right corner of a tensor.

[0133] In at least one embodiment, bounding box can be specified with respect to a size of a tensor. For example, boxBaseCornerDHW and boxFarComerDHW can be used to specify a bounding box using following formulas: boundingBox{D,H, W} = tensorSize{D,H, W} -boxBaseCorner {D,H,W} + boxFarCorner{D,H,W}).

[0134] Fig. 5 illustrates several examples of bounding boxes. For tensor 501, processing logic specifies boxBaseCornerH = -1, boxBaseComerW = -1, boxFarCornerH = -1, and boxFarCornerW = -1. In this example, boxBaseCornerH = -1 and boxBaseComerW = -1 indicates that an upper left side of a bounding box is offset 1 pixel to a left of a left edge of tensor and offset 1 pixel above a top of tensor. Similarly, in this example boxFarCornerH = -1 and boxFarCornerW = -1 indicates that a lower right side of a bounding box is offset 1 pixel to a left of a right side of tensor and offset 1 pixel above a bottom of tensor. For tensorSizeH = 14 and tensorSizeW = 9, boundingBoxH = 14^(-1)-(-1) = 14 and boundingBoxW= 9^(-1) + (-1) = 8. Thus, HW = (14 x 9) elements would be loaded for tensor 501.

[0135] For tensor 503, processing logic specifies boxBaseCornerH = -1, boxBaseComerW = -2, boxFarCornerH = 0, and boxFarCornerW = 1. In this example, boxBaseCornerH = -1 and boxBaseComerW = -2 indicates that an upper left side of a bounding box is offset 2 pixels to a left of a left edge of tensor and offset 1 pixel above a top of tensor. Similarly, in this example boxFarCornerH = 0 and boxFarCornerW = 1 indicates that a lower right side of a bounding box is offset 1 pixel to a right of a right side of tensor and is not vertically offset from a bottom of tensor. For tensorSizeH = 14 and tensorSizeW = 9, boundingBoxH = 14 — (-1) + (0)=15 and boundingBoxW = 9 - (-2) + (1) = 12. Thus, HW = (15 x 12) elements would be loaded for tensor 503.

[0136] For tensor 505, processing logic specifies boxBaseComerH = 1, boxBaseComerW = 1, boxFarCornerH = -2, and boxFarCornerW = -1. In this example, boxBaseComerH = 1 and boxBaseComerW = I indicates that an upper left side of a bounding box is offset 1 pixel to a right of a left edge of tensor and offset 1 pixel below a top of tensor. Similarly, in this example boxFarCornerH = -2 and boxFarCornerW = -1 indicates that a lower right side of a bounding box is offset 1 pixel to a left of a right side of tensor and is vertically offset 2 pixels up from a bottom of tensor. For tensorSizeH = 14 and tensorSizeW = 9, boundingBoxH = 14 - (1) + (-2) = 11 and boundingBoxW = 9-(1)- (-1) = 7. Thus, HW = (11 x 7) elements would be loaded for tensor 505.

[0137] For tensor 507, processing logic specifies boxBaseComerH = 0, boxBaseComerW = 0, boxFarCornerH = 0, and boxFarCornerW = 0. In this example, boxBaseComerH = 0 and boxBaseComerW = 0 indicates that an upper left side of a bounding box at a left top edge of tensor. Similarly, in this example boxFarCornerH = 0 and boxFarCornerW = 0 indicates that a lower right side of a bounding box is at a bottom right edge of tensor. For tensorSizeH = 14 and tensorSizeW = 9, boundingBoxH = 14 - (0) + (0) = 14 and boundingBoxW = 9-(0) + (0) = 9. Thus, HW = (14 x 9) elements would be loaded for tensor 507.

[0138] For tensor 509, processing logic specifies boxBaseComerH = -2, boxBaseComerW = -2, boxFarCornerH = -1, and boxFarCornerW = 0. In this example, boxBaseComerH = -2 and boxBaseComerW = -2 indicates that an upper left side of a bounding box is offset 2 pixels to a left of a left edge of tensor and offset 2 pixels above a top of tensor. Similarly, in this example boxFarCornerH = -1 and boxFarCornerW = 0 indicates that a lower right side of a bounding box at a right edge of tensor and is vertically offset 1 pixel up from a bottom of tensor. For tensorSizeH = 14 and tensorSizeW = 9, boundingBoxH = 14 - (-2) + (-1) = 15 and boundingBoxW = 9 - (-2) + (0) = 11. Thus, HW = (15 * 11) elements would be loaded for tensor 509.

[0139] For tensor 511, processing logic specifies boxBaseComerH = 1, boxBaseComerW = 1, boxFarComerH = 1, and boxFarCornerW = J. In this example, boxBaseComerH = 1 and boxBaseComerW = 1 indicates that an upper left side of a bounding box is offset 1 pixel to a right of a left edge of tensor and offset 1 pixel below a top of tensor. Similarly, in this example boxFarComerH = 1 and boxFarCornerW = 1 indicates that a lower right side of a bounding box is offset 1 pixel to a right of a right side of tensor and is vertically offset 1 pixel down from a bottom of tensor. For tensorSizeH = 14 and tensorSizeW = 9, boundingBoxH = 14 - (1) + (1) = 14 and boundingBoxW = 9-(1) + (1) = 9. Thus, HW = (14 x 9) elements would be loaded for tensor 511.

[0140] Bounding boxes in these examples hold all elements that processing logic could load from global memory to cache / shared memory. [0141 ] In im2col tensor access technique (mode), boundingBox size and location are defined differently than in tiled tensor access technique. In at least one embodiment, a number of boundingBox dimensions is one less than a tensor dimensionality. Parameters used for im2col include, but are not limited to, rangeNDHW, rangeC, boxBaseCornerDHW. boxFarCornerDHW. A boxBaseCornerDHWand boxFarCornerDHW define boundingBox size and location in DHW space. A boxBaseCornerDHW specifies initial coordinates of boundingBox origin which is box upper left comer. A boxFarCornerDHW specifies initial location of an opposite right bottom comer. Comer locations are defined as signed offsets from corresponding tensor comers. Therefore, bounding box comers could be specified both inside and outside of tensor boundaries. Location of bounding box comers is affected by convolution filer size and dilation factor. In at least one embodiment, comer coordinates are calculated as half of a filter size multiplied by a dilation factor. Precision for bounding box comers is chosen to provide wide range of a convolution kernel sizes and dilation factors. Based on a real application analysis higher precision may be needed for tensors with smaller dimensionality. For example, a speech processing application which uses 3D tensors may require dilation factor of up to 8K, while image processing applications that use 4D or 5D tensors need much smaller dilation factors of up to 128. In at least one embodiment, a boxBaseCornerDHW and boxFarCornerDHW define boundingBox sizes using following formulas: boundingBox!DH. W} = tensorSize{D,H, W} - boxBaseCorner{D,H, W} + boxFarCorner{D,H, W}). As far as C dimension a size can be defined by rangeC parameter. In at least one embodiment rangeC indicates how many channels to load for every pixel. In at least one embodiment, when data for a pixel is loaded, a value of rangeC indicates a number of channels for pixel to load in a single instruction. If a tensor includes more channels than a value of rangeC, then remaining channels for pixel may be skipped.

[0142] In im2col mode rangeNDHW can be used to determine how many elements to load along NDHW dimensions and rangeC for dimension C. In at least one embodiment, rangeNDHW indicates how many elements are to be loaded along dimensions of N, D, H and W. For a four dimensional tensor, D may be omitted. For a five dimensional tensor, D may be included. In at 1 east one embodiment, each pixel shown in FIGS. 5-6D also has dimension C (channels) that is not shown. In at least one embodiment, channels is equal to 64. Other numbers of channels may also be used.

[0143] A single request may traverse multiple images from a batch (N dimension) in order to load requested number of elements. When processing logic switches from a current image to a next image, processing logic may skip channels that are outside a range defined by rangeC parameter. In at least one embodiment, in im2col mode coordinates along C and N dimensions are used similar to tiled mode; however, coordinates along W, H, D dimensions specify location of a convolution filter base (upper left corner) in tensor space. For correct processing, a filter corner location is defined within a boundingBox. In addition, coordinate offsets for these dimensions are specified in instructions. In at least one embodiment, offsets are added to filter base coordinates to determine starting locations in tensor space from where a load operation is initiated. In at least one embodiment, same offsets are used to position boundingBox relative to initial coordinates specified in boxBaseComerDHW. Offsets can be applied to a subset of coordinates. Examples illustrating use of im2col mode are shown in Figs. 6A-6D.

[0144] Fig. 6A illustrates processing for requests in im2col mode with padding for coordinate (7,7,4,0) and different offset coordinate values: (0, 0), (1,1), (2,2), according to at least one embodiment.

[0145] In at least one embodiment, a filter 622 such as a 3x3 convolution filter is applied to a tensor with NHWC format = (64x14x9x64). Tensor has one element padding that could be defined as zeros or a constant value, where C is a number of channels per pixel, W is image width, H is image height, and N is batch size (number of images in a batch).

[0146] In at least one embodiment, processing logic has a shared memory that can load up to 64 elements along N, H, W dimensions, and 8 elements along C for each iteration.

[0147] In at least one embedment, a parameter rangeNDHW can be used to determine how many elements to load along NDHW dimensions and a parameter rangeC can be used to determine how many elements to load along C dimension.

[0148] Processing logic can traverse multiple images from a batch of images (N dimension) in order to load elements. In at least one embodiment, when processing logic switches from a current image to a next image, processing logic can skip some channels that are outside a range defined by parameter rangeC.

[0149] In at least one embodiment, filter corner locations are defined within boundingBox. In addition, coordinate offsets for these dimensions can be specified in an instruction. Offsets are added to a filter base coordinates to determine starting locations in tensor space from where a load operation is initiated. Same offsets are used to position boundingBox relative to initial coordinates specified in boxBaseCornerDHW.

[0150] In Fig. 6A, parameters are set up as follows: tensorSize[0]=64; tensorSize / 1 / 9; tensorSize[2]=14; tensorSize[3]=64; rangeNDHW = 64; rangeC = 8; boxBaseCornerW = -1; boxBaseCornerH = -1; boxFarComerW = -1; and boxFarComerH = -1.

[0151] In at least one embodiment, tensorSize[x] specifies a size of a tensor along dimension x. In at least one embodiment, dimension 0 corresponds to C, dimension 1 corresponds to W, dimension 2 corresponds H, and dimension 3 corresponds to N (batch size). Based on above parameters, an example tensor has 64 channels, a width of 9 pixels, a height of 14 pixels, and a batch size of 64. In at least one embodiment, rangeNDHW = 64 indicates that 64 elements are to be loaded along dimensions of N, H and W (for a four dimensional tensor) or along dimensions of N, H, D, and W (for a five dimensional tensor). In at least one embodiment rangeC = 8 indicates that 8 channels are to be loaded for every pixel. Since tensor in example includes 64 channels, 56 channels would be skipped for each pixel.

[0152] Referring to tensor 621, a filter 622 such as a convolutional filter, a dynamic filter, or other type of filter can be applied to tensor 621 to perform an operation. In at least one embodiment, filter 622 can step outside of tensor boundary and access surrounding padding that could be defined as zeros or constant values. Filter 622 can have a filter size (also referred to as a footprint). In at least one embodiment, a filter size for filter 622 is 3x3. Other filter sizes are also possible, examples of which are 3x1, 1x3, 2x3, 3x2, 4x4, 4x6, 6x4, and so on. A filter 622 may apply an operation to all elements in a filter. A 3x3 filter can hold data for 9 pixels, and has 9 different positions. Accordingly, a single pixel may be included in 9 different iterations of application of a 3x3 filter, where for each iteration a pixel is combined with a different set of other pixels in filter. For im2col mode, data for a single pixel is reloaded for each iteration of application of a filter. Accordingly, data for a single pixel may be loaded nine different times for use in a 3x3 filter. By reducing a number of pixels that are accessed using im2col, a number of loads of pixel data can be reduced. [0153 ] In at least one embodiment, processing logic can determine a boundary box for hoxBaseCornerH = -1, boxBaseCornerW = -1, boxFarComerH = -1, and boxFarCornerW = -1. For tensorSizeH = 14 and tensorSizeW=9, boundingBoxH = 14-(-1) + (-1) = 14 and boundingBoxW = 9 - (-1) + (-1) = 9. Thus, boundingBox has HW = (14 x 9) elements.

[0154] Next, processing logic loads elements for coordinates NHWD (7,7,4,0) and offset (0,0). For example, processing logic applies offset (0,0) to bounding box. For offset=(0,0), using a boundary box, processing logic can determine elements to load for filter base coordinates NHWD (7,7,4,0) starting at element 621-1, and rangeNDHW = 64 elements from memory with rangeC = 8 channels per element can be loaded.

[0155] Next, processing logic can load elements for coordinates NHWD (7,7,4,0) and offset (1,1). For example, processing logic applies offset (1,1) to adjust bounding box. For offset=(l,l), using an adjusted boundary box, processing logic can determine elements to load for filter base coordinates NHWD (7,7,4,0) starts at element 621-3, and rangeNDHW = 64 elements from memory with rangeC = 8 channels per element can be loaded.

[0156] Next, processing logic can load elements for filter base coordinates NHWD (7,7,4,0) and offset (2,2). For example, processing logic applies offset (2,2) to adjust bounding box. For offset=(2,2), using adjusted boundary box, processing logic can determine elements to load for filter base coordinates NHWD (7,7,4,0) starting at element 621-5, and rangeNDHW = 64 elements from memory with rangeC = 8 channels per element can be loaded.

[0157] Fig. 6B illustrates processing for requests in im2col mode with no padding for filter base coordinate (7,7,4,0) and different offset coordinate values: (0, 0), (1,1), (2,2), according to at least one embodiment. Fig. 6B is similar to Fig. 6A, except no padding is applied to input tensor.

[0158] In Fig. 6B, a(3 x 3) filter must stay within tensor boundaries, thus, there is no padding / border. In one embodiment, processing logic sets up tensor access parameters as follows: rangeNDHW = 64; rangeC = 8; boxBaseCornerW = 0; boxBaseCornerH = 0; boxFarCornerW = -2; boxFarCornerH =-2.

[0159] In at least one embodiment, processing logic can determine a bounding box for boxBaseCornerH = 0, boxBaseCornerW = 0, boxFarCornerH = -2, and boxFarCornerW = -2. For tensorSizeH= 14 and tensorSizeW = 9, boundingBoxH = 14-(0) + (-2) = 12 and boundingBoxW = 9-(0) + (-2) = 7. Thus, houndingBox has HW = (12 * 7) elements.

[0160] Next, processing logic loads elements for coordinates NHWD (7,7,4,0) and offset (0,0). For example, processing logic applies offset (0,0) to bounding box. For offset=(0,0), using bounding box, processing logic can determine elements to load for filter base coordinates NHWD (7,7,4,0) starts at element 623-1, and rangeNDHW = 64 elements from memory with rangeC = 8 channels per element can be loaded. When elements being loaded reaches boxFarCorner, elements from a next image (image 8) begins loading until 64 elements are loaded.

[0161] Next, processing logic loads elements for filter base coordinates NHWD (7,7,4,0) and offset (1,1). For example, processing logic applies offset (1,1) to bounding box. For offset=(l,l), using bounding box, processing logic can determine elements to load for filter base coordinates NHWD (7,7,4,0) starting at element 623-3, and rangeNDHW = 64 elements from memory with rangeC = 8 channels per element can be loaded. When elements being loaded reaches boxFarCorner, elements from a next image (image 8) begins loading until 64 elements are loaded.

[0162] Next, processing logic loads elements for filter base coordinates NHWD (7,7,4,0) and offset (2,2). For example, processing logic applies offset (2,2) to bounding box. For offset=(2,2), using bounding box, processing logic can determine elements to load for filter base coordinates NHWD (7,7,4,0) starting at element 623-5, and rangeNDHW = 64 elements from memory with rangeC = 8 channels per element can be loaded. When elements being loaded reaches boxFarCorner, elements from a next image (image 8) begins loading until all 64 elements are loaded.

[0163] For comparison, handling of similar convolution cases in tiled mode is illustrated with reference to Figs. 6C-6D. A request may load all pixels needed for convolution computation in all filter locations in tiled mode. In order to achieve this, extra halo pixels may be loaded. In at least one embodiment, a number of halo pixels depends on filter size. Halo pixels can represent zero and / or constant padding elements.

[0164] Fig. 6C illustrates processing for requests in tiled mode with paddings, according to at least one embodiment. For im2col mode, data for each pixel in a tensor may be loaded multiple times, such as one time for each position in a filter applied to a tensor. In contrast, for tiled mode each pixel is loaded once. However, in tiled mode tile quantization can occur, which leads to other inefficiencies. In Fig. 6C, parameters R represents height and S represents width. In at least one embodiment, a (3 x 3) convolution filter is applied to tensor NHWC (64 x 14 x 8 x 64). [0165 ] In at least one embodiment, processing logic loads all pixels needed for convolution computation at all filter locations in a tile. In order to achieve this, extra halo pixels may be loaded. Here, a number of halo pixels depends on a filter size.

[0166] In at least one embodiment, processing logic can specify tensor access parameters as follows: tensorSize[0]=64; tensorSize[l]=8; tensorSize[2]=14; tensorSize[4]=64; boxSize[0] = 8; boxSize[l] = 10; boxSize[2] = 10; boxSize[3] = 1.

[0167] In at least one embodiment, tensorSize[x] specifies a size of a tensor along dimension x. In at least one embodiment, dimension 0 corresponds to C, dimension 1 corresponds to W, dimension 2 corresponds to H, and dimension 4 corresponds to N (batch size). Based on above parameters, an example tensor has 64 channels, a width of 9 pixels, a height of 14 pixels, and a batch size of 64. In at least one embodiment, boxSize[x] specifies how many channels or pixels to load in x dimension. For example, boxSize [0] = 8 indicates that 8 channels are to be loaded for each pixel, boxSizef 1 / 10 indicates that 10 pixels are to be loaded along a horizontal direction, boxSize[2] = 10 indicates that 10 pixels are to be loaded along a vertical direction, and boxSize[3] = 1 indicates that a batch size is 1. In at least one embodiment, batch sizes may be greater than one for tiled mode.

[0168] In at least one embodiment, a filter 622 can be applied to elements of tensor 625. Filter 622 can have a filter size (also referred to as a footprint). In at least one embodiment, a filter size for filter 622 is 3x3. Other filter sizes are also possible, examples of which are 3x1, 1x3, 2x3, 3x2, 4x4, 4x6, 6x4, and so on. A filter 622 may apply an operation to all elements in filter. A 3x3 filter can hold data for 9 pixels, and has 9 different positions. Accordingly, a single pixel may be included in 9 different iterations of application of a 3x3 filter, where for each iteration a pixel is combined with a different set of other pixels m filter. For tiled mode, data for each pixel in a tile is loaded a single time, and that loaded data is applied for each iteration of application of a filter, without a need to reload data for pixels.

[0169] In at least one embodiment, filter 622 can be applied to elements outside of tensor boundary. For example process logic can access surrounding padding (border) that could be defined as zeros or constant values. In at least one embodiment, processing logic loads elements specified by box size. E.g., 10 x 10 tile along H, W dimensions, and 8 elements along C. Here, processing logic loads each 10 x 10 tile with 2 halo rows and 2 halo columns.

[0170] In at least one embodiment, for any given filter location, a (8 x 8) tile is used for convolution calculations. For a request at coordinates (0, -1, -1, 0), negative W, H block coordinates can be used to access pixels outside of tensor boundary. e.g., padding. (8 x 8) tiles (625-1, 625-3, and 625-5) are shown that are used to process filter locations: (0, 0), (1, 1), (2, 2), respectively.

[0171] Fig. 6D illustrates processing for requests in tiled mode without paddings, according to at least one embodiment. Tensor 627 is similar to tensor 625 of Fig. 6C, but filter stays within tensor boundaries and there is no padding. In at least one embodiment, a (3 x 3) convolution filter is applied to tensor layout of NHWC (64 * 14 x 8 * 64).

[0172] In at least one embodiment, processing logic can load a (8 x 8) tile along H, W dimensions, and 8 elements along C. In at least one embodiment, processing logic can specify tensor access parameters as follows: tensor Size! 0]=64; tensorSizef 1]=8: tensorSize[2]=14; tensorSize[4]'=64; boxSize [0] = 8; boxSize [1] = 8; boxSize [2] = 8; boxSize [3] = 1.

[0173] In at least one embodiment, for any given filter location, a (6 x 6) tile is used for convolution calculations. For example, for a request at coordinates (0, 0, 0, 0), setting W, H block coordinates to zero can prevent processing logic accessing elements from outside of tensor boundary. Here, 6x6 tiles (627-1, 627-3, and 627-5) are shown which are used to process filter locations: (0, 0), (1, 1), (2, 2), respectively.

[0174] Fig. 7A is a block diagram of an input tensor 701 used for a hybrid tiled / im2col access technique, according to at least one embodiment. In this example, a tiled / im2col access technique is used to access input tensor 701 to perform a computation with a tile layout of HWC = (128 x 128 x 1).

[0175] In Fig. 7 A, using a tile size of 128 x 128 x 1, dimensions of tensor 701 are used to determine how many tiles are divisible by tensor 701. For example, tensor 701 has a dimension of 280 pixels x 280 pixels x 1, processing logic can use a divide operation to determine a number of full tiles. E.g., 280 divide by 128 = 2 tiles in a height dimension, 280 divide by 128 = 2 tiles in a width dimension, and 1 divide by 1 = 1 tiles in a channel dimension. Therefore, there are 2 x 2 = full 4 tiles in tensor 701 (tiles A-D).

[0176] Using a tile size of 128 x 128 x 1; dimensions of an input tensor can determine how many im2col elements remain in tensor 701 using a remainder operation. In at least one embodiment, im2col portions in an input tensor are elements that did not divide into a tile. In an example, HWC = (280 x (280 rem 128 = 24) x 1) of elements to a right of tiles. In an example, to a bottom portion, there are HWC = ((280 rem 128 = 0) x 280 x 1) of elements. Therefore, in an example there are HWC = 256 x 24 x 1 remainder elements (im2col portions) to a right of tiles (im2col portion 703) and there are HWC = 24 x 280 x 1 remainder elements (im2col portions) below tiles. [0177 ] In at least one embodiment, processing logic then accesses tensor 701 by loading tiles from 4 full tiles, one tile at a time, into shared memory, where tiles are accessed for some arithmetic operations. In at least one embodiment, loading a tile includes loading padding elements of that tile. In at least one embodiment, accessing tensor 701 further includes loading im2col portion 703 into a shared memory, where im2col portion 703 are accessed for some arithmetic operations.

[0178] In at least one embodiment, an arithmetic operation is a convolution operation, for a plurality of strides across tensor 701. In at least one embodiment, processing logic includes a plurality of processing threads, where each thread performs a convolution function corresponding to a stride. In at least one embodiment, processing logic performs convolution functions to tiles A-D, when these tiles are loaded in shared memory, followed by an im2col portion 703, when said im2col portion is loaded in shared memory. In at least one embodiment, distinct (tiled and im2col) outputs from convolution functions are combined to generate an output tensor.

[0179] Fig. 7B is a block diagram of an input tensor 721 used for a combined tiled / im2col access technique, according to at least one embodiment. In this example, input tensor 721 can represent a sequence of 64 images, where tensor 721 has dimensions NHWC = 64 * 320 x 280 x 1.

[0180] In Fig. 7B, a tile size can be selected to be 128 x 128. Using a tile size of 128 * 128, dimensions of an image 731 in tensor 721 are used to determine how many tiles are divisible by an image in tensor 721. For example, image 731 in tensor 721 has dimensions 320 x 280, processing logic can use a divide operation to determine a number of tiles. E.g., 320 divide by 128 = 2 tiles in a height dimension, 280 divide by 128 = 2 tiles in a width dimension. Therefore, there are 2x2 = 4 tiles in image 1 (731) (tiles A-D). Given a sequence of images, tile mappings can be similarly determined for subsequent images. [0181 ] Using tile size of 128 x 128, dimensions of an input tensor can determine how many im2col elements remain in tensor 721 corresponding to image 1 (731) using a remainder operation. In at least one embodiment, im2col portions in an input tensor are elements that does not divide into a tile. E.g., 320 height x (280 rem 128 = 24) width of elements to a right of tiles. For a bottom portion, there are (320 rem 128 = 64) height x 256 width of elements. Therefore, there are 320 x 24 remainder elements (im2col portion 723) to a right of tiles A-D, and 64 x 256 remainder elements (im2col portion 725) to a bottom of tiles A-D. Given a sequence of images, im2col portion mappings can be similarly determined for subsequent images.

[0182] In at least one embodiment, processing logic then accesses tensor 721 by loading tiles from tiles A-H, one tile at a time, into shared memory, where tiles are accessed for some arithmetic operations. In at least one embodiment, loading a tile includes loading padding elements for tile. Once tiles are processed, in at least one embodiment, processing logic loads vertical im2col portions 723, 727 by index, followed by horizontal im2col portion 725 by index into shared memory in such a predetermined order, where im2col portions 723-727 are accessed for some arithmetic operations. In at least one embodiment, horizontal or vertical im2col portions 723-727 are loaded in parts, where each part has a same size as an available processing thread to process im2col portions.

[0183] In at least one embodiment, processing logic accesses tensor 721 to apply a convolution operation to tensor 721 using a convolution filter, in strides. In at least one embodiment, processing logic includes a plurality of processing threads, where each thread performs a convolution function corresponding to a stride in a tile or an im2col portion.

[0184] FIG. 8 is a block diagram of an example input tensor using a tiled access technique, according to at least one embodiment. In this example, input tensor 801 is a matrix. Although a convolution operation for tensor 801 is shown in Fig. 8, tiled / im2col access technique can be used for other arithmetic operations.

[0185] In Fig. 8, in at least one embodiment, processing logic makes a determination that im2col portions have smaller dimensions (total number of elements) than a tile, processing logic then accesses im2col portions using an im2col technique. In at least one embodiment, when an element count in a would-be im2col portion is above a predetermined threshold (e.g., 90%) in comparison with an element count of a tile (e.g., tile quantization effects are minimal), a tiled access technique is used for said tiled portion and said im2col portion. Here, an element count in tiles C and F is greater than 90% in comparison with total element counts in a tile, thus, tiles C and F are accessed using tiled technique. DATA CENTER

[0186] FIG. 9 illustrates an example data center 900, in which at least one embodiment may be used. In at least one embodiment, data center 900 includes a data center infrastructure layer 910, a framework layer 920, a software layer 930 and an application layer 940.

[0187] In at least one embodiment, as shown in FIG. 9, data center infrastructure layer 910 may include a resource orchestrator 912, grouped computing resources 914, and node computing resources (“node C.R.s”) 916(1 )-916(N), where “N” represents a positive integer (which may be a different integer “N” than used in other figures). In at least one embodiment, node C.R.s 916(1)-916(N) may include, but are not limited to, any number of central processing units (“CPUs”) or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processors, etc.), memory storage devices 918(1)-918(N) (e.g., dynamic read-only memory, solid state storage or disk drives), network input / output (“NW I / O”) devices, network switches, virtual machines (“VMs”), power modules, and cooling modules, etc. In at least one embodiment, one or more node C.R.S from among node C.R.S 916(1)-916(N) may be a server having one or more of above-mentioned computing resources.

[0188] In at least one embodiment, grouped computing resources 914 may include separate groupings of node C.R.S housed within one or more racks (not shown), or many racks housed in data centers at various geographical locations (also not shown). In at least one embodiment, separate groupings of node C.R.s within grouped computing resources 914 may include grouped compute, network, memory or storage resources that may be configured or allocated to support one or more workloads. In at least one embodiment, several node C.R.s including CPUs or processors may grouped within one or more racks to provide compute resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches, in any combination.

[0189] In at least one embodiment, resource orchestrator 912 may configure or otherwise control one or more node C.R.S 916(1)-916(N) and / or grouped computing resources 914. In at least one embodiment, resource orchestrator 912 may include a software design infrastructure (“SDI”) management entity for data center 900. In at least one embodiment, resource orchestrator 112 may include hardware, software or some combination thereof.

[0190] In at least one embodiment, as shown in FIG. 9, framework layer 920 includes a job scheduler 922, a configuration manager 924, a resource manager 926 and a distributed file system 928. In at least one embodiment, framework layer 920 may include a framework to support software 932 of software layer 930 and / or one or more application! s) 942 of application layer 940. In at least one embodiment, software 932 or application(s) 942 may respectively include web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud and Microsoft Azure. In at least one embodiment, framework layer 920 may be, but is not limited to, a type of free and open-source software web application framework such as Apache Spark™ (hereinafter “Spark”) that may utilize distributed file system 928 for large-scale data processing (e.g., “big data”). In at least one embodiment job scheduler 922 may include a Spark driver to facilitate scheduling of workloads supported by various layers of data center 900. In at least one embodiment, configuration manager 924 may be capable of configuring different layers such as software layer 930 and framework layer 920 including Spark and distributed file system 928 for supporting large-scale data processing. In at least one embodiment, resource manager 926 may be capable of managing clustered or grouped computing resources mapped to or allocated for support of distributed file system 928 and job scheduler 922. In at least one embodiment, clustered or grouped computing resources may include grouped computing resources 914 at data center infrastructure layer 910. In at least one embodiment, resource manager 926 may coordinate with resource orchestrator 912 to manage these mapped or allocated computing resources. [0191 ] In at least one embodiment, software 932 included in software layer 930 may include software used by at least portions of node C.R.s 916(1)-916(N), grouped computing resources 914, and / or distributed file system 928 of framework layer 920. In at least one embodiment, one or more types of software may include, but are not limited to, Internet web page search software, e-mail virus scan software, database software, and streaming video content software.

[0192] In at least one embodiment, application(s) 942 included in application layer 940 may include one or more types of applications used by at least portions of node C.R.s 916(1)-916(N), grouped computing resources 914, and / or distributed file system 928 of framework layer 920. In at least one embodiment, one or more types of applications may include, but are not limited to, any number of a genomics application, a cognitive compute, application and a machine learning application, including training or inferencing software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.) or other machine learning applications used in conjunction with one or more embodiments. (0193] In at least one embodiment, any of configuration manager 924, resource manager 926, and resource orchestrator 912 may implement any number and type of self-modifying actions based on any amount and type of data acquired in any technically feasible fashion. In at least one embodiment, self-modifying actions may relieve a data center operator of data center 900 from making possibly bad configuration decisions and possibly avoiding underutilized and / or poor performing portions of a data center.

[0194] In at least one embodiment, data center 900 may include tools, services, software or other resources to train one or more machine learning models or predict or infer information using one or more machine learning models according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model may be trained by calculating weight parameters according to a neural network architecture using software and computing resources described above with respect to data center 900. In at least one embodiment, trained machine learning models corresponding to one or more neural networks may be used to infer or predict information using resources described above with respect to data center 900 by using weight parameters calculated through one or more training techniques described herein.

[0195] In at least one embodiment, data center may use CPUs, application-specific integrated circuits (ASICs), GPUs, FPGAs, or other hardware to perform training and / or inferencing using above-described resources. Moreover, one or more software and / or hardware resources described above may be configured as a service to allow users to train or performing inferencing of information, such as image recognition, speech recognition, or other artificial intelligence services. [019€>] Inference and / or training logic 115 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 115 are provided herein in conjunction with FIGS. 1A and / or IB. In at least one embodiment, inference and / or training logic 115 may be used in system FIG. 9 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein. AUTONOMOUS VEHICLE

[0197] FIG. 10A illustrates an example of an autonomous vehicle 1000, according to at least one embodiment. In at least one embodiment, autonomous vehicle 1000 (alternatively referred to herein as “vehicle 1000”) may be, without limitation, a passenger vehicle, such as a car, a truck, a bus, and / or another type of vehicle that accommodates one or more passengers. In at least one embodiment, vehicle 1000 may be a semi-tractor-trailer truck used for hauling cargo. In at least one embodiment, vehicle 1000 may be an airplane, robotic vehicle, or other kind of vehicle.

[0198] Autonomous vehicles may be described in terms of automation levels, defined by National Highway Traffic Safety Administration (“NHTSA”), a division of US Department of Transportation, and Society of Automotive Engineers (“SAE”) “Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles” (e.g., Standard No. J3016-201806, published on June 15, 2018, Standard No. J3016-201609, published on September 30, 2016, and previous and future versions of this standard). In at least one embodiment, vehicle 1000 may be capable of functionality in accordance with one or more of Level 1 through Level 5 of autonomous driving levels. For example, in at least one embodiment, vehicle 1000 may be capable of conditional automation (Level 3), high automation (Level 4), and / or full automation (Level 5), depending on embodiment.

[0199] In at least one embodiment, vehicle 1000 may include, without limitation, components such as a chassis, a vehicle body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other components of a vehicle. In at least one embodiment, vehicle 1000 may include, without limitation, a propulsion system 1050, such as an internal combustion engine, hybrid electric power plant, an all-electric engine, and / or another propulsion system type. In at least one embodiment, propulsion system 1050 may be connected to a drive train of vehicle 1000, which may include, without limitation, a transmission, to enable propulsion of vehicle 1000. In at least one embodiment, propulsion system 1050 may be controlled in response to receiving signals from a throttle / accelerator(s) 1052.

[0200] In at least one embodiment, a steering system 1054, which may include, without limitation, a steering wheel, is used to steer vehicle 1000 (e.g., along a desired path or route) when propulsion system 1050 is operating (e.g., when vehicle 1000 is in motion). In at least one embodiment, steering system 1054 may receive signals from steering actuator(s) 1056. In at least one embodiment, a steering wheel may be optional for full automation (Level 5) functionality. In at least one embodiment, a brake sensor system 1046 may be used to operate vehicle brakes in response to receiving signals from brake actuator(s) 1048 and / or brake sensors.

[0201] In at least one embodiment, control ler(s) 1036, which may include, without limitation, one or more system on chips (“SoCs”) (not shown in FIG. 10A) and / or graphics processing unit(s) (“GPU(s)”), provide signals (e.g., representative of commands) to one or more components and / or systems of vehicle 1000. For instance, in at least one embodiment, controller(s) 1036 may send signals to operate vehicle brakes via brake actuator(s) 1048, to operate steering system 1054 via steering actuator(s) 1056, to operate propulsion system 1050 via throttle / accelerator(s) 1052. In at least one embodiment, controller(s) 1036 may include one or more onboard (e.g., integrated) computing devices that process sensor signals, and output operation commands (e.g., signals representing commands) to enable autonomous driving and / or to assist a human driver in driving vehicle 1000. In at least one embodiment, controller(s) 1036 may include a first controller for autonomous driving functions, a second controller for functional safety functions, a third controller for artificial intelligence functionality (e.g., computer vision), a fourth controller for infotainment functionality, a fifth controller for redundancy in emergency conditions, and / or other controllers. In at least one embodiment, a single controller may handle two or more of above functionalities, two or more controllers may handle a single functionality, and / or any combination thereof.

[0202] In at least one embodiment, controller(s) 1036 provide signals for controlling one or more components and / or systems of vehicle 1000 in response to sensor data received from one or more sensors (e.g., sensor inputs). In at least one embodiment, sensor data may be received from, for example and without limitation, global navigation satellite systems (“GNSS”) sensor(s) 1058 (e.g., Global Positioning System sensor(s)), RADAR sensor(s) 1060, ultrasonic sensor(s) 1062, LIDAR sensor(s) 1064, inertial measurement unit (“IMU”) sensor(s) 1066 (e.g., accelerometer(s), gyroscope(s), a magnetic compass or magnetic compasses, magnetometer(s), etc.), microphone(s) 1096, stereo camera(s) 1068, wide-view camera(s) 1070 (e.g., fisheye cameras), infrared camera(s) 1072, surround camera(s) 1074 (e.g., 360 degree cameras), long-range cameras (not shown in FIG. 10A), mid-range camera(s) (not shown in FIG. 10A), speed sensor(s) 1044 (e.g., for measuring speed of vehicle 1000), vibration sensor(s) 1042, steering sensor(s) 1040, brake sensor(s) (e.g., as part of brake sensor system 1046), and / or other sensor types.

[0203] In at least one embodiment, one or more of controller(s) 1036 may receive inputs (e.g., represented by input data) from an instrument cluster 1032 of vehicle 1000 and provide outputs (e.g., represented by output data, display data, etc.) via a human-machine interface (“HMI”) display 1034, an audible annunciator, a loudspeaker, and / or via other components of vehicle 1000. In at least one embodiment, outputs may include information such as vehicle velocity, speed, time, map data (e.g., a High Definition map (not shown in FIG. 10A), location data (e.g., vehicle’s 1000 location, such as on a map), direction, location of other vehicles (e.g., an occupancy grid), information about objects and status of objects as perceived by controller(s) 1036, etc. For example, in at least one embodiment, HMI display 1034 may display information about presence of one or more objects (e.g., a street sign, caution sign, traffic light changing, etc.), and / or information about driving maneuvers vehicle has made, is making, or will make (e.g., changing lanes now, taking exit 34B in two miles, etc.).

[0204] In at least one embodiment, vehicle 1000 further includes a network interface 1024 which may use wireless antenna(s) 1026 and / or modem(s) to communicate over one or more networks. For example, in at least one embodiment, network interface 1024 may be capable of communication over Long-Term Evolution (“LIE”), Wideband Code Division Multiple Access (“WCDMA”), Universal Mobile Telecommunications System (“UMTS”), Global System for Mobile communication (“GSM”), IMT-CDMA Multi-Carrier (“CDMA2000”) networks, etc. In at least one embodiment, wireless antenna(s) 1026 may also enable communication between objects in environment (e.g., vehicles, mobile devices, etc.), using local area network(s), such as Bluetooth, Bluetooth Low Energy (“LE”), Z-Wave, ZigBee, etc., and / or low power wide-area network(s) (“LPWANs”), such as LoRaWAN, SigFox, etc. protocols.

[0205] Inference and / or training logic 115 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 115 are provided herein in conjunction with FIGS. 1A and / or IB. In at least one embodiment, inference and / or training logic 115 may be used in system FIG. 10A for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0206] FIG. 10B illustrates an example of camera locations and fields of view for autonomous vehicle 1000 of FIG. 10A, according to at least one embodiment. In at least one embodiment, cameras and respective fields of view are one example embodiment and are not intended to be limiting. For instance, m at least one embodiment, additional and / or alternative cameras may be included and / or cameras may be located at different locations on vehicle 1000.

[0207] In at least one embodiment, camera types for cameras may include, but are not limited to, digital cameras that may be adapted for use with components and / or systems of vehicle 1000. In at least one embodiment, camera(s) may operate at automotive safety integrity level (“ASIL”) B and / or at another ASIL. In at least one embodiment, camera types may be capable of any image capture rate, such as 60 frames per second (fps), 1220 fps, 240 fps, etc., depending on embodiment. In at least one embodiment, cameras may be capable of using rolling shutters, global shutters, another type of shutter, or a combination thereof. In at least one embodiment, color filter array may include a red clear clear clear (“RCCC”) color filter array, a red clear clear blue (“RCCB”) color filter array, a red blue green clear (“RBGC”) color filter array, a Foveon X3 color filter array, a Bayer sensors (“RGGB”) color filter array, a monochrome sensor color filter array, and / or another type of color filter array. In at least one embodiment, clear pixel cameras, such as cameras with an RCCC, an RCCB, and / or an RBGC color filter array, may be used in an effort to increase light sensitivity.

[0208] In at least one embodiment, one or more of camera(s) may be used to perform advanced driver assistance systems (“ADAS”) functions (e.g., as part of a redundant or fail-safe design). For example, in at least one embodiment, a Multi-Function Mono Camera may be installed to provide functions including lane departure warning, traffic sign assist and intelligent headlamp control. In at least one embodiment, one or more of camera(s) (e.g., all cameras) may record and provide image data (e.g., video) simultaneously.

[0209] In at least one embodiment, one or more camera may be mounted in a mounting assembly, such as a custom designed (three-dimensional (“3D”) printed) assembly, in order to cut out stray light and reflections from within vehicle 1000 (e.g., reflections from dashboard reflected in windshield mirrors) which may interfere with camera image data capture abilities. With reference to wing-mirror mounting assemblies, in at least one embodiment, wing-mirror assemblies may be custom 3D printed so that a camera mounting plate matches a shape of a wing-mirror. In at least one embodiment, camera(s) may be integrated into wing-mirrors. In at least one embodiment, for side-view cameras, camera(s) may also be integrated within four pillars at each corner of a cabin.

[0210] In at least one embodiment, cameras with a field of view that include portions of an environment in front of vehicle 1000 (e.g., front-facing cameras) may be used for surround view, to help identify forward facing paths and obstacles, as well as aid in, with help of one or more of controller(s) 1036 and / or control SoCs, providing information critical to generating an occupancy grid and / or determining preferred vehicle paths. In at least one embodiment, frontfacing cameras may be used to perform many similar ADAS functions as LIDAR, including, without limitation, emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, front-facing cameras may also be used for ADAS functions and systems including, without limitation, Lane Departure Warnings (“LDW”), Autonomous Cruise Control (“ACC”), and / or other functions such as traffic sign recognition.

[0211] In at least one embodiment, a variety of cameras may be used in a front-facing configuration, including, for example, a monocular camera platform that includes a CMOS (“complementary metal oxide semiconductor”) color imager. In at least one embodiment, a wide-view camera 1070 may be used to perceive objects coming into view from a periphery (e.g., pedestrians, crossing traffic or bicycles). Although only one wide-view camera 1070 is illustrated in FIG. 10B, in other embodiments, there may be any number (including zero) wide-view cameras on vehicle 1000. In at least one embodiment, any number of long-range camera(s) 1098 (e.g., a long-view stereo camera pair) may be used for depth-based object detection, especially for objects for which a neural network has not yet been trained. In at least one embodiment, long-range camera(s) 1098 may also be used for object detection and classification, as well as basic object tracking.

[0212] In at least one embodiment, any number of stereo camera(s) 1068 may also be included in a front-facing configuration. In at least one embodiment, one or more of stereo camera(s) 1068 may include an integrated control unit comprising a scalable processing unit, which may provide a programmable logic (“FPGA”) and a multi-core micro-processor with an integrated Controller Area Network (“CAN”) or Ethernet interface on a single chip. In at least one embodiment, such a unit may be used to generate a 3D map of an environment of vehicle 1000, including a distance estimate for all points in an image. In at least one embodiment, one or more of stereo camera(s) 1068 may include, without limitation, compact stereo vision sensor(s) that may include, without limitation, two camera lenses (one each on left and right) and an image processing chip that may measure distance from vehicle 1000 to target object and use generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. In at least one embodiment, other types of stereo camera(s) 1068 may be used in addition to, or alternatively from, those described herein.

[0213] In at least one embodiment, cameras with a field of view that include portions of environment to sides of vehicle 1000 (e.g., side-view cameras) may be used for surround view, providing information used to create and update an occupancy grid, as well as to generate side impact collision warnings. For example, in at least one embodiment, surround camera(s) 1074 (e.g., four surround cameras as illustrated in FIG. 10B) could be positioned on vehicle 1000. In at least one embodiment, surround camera(s) 1074 may include, without limitation, any number and combination of wide-view cameras, fisheye camera(s), 360 degree camera(s), and / or similar cameras. For instance, in at least one embodiment, four fisheye cameras may be positioned on a front, a rear, and sides of vehicle 1000. In at least one embodiment, vehicle 1000 may use three surround camera(s) 1074 (e.g., left, right, and rear), and may leverage one or more other camera(s) (e.g., a forward-facing camera) as a fourth surround-view camera.

[0214] In at least one embodiment, cameras with a field of view that include portions of an environment behind vehicle 1000 (e.g., rear-view cameras) may be used for parking assistance, surround view, rear collision warnings, and creating and updating an occupancy grid. In at least one embodiment, a wide variety of cameras may be used including, but not limited to, cameras that are also suitable as a front-facing camera(s) (e.g., long-range cameras 1098 and / or mid-range camera(s) 1076, stereo camera(s) 1068), infrared camera(s) 1072, etc.), as described herein.

[0215] Inference and / or training logic 115 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 115 are provided herein in conjunction with FIGS. 1A and / or IB. In at least one embodiment, inference and / or training logic 115 may be used in system FIG. 1 OB for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0216] FIG. 10C is a block diagram illustrating an example system architecture for autonomous vehicle 1000 of FIG. 10A, according to at least one embodiment. In at least one embodiment, each of components, features, and systems of vehicle 1000 in FIG. 10C is illustrated as being connected via a bus 1002. In at least one embodiment, bus 1002 may include, without limitation, a CAN data interface (alternatively referred to herein as a “CAN bus”). In at least one embodiment, a CAN may be a network inside vehicle 1000 used to aid in control of various features and functionality of vehicle 1000, such as actuation of brakes, acceleration, braking, steering, windshield wipers, etc. In at least one embodiment, bus 1002 may be configured to have dozens or even hundreds of nodes, each with its own unique identifier (e.g., a CAN ID). In at least one embodiment, bus 1002 may be read to find steering wheel angle, ground speed, engine revolutions per minute (“RPMs”), button positions, and / or other vehicle status indicators. In at least one embodiment, bus 1002 may be a CAN bus that is ASIL B compliant. [0217 ] In at least one embodiment, in addition to, or alternatively from CAN, FlexRay and / or Ethernet protocols may be used. In at least one embodiment, there may be any number of busses forming bus 1002, which may include, without limitation, zero or more CAN busses, zero or more FlexRay busses, zero or more Ethernet busses, and / or zero or more other types of busses using different protocols. In at least one embodiment, two or more busses may be used to perform different functions, and / or may be used for redundancy. For example, a first bus may be used for collision avoidance functionality and a second bus may be used for actuation control. In at least one embodiment, each bus of bus 1002 may communicate with any of components of vehicle 1000, and two or more busses of bus 1002 may communicate with corresponding components. In at least one embodiment, each of any number of system(s) on chip(s) (“SoC(s)”) 1004 (such as SoC 1004(A) and SoC 1004(B), each of controller(s) 1036, and / or each computer within vehicle may have access to same input data (e.g., inputs from sensors of vehicle 1000), and may be connected to a common bus, such CAN bus.

[0218] In at least one embodiment, vehicle 1000 may include one or more controller(s) 1036, such as those described herein with respect to FIG. 10A. In at least one embodiment, controller(s) 1036 may be used for a variety of functions. In at least one embodiment, controller(s) 1036 may be coupled to any of various other components and systems of vehicle 1000, and may be used for control of vehicle 1000, artificial intelligence of vehicle 1000, infotainment for vehicle 1000, and / or other functions.

[0219] In at least one embodiment, vehicle 1000 may include any number of SoCs 1004. In at least one embodiment, each of SoCs 1004 may include, without limitation, central processing units (“CPU(s)”) 1006, graphics processing units (“GPU(s)”) 1008, processor(s) 1010, cache(s) 1012, accelerator(s) 1014, data store(s) 1016, and / or other components and features not illustrated. In at least one embodiment, SoC(s) 1004 may be used to control vehicle 1000 in a variety of platforms and systems. For example, in at least one embodiment, SoC(s) 1004 may be combined in a system (e.g., system of vehicle 1000) with a High Definition (“HD”) map 1022 which may obtain map refreshes and / or updates via network interface 1024 from one or more servers (not shown in FIG. 10C).

[0220] In at least one embodiment, CPU(s) 1006 may include a CPU cluster or CPU complex (alternatively referred to herein as a “CCPLEX”). In at least one embodiment, CPU(s) 1006 may include multiple cores and / or level two (“L2”) caches. For instance, in at least one embodiment, CPU(s) 1006 may include eight cores in a coherent multi-processor configuration. In at least one embodiment, CPU(s) 1006 may include four dual-core clusters where each cluster has a dedicated L2 cache (e.g., a 2 megabyte (MB) L2 cache). In at least one embodiment, CPU(s) 1006 (e.g., CCPLEX) may be configured to support simultaneous cluster operations enabling any combination of clusters of CPU(s) 1006 to be active at any given time. [0221 ] In at least one embodiment, one or more of CPU(s) 1006 may implement power management capabilities that include, without limitation, one or more of following features: individual hardware blocks may be clock-gated automatically when idle to save dynamic power; each core clock may be gated when such core is not actively executing instructions due to execution of Wait for Interrupt (“WFI”) / Wait for Event (“WFE”) instructions; each core may be independently power-gated; each core cluster may be independently clock-gated when all cores are clock-gated or power-gated; and / or each core cluster may be independently power-gated when all cores are power-gated. In at least one embodiment, CPU(s) 1006 may further implement an enhanced algorithm for managing power states, where allowed power states and expected wakeup times are specified, and hardware / microcode determines which best power state to enter for core, cluster, and CCPLEX. In at least one embodiment, processing cores may support simplified power state entry sequences in software with work offloaded to microcode.

[0222] In at least one embodiment, GPU(s) 1008 may include an integrated GPU (alternatively referred to herein as an “iGPU”). In at least one embodiment, GPU(s) 1008 may be programmable and may be efficient for parallel workloads. In at least one embodiment, GPU(s) 1008 may use an enhanced tensor instruction set. In at least one embodiment, GPU(s) 1008 may include one or more streaming microprocessors, where each streaming microprocessor may include a level one (“LI”) cache (e.g., an LI cache with at least 96 KB storage capacity), and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache with a 512 KB storage capacity). In at least one embodiment, GPU(s) 1008 may include at least eight streaming microprocessors. In at least one embodiment, GPU(s) 1008 may use compute application programming interface(s) (API(s)). In at least one embodiment, GPU(s) 1008 may use one or more parallel computing platforms and / or programming models (e.g., NVIDIA’s CUDA model).

[0223] In at least one embodiment, one or more of GPU(s) 1008 may be power-optimized for best performance in automotive and embedded use cases. For example, in at least one embodiment, GPU(s) 1008 could be fabricated on Fin field-effect transistor (“FinFET”) circuitry. In at least one embodiment, each streaming microprocessor may incorporate a number of mixed-precision processing cores partitioned into multiple blocks. For example, and without limitation, 64 PF32 cores and 32 PF64 cores could be partitioned into four processing blocks. In at least one embodiment, each processing block could be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA Tensor cores for deep learning matrix arithmetic, a level zero (“L0”) instruction cache, a warp scheduler, a dispatch unit, and / or a 64 KB register file. In at least one embodiment, streaming microprocessors may include independent parallel integer and floating-point data paths to provide for efficient execution of workloads with a mix of computation and addressing calculations. In at least one embodiment, streaming microprocessors may include independent thread scheduling capability to enable finer-grain synchronization and cooperation between parallel threads. In at least one embodiment, streaming microprocessors may include a combined LI data cache and shared memory unit in order to improve performance while simplifying programming.

[0224] In at least one embodiment, one or more of GPU(s) 1008 may include a high bandwidth memory (“HBM) and / or a 16 GB high-bandwidth memory second generation (“HBM2”) memory subsystem to provide, in some examples, about 900 GB second peak memory bandwidth. In at least one embodiment, in addition to, or alternatively from, HBM memory, a synchronous graphics random-access memory (“SGRAM”) may be used, such as a graphics double data rate type five synchronous random-access memory (“GDDR5”).

[0225] In at least one embodiment, GPU(s) 1008 may include unified memory technology. In at least one embodiment, address translation services (“ATS”) support may be used to allow GPU(s) 1008 to access CPU(s) 1006 page tables directly. In at least one embodiment, embodiment, when a GPU of GPU(s) 1008 memory management unit (“MMU”) experiences a miss, an address translation request may be transmitted to CPU(s) 1006. In response, 2 CPU of CPU(s) 1006 may look in its page tables for a virtual-to-physical mapping for an address and transmit translation back to GPU(s) 1008, in at least one embodiment. In at least one embodiment, unified memory technology may allow a single unified virtual address space for memory of both CPU(s) 1006 and GPU(s) 1008, thereby simplifying GPU(s) 1008 programming and porting of applications to GPU(s) 1008.

[0226] In at least one embodiment, GPU(s) 1008 may include any number of access counters that may keep track of frequency of access of GPU(s) 1008 to memory of other processors. In at least one embodiment, access counter(s) may help ensure that memory pages are moved to physical memory of a processor that is accessing pages most frequently, thereby improving efficiency for memory ranges shared between processors.

[0227] In at least one embodiment, one or more of SoC(s) 1004 may include any number of cache(s) 1012, including those described herein. For example, in at least one embodiment, cache(s) 1012 could include a level three (“L3”) cache that is available to both CPU(s) 1006 and GPU(s) 1008 (e.g., that is connected to CPU(s) 1006 and GPU(s) 1008). In at least one embodiment, cache(s) 1012 may include a write-back cache that may keep track of states of lines, such as by using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, a L3 cache may include 4 MB of memory or more, depending on embodiment, although smaller cache sizes may be used.

[0228] In at least one embodiment, one or more of SoC(s) 1004 may include one or more accelerator(s) 1014 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, SoC(s) 1004 may include a hardware acceleration cluster that may include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, large on-chip memory (e.g., 4 MB of SRAM), may enable a hardware acceleration cluster to accelerate neural networks and other calculations. In at least one embodiment, a hardware acceleration cluster may be used to complement GPU(s) 1008 and to off-load some of tasks of GPU(s) 1008 (e.g., to free up more cycles of GPU(s) 1008 for performing other tasks). In at least one embodiment, accelerator(s) 1014 could be used for targeted workloads (e.g., perception, convolutional neural networks (“CNNs”), recurrent neural networks (“RNNs”), etc.) that are stable enough to be amenable to acceleration. In at least one embodiment, a CNN may include a region-based or regional convolutional neural networks (“RCNNs”) and Fast RCNNs (e.g., as used for object detection) or other type of CNN. [()229] In at least one embodiment, accelerator!s) 1014 (e.g., hardware acceleration cluster) may include one or more deep learning accelerator (“DLA”). In at least one embodiment, DLA(s) may include, without limitation, one or more Tensor processing units (“TPUs”) that may be configured to provide an additional ten trillion operations per second for deep learning applications and inferencing. In at least one embodiment, TPUs may be accelerators configured to, and optimized for, performing image processing functions (e.g., for CNNs, RCNNs, etc.). In at least one embodiment, DLA(s) may further be optimized for a specific set of neural network types and floating point operations, as well as inferencing. In at least one embodiment, design of DLA(s) may provide more performance per millimeter than a typical general-purpose GPU, and typically vastly exceeds performance of a CPU. In at least one embodiment, TPU(s) may perform several functions, including a single-instance convolution function, supporting, for example, INT8, INTI 6, and FP16 data types for both features and weights, as well as postprocessor functions. In at least one embodiment, DLA(s) may quickly and efficiently execute neural networks, especially CNNs, on processed or unprocessed data for any of a variety of functions, including, for example and without limitation: a CNN for object identification and detection using data from camera sensors; a CNN for distance estimation using data from camera sensors; a CNN for emergency vehicle detection and identification and detection using data from microphones; a CNN for facial recognition and vehicle owner identification using data from camera sensors; and / or a CNN for security and / or safety related events.

[0230] In at least one embodiment, DLA(s) may perform any function of GPU(s) 1008, and by using an inference accelerator, for example, a designer may target either DLA(s) or GPU(s) 1008 for any function. For example, in at least one embodiment, a designer may focus processing of CNNs and floating point operations on DLA(s) and leave other functions to GPU(s) 1008 and / or accelerator(s) 1014. [0231 ] In at least one embodiment, accelerator(s) 1014 may include programmable vision accelerator (“PVA”), which may alternatively be referred to herein as a computer vision accelerator. In at least one embodiment, PVA may be designed and configured to accelerate computer vision algorithms for advanced driver assistance system (“ADAS”) 1038, autonomous driving, augmented reality (“AR”) applications, and / or virtual reality (“VR”) applications. In at least one embodiment, PVA may provide a balance between performance and flexibility. For example, in at least one embodiment, each PVA may include, for example and without limitation, any number of reduced instruction set computer (“RISC”) cores, direct memory access (“DMA”), and / or any number of vector processors.

[0232] In at least one embodiment, RISC cores may interact with image sensors (e.g., image sensors of any cameras described herein), image signal processor(s), etc. In at least one embodiment, each RISC core may include any amount of memory. In at least one embodiment, RISC cores may use any of a number of protocols, depending on embodiment. In at least one embodiment, RISC cores may execute a real-time operating system (“RTOS”). In at least one embodiment, RISC cores may be implemented using one or more integrated circuit devices, application specific integrated circuits (“ASICs”), and / or memory devices. For example, in at least one embodiment, RISC cores could include an instruction cache and / or a tightly coupled RAM.

[0233] In at least one embodiment, DMA may enable components of PVA to access system memory independently of CPU(s) 1006. In at least one embodiment, DMA may support any number of features used to provide optimization to a PVA including, but not limited to, supporting multi-dimensional addressing and / or circular addressing. In at least one embodiment, DMA may support up to six or more dimensions of addressing, which may include, without limitation, block width, block height, block depth, horizontal block stepping, vertical block stepping, and / or depth stepping.

[0234] In at least one embodiment, vector processors may be programmable processors that may be designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing capabilities. In at least one embodiment, a PVA may include a PVA core and two vector processing subsystem partitions. In at least one embodiment, a PVA core may include a processor subsystem, DMA engine(s) (e.g., two DMA engines), and / or other peripherals. In at least one embodiment, a vector processing subsystem may operate as a primary processing engine of a PVA, and may include a vector processing unit (“VPU”), an instruction cache, and / or vector memory (e.g., “VMEM”). In at least one embodiment, VPU core may include a digital signal processor such as, for example, a single instruction, multiple data (“SIMD”), very long instruction word (“VLIW”) digital signal processor. In at least one embodiment, a combination of SIMD and VLIW may enhance throughput and speed.

[0235] In at least one embodiment, each of vector processors may include an instruction cache and may be coupled to dedicated memory. As a result, in at least one embodiment, each of vector processors may be configured to execute independently of other vector processors. In at least one embodiment, vector processors that are included in a particular PVA may be configured to employ data parallelism. For instance, in at least one embodiment, plurality of vector processors included in a single PVA may execute a common computer vision algorithm, but on different regions of an image. In at least one embodiment, vector processors included in a particular PVA may simultaneously execute different computer vision algorithms, on one image, or even execute different algorithms on sequential images or portions of an image. In at least one embodiment, among other things, any number of PVAs may be included in hardware acceleration cluster and any number of vector processors may be included in each PVA. In at least one embodiment, PVA may include additional error correcting code (“ECC”) memory, to enhance overall system safety.

[0236] In at least one embodiment, accelerator(s) 1014 may include a computer vision network on-chip and static random-access memory (“SRAM”), for providing a high-bandwidth, low latency SRAM for accelerator(s) 1014. In at least one embodiment, on-chip memory may include at least 4 MB SRAM, comprising, for example and without limitation, eight field-configurable memory blocks, that may be accessible by both a PVA and a DLA. In at least one embodiment, each pair of memory blocks may include an advanced peripheral bus (“APB”) interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, a PVA and a DLA may access memory via a backbone that provides a PVA and a DLA with high-speed access to memory. In at least one embodiment, a backbone may include a computer vision network on-chip that interconnects a PVA and a DLA to memory (e.g., using APB).

[0237] In at least one embodiment, a computer vision network on-chip may include an interface that determines, before transmission of any control signal / address / data, that both a PVA and a DLA provide ready and valid signals. In at least one embodiment, an interface may provide for separate phases and separate channels for transmitting control signals / addresses / data, as well as burst-type communications for continuous data transfer. In at least one embodiment, an interface may comply with International Organization for Standardization (“ISO”) 26262 or International Electrotechnical Commission (“IEC”) 61508 standards, although other standards and protocols may be used.

[0238] In at least one embodiment, one or more of SoC(s) 1004 may include a real-time raytracing hardware accelerator. In at least one embodiment, real-time ray-tracing hardware accelerator may be used to quickly and efficiently determine positions and extents of objects (e.g., within a world model), to generate real-time visualization simulations, for RADAR signal interpretation, for sound propagation synthesis and / or analysis, for simulation of SONAR systems, for general wave propagation simulation, for comparison to LIDAR data for purposes of localization and / or other functions, and / or for other uses.

[0239] In at least one embodiment, accelerator(s) 1014 can have a wide array of uses for autonomous driving. In at least one embodiment, a PVA may be used for key processing stages in ADAS and autonomous vehicles. In at least one embodiment, a PVA’s capabilities are a good match for algorithmic domains needing predictable processing, at low power and low latency. In other words, a PVA performs well on semi-dense or dense regular computation, even on small data sets, which might require predictable run-times with low latency and low power. In at least one embodiment, such as in vehicle 1000, PVAs might be designed to run classic computer vision algorithms, as they can be efficient at object detection and operating on integer math.

[0240] For example, according to at least one embodiment of technology, a PVA is used to perform computer stereo vision. In at least one embodiment, a semi-global matching-based algorithm may be used in some examples, although this is not intended to be limiting. In at least one embodiment, applications for Level 3-5 autonomous driving use motion estimation / stereo matching on-the-fly (e.g., structure from motion, pedestrian recognition, lane detection, etc.). In at least one embodiment, a PVA may perform computer stereo vision functions on inputs from two monocular cameras. [0241 ] In at least one embodiment, a PVA may be used to perform dense optical flow. For example, in at least one embodiment, a PVA could process raw RADAR data (e.g., using a 4D Fast Fourier Transform) to provide processed RADAR data. In at least one embodiment, a PVA is used for time of flight depth processing, by processing raw time of flight data to provide processed time of flight data, for example. [9242 ] In at least one embodiment, a DLA may be used to run any type of network to enhance control and driving safety, including for example and without limitation, a neural network that outputs a measure of confidence for each object detection. In at least one embodiment, confidence may be represented or interpreted as a probability, or as providing a relative “weight” of each detection compared to other detections. In at least one embodiment, a confidence measure enables a system to make further decisions regarding which detections should be considered as true positive detections rather than false positive detections. In at least one embodiment, a system may set a threshold value for confidence and consider only detections exceeding threshold value as true positive detections. In an embodiment in which an automatic emergency braking (“AEB”) system is used, false positive detections would cause vehicle to automatically perform emergency braking, which is obviously undesirable. In at least one embodiment, highly confident detections may be considered as triggers for AEB. In at least one embodiment, a DLA may run a neural network for regressing confidence value. In at least one embodiment, neural network may take as its input at least some subset of parameters, such as bounding box dimensions, ground plane estimate obtained (e.g., from another subsystem), output from IMU sensor(s) 1066 that correlates with vehicle 1000 orientation, distance, 3D location estimates of object obtained from neural network and / or other sensors (e.g., LIDAR sensor(s) 1064 or RADAR sensor(s) 1060), among others.

[0243] In at least one embodiment, one or more of SoC(s) 1004 may include data store(s) 1016 (e.g., memory). In at least one embodiment, data store(s) 1016 may be on-chip memory of SoC(s) 1004, which may store neural networks to be executed on GPU(s) 1008 and / or a DLA. In at least one embodiment, data store(s) 1016 may be large enough in capacity to store multiple instances of neural networks for redundancy and safety. In at least one embodiment, data store(s) 1016 may comprise L2 or L3 cache(s).

[0244] In at least one embodiment, one or more of SoC(s) 1004 may include any number of processor(s) 1010 (e.g., embedded processors). In at least one embodiment, processor(s) 1010 may include a boot and power management processor that may be a dedicated processor and subsystem to handle boot power and management functions and related security enforcement. In at least one embodiment, a boot and power management processor may be a part of a boot sequence of SoC(s) 1004 and may provide runtime power management services. In at least one embodiment, a boot power and management processor may provide clock and voltage programming, assistance in system low power state transitions, management of SoC(s) 1004 thermals and temperature sensors, and / or management of SoC(s) 1004 power states. In at least one embodiment, each temperature sensor may be implemented as a ring-oscillator whose output frequency is proportional to temperature, and SoC(s) 1004 may use ring-oscillators to detect temperatures of CPU(s) 1006, GPU(s) 1008, and / or accelerator(s) 1014. In at least one embodiment, if temperatures are determined to exceed a threshold, then a boot and power management processor may enter a temperature fault routine and put SoC(s) 1004 into a lower power state and / or put vehicle 1000 into a chauffeur to safe stop mode (e.g., bring vehicle 1000 to a safe stop).

[0245] In at least one embodiment, processor(s) 1010 may further include a set of embedded processors that may serve as an audio processing engine which may be an audio subsystem that enables full hardware support for multi-channel audio over multiple interfaces, and a broad and flexible range of audio I / O interfaces. In at least one embodiment, an audio processing engine is a dedicated processor core with a digital signal processor with dedicated RAM.

[0246] In at least one embodiment, processor(s) 1010 may further include an always-on processor engine that may provide necessary hardware features to support low power sensor management and wake use cases. In at least one embodiment, an always-on processor engine may include, without limitation, a processor core, a tightly coupled RAM, supporting peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0247] In at least one embodiment, processor(s) 1010 may further include a safety cluster engine that includes, without limitation, a dedicated processor subsystem to handle safety management for automotive applications. In at least one embodiment, a safety cluster engine may include, without limitation, two or more processor cores, a tightly coupled RAM, support peripherals (e.g., timers, an interrupt controller, etc.), and / or routing logic. In a safety mode, two or more cores may operate, in at least one embodiment, in a lockstep mode and function as a single core with comparison logic to detect any differences between their operations. In at least one embodiment, processor(s) 1010 may further include a real-time camera engine that may include, without limitation, a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, processor(s) 1010 may further include a high-dynamic range signal processor that may include, without limitation, an image signal processor that is a hardware engine that is part of a camera processing pipeline.

[0248] In at least one embodiment, processor(s) 1010 may include a video image compositor that may be a processing block (e.g., implemented on a microprocessor) that implements video post-processing functions needed by a video playback application to produce a final image for a player window. In at least one embodiment, a video image compositor may perform lens distortion correction on wide-view camera(s) 1070, surround camera(s) 1074, and / or on in-cabin monitoring camera sensor(s). In at least one embodiment, in-cabin monitoring camera sensor(s) are preferably monitored by a neural network running on another instance of SoC 1004, configured to identify in cabin events and respond accordingly. In at least one embodiment, an in-cabin system may perform, without limitation, lip reading to activate cellular service and place a phone call, dictate emails, change a vehicle’s destination, activate or change a vehicle’s infotainment system and settings, or provide voice-activated web surfing. In at least one embodiment, certain functions are available to a driver when a vehicle is operating in an autonomous mode and are disabled otherwise.

[0249] In at least one embodiment, a video image compositor may include enhanced temporal noise reduction for both spatial and temporal noise reduction. For example, in at least one embodiment, where motion occurs in a video, noise reduction weights spatial information appropriately, decreasing weights of information provided by adjacent frames. In at least one embodiment, where an image or portion of an image does not include motion, temporal noise reduction performed by video image compositor may use information from a previous image to reduce noise in a current image.

[0250] In at least one embodiment, a video image compositor may also be configured to perform stereo rectification on input stereo lens frames. In at least one embodiment, a video image compositor may further be used for user interface composition when an operating system desktop is in use, and GPU(s) 1008 are not required to continuously render new surfaces. In at least one embodiment, when GPU(s) 1008 are powered on and active doing 3D rendering, a video image compositor may be used to offload GPU(s) 1008 to improve performance and responsiveness. [0251 ] In at least one embodiment, one or more SoC of SoC(s) 1004 may further include a mobile industry processor interface (“MIPI”) camera serial interface for receiving video and input from cameras, a high-speed interface, and / or a video input block that may be used for a camera and related pixel input functions. In at least one embodiment, one or more of SoC(s) 1004 may further include an input / output controller(s) that may be controlled by software and may be used for receiving I / O signals that are uncommitted to a specific role.

[0252] In at least one embodiment, one or more of SoC(s) 1004 may further include a broad range of peripheral interfaces to enable communication with peripherals, audio encoders / decoders (“codecs”), power management, and / or other devices. In at least one embodiment, SoC(s) 1004 may be used to process data from cameras (e.g., connected over Gigabit Multimedia Serial Link and Ethernet channels), sensors (e.g., LIDAR sensor(s) 1064, RADAR sensor(s) 1060, etc. that may be connected over Ethernet channels), data from bus 1002 (e.g., speed of vehicle 1000, steering wheel position, etc.), data from GNSS sensor(s) 1058 (e.g., connected over a Ethernet bus or a CAN bus), etc. In at least one embodiment, one or more SoC of SoC(s) 1004 may further include dedicated high-performance mass storage controllers that may include their own DMA engines, and that may be used to free CPU(s) 1006 from routine data management tasks.

[0253] In at least one embodiment, SoC(s) 1004 may be an end-to-end platform with a flexible architecture that spans automation Levels 3-5, thereby providing a comprehensive functional safety architecture that leverages and makes efficient use of computer vision and ADAS techniques for diversity and redundancy, and provides a platform for a flexible, reliable driving software stack, along with deep learning tools. In at least one embodiment, SoC(s) 1004 may be faster, more reliable, and even more energy-efficient and space-efficient than conventional systems. For example, in at least one embodiment, accelerator(s) 1014, when combined with CPU(s) 1006, GPU(s) 1008, and data store(s) 1016, may provide for a fast, efficient platform for Level 3-5 autonomous vehicles.

[0254] In at least one embodiment, computer vision algorithms may be executed on CPUs, which may be configured using a high-level programming language, such as C, to execute a wide variety of processing algorithms across a wide variety of visual data. However, in at least one embodiment, CPUs are oftentimes unable to meet performance requirements of many computer vision applications, such as those related to execution time and power consumption, for example. In at least one embodiment, many CPUs are unable to execute complex object detection algorithms in real-time, which is used in in-vehicle ADAS applications and in practical Level 3-5 autonomous vehicles.

[0255] Embodiments described herein allow for multiple neural networks to be performed simultaneously and / or sequentially, and for results to be combined together to enable Level 3-5 autonomous driving functionality. For example, in at least one embodiment, a CNN executing on a DLA or a discrete GPU (e.g., GPU(s) 1020) may include text and word recognition, allowing reading and understanding of traffic signs, including signs for which a neural network has not been specifically trained. In at least one embodiment, a DLA may further include a neural network that is able to identify, interpret, and provide semantic understanding of a sign, and to pass that semantic understanding to path planning modules running on a CPU Complex.

[0256] In at least one embodiment, multiple neural networks may be run simultaneously, as for Level 3, 4, or 5 driving. For example, in at least one embodiment, a warning sign stating “Caution: flashing lights indicate icy conditions,” along with an electric light, may be independently or collectively interpreted by several neural networks. In at least one embodiment, such warning sign itself may be identified as a traffic sign by a first deployed neural network (e.g., a neural network that has been trained), text “flashing lights indicate icy conditions” may be interpreted by a second deployed neural network, which informs a vehicle’s path planning software (preferably executing on a CPU Complex) that when flashing lights are detected, icy conditions exist. In at least one embodiment, a flashing light may be identified by operating a third deployed neural network over multiple frames, informing a vehicle’s path-planning software of a presence (or an absence) of flashing lights. In at least one embodiment, all three neural networks may run simultaneously, such as within a DLA and / or on GPU(s) 1008.

[0257] In at least one embodiment, a CNN for facial recognition and vehicle owner identification may use data from camera sensors to identify presence of an authorized driver and / or owner of vehicle 1000. In at least one embodiment, an always-on sensor processing engine may be used to unlock a vehicle when an owner approaches a driver door and turns on lights, and, in a security mode, to disable such vehicle when an owner leaves such vehicle. In this way, SoC(s) 1004 provide for security against theft and / or carjacking.

[0258] In at least one embodiment, a CNN for emergency vehicle detection and identification may use data from microphones 1096 to detect and identify emergency vehicle sirens. In at least one embodiment, SoC(s) 1004 use a CNN for classifying environmental and urban sounds, as well as classifying visual data. In at least one embodiment, a CNN running on a DLA is trained to identify a relative closing speed of an emergency vehicle (e.g., by using a Doppler effect). In at least one embodiment, a CNN may also be trained to identify emergency vehicles specific to a local area in which a vehicle is operating, as identified by GNSS sensor(s) 1058. In at least one embodiment, when operating in Europe, a CNN will seek to detect European sirens, and when in North America, a CNN will seek to identify only North American sirens. In at least one embodiment, once an emergency vehicle is detected, a control program may be used to execute an emergency vehicle safety routine, slowing a vehicle, pulling over to a side of a road, parking a vehicle, and / or idling a vehicle, with assistance of ultrasonic sensor(s) 1062, until emergency vehicles pass. (0259] In at least one embodiment, vehicle 1000 may include CPU(s) 1018 (e.g., discrete CPU(s), or dCPU(s)), that may be coupled to SoC(s) 1004 via a high-speed interconnect (e.g., PCIe). In at least one embodiment, CPU(s) 1018 may include an X86 processor, for example. CPU(s) 1018 may be used to perform any of a variety of functions, including arbitrating potentially inconsistent results between ADAS sensors and SoC(s) 1004 , and / or monitoring status and health of controller(s) 1036 and / or an infotainment system on a chip (“infotainment SoC”) 1030, for example.

[0260] In at least one embodiment, vehicle 1000 may include GPU(s) 1020 (e.g., discrete GPU(s), or dGPU(s)), that may be coupled to SoC(s) 1004 via a high-speed interconnect (e.g., NVIDIA’s NVLINK channel). In at least one embodiment, GPU(s) 1020 may provide additional artificial intelligence functionality, such as by executing redundant and / or different neural networks, and may be used to train and / or update neural networks based at least in part on input (e.g., sensor data) from sensors of a vehicle 1000.

[0261] In at least one embodiment, vehicle 1000 may further include network interface 1024 which may include, without limitation, wireless antenna(s) 1026 (e.g., one or more wireless antennas for different communication protocols, such as a cellular antenna, a Bluetooth antenna, etc.). In at least one embodiment, network interface 1024 may be used to enable wireless connectivity to Internet cloud services (e.g., with server(s) and / or other network devices), with other vehicles, and / or with computing devices (e.g., client devices of passengers). In at least one embodiment, to communicate with other vehicles, a direct link may be established between vehicle 1000 and another vehicle and / or an indirect link may be established (e.g., across networks and over Internet). In at least one embodiment, direct links may be provided using a vehicle-to-vehicle communication link. In at least one embodiment, a vehicle-to-vehicle communication link may provide vehicle 1000 information about vehicles in proximity to vehicle 1000 (e.g., vehicles in front of, on a side of, and / or behind vehicle 1000). In at least one embodiment, such aforementioned functionality may be part of a cooperative adaptive cruise control functionality of vehicle 1000.

[0262] In at least one embodiment, network interface 1024 may include an SoC that provides modulation and demodulation functionality and enables controller(s) 1036 to communicate over wireless networks. In at least one embodiment, network interface 1024 may include a radio frequency front-end for up-conversion from baseband to radio frequency, and down conversion from radio frequency to baseband. In at least one embodiment, frequency conversions may be performed in any technically feasible fashion. For example, frequency conversions could be performed through well-known processes, and / or using super-heterodyne processes. In at least one embodiment, radio frequency front end functionality may be provided by a separate chip. In at least one embodiment, network interfaces may include wireless functionality for communicating over LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, WiFi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0263] In at least one embodiment, vehicle 1000 may further include data store(s) 1028 which may include, without limitation, off-chip (e.g., off SoC(s) 1004) storage. In at least one embodiment, data store(s) 1028 may include, without limitation, one or more storage elements including RAM, SRAM, dynamic random-access memory (“DRAM”), video random-access memory (“VRAM’), flash memory, hard disks, and / or other components and / or devices that may store at least one bit of data.

[0264] In at least one embodiment, vehicle 1000 may further include GNSS sensor(s) 1058 (e.g., GPS and / or assisted GPS sensors), to assist in mapping, perception, occupancy grid generation, and / or path planning functions. In at least one embodiment, any number of GNSS sensor(s) 1058 may be used, including, for example and without limitation, a GPS using a Universal Serial Bus (“USB”) connector with an Ethernet-to-Serial (e.g., RS-232) bridge.

[0265] In at least one embodiment, vehicle 1000 may further include RADAR sensor(s) 1060. In at least one embodiment, RADAR sensor(s) 1060 may be used by vehicle 1000 for long-range vehicle detection, even in darkness and / or severe weather conditions. In at least one embodiment, RADAR functional safety levels may be ASIL B. In at least one embodiment, RADAR sensor(s) 1060 may use a CAN bus and / or bus 1002 (e.g., to transmit data generated by RADAR sensor(s) 1060) for control and to access object tracking data, with access to Ethernet channels to access raw data in some examples. In at least one embodiment, a wide variety of RADAR sensor types may be used. For example, and without limitation, RADAR sensor(s) 1060 may be suitable for front, rear, and side RADAR use. In at least one embodiment, one or more sensor of RADAR sensors(s) 1060 is a Pulse Doppler RADAR sensor.

[0266] In at least one embodiment, RADAR sensor(s) 1060 may include different configurations, such as long-range with narrow field of view, short-range with wide field of view, short-range side coverage, etc. In at least one embodiment, long-range RADAR may be used for adaptive cruise control functionality. In at least one embodiment, long-range RADAR systems may provide a broad field of view realized by two or more independent scans, such as within a 250 m (meter) range. In at least one embodiment, RADAR sensor(s) 1060 may help in distinguishing between static and moving objects, and may be used by ADAS system 1038 for emergency brake assist and forward collision warning. In at least one embodiment, sensors 1060(s) included in a long-range RADAR system may include, without limitation, monostatic multimodal RADAR with multiple (e.g., six or more) fixed RADAR antennae and a high-speed CAN and FlexRay interface. In at least one embodiment, with six antennae, a central four antennae may create a focused beam pattern, designed to record vehicle’s 1000 surroundings at higher speeds with minimal interference from traffic in adjacent lanes. In at least one embodiment, another two antennae may expand field of view, making it possible to quickly detect vehicles entering or leaving a lane of vehicle 1000.

[0267] In at least one embodiment, mid-range RADAR systems may include, as an example, a range of up to 160 m (front) or 80 m (rear), and a field of view of up to 42 degrees (front) or 150 degrees (rear). In at least one embodiment, short-range RADAR systems may include, without limitation, any number of RADAR sensor(s) 1060 designed to be installed at both ends of a rear bumper. When installed at both ends of a rear bumper, in at least one embodiment, a RADAR sensor system may create two beams that constantly monitor blind spots in a rear direction and next to a vehicle. In at least one embodiment, short-range RADAR systems may be used in ADAS system 1038 for blind spot detection and / or lane change assist.

[0268] In at least one embodiment, vehicle 1000 may further include ultrasonic sensor(s) 1062. In at least one embodiment, ultrasonic sensor(s) 1062, which may be positioned at a front, a back, and / or side location of vehicle 1000, may be used for parking assist and / or to create and update an occupancy grid. In at least one embodiment, a wide variety of ultrasonic sensor(s) 1062 may be used, and different ultrasonic sensor(s) 1062 may be used for different ranges of detection (e.g., 2.5 m, 4 m). In at least one embodiment, ultrasonic sensor(s) 1062 may operate at functional safety levels of ASIL B.

[0269] In at least one embodiment, vehicle 1000 may include LIDAR sensor(s) 1064. In at least one embodiment, LIDAR sensor(s) 1064 may be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, LIDAR sensor(s) 1064 may operate at functional safety level ASIL B. In at least one embodiment, vehicle 1000 may include multiple LIDAR sensors 1064 (e.g., two, four, six, etc.) that may use an Ethernet channel (e.g., to provide data to a Gigabit Ethernet switch).

[0270] In at least one embodiment, LIDAR sensor(s) 1064 may be capable of providing a list of objects and their distances for a 360-degree field of view. In at least one embodiment, commercially available LIDAR sensor(s) 1064 may have an advertised range of approximately 100 m, with an accuracy of 2 cm to 3 cm, and with support for a 100 Mbps Ethernet connection, for example. In at least one embodiment, one or more non-protruding LIDAR sensors may be used. In such an embodiment, LIDAR sensor(s) 1064 may include a small device that may be embedded into a front, a rear, a side, and / or a corner location of vehicle 1000. In at least one embodiment, LIDAR sensor(s) 1064, in such an embodiment, may provide up to a 120-degree horizontal and 35-degree vertical field-of-view, with a 200 m range even for low-reflectivity objects. In at least one embodiment, front-mounted LIDAR sensor(s) 1064 may be configured for a horizontal field of view between 45 degrees and 135 degrees. [0271 ] In at least one embodiment, LIDAR technologies, such as 3D flash LIDAR, may also be used. In at least one embodiment, 3D flash LIDAR uses a flash of a laser as a transmission source, to illuminate surroundings of vehicle 1000 up to approximately 200 m. In at least one embodiment, a flash LIDAR unit includes, without limitation, a receptor, which records laser pulse transit time and reflected light on each pixel, which in turn corresponds to a range from vehicle 1000 to objects. In at least one embodiment, flash LIDAR may allow for highly accurate and distortion-free images of surroundings to be generated with every laser flash. In at least one embodiment, four flash LIDAR sensors may be deployed, one at each side of vehicle 1000. In at least one embodiment, 3D flash LIDAR systems include, without limitation, a solid-state 3D staring array LIDAR camera with no moving parts other than a fan (e.g., a non-scanning LIDAR device). In at least one embodiment, flash LIDAR device may use a 5 nanosecond class I (eye safe) laser pulse per frame and may capture reflected laser light as a 3D range point cloud and co-registered intensity data.

[0272] In at least one embodiment, vehicle 1000 may further include IMU sensor(s) 1066. In at least one embodiment, IMU sensor(s) 1066 may be located at a center of a rear axle of vehicle 1000. In at least one embodiment, IMU sensor(s) 1066 may include, for example and without limitation, accelerometer(s), magnetometer(s), gyroscope(s), a magnetic compass, magnetic compasses, and / or other sensor types. In at least one embodiment, such as in six-axis applications, IMU sensor(s) 1066 may include, without limitation, accelerometers and gyroscopes. In at least one embodiment, such as in nine-axis applications, IMU sensor(s) 1066 may include, without limitation, accelerometers, gyroscopes, and magnetometers.

[0273] In at least one embodiment, IMU sensor(s) 1066 may be implemented as a miniature, high performance GPS-Aided Inertial Navigation System (“GPS / INS”) that combines microelectro-mechanical systems (“MEMS”) inertial sensors, a high-sensitivity GPS receiver, and advanced Kalman filtering algorithms to provide estimates of position, velocity, and attitude. In at least one embodiment, IMU sensor(s) 1066 may enable vehicle 1000 to estimate its heading without requiring input from a magnetic sensor by directly observing and correlating changes in velocity from a GPS to IMU sensor(s) 1066. In at least one embodiment, IMU sensor(s) 1066 and GNSS sensor(s) 1058 may be combined in a single integrated unit.

[0274] In at least one embodiment, vehicle 1000 may include microphone(s) 1096 placed in and / or around vehicle 1000. In at least one embodiment, microphone(s) 1096 may be used for emergency vehicle detection and identification, among other things.

[0275] In at least one embodiment, vehicle 1000 may further include any number of camera types, including stereo camera(s) 1068, wide-view camera(s) 1070, infrared camera(s) 1072, surround camera(s) 1074, long-range camera(s) 1098, mid-range camera(s) 1076, and / or other camera types. In at least one embodiment, cameras may be used to capture image data around an entire periphery of vehicle 1000. In at least one embodiment, which types of cameras used depends on vehicle 1000. In at least one embodiment, any combination of camera types may be used to provide necessary coverage around vehicle 1000. In at least one embodiment, a number of cameras deployed may differ depending on embodiment. For example, in at least one embodiment, vehicle 1000 could include six cameras, seven cameras, ten cameras, twelve cameras, or another number of cameras. In at least one embodiment, cameras may support, as an example and without limitation, Gigabit Multimedia Serial Link (“GMSL”) and / or Gigabit Ethernet communications. In at least one embodiment, each camera might be as described with more detail previously herein with respect to FIG. 10A and FIG. 10B.

[0276] In at least one embodiment, vehicle 1000 may further include vibration sensor(s) 1042. In at least one embodiment, vibration sensor(s) 1042 may measure vibrations of components of vehicle 1000, such as axle(s). For example, in at least one embodiment, changes in vibrations may indicate a change in road surfaces. In at least one embodiment, when two or more vibration sensors 1042 are used, differences between vibrations may be used to determine friction or slippage of road surface (e.g., when a difference in vibration is between a power-driven axle and a freely rotating axle).

[0277] In at least one embodiment, vehicle 1000 may include ADAS system 1038. In at least one embodiment, ADAS system 1038 may include, without limitation, an SoC, in some examples. In at least one embodiment, ADAS system 1038 may include, without limitation, any number and combination of an autonomous / adaptive / automatic cruise control (“ACC”) system, a cooperative adaptive cruise control (“CACC”) system, a forward crash warning (“FCW”) system, an automatic emergency braking (“AEB”) system, a lane departure warning (“LDW)” system, a lane keep assist (“LKA”) system, a blind spot warning (“BSW”) system, a rear crosstraffic warning (“RCTW”) system, a collision warning (“CW”) system, a lane centering (“LC”) system, and / or other systems, features, and / or functionality.

[0278] In at least one embodiment, ACC system may use RADAR sensor(s) 1060, LIDAR sensor(s) 1064, and / or any number of camera(s). In at least one embodiment, ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, a longitudinal ACC system monitors and controls distance to another vehicle immediately ahead of vehicle 1000 and automatically adjusts speed of vehicle 1000 to maintain a safe distance from vehicles ahead. In at least one embodiment, a lateral ACC system performs distance keeping, and advises vehicle 1000 to change lanes when necessary. In at least one embodiment, a lateral ACC is related to other ADAS applications, such as LC and CW.

[0279] In at least one embodiment, a CACC system uses information from other vehicles that may be received via network interface 1024 and / or wireless antenna(s) 1026 from other vehicles via a wireless link, or indirectly, over a network connection (e.g., over Internet). In at least one embodiment, direct links may be provided by a vehicle-to-vehicle (“V2V”) communication link, while indirect links may be provided by an infrastructure-to-vehicle (“I2V”) communication link. In general, V2V communication provides information about immediately preceding vehicles (e.g., vehicles immediately ahead of and in same lane as vehicle 1000), while I2V communication provides information about traffic further ahead. In at least one embodiment, a CACC system may include either or both I2V and V2V information sources. In at least one embodiment, given information of vehicles ahead of vehicle 1000, a CACC system may be more reliable and it has potential to improve traffic flow smoothness and reduce congestion on road.

[0280] In at least one embodiment, an FCW system is designed to alert a driver to a hazard, so that such driver may take corrective action. In at least one embodiment, an FCW system uses a front-facing camera and / or RADAR sensor(s) 1060, coupled to a dedicated processor, digital signal processor (“DSP”), FPGA, and / or ASIC, that is electrically coupled to provide driver feedback, such as a display, speaker, and / or vibrating component. In at least one embodiment, an FCW system may provide a warning, such as in form of a sound, visual warning, vibration and / or a quick brake pulse. [0281 ] In at least one embodiment, an AEB system detects an impending forward collision with another vehicle or other object, and may automatically apply brakes if a driver does not take corrective action within a specified time or distance parameter. In at least one embodiment, AEB system may use front-facing camera(s) and / or RADAR sensor(s) 1060, coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when an AEB system detects a hazard, it will typically first alert a driver to take corrective action to avoid collision and, if that driver does not take corrective action, that AEB system may automatically apply brakes m an effort to prevent, or at least mitigate, an impact of a predicted collision. In at least one embodiment, an AEB system may include techniques such as dynamic brake support and / or crash imminent braking.

[0282] In at least one embodiment, an LDW system provides visual, audible, and / or tactile warnings, such as steering wheel or seat vibrations, to alert driver when vehicle 1000 crosses lane markings. In at least one embodiment, an LDW system does not activate when a driver indicates an intentional lane departure, such as by activating a turn signal. In at least one embodiment, an LDW system may use front-side facing cameras, coupled to a dedicated processor, DSP, FPGA, and / or ASIC, that is electrically coupled to provide driver feedback, such as a display, speaker, and / or vibrating component. In at least one embodiment, an LKA system is a variation of an LDW system. In at least one embodiment, an LKA system provides steering input or braking to correct vehicle 1000 if vehicle 1000 starts to exit its lane. (0283] In at least one embodiment, a BSW system detects and warns a driver of vehicles in an automobile’s blind spot. In at least one embodiment, a BSW system may provide a visual, audible, and / or tactile alert to indicate that merging or changing lanes is unsafe. In at least one embodiment, a BSW system may provide an additional warning when a driver uses a turn signal. In at least one embodiment, a BSW system may use rear-side facing camera(s) and / or RADAR sensor(s) 1060, coupled to a dedicated processor, DSP, FPGA, and / or ASIC, that is electrically coupled to driver feedback, such as a display, speaker, and / or vibrating component.

[0284] In at least one embodiment, an RCTW system may provide visual, audible, and / or tactile notification when an object is detected outside a rear-camera range when vehicle 1000 is backing up. In at least one embodiment, an RCTW system includes an AEB system to ensure that vehicle brakes are applied to avoid a crash. In at least one embodiment, an RCTW system may use one or more rear-facing RADAR sensor(s) 1060, coupled to a dedicated processor, DSP, FPGA, and / or ASIC, that is electrically coupled to provide driver feedback, such as a display, speaker, and / or vibrating component.

[0285] In at least one embodiment, conventional ADAS systems may be prone to false positive results which may be annoying and distracting to a driver, but typically are not catastrophic, because conventional ADAS systems alert a driver and allow that driver to decide whether a safety condition truly exists and act accordingly. In at least one embodiment, vehicle 1000 itself decides, in case of conflicting results, whether to heed result from a primary computer or a secondary computer (e.g., a first controller or a second controller of controllers 1036). For example, in at least one embodiment, ADAS system 1038 may be a backup and / or secondary computer for providing perception information to a backup computer rationality module. In at least one embodiment, a backup computer rationality monitor may run redundant diverse software on hardware components to detect faults in perception and dynamic driving tasks. In at least one embodiment, outputs from ADAS system 1038 may be provided to a supervisory MCU. In at least one embodiment, if outputs from a primary computer and outputs from a secondary computer conflict, a supervisory MCU determines how to reconcile conflict to ensure safe operation.

[0286] In at least one embodiment, a primary computer may be configured to provide a supervisory MCU with a confidence score, indicating that primary computer’s confidence in a chosen result. In at least one embodiment, if that confidence score exceeds a threshold, that supervisory MCU may follow that primary computer’s direction, regardless of whether that secondary computer provides a conflicting or inconsistent result. In at least one embodiment, where a confidence score does not meet a threshold, and where primary and secondary computers indicate different results (e.g., a conflict), a supervisory MCU may arbitrate between computers to determine an appropriate outcome.

[0287] In at least one embodiment, a supervisory MCU may be configured to run a neural network(s) that is trained and configured to determine, based at least in part on outputs from a primary computer and outputs from a secondary computer, conditions under which that secondary computer provides false alarms. In at least one embodiment, neural network(s) in a supervisory MCU may learn when a secondary computer’s output may be trusted, and when it cannot. For example, in at least one embodiment, when that secondary computer is a RADAR-based FCW system, a neural network(s) in that supervisory MCU may learn when an FCW system is identifying metallic objects that are not, in fact, hazards, such as a drainage grate or manhole cover that triggers an alarm. In at least one embodiment, when a secondary computer is a camera-based LDW system, a neural network in a supervisory MCU may learn to override LDW when bicyclists or pedestrians are present and a lane departure is, in fact, a safest maneuver. In at least one embodiment, a supervisory MCU may include at least one of a DLA or a GPU suitable for running neural network(s) with associated memory. In at least one embodiment, a supervisory MCU may comprise and / or be included as a component of SoC(s) 1004.

[0288] In at least one embodiment, ADAS system 1038 may include a secondary computer that performs ADAS functionality using traditional rules of computer vision. In at least one embodiment, that secondary computer may use classic computer vision rules (if-then), and presence of a neural network(s) in a supervisory MCU may improve reliability, safety and performance. For example, in at least one embodiment, diverse implementation and intentional non-identity makes an overall system more fault-tolerant, especially to faults caused by software (or software-hardware interface) functionality. For example, in at least one embodiment, if there is a software bug or error in software running on a primary computer, and non-identical software code running on a secondary computer provides a consistent overall result, then a supervisory MCU may have greater confidence that an overall result is correct, and a bug in software or hardware on that primary computer is not causing a material error.

[0289] In at least one embodiment, an output of ADAS system 1038 may be fed into a primary computer’s perception block and / or a primary computer’s dynamic driving task block. For example, in at least one embodiment, if ADAS system 1038 indicates a forward crash warning due to an object immediately ahead, a perception block may use this information when identifying objects. In at least one embodiment, a secondary computer may have its own neural network that is trained and thus reduces a risk of false positives, as described herein.

[0290] In at least one embodiment, vehicle 1000 may further include infotainment SoC 1030 (e.g., an in-vehicle infotainment system (IVI)). Although illustrated and described as an SoC, infotainment system SoC 1030, in at least one embodiment, may not be an SoC, and may include, without limitation, two or more discrete components. In at least one embodiment, infotainment SoC 1030 may include, without limitation, a combination of hardware and software that may be used to provide audio (e.g., music, a personal digital assistant, navigational instructions, news, radio, etc.), video (e.g., TV, movies, streaming, etc.), phone (e.g., hands-free calling), network connectivity (e.g., LTE, WiFi, etc.), and / or information services (e.g., navigation systems, rear-parking assistance, a radio data system, vehicle related information such as fuel level, total distance covered, brake fuel level, oil level, door open / close, air filter information, etc.) to vehicle 1000. For example, infotainment SoC 1030 could include radios, disk players, navigation systems, video players, USB and Bluetooth connectivity, carputers, in-car entertainment, WiFi, steering wheel audio controls, hands free voice control, a heads-up display (“HUD”), HMI display 1034, a telematics device, a control panel (e.g., for controlling and / or interacting with various components, features, and / or systems), and / or other components. In at least one embodiment, infotainment SoC 1030 may further be used to provide information (e.g., visual and / or audible) to user(s) of vehicle 1000, such as information from ADAS system 1038, autonomous driving information such as planned vehicle maneuvers, trajectories, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.), and / or other information.

[0291] In at least one embodiment, infotainment SoC 1030 may include any amount and type of GPU functionality. In at least one embodiment, infotainment SoC 1030 may communicate over bus 1002 with other devices, systems, and / or components of vehicle 1000. In at least one embodiment, infotainment SoC 1030 may be coupled to a supervisory MCU such that a GPU of an infotainment system may perform some self-driving functions in event that primary controller(s) 1036 (e.g., primary and / or backup computers of vehicle 1000) fail. In at least one embodiment, infotainment SoC 1030 may put vehicle 1000 into a chauffeur to safe stop mode, as described herein. |0292] In at least one embodiment, vehicle 1000 may further include instrument cluster 1032 (e.g., a digital dash, an electronic instrument cluster, a digital instrument panel, etc.). In at least one embodiment, instrument cluster 1032 may include, without limitation, a controller and / or supercomputer (e.g., a discrete controller or supercomputer). In at least one embodiment, instrument cluster 1032 may include, without limitation, any number and combination of a set of instrumentation such as a speedometer, fuel level, oil pressure, tachometer, odometer, turn indicators, gearshift position indicator, seat belt warning light(s), parking-brake warning light(s), engine-malfunction light(s), supplemental restraint system (e.g., airbag) information, lighting controls, safety system controls, navigation information, etc. In some examples, information may be displayed and / or shared among infotainment SoC 1030 and instrument cluster 1032. In at least one embodiment, instrument cluster 1032 may be included as part of infotainment SoC 1030, or vice versa.

[0293] Inference and / or training logic 115 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 115 are provided herein in conjunction with FIGS. 1A and / or IB. In at least one embodiment, inference and / or training logic 115 may be used in system FIG. 10C for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0294] FIG. 10D is a diagram of a system 1078 for communication between cloud-based server(s) and autonomous vehicle 1000 of FIG. 10A, according to at least one embodiment. In at least one embodiment, system 1078 may include, without limitation, server(s) 1078, network(s) 1090, and any number and type of vehicles, including vehicle 1000. In at least one embodiment, server(s) 1078 may include, without limitation, a plurality of GPUs 1084(A)-1084(H) (collectively referred to herein as GPUs 1084), PCIe switches 1082(A)-1082(D) (collectively referred to herein as PCIe switches 1082), and / or CPUs 1080(A)-1080(B) (collectively referred to herein as CPUs 1080). In at least one embodiment, GPUs 1084, CPUs 1080, and PCIe switches 1082 may be interconnected with high-speed interconnects such as, for example and without limitation, NVLink interfaces 1088 developed by NVIDIA and / or PCIe connections 1086. In at least one embodiment, GPUs 1084 are connected via an NVLink and / or NVSwitch SoC and GPUs 1084 and PCIe switches 1082 are connected via PCIe interconnects. Although eight GPUs 1084, two CPUs 1080, and four PCIe switches 1082 are illustrated, this is not intended to be limiting. In at least one embodiment, each of server(s) 1078 may include, without limitation, any number of GPUs 1084, CPUs 1080, and / or PCIe switches 1082, in any combination. For example, in at least one embodiment, server(s) 1078 could each include eight, sixteen, thirty-two, and / or more GPUs 1084.

[0295] In at least one embodiment, server(s) 1078 may receive, over network(s) 1090 and from vehicles, image data representative of images showing unexpected or changed road conditions, such as recently commenced road-work. In at least one embodiment, server(s) 1078 may transmit, over network(s) 1090 and to vehicles, neural networks 1092, updated or otherwise, and / or map information 1094, including, without limitation, information regarding traffic and road conditions. In at least one embodiment, updates to map information 1094 may include, without limitation, updates for HD map 1022, such as information regarding construction sites, potholes, detours, flooding, and / or other obstructions. In at least one embodiment, neural networks 1092, and / or map information 1094 may have resulted from new training and / or experiences represented in data received from any number of vehicles in an environment, and / or based at least in part on training performed at a data center (e.g., using server(s) 1078 and / or other servers).

[0296] In at least one embodiment, server(s) 1078 may be used to train machine learning models (e.g., neural networks) based at least in part on training data. In at least one embodiment, training data may be generated by vehicles, and / or may be generated in a simulation (e.g., using a game engine). In at least one embodiment, any amount of training data is tagged (e.g., where associated neural network benefits from supervised learning) and / or undergoes other preprocessing. In at least one embodiment, any amount of training data is not tagged and / or pre-processed (e.g., where associated neural network does not require supervised learning). In at least one embodiment, once machine learning models are trained, machine learning models may be used by vehicles (e.g., transmitted to vehicles over network(s) 1090), and / or machine learning models may be used by server(s) 1078 to remotely monitor vehicles. [02971 In at least one embodiment, server(s) 1078 may receive data from vehicles and apply data to up-to-date real-time neural networks for real-time intelligent inferencing. In at least one embodiment, server(s) 1078 may include deep-learning supercomputers and / or dedicated AI computers powered by GPU(s) 1084, such as a DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, server(s) 1078 may include deep learning infrastructure that uses CPU-powered data centers.

[0298] In at least one embodiment, deep-learning infrastructure of server(s) 1078 may be capable of fast, real-time inferencing, and may use that capability to evaluate and verify health of processors, software, and / or associated hardware in vehicle 1000. For example, in at least one embodiment, deep-learning infrastructure may receive periodic updates from vehicle 1000, such as a sequence of images and / or objects that vehicle 1000 has located in that sequence of images (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, deep-learning infrastructure may run its own neural network to identify objects and compare them with objects identified by vehicle 1000 and, if results do not match and deep-learning infrastructure concludes that AI in vehicle 1000 is malfunctioning, then server(s) 1078 may transmit a signal to vehicle 1000 instructing a fail-safe computer of vehicle 1000 to assume control, notify passengers, and complete a safe parking maneuver.

[0299] In at least one embodiment, server(s) 1078 may include GPU(s) 1084 and one or more programmable inference accelerators (e.g., NVIDIA’s TensorRT 3 devices). In at least one embodiment, a combination of GPU-powered servers and inference acceleration may make realtime responsiveness possible. In at least one embodiment, such as where performance is less critical, servers powered by CPUs, FPGAs, and other processors may be used for inferencing. In at least one embodiment, hardware structure(s) 115 are used to perform one or more embodiments. Details regarding hardware structure(x) 115 are provided herein in conjunction with FIGS. 1A and / or IB. COMPUTER SYSTEMS

[0300] FIG. 11 is a block diagram illustrating an exemplary computer system, which may be a system with interconnected devices and components, a system-on-a-chip (SOC) or some combination thereof formed with a processor that may include execution units to execute an instruction, according to at least one embodiment. In at least one embodiment, a computer system 1100 may include, without limitation, a component, such as a processor 1102 to employ execution units including logic to perform algorithms for process data, in accordance with present disclosure, such as in embodiment described herein. In at least one embodiment, computer system 1100 may include processors, such as PENTIUM® Processor family, Xeon™, Itanium®, XScale™ and / or StrongARM™, Intel® Core™, or Intel® Nervana™ microprocessors available from Intel Corporation of Santa Clara, California, although other systems (including PCs having other microprocessors, engineering workstations, set-top boxes and like) may also be used. In at least one embodiment, computer system 1100 may execute a version of WINDOWS operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (UNIX and Linux, for example), embedded software, and / or graphical user interfaces, may also be used. [0301 ] Embodiments may be used in other devices such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants (“PDAs”), and handheld PCs. In at least one embodiment, embedded applications may include a microcontroller, a DSP, system on a chip, network computers (“NetPCs”), set-top boxes, network hubs, wide area network (“WAN”) switches, or any other system that may perform one or more instructions in accordance with at least one embodiment.

[0302] In at least one embodiment, computer system 1100 may include, without limitation, processor 1102 that may include, without limitation, one or more execution units 1108 to perform machine learning model training and / or inferencing according to techniques described herein. In at least one embodiment, computer system 1100 is a single processor desktop or server system, but in another embodiment, computer system 1100 may be a multiprocessor system. In at least one embodiment, processor 1102 may include, without limitation, a complex instruction set computer (“CISC”) microprocessor, a reduced instruction set computing (“RISC”) microprocessor, a very long instruction word (“VLIW”) microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as a digital signal processor, for example. In at least one embodiment, processor 1102 may be coupled to a processor bus 1110 that may transmit data signals between processor 1102 and other components in computer system 1100.

[0303] In at least one embodiment, processor 1102 may include, without limitation, a Level 1 (“LI”) internal cache memory (“cache”) 1104. In at least one embodiment, processor 1102 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory may reside external to processor 1102. Other embodiments may also include a combination of both internal and external caches depending on particular implementation and needs. In at least one embodiment, a register file 1106 may store different types of data in various registers including, without limitation, integer registers, floating point registers, status registers, and an instruction pointer register.

[0304] In at least one embodiment, execution unit 1108, including, without limitation, logic to perform integer and floating point operations, also resides in processor 1102. In at least one embodiment, processor 1102 may also include a microcode (“ucode”) read only memory (“ROM”) that stores microcode for certain macro instructions. In at least one embodiment, execution unit 1108 may include logic to handle a packed instruction set 1109. In at least one embodiment, by including packed instruction set 1109 in an instruction set of a general-purpose processor, along with associated circuitry to execute instructions, operations used by many multimedia applications may be performed using packed data in processor 1102. In at least one embodiment, many multimedia applications may be accelerated and executed more efficiently by using a full width of a processor’s data bus for performing operations on packed data, which may eliminate a need to transfer smaller units of data across that processor’s data bus to perform one or more operations one data element at a time.

[0305] In at least one embodiment, execution unit 1108 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, computer system 1100 may include, without limitation, a memory 1120. In at least one embodiment, memory 1120 may be a Dynamic Random Access Memory (“DRAM”) device, a Static Random Access Memory (“SRAM”) device, a flash memory device, or another memory device. In at least one embodiment, memory 1120 may store instruction(s) 1119 and / or data 1121 represented by data signals that may be executed by processor 1102.

[0306] In at least one embodiment, a system logic chip may be coupled to processor bus 1110 and memory 1120. In at least one embodiment, a system logic chip may include, without limitation, a memory controller hub (“MCH”) 1116, and processor 1102 may communicate with MCH 1116 via processor bus 1110. In at least one embodiment, MCH 1116 may provide a high bandwidth memory path 1118 to memory 1120 for instruction and data storage and for storage of graphics commands, data and textures. In at least one embodiment, MCH 1116 may direct data signals between processor 1102, memory 1120, and other components in computer system 1100 and to bridge data signals between processor bus 1110, memory 1120, and a system I / O interface 1122. In at least one embodiment, a system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, MCH 1116 may be coupled to memory 1120 through high bandwidth memory path 1118 and a graphics / video card 1112 may be coupled to MCH 1116 through an Accelerated Graphics Port (“AGP”) interconnect 1114.

[0307] In at least one embodiment, computer system 1100 may use system I / O interface 1122 as a proprietary hub interface bus to couple MCH 1116 to an I / O controller hub (“ICH”) 1130. In at least one embodiment, ICH 1130 may provide direct connections to some I / O devices via a local I / O bus. In at least one embodiment, a local I / O bus may include, without limitation, a high-speed I / O bus for connecting peripherals to memory 1120, a chipset, and processor 1102. Examples may include, without limitation, an audio controller 1129, a firmware hub (“flash BIOS”) 1128, a wireless transceiver 1126, a data storage 1124, a legacy I / O controller 1123 containing user input and keyboard interfaces 1125, a serial expansion port 1127, such as a USB port, and a network controller 1134. In at least one embodiment, data storage 1124 may comprise a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device. [030S] In at least one embodiment, FIG. 11 illustrates a system, which includes interconnected hardware devices or “chips”, whereas in other embodiments, FIG. 11 may illustrate an exemplary SoC. In at least one embodiment, devices illustrated in FIG. 11 may be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe) or some combination thereof. In at least one embodiment, one or more components of computer system 1100 are interconnected using compute express link (CXL) interconnects.

[0309] Inference and / or training logic 115 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 115 are provided herein in conjunction with FIGS. IA and / or IB. In at least one embodiment, inference and / or training logic 115 may be used in system FIG. 11 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0310] FIG. 12 is a block diagram illustrating an electronic device 1200 for utilizing a processor 1210, according to at least one embodiment. In at least one embodiment, electronic device 1200 may be, for example and without limitation, a notebook, a tower server, a rack server, a blade server, a laptop, a desktop, a tablet, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0311] In at least one embodiment, electronic device 1200 may include, without limitation, processor 1210 communicatively coupled to any suitable number or kind of components, peripherals, modules, or devices. In at least one embodiment, processor 1210 is coupled using a bus or interface, such as a I2C bus, a System Management Bus (“SMBus”), a Low Pin Count (LPC) bus, a Serial Peripheral Interface (“SPI”), a High Definition Audio (“HDA”) bus, a Serial Advance Technology Attachment (“SATA”) bus, a Universal Serial Bus (“USB”) (versions 1, 2, 3, etc.), or a Universal Asynchronous Receiver Transmitter (“UART”) bus. In at least one embodiment, FIG. 12 illustrates a system, which includes interconnected hardware devices or “chips”, whereas in other embodiments, FIG. 12 may illustrate an exemplary SoC. In at least one embodiment, devices illustrated in FIG. 12 may be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe) or some combination thereof. In at least one embodiment, one or more components of FIG. 12 are interconnected using compute express link (CXL) interconnects.

[0312] In at least one embodiment, FIG 12 may include a display 1224, a touch screen 1225, a touch pad 1230, a Near Field Communications unit (“NFC”) 1245, a sensor hub 1240, a thermal sensor 1246, an Express Chipset (“EC”) 1235, a Trusted Platform Module (“TPM”) 1238, BlOS / firmware / flash memory (“BIOS, FW Flash”) 1222, a DSP 1260, a drive 1220 such as a Solid State Disk (“SSD”) or a Hard Disk Drive (“HDD”), a wireless local area network unit (“WLAN”) 1250, a Bluetooth unit 1252, a Wireless Wide Area Network unit (“WWAN”) 1256, a Global Positioning System (GPS) unit 1255, a camera (“USB 3.0 camera”) 1254 such as a USB 3.0 camera, and / or a Low Power Double Data Rate (“LPDDR”) memory unit (“LPDDR3”) 1215 implemented in, for example, an LPDDR3 standard. These components may each be implemented in any suitable manner.

[0313] In at least one embodiment, other components may be communicatively coupled to processor 1210 through components described herein. In at least one embodiment, an accelerometer 1241, an ambient light sensor (“ALS”) 1242, a compass 1243, and a gyroscope 1244 may be communicatively coupled to sensor hub 1240. In at least one embodiment, a thermal sensor 1239, a fan 1237, a keyboard 1236, and touch pad 1230 may be communicatively coupled to EC 1235. In at least one embodiment, speakers 1263, headphones 1264, and a microphone (“rmc”) 1265 may be communicatively coupled to an audio unit (“audio codec and class D amp”) 1262, which may in turn be communicatively coupled to DSP 1260. In at least one embodiment, audio unit 1262 may include, for example and without limitation, an audio coder / decoder (“codec”) and a class D amplifier. In at least one embodiment, a SIM card (“SIM’) 1257 may be communicatively coupled to WWAN unit 1256. In at least one embodiment, components such as WLAN unit 1250 and Bluetooth unit 1252, as well as WWAN unit 1256 may be implemented in a Next Generation Form Factor (“NGFF”).

[0314] Inference and / or training logic 115 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 115 are provided herein in conjunction with FIGS. 1A and / or IB. In at least one embodiment, inference and / or training logic 115 may be used in system FIG. 12 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0315] FIG. 13 illustrates a computer system 1300, according to at least one embodiment. In at least one embodiment, computer system 1300 is configured to implement various processes and methods described throughout this disclosure.

[0316] In at least one embodiment, computer system 1300 comprises, without limitation, at least one central processing unit (“CPU”) 1302 that is connected to a communication bus 1310 implemented using any suitable protocol, such as PCI (“Peripheral Component Interconnect”), peripheral component interconnect express (“PCI-Express”), AGP (“Accelerated Graphics Port”), HyperTransport, or any other bus or point-to-point communication protocol(s). In at least one embodiment, computer system 1300 includes, without limitation, a main memory 1304 and control logic (e.g., implemented as hardware, software, or a combination thereof) and data are stored in main memory 1304, which may take form of random access memory (“RAM”). In at least one embodiment, a network interface subsystem (“network interface”) 1322 provides an interface to other computing devices and networks for receiving data from and transmitting data to other systems with computer system 1300.

[0317] In at least one embodiment, computer system 1300, in at least one embodiment, includes, without limitation, input devices 1308, a parallel processing system 1312, and display devices 1306 that can be implemented using a conventional cathode ray tube (“CRT”), a liquid crystal display (“LCD”), a light emitting diode (“LED”) display, a plasma display, or other suitable display technologies. In at least one embodiment, user input is received from input devices 1308 such as keyboard, mouse, touchpad, microphone, etc. In at least one embodiment, each module described herein can be situated on a single semiconductor platform to form a processing system.

[0318] Inference and / or training logic 115 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 115 are provided herein in conjunction with FIGS. 1A and / or IB. In at least one embodiment, inference and / or training logic 115 may be used in system FIG. 13 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0319] FIG. 14 illustrates a computer system 1400, according to at least one embodiment. In at least one embodiment, computer system 1400 includes, without limitation, a computer 1410 and a USB stick 1420. In at least one embodiment, computer 1410 may include, without limitation, any number and type of processor(s) (not shown) and a memory (not shown). In at least one embodiment, computer 1410 includes, without limitation, a server, a cloud instance, a laptop, and a desktop computer. 10320] In at least one embodiment, USB stick 1420 includes, without limitation, a processing unit 1430, a USB interface 1440, and USB interface logic 1450. In at least one embodiment, processing unit 1430 may be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, processing unit 1430 may include, without limitation, any number and type of processing cores (not shown). In at least one embodiment, processing unit 1430 comprises an application specific integrated circuit (“ASIC”) that is optimized to perform any amount and type of operations associated with machine learning. For instance, in at least one embodiment, processing unit 1430 is a tensor processing unit (“TPC”) that is optimized to perform machine learning inference operations. In at least one embodiment, processing unit 1430 is a vision processing unit (“VPU”) that is optimized to perform machine vision and machine learning inference operations.

[0321] In at least one embodiment, USB interface 1440 may be any type of USB connector or USB socket. For instance, in at least one embodiment, USB interface 1440 is a USB 3.0 Type-C socket for data and power. In at least one embodiment, USB interface 1440 is a USB 3.0 Type-A connector. In at least one embodiment, USB interface logic 1450 may include any amount and type of logic that enables processing unit 1430 to interface with devices (e.g., computer 1410) via USB interface 1440.

[0322] Inference and / or training logic 115 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 115 are provided herein in conjunction with FIGS. 1A and / or IB. In at least one embodiment, inference and / or training logic 115 may be used in system FIG. 14 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0323] FIG. 15A illustrates an exemplary architecture in which a plurality of GPUs 1510(1)-1510(N) is communicatively coupled to a plurality of multi-core processors 1505(1 )-1505(M) over high-speed links 1540(1)-1540(N) (e.g., buses, point-to-point interconnects, etc.). In at least one embodiment, high-speed links 1540(1)- 1540(N) support a communication throughput of 4 GB / s, 30 GB / s, 80 GB / s or higher. In at least one embodiment, various interconnect protocols may be used including, but not limited to, PCIe 4.0 or 5.0 and NVLink 2.0. In various figures, “N” and “M” represent positive integers, values of which may be different from figure to figure.

[0324] In addition, and in at least one embodiment, two or more of GPUs 1510 are interconnected over high-speed links 1529(1)-1529(2), which may be implemented using similar or different protocols / links than those used for high-speed links 1540(l)-1540(N). Similarly, two or more of multi-core processors 1505 may be connected over a high-speed link 1528 which may be symmetric multi-processor (SMP) buses operating at 20 GB / s, 30 GB / s, 120 GB / s or higher. Alternatively, all communication between various system components shown in FIG. 15A may be accomplished using similar protocols / links (e.g., over a common interconnection fabric).

[0325] In at least one embodiment, each multi-core processor 1505 is communicatively coupled to a processor memory 1501(l)-1501(M), via memory interconnects 1526(1)-1526(M), respectively, and each GPU 1510(1)-1510(N) is communicatively coupled to GPU memory 1520(1)-1520(N) over GPU memory interconnects 1550(1 )-1550(N), respectively. In at least one embodiment, memory interconnects 1526 and 1550 may utilize similar or different memory access technologies. By way of example, and not limitation, processor memories 1501(1)-1501(M) and GPU memories 1520 may be volatile memories such as dynamic random access memories (DRAMs) (including stacked DRAMs), Graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or High Bandwidth Memory (HBM) and / or may be non-volatile memories such as 3D XPoint or Nano-Ram. In at least one embodiment, some portion of processor memories 1501 may be volatile memory and another portion may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0326] As described herein, although various multi-core processors 1505 and GPUs 1510 may be physically coupled to a particular memory 1501, 1520, respectively, and / or a unified memory architecture may be implemented in which a virtual system address space (also referred to as “effective address” space) is distributed among various physical memories. For example, processor memories 15O1(1)-15O1(M) may each comprise 64 GB of system memory address space and GPU memories 1520(1)-1520(N) may each comprise 32 GB of system memory address space resulting in a total of 256 GB addressable memory when M=2 and N=4. Other values for N and M are possible.

[0327] FIG. 15B illustrates additional details for an interconnection between a multi-core processor 1507 and a graphics acceleration module 1546 in accordance with one exemplary embodiment. In at least one embodiment, graphics acceleration module 1546 may include one or more GPU chips integrated on a line card which is coupled to processor 1507 via high-speed link 1540 (e.g., a PCIe bus, NVLink, etc.). In at least one embodiment, graphics acceleration module 1546 may alternatively be integrated on a package or chip with processor 1507.

[0328] In at least one embodiment, processor 1507 includes a plurality of cores 1560A-1560D, each with a translation lookaside buffer (“TLB”) 1561 A-1561D and one or more caches 1562A-1562D. In at least one embodiment, cores 1560A-1560D may include various other components for executing instructions and processing data that are not illustrated. In at least one embodiment, caches 1562A-1562D may comprise Level 1 (LI) and Level 2 (L2) caches. In addition, one or more shared caches 1556 may be included in caches 1562A-1562D and shared by sets of cores 1560A-1560D. For example, one embodiment of processor 1507 includes 24 cores, each with its own LI cache, twelve shared L2 caches, and twelve shared L3 caches. In this embodiment, one or more L2 and L3 caches are shared by two adjacent cores. In at least one embodiment, processor 1507 and graphics acceleration module 1546 connect with system memory 1514, which may include processor memories 1501(l)-1501(M) of FIG. 15A.

[0329] In at least one embodiment, coherency is maintained for data and instructions stored in various caches 1562A-1562D, 1556 and system memory 1514 via inter-core communication over a coherence bus 1564. In at least one embodiment, for example, each cache may have cache coherency logic / circuitry associated therewith to communicate to over coherence bus 1564 m response to detected reads or writes to particular cache lines. In at least one embodiment, a cache snooping protocol is implemented over coherence bus 1564 to snoop cache accesses.

[0330] In at least one embodiment, a proxy circuit 1525 communicatively couples graphics acceleration module 1546 to coherence bus 1564, allowing graphics acceleration module 1546 to participate in a cache coherence protocol as a peer of cores 1560A-1560D. In particular, m at least one embodiment, an interface 1535 provides connectivity to proxy circuit 1525 over highspeed link 1540 and an interface 1537 connects graphics acceleration module 1546 to high-speed link 1540. [0331 ] In at least one embodiment, an accelerator integration circuit 1536 provides cache management, memory access, context management, and interrupt management services on behalf of a plurality of graphics processing engines 1531 (1)-1531 (N) of graphics acceleration module 1546. In at least one embodiment, graphics processing engines 1531 (1)-1531 (N) may each comprise a separate GPU. In at least one embodiment, graphics processing engines 1531 (1 )-1531 (N) alternatively may comprise different types of graphics processing engines within a GPU, such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and blit engines. In at least one embodiment, graphics acceleration module 1546 may be a GPU with a plurality of graphics processing engines 1531(1)-1531(N) or graphics processing engines 1531 (1)-1531 (N) may be individual GPUs integrated on a common package, line card, or chip.

[0332] In at least one embodiment, accelerator integration circuit 1536 includes a memory management unit (MMU) 1539 for performing various memory management functions such as virtual-to-physical memory translations (also referred to as effective-to-real memory translations) and memory access protocols for accessing system memory 1514. In at least one embodiment, MMU 1539 may also include a translation lookaside buffer (TLB) (not shown) for caching virtual / effective to physical / real address translations. In at least one embodiment, a cache 1538 can store commands and data for efficient access by graphics processing engines 1531 (1 )-1531 (N). In at least one embodiment, data stored in cache 1538 and graphics memories 1533(1)-1533(M) is kept coherent with core caches 1562A-1562D, 1556 and system memory 1514, possibly using a fetch unit 1544. As mentioned, this may be accomplished via proxy circuit 1525 on behalf of cache 1538 and memories 1533( 1 )-1533(M) (e.g., sending updates to cache 1538 related to modifications / accesses of cache lines on processor caches 1562A-1562D, 1556 and receiving updates from cache 1538). [0333 ] In at least one embodiment, a set of registers 1545 store context data for threads executed by graphics processing engines 1531(1)-1531(N) and a context management circuit 1548 manages thread contexts. For example, context management circuit 1548 may perform save and restore operations to save and restore contexts of various threads during contexts switches (e.g., where a first thread is saved and a second thread is stored so that a second thread can be execute by a graphics processing engine). For example, on a context switch, context management circuit 1548 may store current register values to a designated region in memory (e.g., identified by a context pointer). It may then restore register values when returning to a context. In at least one embodiment, an interrupt management circuit 1547 receives and processes interrupts received from system devices.

[0334] In at least one embodiment, virtual / effective addresses from a graphics processing engine 1531 are translated to real / physical addresses in system memory 1514 by MMU 1539. In at least one embodiment, accelerator integration circuit 1536 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 1546 and / or other accelerator devices. In at least one embodiment, graphics accelerator module 1546 may be dedicated to a single application executed on processor 1507 or may be shared between multiple applications. In at least one embodiment, a virtualized graphics execution environment is presented in which resources of graphics processing engines 1531 (1 )-1531 (N) are shared with multiple applications or virtual machines (VMs). In at least one embodiment, resources may be subdivided into “slices” which are allocated to different VMs and / or applications based on processing requirements and priorities associated with VMs and / or applications.

[0335] In at least one embodiment, accelerator integration circuit 1536 performs as a bridge to a system for graphics acceleration module 1546 and provides address translation and system memory cache services. In addition, in at least one embodiment, accelerator integration circuit 1536 may provide virtualization facilities for a host processor to manage virtualization of graphics processing engines 1531(1)-1531(N), interrupts, and memory management.

[0336] In at least one embodiment, because hardware resources of graphics processing engines 1531 (1 )-1531 (N) are mapped explicitly to a real address space seen by host processor 1507, any host processor can address these resources directly using an effective address value. In at least one embodiment, one function of accelerator integration circuit 1536 is physical separation of graphics processing engines 1531 (1)-1531 (N) so that they appear to a system as independent units.

[0337] In at least one embodiment, one or more graphics memories 1533(1)-1533(M) are coupled to each of graphics processing engines 1531(1)-1531(N), respectively and N=M. In at least one embodiment, graphics memories 1533(1)-1533(M) store instructions and data being processed by each of graphics processing engines 1531(1)-1531(N). In at least one embodiment, graphics memories 1533( 1 )-1533(M) may be volatile memories such as DRAMs (including stacked DRAMs), GDDR memory (e g., GDDR5, GDDR6), or HBM, and / or may be nonvolatile memories such as 3D XPoint or Nano-Ram.

[0338] In at least one embodiment, to reduce data traffic over high-speed link 1540, biasing techniques can be used to ensure that data stored in graphics memories 1533(1)-1533(M) is data that will be used most frequently by graphics processing engines 1531(1 )-1531 (N) and preferably not used by cores 1560A-1560D (at least not frequently). Similarly, in at least one embodiment, a biasing mechanism attempts to keep data needed by cores (and preferably not graphics processing engines 1531 (1)-1531 (N)) within caches 1562A-1562D, 1556 and system memory 1514.

[0339] FIG. 15C illustrates another exemplary embodiment in which accelerator integration circuit 1536 is integrated within processor 1507. In this embodiment, graphics processing engines 1531(1)-1531(N) communicate directly over high-speed link 1540 to accelerator integration circuit 1536 via interface 1537 and interface 1535 (which, again, may be any form of bus or interface protocol). In at least one embodiment, accelerator integration circuit 1536 may perform similar operations as those described with respect to FIG. 15B, but potentially at a higher throughput given its close proximity to coherence bus 1564 and caches 1562A-1562D, 1556. In at least one embodiment, an accelerator integration circuit supports different programming models including a dedicated-process programming model (no graphics acceleration module virtualization) and shared programming models (with virtualization), which may include programming models which are controlled by accelerator integration circuit 1536 and programming models which are controlled by graphics acceleration module 1546.

[0340] In at least one embodiment, graphics processing engines 1531(1)-1531 (N) are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can funnel other application requests to graphics processing engines 1531(1)-1531 (N), providing virtualization within a VM / partition. [0341 ] In at least one embodiment, graphics processing engines 1531(1)-1531 (N), may be shared by multiple VM / application partitions. In at least one embodiment, shared models may use a system hypervisor to virtualize graphics processing engines 1531 (1 )-1531 (N) to allow access by each operating system. In at least one embodiment, for single-partition systems without a hypervisor, graphics processing engines 1531(1)-1531(N) are owned by an operating system. In at least one embodiment, an operating system can virtualize graphics processing engines 1531(1)-1531(N) to provide access to each process or application.

[0342] In at least one embodiment, graphics acceleration module 1546 or an individual graphics processing engine 1531 (1)-1531(N) selects a process element using a process handle. In at least one embodiment, process elements are stored in system memory 1514 and are addressable using an effective address to real address translation technique described herein. In at least one embodiment, a process handle may be an implementation-specific value provided to a host process when registering its context with graphics processing engine 1531 (1)-1531 (N) (that is, calling system software to add a process element to a process element linked list). In at least one embodiment, a lower 16-bits of a process handle may be an offset of a process element within a process element linked list.

[0343] FIG. 15D illustrates an exemplary accelerator integration slice 1590. In at least one embodiment, a “slice” comprises a specified portion of processing resources of accelerator integration circuit 1536. In at least one embodiment, an application is effective address space 1582 within system memory 1514 stores process elements 1583. In at least one embodiment, process elements 1583 are stored in response to GPU invocations 1581 from applications 1580 executed on processor 1507. In at least one embodiment, a process element 1583 contains process state for corresponding application 1580. In at least one embodiment, a work descriptor (WD) 1584 contained in process element 1583 can be a single job requested by an application or may contain a pointer to a queue of jobs. In at least one embodiment, WD 1584 is a pointer to a job request queue in an application’s effective address space 1582.

[0344] In at least one embodiment, graphics acceleration module 1546 and / or individual graphics processing engines 1531(1)-1531 (N) can be shared by all or a subset of processes in a system. In at least one embodiment, an infrastructure for setting up process states and sending a WD 1584 to a graphics acceleration module 1546 to start a job in a virtualized environment may be included.

[0345] In at least one embodiment, a dedicated-process programming model is implementation-specific. In at least one embodiment, in this model, a single process owns graphics acceleration module 1546 or an individual graphics processing engine 1531. In at least one embodiment, when graphics acceleration module 1546 is owned by a single process, a hypervisor initializes accelerator integration circuit 1536 for an owning partition and an operating system initializes accelerator integration circuit 1536 for an owning process when graphics acceleration module 1546 is assigned.

[0346] In at least one embodiment, in operation, a WD fetch unit 1591 in accelerator integration slice 1590 fetches next WD 1584, which includes an indication of work to be done by one or more graphics processing engines of graphics acceleration module 1546. In at least one embodiment, data from WD 1584 may be stored in registers 1545 and used by MMU 1539, interrupt management circuit 1547 and / or context management circuit 1548 as illustrated. For example, one embodiment of MMU 1539 includes segment / page walk circuitry for accessing segment / page tables 1586 within an OS virtual address space 1585. In at least one embodiment, interrupt management circuit 1547 may process interrupt events 1592 received from graphics acceleration module 1546. In at least one embodiment, when performing graphics operations, an effective address 1593 generated by a graphics processing engine 1531 (1)-1531 (N) is translated to a real address by MMU 1539.

[0347] In at least one embodiment, registers 1545 are duplicated for each graphics processing engine 1531 (1)-1531(N) and / or graphics acceleration module 1546 and may be initialized by a hypervisor or an operating system. In at least one embodiment, each of these duplicated registers may be included in an accelerator integration slice 1590. Exemplary registers that may be initialized by a hypervisor are shown in Table 1. Table 1 - Hypervisor Initialized Registers Register # Description 1 Slice Control Register 2 Real Address (RA) Scheduled Processes Area Pointer 3 Authority Mask Override Register 4 Interrupt Vector Table Entry Offset 5 Interrupt Vector Table Entry Limit 6 State Register 7 Logical Partition ID 8 Real address (RA) Hypervisor Accelerator Utilization Record Pointer 9 Storage Description Register

[0348] Exemplary registers that may be initialized by an operating system are shown in Table 2. Table 2 - Operating System Initialized Registers Register # Description 1 Process and Thread Identification 2 Effective Address (EA) Context Save / Restore Pointer 3 Virtual Address (VA) Accelerator Utilization Record Pointer 4 Virtual Address (VA) Storage Segment Table Pointer 5 Authority Mask 6 Work descriptor

[0349] In at least one embodiment, each WD 1584 is specific to a particular graphics acceleration module 1546 and / or graphics processing engines 1531 (1)-1531 (N). In at least one embodiment, it contains all information required by a graphics processing engine 1531(1)-1531(N) to do work, or it can be a pointer to a memory location where an application has set up a command queue of work to be completed. 10350] FIG. 15E illustrates additional details for one exemplary embodiment of a shared model. This embodiment includes a hypervisor real address space 1598 in which a process element list 1599 is stored. In at least one embodiment, hypervisor real address space 1598 is accessible via a hypervisor 1596 which virtualizes graphics acceleration module engines for operating system 1595. [03511 In at least one embodiment, shared programming models allow for all or a subset of processes from all or a subset of partitions in a system to use a graphics acceleration module 1546. In at least one embodiment, there are two programming models where graphics acceleration module 1546 is shared by multiple processes and partitions, namely time-sliced shared and graphics directed shared.

[0352] In at least one embodiment, in this model, system hypervisor 1596 owns graphics acceleration module 1546 and makes its function available to all operating systems 1595. In at least one embodiment, for a graphics acceleration module 1546 to support virtualization by system hypervisor 1596, graphics acceleration module 1546 may adhere to certain requirements, such as (1) an application’s job request must be autonomous (that is, state does not need to be maintained between jobs), or graphics acceleration module 1546 must provide a context save and restore mechanism, (2) an application’s job request is guaranteed by graphics acceleration module 1546 to complete in a specified amount of time, including any translation faults, or graphics acceleration module 1546 provides an ability to preempt processing of a job, and (3) graphics acceleration module 1546 must be guaranteed fairness between processes when operating in a directed shared programming model.

[0353] In at least one embodiment, application 1580 is required to make an operating system 1595 system call with a graphics acceleration module type, a work descriptor (WD), an authority mask register (AMR) value, and a context save / restore area pointer (CSRP). In at least one embodiment, graphics acceleration module type describes a targeted acceleration function for a system call. In at least one embodiment, graphics acceleration module type may be a system specific value. In at least one embodiment, WD is formatted specifically for graphics acceleration module 1546 and can be in a form of a graphics acceleration module 1546 command, an effective address pointer to a user-defined structure, an effective address pointer to a queue of commands, or any other data structure to describe work to be done by graphics acceleration module 1546.

[0354] In at least one embodiment, an AMR value is an AMR state to use for a current process. In at least one embodiment, a value passed to an operating system is similar to an application setting an AMR. In at least one embodiment, if accelerator integration circuit 1536 (not shown) and graphics acceleration module 1546 implementations do not support a User Authority Mask Override Register (UAMOR), an operating system may apply a current UAMOR value to an AMR value before passing an AMR in a hypervisor call. In at least one embodiment, hypervisor 1596 may optionally apply a current Authority Mask Override Register (AMOR) value before placing an AMR into process element 1583. In at least one embodiment, CSRP is one of registers 1545 containing an effective address of an area in an application’s effective address space 1582 for graphics acceleration module 1546 to save and restore context state. In at least one embodiment, this pointer is optional if no state is required to be saved between jobs or when a job is preempted. In at least one embodiment, context save / restore area may be pinned system memory.

[0355] Upon receiving a system call, operating system 1595 may verify that application 1580 has registered and been given authority to use graphics acceleration module 1546. In at least one embodiment, operating system 1595 then calls hypervisor 1596 with information shown in Table 3. Table 3 - OS to Hypervisor Call Parameters Parameter # Description 1 A work descriptor (WD) 2 An Authority Mask Register (AMR) value (potentially masked) 3 An effective address (EA) Context Save / Restore Area Pointer (CSRP) 4 A process ID (PID) and optional thread ID (TID) 5 A virtual address (VA) accelerator utilization record pointer (AURP) 6 Virtual address of storage segment table pointer (SSTP) 7 A logical interrupt service number (LISN)

[0356] In at least one embodiment, upon receiving a hypervisor call, hypervisor 1596 verifies that operating system 1595 has registered and been given authority to use graphics acceleration module 1546. In at least one embodiment, hypervisor 1596 then puts process element 1583 into a process element linked list for a corresponding graphics acceleration module 1546 type. In at least one embodiment, a process element may include information shown in Table 4. Table 4 -Process Element Information Element # Description 1 A work descriptor (WD) 2 An Authority Mask Register (AMR) value (potentially masked). 3 An effective address (EA) Context Save / Restore Area Pointer (CSRP) 4 A process ID (PID) and optional thread ID (TID) 5 A virtual address (VA) accelerator utilization record pointer (AURP) 6 Virtual address of storage segment table pointer (SSTP) 7 A logical interrupt service number (LISN) 8 Interrupt vector table, derived from hypervisor call parameters 9 A state register (SR) value 10 A logical partition ID (LPID) 11 A real address (RA) hypervisor accelerator utilization record pointer 12 Storage Descriptor Register (SDR)

[0357] In at least one embodiment, hypervisor initializes a plurality of accelerator integration slice 1590 registers 1545.

[0358] As illustrated in FIG. 15F, in at least one embodiment, a unified memory is used, addressable via a common virtual memory address space used to access physical processor memories 1501 (1 )-1501 (N) and GPU memories 1520(l)-1520(N). In this implementation, operations executed on GPUs 1510(1)- 1510(N) utilize a same virtual / effective memory address space to access processor memories 1501(1)-1501 (M) and vice versa, thereby simplifying programmability. In at least one embodiment, a first portion of a virtual / effective address space is allocated to processor memory 1501(1), a second portion to second processor memory 1501(N), a third portion to GPU memory 1520(1), and so on. In at least one embodiment, an entire virtual / effective memory space (sometimes referred to as an effective address space) is thereby distributed across each of processor memories 1501 and GPU memories 1520, allowing any processor or GPU to access any physical memory with a virtual address mapped to that memory.

[0359] In at least one embodiment, bias / coherence management circuitry 1594A-1594E within one or more of MMUs 1539A-1539E ensures cache coherence between caches of one or more host processors (e.g., 1505) and GPUs 1510 and implements biasing techniques indicating physical memories in which certain types of data should be stored. In at least one embodiment, while multiple instances of bias / coherence management circuitry 1594A-1594E are illustrated in FIG. 15F, bias / coherence circuitry may be implemented within an MMU of one or more host processors 1505 and / or within accelerator integration circuit 1536.

[0360] One embodiment allows GPU memories 1520 to be mapped as part of system memory, and accessed using shared virtual memory (SVM) technology, but without suffering performance drawbacks associated with full system cache coherence. In at least one embodiment, an ability for GPU memories 1520 to be accessed as system memory without onerous cache coherence overhead provides a beneficial operating environment for GPU offload. In at least one embodiment, this arrangement allows software of host processor 1505 to setup operands and access computation results, without overhead of tradition I / O DMA data copies. In at least one embodiment, such traditional copies involve driver calls, interrupts and memory mapped I / O (MMIO) accesses that are all inefficient relative to simple memory accesses. In at least one embodiment, an ability to access GPU memories 1520 without cache coherence overheads can be critical to execution time of an offloaded computation. In at least one embodiment, in cases with substantial streaming write memory traffic, for example, cache coherence overhead can significantly reduce an effective write bandwidth seen by a GPU 1510. In at least one embodiment, efficiency of operand setup, efficiency of results access, and efficiency of GPU computation may play a role in determining effectiveness of a GPU offload.

[0361] In at least one embodiment, selection of GPU bias and host processor bias is driven by a bias tracker data structure. In at least one embodiment, a bias table may be used, for example, which may be a page-granular structure (e.g., controlled at a granularity of a memory page) that includes 1 or 2 bits per GPU-attached memory page. In at least one embodiment, a bias table may be implemented in a stolen memory range of one or more GPU memories 1520, with or without a bias cache in a GPU 1510 (e.g., to cache frequently / recently used entries of a bias table). Alternatively, in at least one embodiment, an entire bias table may be maintained within a GPU.

[0362] In at least one embodiment, a bias table entry associated with each access to a GPU attached memory 1520 is accessed prior to actual access to a GPU memory, causing following operations. In at least one embodiment, local requests from a GPU 1510 that find their page in GPU bias are forwarded directly to a corresponding GPU memory 1520. In at least one embodiment, local requests from a GPU that find their page in host bias are forwarded to processor 1505 (e.g., over a high-speed link as described herein). In at least one embodiment, requests from processor 1505 that find a requested page in host processor bias complete a request like a normal memory read. Alternatively, requests directed to a GPU-biased page may be forwarded to a GPU 1510. In at least one embodiment, a GPU may then transition a page to a host processor bias if it is not currently using a page. In at least one embodiment, a bias state of a page can be changed either by a software-based mechanism, a hardware-assisted software-based mechanism, or, for a limited set of cases, a purely hardware-based mechanism.

[0363] In at least one embodiment, one mechanism for changing bias state employs an API call (e.g., OpenCL), which, in turn, calls a GPU’s device driver which, in turn, sends a message (or enqueues a command descriptor) to a GPU directing it to change a bias state and, for some transitions, perform a cache flushing operation in a host. In at least one embodiment, a cache flushing operation is used for a transition from host processor 1505 bias to GPU bias, but is not for an opposite transition.

[0364] In at least one embodiment, cache coherency is maintained by temporarily rendering GPU-biased pages uncacheable by host processor 1505. In at least one embodiment, to access these pages, processor 1505 may request access from GPU 1510, which may or may not grant access right away. In at least one embodiment, thus, to reduce communication between processor 1505 and GPU 1510 it is beneficial to ensure that GPU-biased pages are those which are required by a GPU but not host processor 1505 and vice versa.

[0365] Hardware structure(s) 115 are used to perform one or more embodiments. Details regarding a hardware structure(s) 115 may be provided herein in conjunction with FIGS. 1A and / or IB.

[0366] FIG. 16 illustrates exemplary integrated circuits and associated graphics processors that may be fabricated using one or more IP cores, according to various embodiments described herein. In addition to what is illustrated, other logic and circuits may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0367] FIG. 16 is a block diagram illustrating an exemplary system on a chip integrated circuit 1600 that may be fabricated using one or more IP cores, according to at least one embodiment. In at least one embodiment, integrated circuit 1600 includes one or more application processor(s) 1605 (e.g., CPUs), at least one graphics processor 1610, and may additionally include an image processor 1615 and / or a video processor 1620, any of which may be a modular IP core. In at least one embodiment, integrated circuit 1600 includes peripheral or bus logic including a USB controller 1625, a CART controller 1630, an SPI / SDIO controller 1635, and an I22S / I22C controller 1640. In at least one embodiment, integrated circuit 1600 can include a display device 1645 coupled to one or more of a high-defmition multimedia interface (HDMI) controller 1650 and a mobile industry processor interface (MIPI) display interface 1655. In at least one embodiment, storage may be provided by a flash memory subsystem 1660 including flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1665 for access to SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits additionally include an embedded security engine 1670.

[0368] Inference and / or training logic 115 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 115 are provided herein in conjunction with FIGS. 1A and / or IB. In at least one embodiment, inference and / or training logic 115 may be used in integrated circuit 1600 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0369] FIGS. 17A-17B illustrate exemplary integrated circuits and associated graphics processors that may be fabricated using one or more IP cores, according to various embodiments described herein. In addition to what is illustrated, other logic and circuits may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0370] FIGS. 17A-17B are block diagrams illustrating exemplary graphics processors for use within an SoC, according to embodiments described herein. FIG. 17A illustrates an exemplary graphics processor 1710 of a system on a chip integrated circuit that may be fabricated using one or more IP cores, according to at least one embodiment. FIG. 17B illustrates an additional exemplary graphics processor 1740 of a system on a chip integrated circuit that may be fabricated using one or more IP cores, according to at least one embodiment. In at least one embodiment, graphics processor 1710 of FIG. 17A is a low power graphics processor core. In at least one embodiment, graphics processor 1740 of FIG. 17B is a higher performance graphics processor core. In at least one embodiment, each of graphics processors 1710, 1740 can be variants of graphics processor 1610 of FIG. 16. [0371 ] In at least one embodiment, graphics processor 1710 includes a vertex processor 1705 and one or more fragment processor(s) 1715A-1715N (e.g., 1715A, 1715B, 1715C, 1715D, through 1715N-1, and 1715N). In at least one embodiment, graphics processor 1710 can execute different shader programs via separate logic, such that vertex processor 1705 is optimized to execute operations for vertex shader programs, while one or more fragment processor(s) 171 SA-1715N execute fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, vertex processor 1705 performs a vertex processing stage of a 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, fragment processor(s) 1715A-1715N use primitive and vertex data generated by vertex processor 1705 to produce a framebuffer that is displayed on a display device. In at least one embodiment, fragment processor(s) 1715A-1715N are optimized to execute fragment shader programs as provided for in an OpenGL API, which may be used to perform similar operations as a pixel shader program as provided for in a Direct 3D API.

[0372] In at least one embodiment, graphics processor 1710 additionally includes one or more memory management units (MMUs) 1720A-1720B, cache(s) 1725A-1725B, and circuit interconnect(s) 1730A-1730B. In at least one embodiment, one or more MMU(s) 1720A-1720B provide for virtual to physical address mapping for graphics processor 1710, including for vertex processor 1705 and / or fragment processor(s) 1715A-1715N, which may reference vertex or image / texture data stored in memory, in addition to vertex or image / texture data stored in one or more cache(s) 1725A-1725B. In at least one embodiment, one or more MMU(s) 1720A-1720B may be synchronized with other MMUs within a system, including one or more MMUs associated with one or more application processor(s) 1605, image processors 1015, and / or video processors 1620 of FIG. 16, such that each processor 1605-1620 can participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnect(s) 1730A-1730B enable graphics processor 1710 to interface with other IP cores within SoC, either via an internal bus of SoC or via a direct connection.

[0373] In at least one embodiment, graphics processor 1740 includes one or more shader core(s) 1755A-1755N (e.g., 1755A, 1755B, 1755C, 1755D, 1755E, 1755F, through 1755N-1, and 1755N) as shown in FIG. 17B, which provides for a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code to implement vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, a number of shader cores can vary. In at least one embodiment, graphics processor 1740 includes an inter-core task manager 1745, which acts as a thread dispatcher to dispatch execution threads to one or more shader cores 1755A-1755N and a tiling unit 1758 to accelerate tiling operations for tile-based rendering, in which rendering operations for a scene are subdivided in image space, for example to exploit local spatial coherence within a scene or to optimize use of internal caches.

[0374] Inference and / or training logic 115 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 115 are provided herein in conjunction with FIGS. 1A and / or IB. In at least one embodiment, inference and / or training logic 115 may be used in integrated circuit 11A and / or 1 IB for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein. (0375] FIGS. 18A-18B illustrate additional exemplary graphics processor logic according to embodiments described herein. FIG. 18A illustrates a graphics core 1800 that may be included within graphics processor 1610 of FIG. 16, in at least one embodiment, and may be a unified shader core 1755A-1755N as in FIG. 17B in at least one embodiment. FIG. 18B illustrates a highly-parallel general-purpose graphics processing unit (“GPGPU”) 1830 suitable for deployment on a multi-chip module in at least one embodiment. [()376] In at least one embodiment, graphics core 1800 includes a shared instruction cache 1802, a texture unit 1818, and a cache / shared memory 1820 that are common to execution resources within graphics core 1800. In at least one embodiment, graphics core 1800 can include multiple slices 1801 A-180IN or a partition for each core, and a graphics processor can include multiple instances of graphics core 1800. In at least one embodiment, slices 1801A-1801N can include support logic including a local instruction cache 1804A-1804N, a thread scheduler 1806A-1806N, a thread dispatcher 1808A-1808N, and a set of registers 1810A-1810N. In at least one embodiment, slices 1801A-1801N can include a set of additional function units (AFUs 1812A-1812N), floating-point units (FPUs 1814A-1814N), integer arithmetic logic units (ALUs 1816A-1816N), address computational units (ACUs 1813A-1813N), double-precision floatingpoint units (DPFPUs 1815A-1815N), and matrix processing units (MPUs 1817A-1817N).

[0377] In at least one embodiment, FPUs 1814A-1814N can perform single-precision (32-bit) and half-precision (16-bit) floating point operations, while DPFPUs 1815A-1815N perform double precision (64-bit) floating point operations. In at least one embodiment, ALUs 1816A-1816N can perform variable precision integer operations at 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed precision operations. In at least one embodiment, MPUs 1817A-1817N can also be configured for mixed precision matrix operations, including halfprecision floating point and 8-bit integer operations. In at least one embodiment, MPUs 1817-1817N can perform a variety of matrix operations to accelerate machine learning application frameworks, including enabling support for accelerated general matrix to matrix multiplication (GEMM). In at least one embodiment, AFUs 1812A-1812N can perform additional logic operations not supported by floating-point or integer units, including trigonometric operations (e.g., sine, cosine, etc.).

[0378] Inference and / or training logic 115 are used to perform mferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 115 are provided herein in conjunction with FIGS. 1A and / or IB. In at least one embodiment, inference and / or training logic 115 may be used in graphics core 1800 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0379] FIG. 18B illustrates a general-purpose processing unit (GPGPU) 1830 that can be configured to enable highly-parallel compute operations to be performed by an array of graphics processing units, in at least one embodiment. In at least one embodiment, GPGPU 1830 can be linked directly to other instances of GPGPU 1830 to create a multi-GPU cluster to improve training speed for deep neural networks. In at least one embodiment, GPGPU 1830 includes a host interface 1832 to enable a connection with a host processor. In at least one embodiment, host interface 1832 is a PCI Express interface. In at least one embodiment, host interface 1832 can be a vendor-specific communications interface or communications fabric. In at least one embodiment, GPGPU 1830 receives commands from a host processor and uses a global scheduler 1834 to distribute execution threads associated with those commands to a set of compute clusters 1836A-1836H. In at least one embodiment, compute clusters 1836A-1836H share a cache memory 1838. In at least one embodiment, cache memory 1838 can serve as a higher-level cache for cache memories within compute clusters 1836A-1836H.

[0380] In at least one embodiment, GPGPU 1830 includes memory 1844A-1844B coupled with compute clusters 1836A-1836H via a set of memory controllers 1842A-1842B. In at least one embodiment, memory 1844A-1844B can include various types of memory devices including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. [038 i] In at least one embodiment, compute clusters 1836A-1836H each include a set of graphics cores, such as graphics core 1800 of FIG. 18A, which can include multiple types of integer and floating point logic units that can perform computational operations at a range of precisions including suited for machine learning computations. For example, in at least one embodiment, at least a subset of floating point units in each of compute clusters 1836A-1836H can be configured to perform 16-bit or 32-bit floating point operations, while a different subset of floating point units can be configured to perform 64-bit floating point operations.

[0382] In at least one embodiment, multiple instances of GPGPU 1830 can be configured to operate as a compute cluster. In at least one embodiment, communication used by compute clusters 1836A-1836H for synchronization and data exchange varies across embodiments. In at least one embodiment, multiple instances of GPGPU 1830 communicate over host interface 1832. In at least one embodiment, GPGPU 1830 includes an I / O hub 1839 that couples GPGPU 1830 with a GPU link 1840 that enables a direct connection to other instances of GPGPU 1830. In at least one embodiment, GPU link 1840 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 1830. In at least one embodiment, GPU link 1840 couples with a high-speed interconnect to transmit and receive data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 1830 are located in separate data processing systems and communicate via a network device that is accessible via host interface 1832. In at least one embodiment GPU link 1840 can be configured to enable a connection to a host processor in addition to or as an alternative to host interface 1832. J0383] In at least one embodiment, GPGPU 1830 can be configured to train neural networks. In at least one embodiment, GPGPU 1830 can be used within an inferencing platform. In at least one embodiment, in which GPGPU 1830 is used for inferencing, GPGPU 1830 may include fewer compute clusters 1836A-1836H relative to when GPGPU 1830 is used for training a neural network. In at least one embodiment, memory technology associated with memory 1844A-1844B may differ between inferencing and training configurations, with higher bandwidth memory technologies devoted to training configurations. In at least one embodiment, an inferencing configuration of GPGPU 1830 can support inferencing specific instructions. For example, in at least one embodiment, an inferencing configuration can provide support for one or more 8-bit integer dot product instructions, which may be used during inferencing operations for deployed neural networks.

[0384] Inference and / or training logic 115 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 115 are provided herein in conjunction with FIGS. 1A and / or IB. In at least one embodiment, inference and / or training logic 115 may be used in GPGPU 1830 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0385] FIG. 19 is a block diagram illustrating a computing system 1900 according to at least one embodiment. In at least one embodiment, computing system 1900 includes a processing subsystem 1901 having one or more processor(s) 1902 and a system memory 1904 communicating via an interconnection path that may include a memory hub 1905. In at least one embodiment, memory hub 1905 may be a separate component within a chipset component or may be integrated within one or more processor(s) 1902. In at least one embodiment, memory hub 1905 couples with an I / O subsystem 1911 via a communication link 1906. In at least one embodiment, I / O subsystem 1911 includes an I / O hub 1907 that can enable computing system 1900 to receive input from one or more input device(s) 1908. In at least one embodiment, I / O hub 1907 can enable a display controller, which may be included in one or more processor(s) 1902, to provide outputs to one or more display device(s) 1910A. In at least one embodiment, one or more display device(s) 1910A coupled with I / O hub 1907 can include a local, internal, or embedded display device.

[0386] In at least one embodiment, processing subsystem 1901 includes one or more parallel processor(s) 1912 coupled to memory hub 1905 via a bus or other communication link 1913. In at least one embodiment, communication link 1913 may use one of any number of standards based communication link technologies or protocols, such as, but not limited to PCI Express, or may be a vendor-specific communications interface or communications fabric. In at least one embodiment, one or more parallel processor(s) 1912 form a computationally focused parallel or vector processing system that can include a large number of processing cores and / or processing clusters, such as a many-integrated core (MIC) processor. In at least one embodiment, some or all of parallel processor(s) 1912 form a graphics processing subsystem that can output pixels to one of one or more display device(s) 1910A coupled via I / O Hub 1907. In at least one embodiment, parallel processor(s) 1912 can also include a display controller and display interface (not shown) to enable a direct connection to one or more display device(s) 191 OB.

[0387] In at least one embodiment, a system storage unit 1914 can connect to I / O hub 1907 to provide a storage mechanism for computing system 1900. In at least one embodiment, an I / O switch 1916 can be used to provide an interface mechanism to enable connections between I / O hub 1907 and other components, such as a network adapter 1918 and / or a wireless network adapter 1919 that may be integrated into platform, and various other devices that can be added via one or more add-in device(s) 1920. In at least one embodiment, network adapter 1918 can be an Ethernet adapter or another wired network adapter. In at least one embodiment, wireless network adapter 1919 can include one or more of a Wi-Fi, Bluetooth, near field communication (NFC), or other network device that includes one or more wireless radios. 10388] In at least one embodiment, computing system 1900 can include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, and like, may also be connected to I / O hub 1907. In at least one embodiment, communication paths interconnecting various components in FIG. 19 may be implemented using any suitable protocols, such as PCI (Peripheral Component Interconnect) based protocols (e.g., PCI-Express), or other bus or point-to-point communication interfaces and / or protocol(s), such as NV-Link high-speed interconnect, or interconnect protocols.

[0389] In at least one embodiment, parallel processor(s) 1912 incorporate circuitry optimized for graphics and video processing, including, for example, video output circuitry, and constitutes a graphics processing unit (GPU). In at least one embodiment, parallel processor(s) 1912 incorporate circuitry optimized for general purpose processing. In at least embodiment, components of computing system 1900 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, parallel processor(s) 1912, memory hub 1905, processor(s) 1902, and I / O hub 1907 can be integrated into a system on chip (SoC) integrated circuit. In at least one embodiment, components of computing system 1900 can be integrated into a single package to form a system in package (SIP) configuration. In at least one embodiment, at least a portion of components of computing system 1900 can be integrated into a multi-chip module (MCM), which can be interconnected with other multi-chip modules into a modular computing system.

[0390] Inference and / or training logic 115 are used to perform mferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 115 are provided herein in conjunction with FIGS. 1A and / or IB. In at least one embodiment, inference and / or training logic 115 may be used computing system 1900 of FIG. 19 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein. PROCESSORS [0391 ] FIG. 20A illustrates a parallel processor 2000 according to at least one embodiment. In at least one embodiment, various components of parallel processor 2000 may be implemented using one or more integrated circuit devices, such as programmable processors, application specific integrated circuits (ASICs), or field programmable gate arrays (FPGA). In at least one embodiment, illustrated parallel processor 2000 is a variant of one or more parallel processor(s) 1912 shown in FIG. 19 according to an exemplary embodiment.

[0392] In at least one embodiment, parallel processor 2000 includes a parallel processing unit 2002. In at least one embodiment, parallel processing unit 2002 includes an I / O unit 2004 that enables communication with other devices, including other instances of parallel processing unit 2002. In at least one embodiment, I / O unit 2004 may be directly connected to other devices. In at least one embodiment, I / O unit 2004 connects with other devices via use of a hub or switch interface, such as a memory hub 2005. In at least one embodiment, connections between memory hub 2005 and I / O unit 2004 form a communication link 2013. In at least one embodiment, I / O unit 2004 connects with a host interface 2006 and a memory crossbar 2016, where host interface 2006 receives commands directed to performing processing operations and memory crossbar 2016 receives commands directed to performing memory operations.

[0393] In at least one embodiment, when host interface 2006 receives a command buffer via I / O unit 2004, host interface 2006 can direct work operations to perform those commands to a front end 2008. In at least one embodiment, front end 2008 couples with a scheduler 2010, which is configured to distribute commands or other work items to a processing cluster array 2012. In at least one embodiment, scheduler 2010 ensures that processing cluster array 2012 is properly configured and in a valid state before tasks are distributed to a cluster of processing cluster array 2012. In at least one embodiment, scheduler 2010 is implemented via firmware logic executing on a microcontroller. In at least one embodiment, microcontroller implemented scheduler 2010 is configurable to perform complex scheduling and work distribution operations at coarse and fine granularity, enabling rapid preemption and context switching of threads executing on processing array 2012. In at least one embodiment, host software can prove workloads for scheduling on processing cluster array 2012 via one of multiple graphics processing paths. In at least one embodiment, workloads can then be automatically distributed across processing array cluster 2012 by scheduler 2010 logic within a microcontroller including scheduler 2010.

[0394] In at least one embodiment, processing cluster array 2012 can include up to “N” processing clusters (e.g., cluster 2014A, cluster 2014B, through cluster 2014N), where “N” represents a positive integer (which may be a different integer “N” than used in other figures). In at least one embodiment, each cluster 2014A-2014N of processing cluster array 2012 can execute a large number of concurrent threads. In at least one embodiment, scheduler 2010 can allocate work to clusters 2014A-2014N of processing cluster array 2012 using various scheduling and / or work distribution algorithms, which may vary depending on workload arising for each type of program or computation. In at least one embodiment, scheduling can be handled dynamically by scheduler 2010, or can be assisted in part by compiler logic during compilation of program logic configured for execution by processing cluster array 2012. In at least one embodiment, different clusters 2014A-2014N of processing cluster array 2012 can be allocated for processing different types of programs or for performing different types of computations.

[0395] In at least one embodiment, processing cluster array 2012 can be configured to perform various types of parallel processing operations. In at least one embodiment, processing cluster array 2012 is configured to perform general-purpose parallel compute operations. For example, in at least one embodiment, processing cluster array 2012 can include logic to execute processing tasks including filtering of video and / or audio data, performing modeling operations, including physics operations, and performing data transformations.

[0396] In at least one embodiment, processing cluster array 2012 is configured to perform parallel graphics processing operations. In at least one embodiment, processing cluster array 2012 can include additional logic to support execution of such graphics processing operations, including but not limited to, texture sampling logic to perform texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, processing cluster array 2012 can be configured to execute graphics processing related shader programs such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, parallel processing unit 2002 can transfer data from system memory via I / O unit 2004 for processing. In at least one embodiment, during processing, transferred data can be stored to on-chip memory (e.g., parallel processor memory 2022) during processing, then written back to system memory.

[0397] In at least one embodiment, when parallel processing unit 2002 is used to perform graphics processing, scheduler 2010 can be configured to divide a processing workload into approximately equal sized tasks, to better enable distribution of graphics processing operations to multiple clusters 2014A-2014N of processing cluster array 2012. In at least one embodiment, portions of processing cluster array 2012 can be configured to perform different types of processing. For example, in at least one embodiment, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen space operations, to produce a rendered image for display. In at least one embodiment, intermediate data produced by one or more of clusters 2014A-2014N may be stored in buffers to allow intermediate data to be transmitted between clusters 2014A-2014N for further processing.

[0398] In at least one embodiment, processing cluster array 2012 can receive processing tasks to be executed via scheduler 2010, which receives commands defining processing tasks from front end 2008. In at least one embodiment, processing tasks can include indices of data to be processed, e.g., surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands defining how data is to be processed (e.g., what program is to be executed). In at least one embodiment, scheduler 2010 may be configured to fetch indices corresponding to tasks or may receive indices from front end 2008. In at least one embodiment, front end 2008 can be configured to ensure processing cluster array 2012 is configured to a valid state before a workload specified by incoming command buffers (e.g., batch-buffers, push buffers, etc.) is initiated. (()399] In at least one embodiment, each of one or more instances of parallel processing unit 2002 can couple with a parallel processor memory 2022. In at least one embodiment, parallel processor memory 2022 can be accessed via memory crossbar 2016, which can receive memory requests from processing cluster array 2012 as well as I / O unit 2004. In at least one embodiment, memory crossbar 2016 can access parallel processor memory 2022 via a memory interface 2018. In at least one embodiment, memory interface 2018 can include multiple partition units (e.g., partition unit 2020A, partition unit 2020B, through partition unit 2020N) that can each couple to a portion (e.g., memory unit) of parallel processor memory 2022. In at least one embodiment, a number of partition units 2020A-2020N is configured to be equal to a number of memory units, such that a first partition unit 2020A has a corresponding first memory unit 2024A, a second partition unit 2020B has a corresponding memory unit 2024B, and an N-th partition unit 2020N has a corresponding N-th memory unit 2024N. In at least one embodiment, a number of partition units 2020A-2020N may not be equal to a number of memory units.

[0400] In at least one embodiment, memory units 2024A-2024N can include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory units 2024A-2024N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). In at least one embodiment, render targets, such as frame buffers or texture maps may be stored across memory units 2024A-2024N, allowing partition units 2020A-2020N to write portions of each render target in parallel to efficiently use available bandwidth of parallel processor memory 2022. In at least one embodiment, a local instance of parallel processor memory 2022 may be excluded in favor of a unified memory design that utilizes system memory in conjunction with local cache memory. [0401 ] In at least one embodiment, any one of clusters 2014A-2014N of processing cluster array 2012 can process data that will be written to any of memory units 2024A-2024N within parallel processor memory 2022. In at least one embodiment, memory crossbar 2016 can be configured to transfer an output of each cluster 2014A-2014N to any partition unit 2020A-2020N or to another cluster 2014A-2014N, which can perform additional processing operations on an output. In at least one embodiment, each cluster 2014A-2014N can communicate with memory interface 2018 through memory crossbar 2016 to read from or write to various external memory devices. In at least one embodiment, memory crossbar 2016 has a connection to memory interface 2018 to communicate with I / O unit 2004, as well as a connection to a local instance of parallel processor memory 2022, enabling processing units within different processing clusters 2014A-2014N to communicate with system memory or other memory that is not local to parallel processing unit 2002. In at least one embodiment, memory crossbar 2016 can use virtual channels to separate traffic streams between clusters 2014A-2014N and partition units 2020A-2020N.

[0402] In at least one embodiment, multiple instances of parallel processing unit 2002 can be provided on a single add-in card, or multiple add-in cards can be interconnected. In at least one embodiment, different instances of parallel processing unit 2002 can be configured to interoperate even if different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. For example, in at least one embodiment, some instances of parallel processing unit 2002 can include higher precision floating point units relative to other instances. In at least one embodiment, systems incorporating one or more instances of parallel processing unit 2002 or parallel processor 2000 can be implemented in a variety of configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems. [0403 ] FIG. 20B is a block diagram of a partition unit 2020 according to at least one embodiment. In at least one embodiment, partition unit 2020 is an instance of one of partition units 2020A-2020N of FIG. 20A. In at least one embodiment, partition unit 2020 includes an L2 cache 2021, a frame buffer interface 2025, and a ROP 2026 (raster operations unit). In at least one embodiment, L2 cache 2021 is a read / write cache that is configured to perform load and store operations received from memory crossbar 2016 and ROP 2026. In at least one embodiment, read misses and urgent write-back requests are output by L2 cache 2021 to frame buffer interface 2025 for processing. In at least one embodiment, updates can also be sent to a frame buffer via frame buffer interface 2025 for processing. In at least one embodiment, frame buffer interface 2025 interfaces with one of memory units in parallel processor memory, such as memory units 2024A-2024N of FIG. 20 (e.g., within parallel processor memory 2022). (0404] In at least one embodiment, ROP 2026 is a processing unit that performs raster operations such as stencil, z test, blending, etc. In at least one embodiment, ROP 2026 then outputs processed graphics data that is stored in graphics memory. In at least one embodiment, ROP 2026 includes compression logic to compress depth or color data that is written to memory and decompress depth or color data that is read from memory. In at least one embodiment, compression logic can be lossless compression logic that makes use of one or more of multiple compression algorithms. In at least one embodiment, a type of compression that is performed by ROP 2026 can vary based on statistical characteristics of data to be compressed. For example, in at least one embodiment, delta color compression is performed on depth and color data on a pertile basis.

[0405] In at least one embodiment, ROP 2026 is included within each processing cluster (e.g., cluster 2014A-2014N of FIG. 20A) instead of within partition unit 2020. In at least one embodiment, read and write requests for pixel data are transmitted over memory crossbar 2016 instead of pixel fragment data. In at least one embodiment, processed graphics data may be displayed on a display device, such as one of one or more display device(s) 1910 of FIG. 19, routed for further processing by processor(s) 1302, or routed for further processing by one of processing entities within parallel processor 2000 of FIG. 20A.

[0406] FIG. 20C is a block diagram of a processing cluster 2014 within a parallel processing unit according to at least one embodiment. In at least one embodiment, a processing cluster is an instance of one of processing clusters 2014A-2014N of FIG. 20A. In at least one embodiment, processing cluster 2014 can be configured to execute many threads in parallel, where “thread” refers to an instance of a particular program executing on a particular set of input data. In at least one embodiment, single-instruction, multiple-data (SIMD) instruction issue techniques are used to support parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, single-instruction, multiple-thread (SIMT) techniques are used to support parallel execution of a large number of generally synchronized threads, using a common instruction unit configured to issue instructions to a set of processing engines within each one of processing clusters.

[0407] In at least one embodiment, operation of processing cluster 2014 can be controlled via a pipeline manager 2032 that distributes processing tasks to SIMT parallel processors. In at least one embodiment, pipeline manager 2032 receives instructions from scheduler 2010 of FIG. 20A and manages execution of those instructions via a graphics multiprocessor 2034 and / or a texture unit 2036. In at least one embodiment, graphics multiprocessor 2034 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors of differing architectures may be included within processing cluster 2014. In at least one embodiment, one or more instances of graphics multiprocessor 2034 can be included within a processing cluster 2014. In at least one embodiment, graphics multiprocessor 2034 can process data and a data crossbar 2040 can be used to distribute processed data to one of multiple possible destinations, including other shader units. In at least one embodiment, pipeline manager 2032 can facilitate distribution of processed data by specifying destinations for processed data to be distributed via data crossbar 2040.

[0408] In at least one embodiment, each graphics multiprocessor 2034 within processing cluster 2014 can include an identical set of functional execution logic (e.g., arithmetic logic units, load-store units, etc.). In at least one embodiment, functional execution logic can be configured in a pipelined manner in which new instructions can be issued before previous instructions are complete. In at least one embodiment, functional execution logic supports a variety of operations including integer and floating point arithmetic, comparison operations, Boolean operations, bit-shifting, and computation of various algebraic functions. In at least one embodiment, same functional-unit hardware can be leveraged to perform different operations and any combination of functional units may be present. [0409 ] In at least one embodiment, instructions transmitted to processing cluster 2014 constitute a thread. In at least one embodiment, a set of threads executing across a set of parallel processing engines is a thread group. In at least one embodiment, a thread group executes a common program on different input data. In at least one embodiment, each thread within a thread group can be assigned to a different processing engine within a graphics multiprocessor 2034. In at least one embodiment, a thread group may include fewer threads than a number of processing engines within graphics multiprocessor 2034. In at least one embodiment, when a thread group includes fewer threads than a number of processing engines, one or more of processing engines may be idle during cycles in which that thread group is being processed. In at least one embodiment, a thread group may also include more threads than a number of processing engines within graphics multiprocessor 2034. In at least one embodiment, when a thread group includes more threads than number of processing engines within graphics multiprocessor 2034, processing can be performed over consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed concurrently on a graphics multiprocessor 2034.

[0410] In at least one embodiment, graphics multiprocessor 2034 includes an internal cache memory to perform load and store operations. In at least one embodiment, graphics multiprocessor 2034 can forego an internal cache and use a cache memory (e.g., LI cache 2048) within processing cluster 2014. In at least one embodiment, each graphics multiprocessor 2034 also has access to L2 caches within partition units (e.g., partition units 2020A-2020N of FIG. 20A) that are shared among all processing clusters 2014 and may be used to transfer data between threads. In at least one embodiment, graphics multiprocessor 2034 may also access off-chip global memory, which can include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory external to parallel processing unit 2002 may be used as global memory. In at least one embodiment, processing cluster 2014 includes multiple instances of graphics multiprocessor 2034 and can share common instructions and data, which may be stored in LI cache 2048.

[0411] In at least one embodiment, each processing cluster 2014 may include an MMU 2045 (memory management unit) that is configured to map virtual addresses into physical addresses. In at least one embodiment, one or more instances of MMU 2045 may reside within memory interface 2018 of FIG. 20A. In at least one embodiment, MMU 2045 includes a set of page table entries (PTEs) used to map a virtual address to a physical address of a tile and optionally a cache line index. In at least one embodiment, MMU 2045 may include address translation lookaside buffers (TLB) or caches that may reside within graphics multiprocessor 2034 or LI 2048 cache or processing cluster 2014. In at least one embodiment, a physical address is processed to distribute surface data access locally to allow for efficient request interleaving among partition units. In at least one embodiment, a cache line index may be used to determine whether a request for a cache line is a hit or miss.

[0412] In at least one embodiment, a processing cluster 2014 may be configured such that each graphics multiprocessor 2034 is coupled to a texture unit 2036 for performing texture mapping operations, e.g., determining texture sample positions, reading texture data, and filtering texture data. In at least one embodiment, texture data is read from an internal texture LI cache (not shown) or from an LI cache within graphics multiprocessor 2034 and is fetched from an L2 cache, local parallel processor memory, or system memory, as needed. In at least one embodiment, each graphics multiprocessor 2034 outputs processed tasks to data crossbar 2040 to provide processed task to another processing cluster 2014 for further processing or to store processed task in an L2 cache, local parallel processor memory, or system memory via memory crossbar 2016. In at least one embodiment, a preROP 2042 (pre-raster operations unit) is configured to receive data from graphics multiprocessor 2034, and direct data to ROP units, which may be located with partition units as described herein (e.g., partition units 2020A-2020N of FIG. 20A). In at least one embodiment, preROP 2042 unit can perform optimizations for color blending, organizing pixel color data, and performing address translations.

[0413] Inference and / or training logic 115 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 115 are provided herein in conjunction with FIGS. 1A and / or IB. In at least one embodiment, inference and / or training logic 115 may be used in graphics processing cluster 2014 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0414] FIG. 20D shows a graphics multiprocessor 2034 according to at least one embodiment. In at least one embodiment, graphics multiprocessor 2034 couples with pipeline manager 2032 of processing cluster 2014. In at least one embodiment, graphics multiprocessor 2034 has an execution pipeline including but not limited to an instruction cache 2052, an instruction unit 2054, an address mapping unit 2056, a register file 2058, one or more general purpose graphics processing unit (GPGPU) cores 2062, and one or more load / store units 2066. In at least one embodiment, GPGPU cores 2062 and load / store units 2066 are coupled with cache memory 2072 and shared memory 2070 via a memory and cache interconnect 2068.

[0415] In at least one embodiment, instruction cache 2052 receives a stream of instructions to execute from pipeline manager 2032. In at least one embodiment, instructions are cached in instruction cache 2052 and dispatched for execution by an instruction unit 2054. In at least one embodiment, instruction unit 2054 can dispatch instructions as thread groups (e.g., warps), with each thread of thread group assigned to a different execution unit within GPGPU cores 2062. In at least one embodiment, an instruction can access any of a local, shared, or global address space by specifying an address within a unified address space. In at least one embodiment, address mapping unit 2056 can be used to translate addresses in a unified address space into a distinct memory address that can be accessed by load / store units 2066.

[0416] In at least one embodiment, register file 2058 provides a set of registers for functional units of graphics multiprocessor 2034. In at least one embodiment, register file 2058 provides temporary storage for operands connected to data paths of functional units (e.g., GPGPU cores 2062, load / store units 2066) of graphics multiprocessor 2034. In at least one embodiment, register file 2058 is divided between each of functional units such that each functional unit is allocated a dedicated portion of register file 2058. In at least one embodiment, register file 2058 is divided between different warps being executed by graphics multiprocessor 2034.

[0417] In at least one embodiment, GPGPU cores 2062 can each include floating point units (FPUs) and / or integer arithmetic logic units (ALUs) that are used to execute instructions of graphics multiprocessor 2034. In at least one embodiment, GPGPU cores 2062 can be similar in architecture or can differ in architecture. In at least one embodiment, a first portion of GPGPU cores 2062 include a single precision FPU and an integer ALU while a second portion of GPGPU cores include a double precision FPU. In at least one embodiment, FPUs can implement IEEE 754-2008 standard floating point arithmetic or enable variable precision floating point arithmetic. In at least one embodiment, graphics multiprocessor 2034 can additionally include one or more fixed function or special function units to perform specific functions such as copy rectangle or pixel blending operations. In at least one embodiment, one or more of GPGPU cores 2062 can also include fixed or special function logic.

[0418] In at least one embodiment, GPGPU cores 2062 include SIMD logic capable of performing a single instruction on multiple sets of data. In at least one embodiment, GPGPU cores 2062 can physically execute SIMD4, SIMD8, and SIMD 16 instructions and logically execute SIMD I. SIMD2, and SIMD32 instructions. In at least one embodiment, SIMD instructions for GPGPU cores can be generated at compile time by a shader compiler or automatically generated when executing programs written and compiled for single program multiple data (SPMD) or SIMT architectures. In at least one embodiment, multiple threads of a program configured for an SIMT execution model can executed via a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads that perform same or similar operations can be executed in parallel via a single SIMD8 logic unit.

[0419] In at least one embodiment, memory and cache interconnect 2068 is an interconnect network that connects each functional unit of graphics multiprocessor 2034 to register file 2058 and to shared memory 2070. In at least one embodiment, memory and cache interconnect 2068 is a crossbar interconnect that allows load store unit 2066 to implement load and store operations between shared memory 2070 and register file 2058. In at least one embodiment, register file 2058 can operate at a same frequency as GPGPU cores 2062, thus data transfer between GPGPU cores 2062 and register file 2058 can have very low latency. In at least one embodiment, shared memory 2070 can be used to enable communication between threads that execute on functional units within graphics multiprocessor 2034. In at least one embodiment, cache memory 2072 can be used as a data cache for example, to cache texture data communicated between functional units and texture unit 2036. In at least one embodiment, shared memory 2070 can also be used as a program managed cache. In at least one embodiment, threads executing on GPGPU cores 2062 can programmatically store data within shared memory in addition to automatically cached data that is stored within cache memory 2072.

[0420] In at least one embodiment, a parallel processor or GPGPU as described herein is communicatively coupled to host / processor cores to accelerate graphics operations, machinelearning operations, pattern analysis operations, and various general purpose GPU (GPGPU) functions. In at least one embodiment, a GPU may be communicatively coupled to host processor / cores over a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, a GPU may be integrated on a package or chip as cores and communicatively coupled to cores over an internal processor bus / interconnect internal to a package or chip. In at least one embodiment, regardless a manner in which a GPU is connected, processor cores may allocate work to such GPU in a form of sequences of commands / instructions contained in a work descriptor. In at least one embodiment, that GPU then uses dedicated circuitry / logic for efficiently processing these commands / instructions. [0421 ] Inference and / or training logic 115 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 115 are provided herein in conjunction with FIGS. 1A and / or IB. In at least one embodiment, inference and / or training logic 115 may be used in graphics multiprocessor 2034 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0422] FIG. 21 illustrates a multi-GPU computing system 2100, according to at least one embodiment. In at least one embodiment, multi-GPU computing system 2100 can include a processor 2102 coupled to multiple general purpose graphics processing units (GPGPUs) 2106A-D via a host interface switch 2104. In at least one embodiment, host interface switch 2104 is a PCI express switch device that couples processor 2102 to a PCI express bus over which processor 2102 can communicate with GPGPUs 2106A-D. In at least one embodiment, GPGPUs 2106A-D can interconnect via a set of high-speed point-to-point GPU-to-GPU links 2116. In at least one embodiment, GPU-to-GPU links 2116 connect to each of GPGPUs 2106A-D via a dedicated GPU link. In at least one embodiment, P2P GPU links 2116 enable direct communication between each of GPGPUs 2106A-D without requiring communication over host interface bus 2104 to which processor 2102 is connected. In at least one embodiment, with GPU-to-GPU traffic directed to P2P GPU links 2116, host interface bus 2104 remains available for system memory access or to communicate with other instances of multi-GPU computing system 2100, for example, via one or more network devices. While in at least one embodiment GPGPUs 2106A-D connect to processor 2102 via host interface switch 2104, in at least one embodiment processor 2102 includes direct support for P2P GPU links 2116 and can connect directly to GPGPUs 2106A-D.

[0423] Inference and / or training logic 115 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 115 are provided herein in conjunction with FIGS. 1A and / or IB. In at least one embodiment, inference and / or training logic 115 may be used in multi-GPU computing system 1500 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0424] FIG. 22 is a block diagram of a graphics processor 2200, according to at least one embodiment. In at least one embodiment, graphics processor 2200 includes a ring interconnect 2202, a pipeline front-end 2204, a media engine 2237, and graphics cores 2280A-2280N. In at least one embodiment, ring interconnect 2202 couples graphics processor 2200 to other processing units, including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, graphics processor 2200 is one of many processors integrated within a multi-core processing system.

[0425] In at least one embodiment, graphics processor 2200 receives batches of commands via ring interconnect 2202. In at least one embodiment, incoming commands are interpreted by a command streamer 2203 in pipeline front-end 2204. In at least one embodiment, graphics processor 2200 includes scalable execution logic to perform 3D geometry processing and media processing via graphics core(s) 2280A-2280N. In at least one embodiment, for 3D geometry processing commands, command streamer 2203 supplies commands to geometry pipeline 2236. In at least one embodiment, for at least some media processing commands, command streamer 2203 supplies commands to a video front end 2234, which couples with media engine 2237. In at least one embodiment, media engine 2237 includes a Video Quality Engine (VQE) 2230 for video and image post-processing and a multi-format encode / decode (MFX) 2233 engine to provide hardware-accelerated media data encoding and decoding. In at least one embodiment, geometry pipeline 2236 and media engine 2237 each generate execution threads for thread execution resources provided by at least one graphics core 2280.

[0426] In at least one embodiment, graphics processor 2200 includes scalable thread execution resources featuring graphics cores 2280A-2280N (which can be modular and are sometimes referred to as core slices), each having multiple sub-cores 2250A-50N, 2260A-2260N (sometimes referred to as core sub-slices). In at least one embodiment, graphics processor 2200 can have any number of graphics cores 2280A. In at least one embodiment, graphics processor 2200 includes a graphics core 2280A having at least a first sub-core 2250A and a second subcore 2260A. In at least one embodiment, graphics processor 2200 is a low power processor with a single sub-core (e.g., 2250A). In at least one embodiment, graphics processor 2200 includes multiple graphics cores 2280A-2280N, each including a set of first sub-cores 2250A-2250N and a set of second sub-cores 2260A-2260N. In at least one embodiment, each sub-core in first subcores 2250A-2250N includes at least a first set of execution units 2252A-2252N and media / texture samplers 2254A-2254N. In at least one embodiment, each sub-core in second subcores 2260A-2260N includes at least a second set of execution units 2262A-2262N and samplers 2264A-2264N. In at least one embodiment, each sub-core 2250A-2250N, 2260A-2260N shares a set of shared resources 2270A-2270N. In at least one embodiment, shared resources include shared cache memory and pixel operation logic.

[0427] Inference and / or training logic 115 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 115 are provided herein in conjunction with FIGS. 1A and / or IB. In at least one embodiment, inference and / or training logic 115 may be used in graphics processor 2200 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0428] FIG. 23 is a block diagram illustrating micro-architecture for a processor 2300 that may include logic circuits to perform instructions, according to at least one embodiment. In at least one embodiment, processor 2300 may perform instructions, including x86 instructions, ARM instructions, specialized instructions for application-specific integrated circuits (ASICs), etc. In at least one embodiment, processor 2300 may include registers to store packed data, such as 64-bit wide MMX™ registers in microprocessors enabled with MMX technology from Intel Corporation of Santa Clara, Calif. In at least one embodiment, MMX registers, available in both integer and floating point forms, may operate with packed data elements that accompany single instruction, multiple data (“SIMD”) and streaming SIMD extensions (“SSE”) instructions. In at least one embodiment, 128-bit wide XMM registers relating to SSE2, SSE3, SSE4, AVX, or beyond (referred to generically as “SSEx”) technology may hold such packed data operands. In at least one embodiment, processor 2300 may perform instructions to accelerate machine learning or deep learning algorithms, training, or inferencing. (0429] In at least one embodiment, processor 2300 includes an in-order front end (“front end”) 2301 to fetch instructions to be executed and prepare instructions to be used later in a processor pipeline. In at least one embodiment, front end 2301 may include several units. In at least one embodiment, an instruction prefetcher 2326 fetches instructions from memory and feeds instructions to an instruction decoder 2328 which in turn decodes or interprets instructions. For example, in at least one embodiment, instruction decoder 2328 decodes a received instruction into one or more operations called “micro-instructions” or “micro-operations” (also called “micro ops” or “uops”) that a machine may execute. In at least one embodiment, instruction decoder 2328 parses an instruction into an opcode and corresponding data and control fields that may be used by micro-architecture to perform operations in accordance with at least one embodiment. In at least one embodiment, a trace cache 2330 may assemble decoded uops into program ordered sequences or traces in a uop queue 2334 for execution. In at least one embodiment, when trace cache 2330 encounters a complex instruction, a microcode ROM 2332 provides uops needed to complete an operation.

[0430] In at least one embodiment, some instructions may be converted into a single micro-op, whereas others need several micro-ops to complete full operation. In at least one embodiment, if more than four micro-ops are needed to complete an instruction, instruction decoder 2328 may access microcode ROM 2332 to perform that instruction. In at least one embodiment, an instruction may be decoded into a small number of micro-ops for processing at instruction decoder 2328. In at least one embodiment, an instruction may be stored within microcode ROM 2332 should a number of micro-ops be needed to accomplish such operation. In at least one embodiment, trace cache 2330 refers to an entry point programmable logic array (“PLA”) to determine a correct micro-instruction pointer for reading microcode sequences to complete one or more instructions from microcode ROM 2332 in accordance with at least one embodiment. In at least one embodiment, after microcode ROM 2332 finishes sequencing micro-ops for an instruction, front end 2301 of a machine may resume fetching micro-ops from trace cache 2330. [043 i ] In at least one embodiment, out-of-order execution engine (“out of order engine”) 2303 may prepare instructions for execution. In at least one embodiment, out-of-order execution logic has a number of buffers to smooth out and re-order flow of instructions to optimize performance as they go down a pipeline and get scheduled for execution. In at least one embodiment, out-of-order execution engine 2303 includes, without limitation, an allocator / register renamer 2340, a memory uop queue 2342, an integer / floating point uop queue 2344, a memory scheduler 2346, a fast scheduler 2302, a slow / general floating point scheduler (“slow / general FP scheduler”) 2304, and a simple floating point scheduler (“simple FP scheduler”) 2306. In at least one embodiment, fast schedule 2302, slow / general floating point scheduler 2304, and simple floating point scheduler 2306 are also collectively referred to herein as “uop schedulers 2302, 2304, 2306.” In at least one embodiment, allocator / register renamer 2340 allocates machine buffers and resources that each uop needs in order to execute. In at least one embodiment, allocator / register renamer 2340 renames logic registers onto entries in a register file. In at least one embodiment, allocator / register renamer 2340 also allocates an entry for each uop in one of two uop queues, memory uop queue 2342 for memory operations and integer / floating point uop queue 2344 for non-memory operations, in front of memory scheduler 2346 and uop schedulers 2302, 2304, 2306. In at least one embodiment, uop schedulers 2302, 2304, 2306, determine when a uop is ready to execute based on readiness of their dependent input register operand sources and availability of execution resources uops need to complete their operation. In at least one embodiment, fast scheduler 2302 may schedule on each half of a mam clock cycle while slow / general floating point scheduler 2304 and simple floating point scheduler 2306 may schedule once per main processor clock cycle. In at least one embodiment, uop schedulers 2302, 2304, 2306 arbitrate for dispatch ports to schedule uops for execution.

[0432] In at least one embodiment, execution block 2311 includes, without limitation, an integer register file-bypass network 2308, a floating point register file / bypass network (“FP register file / bypass network”) 2310, address generation units (“AGUs”) 2312 and 2314, fast Arithmetic Logic Units (ALUs) (“fast ALUs”) 2316 and 2318, a slow Arithmetic Logic Unit (“slow ALU”) 2320, a floating point ALU (“FP”) 2322, and a floating point move unit (“FP move”) 2324. In at least one embodiment, integer register file / bypass network 2308 and floating point register file / bypass network 2310 are also referred to herein as “register files 2308, 2310.” In at least one embodiment, AGUSs 2312 and 2314, fast ALUs 2316 and 2318, slow ALU 2320, floating point ALU 2322, and floating point move unit 2324 are also referred to herein as “execution units 2312, 2314, 2316, 2318, 2320, 2322, and 2324.” In at least one embodiment, execution block 2311 may include, without limitation, any number (including zero) and type of register files, bypass networks, address generation units, and execution units, in any combination.

[0433] In at least one embodiment, register networks 2308, 2310 may be arranged between uop schedulers 2302, 2304, 2306, and execution units 2312, 2314, 2316, 2318, 2320, 2322, and 2324. In at least one embodiment, integer register file / bypass network 2308 performs integer operations. In at least one embodiment, floating point register file / bypass network 2310 performs floating point operations. In at least one embodiment, each of register networks 2308, 2310 may include, without limitation, a bypass network that may bypass or forward just completed results that have not yet been written into a register file to new dependent uops. In at least one embodiment, register networks 2308, 2310 may communicate data with each other. In at least one embodiment, integer register file / bypass network 2308 may include, without limitation, two separate register files, one register file for a low-order thirty-two bits of data and a second register file for a high order thirty-two bits of data. In at least one embodiment, floating point register file / bypass network 2310 may include, without limitation, 128-bit wide entries because floating point instructions typically have operands from 64 to 128 bits in width.

[0434] In at least one embodiment, execution units 2312, 2314, 2316, 2318, 2320, 2322, 2324 may execute instructions. In at least one embodiment, register networks 2308, 2310 store integer and floating point data operand values that micro-instructions need to execute. In at least one embodiment, processor 2300 may include, without limitation, any number and combination of execution units 2312, 2314, 2316, 2318, 2320, 2322, 2324. In at least one embodiment, floating point ALU 2322 and floating point move unit 2324, may execute floating point, MMX, SIMD, AVX and SSE, or other operations, including specialized machine learning instructions. In at least one embodiment, floating point ALU 2322 may include, without limitation, a 64-bit by 64-bit floating point divider to execute divide, square root, and remainder micro ops. In at least one embodiment, instructions involving a floating point value may be handled with floating point hardware. In at least one embodiment, ALU operations may be passed to fast ALUs 2316, 2318. In at least one embodiment, fast ALUS 2316, 2318 may execute fast operations with an effective latency of half a clock cycle. In at least one embodiment, most complex integer operations go to slow ALU 2320 as slow ALU 2320 may include, without limitation, integer execution hardware for long-latency type of operations, such as a multiplier, shifts, flag logic, and branch processing. In at least one embodiment, memory load / store operations may be executed by AGUs 2312, 2314. In at least one embodiment, fast ALU 2316, fast ALU 2318, and slow ALU 2320 may perform integer operations on 64-bit data operands. In at least one embodiment, fast ALU 2316, fast ALU 2318, and slow ALU 2320 may be implemented to support a variety of data bit sizes including sixteen, thirty-two, 128, 256, etc. In at least one embodiment, floating point ALU 2322 and floating point move unit 2324 may be implemented to support a range of operands having bits of various widths, such as 128-bit wide packed data operands in conjunction with SI MD and multimedia instructions. [0435 ] In at least one embodiment, uop schedulers 2302, 2304, 2306 dispatch dependent operations before a parent load has finished executing. In at least one embodiment, as uops may be speculatively scheduled and executed in processor 2300, processor 2300 may also include logic to handle memory misses. In at least one embodiment, if a data load misses in a data cache, there may be dependent operations in flight in a pipeline that have left a scheduler with temporarily incorrect data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use incorrect data. In at least one embodiment, dependent operations might need to be replayed and independent ones may be allowed to complete. In at least one embodiment, schedulers and a replay mechanism of at least one embodiment of a processor may also be designed to catch instruction sequences for text string comparison operations. [0436 j In at least one embodiment, “registers” may refer to on-board processor storage locations that may be used as part of instructions to identify operands. In at least one embodiment, registers may be those that may be usable from outside of a processor (from a programmer’s perspective). In at least one embodiment, registers might not be limited to a particular type of circuit. Rather, in at least one embodiment, a register may store data, provide data, and perform functions described herein. In at least one embodiment, registers described herein may be implemented by circuitry within a processor using any number of different techniques, such as dedicated physical registers, dynamically allocated physical registers using register renaming, combinations of dedicated and dynamically allocated physical registers, etc. In at least one embodiment, integer registers store 32-bit integer data. A register file of at least one embodiment also contains eight multimedia SIMD registers for packed data. [0437 ] Inference and / or training logic 115 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 115 are provided herein in conjunction with FIGS. 1A and / or IB. In at least one embodiment portions or all of inference and / or training logic 115 may be incorporated into execution block 2311 and other memory or registers shown or not shown. For example, in at least one embodiment, training and / or inferencing techniques described herein may use one or more of ALUs illustrated in execution block 2311. Moreover, weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure ALUs of execution block 2311 to perform one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0438] FIG. 24 illustrates a deep learning application processor 2400, according to at least one embodiment. In at least one embodiment, deep learning application processor 2400 uses instructions that, if executed by deep learning application processor 2400, cause deep learning application processor 2400 to perform some or all of processes and techniques described throughout this disclosure. In at least one embodiment, deep learning application processor 2400 is an application-specific integrated circuit (ASIC). In at least one embodiment, application processor 2400 performs matrix multiply operations either “hard-wired” into hardware as a result of performing one or more instructions or both. In at least one embodiment, deep learning application processor 2400 includes, without limitation, processing clusters 2410(1)-2410(12), Inter-Chip Links (“ICLs”) 2420(1)-2420(12), Inter-Chip Controllers (“ICCs”) 2430(1)-2430(2), high-bandwidth memory second generation (“HBM2”) 2440(1)-2440(4), memory controllers (“Mem Ctrlrs”) 2442(1)-2442(4), high bandwidth memory physical layer (“HBM PHY”) 2444(1)-2444(4), a management-controller central processing unit (“management-controller CPU”) 2450, a Serial Peripheral Interface, Inter-Integrated Circuit, and General Purpose Input / Output block (“SPI, I2C, GPIO”) 2460, a peripheral component interconnect express controller and direct memory access block (“PCIe Controller and DMA”) 2470, and a sixteen-lane peripheral component interconnect express port (“PCI Express x 16”) 2480.

[0439] In at least one embodiment, processing clusters 2410 may perform deep learning operations, including inference or prediction operations based on weight parameters calculated one or more training techniques, including those described herein. In at least one embodiment, each processing cluster 2410 may include, without limitation, any number and type of processors. In at least one embodiment, deep learning application processor 2400 may include any number and type of processing clusters. In at least one embodiment, Inter-Chip Links 2420 are bi-directional. In at least one embodiment, Inter-Chip Links 2420 and Inter-Chip Controllers 2430 enable multiple deep learning application processors 2400 to exchange information, including activation information resulting from performing one or more machine learning algorithms embodied in one or more neural networks. In at least one embodiment, deep learning application processor 2400 may include any number (including zero) and type of ICLs 2420 and ICCs 2430.

[0440] In at least one embodiment, HBM2s 2440 provide a total of 32 Gigabytes (GB) of memory. In at least one embodiment, HBM2 2440(i) is associated with both memory controller 2442(i) and HBM PHY 2444(i) where “i” is an arbitrary integer. In at least one embodiment, any number of HBM2s 2440 may provide any type and total amount of high bandwidth memory and may be associated with any number (including zero) and type of memory controllers 2442 and HBM PHYs 2444. In at least one embodiment, SPI, I2C, GPIO 2460, PCIe Controller and DMA 2470, and / or PCIe 2480 may be replaced with any number and type of blocks that enable any number and type of communication standards in any technically feasible fashion. [0441 ] Inference and / or training logic 115 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 115 are provided herein in conjunction with FIGS. 1A and / or IB. In at least one embodiment, deep learning application processor is used to train a machine learning model, such as a neural network, to predict or infer information provided to deep learning application processor 2400. In at least one embodiment, deep learning application processor 2400 is used to infer or predict information based on a trained machine learning model (e.g., neural network) that has been trained by another processor or system or by deep learning application processor 2400. In at least one embodiment, processor 2400 may be used to perform one or more neural network use cases described herein.

[0442] FIG. 25 is a block diagram of a neuromorphic processor 2500, according to at least one embodiment. In at least one embodiment, neuromorphic processor 2500 may receive one or more inputs from sources external to neuromorphic processor 2500. In at least one embodiment, these inputs may be transmitted to one or more neurons 2502 within neuromorphic processor 2500. In at least one embodiment, neurons 2502 and components thereof may be implemented using circuitry or logic, including one or more arithmetic logic units (ALUs). In at least one embodiment, neuromorphic processor 2500 may include, without limitation, thousands or millions of instances of neurons 2502, but any suitable number of neurons 2502 may be used. In at least one embodiment, each instance of neuron 2502 may include a neuron input 2504 and a neuron output 2506. In at least one embodiment, neurons 2502 may generate outputs that may be transmitted to inputs of other instances of neurons 2502. For example, in at least one embodiment, neuron inputs 2504 and neuron outputs 2506 may be interconnected via synapses 2508.

[0443] In at least one embodiment, neurons 2502 and synapses 2508 may be interconnected such that neuromorphic processor 2500 operates to process or analyze information received by neuromorphic processor 2500. In at least one embodiment, neurons 2502 may transmit an output pulse (or “fire” or “spike”) when inputs received through neuron input 2504 exceed a threshold. In at least one embodiment, neurons 2502 may sum or integrate signals received at neuron inputs 2504. For example, in at least one embodiment, neurons 2502 may be implemented as leaky integrate-and-fire neurons, wherein if a sum (referred to as a “membrane potential”) exceeds a threshold value, neuron 2502 may generate an output (or “fire”) using a transfer function such as a sigmoid or threshold function. In at least one embodiment, a leaky integrate-and-fire neuron may sum signals received at neuron inputs 2504 into a membrane potential and may also apply a decay factor (or leak) to reduce a membrane potential. In at least one embodiment, a leaky integrate-and-fire neuron may fire if multiple input signals are received at neuron inputs 2504 rapidly enough to exceed a threshold value (i.e., before a...

Claims

1. A processor comprising:one or more circuits to cause a first one or more portions of at least one tensor to be accessed from a memory using a first technique and a second one or more portions of the at least one tensor to be accessed from the memory using a second technique in response to a user causing the processor to combine the first and second techniques.

2. The processor of claim 1, wherein the first technique is to cause the one or more circuits to: load data from a plurality of cells corresponding to the first one or more portions into a cache, wherein the first one or more portions comprises one or more tiles of predetermined dimensions, and wherein the cache is accessible by one or more processing threads of the processor.

3. The processor of claim 2, wherein the one or more circuits are further to: perform convolution operations between a plurality of cell patches in the plurality of cells and a convolutional filter to generate a first output, wherein the convolution operations for each cell in the first output is performed by a separate processing thread of the one or more processing threads.

4. The processor of claim 3, wherein the convolutional filter comprises a plurality of weight values for a convolution layer of a convolutional neural network model.

5. The processor of any of claims 2-4, wherein the one or more circuits are further to: load padding elements or zero-padding cells corresponding to the one of the first one or more portions into the cache.

6. The processor of any of claims 2-5, wherein the one or more circuits are further to:make a determination that the second one or more portions have smaller dimensions than the predetermined dimensions; andaccess the second one or more portions of the at least one tensor from the memory responsive to the determination.

7. The processor of any preceding claim, wherein the second technique is to cause the one or more circuits to:apply a transformation to one or more blocks of the at least one tensor to unroll the one or more blocks into at least one two-dimensional (2D) tensor;load the at least one 2D tensor into a cache; andperform, using data in the cache, a convolution operation between the convolutional filter and the at least one tensor, via general matrix multiply, to obtain a second output.

8. The processor of any preceding claim, wherein the one or more circuits are further to:generate a first output using the first technique;generate a second output using the second technique; andcombine the first output and the second output to generate an output tensor.

9. The processor of any preceding claim, wherein the tensor represents one of: an input layer of a convolutional neural network or a feature map of an inner layer of the convolutional neural network.

10. The processor of any preceding claim, wherein the processor is arranged to determine the second one or more portions using a remainder operation.

11. The processor of claim 10, wherein the processor is arranged to divide the tensorinto one or more tiles, wherein the second one or more portions are remainder elements of the tensor that did not evenly divide into a tile.

12. A method, comprising:accessing, by a processor, a first one or more portions of at least one tensor from a memory using a first technique and a second one or more portions of the at least one tensor fromthe memory using a second technique in response to an input to combine the first and second techniques.

13. The method of claim 12, wherein the first technique comprises loading data from a plurality of cells corresponding to the first one or more portions into a cache, wherein the first one or more portions comprises one or more tiles of predetermined dimensions, and wherein the cache is accessible by one or more processing threads of the processor.

14. The method of claim 13, further comprising: performing convolution operations between a plurality of cell patches in the plurality of cells and a convolutional filter to generate a first output, wherein the convolution operations for each cell in the first output is performed by a separate processing thread of the one or more processing threads.

15. The method of claim 14, wherein the convolutional filter comprises a plurality of weight values for a convolution layer of a convolutional neural network model.

16. The method of any of claims 13-15, further comprising: loading padding elements corresponding to the one of the first one or more portions into the cache.

17. The method of any of claims 13-16, further comprising:making a determination that the second one or more portions have smaller dimensions than the predetermined dimensions; andaccessing the second one or more portions of the at least one tensor from the memory responsive to the determination.

18. The method of any of claims 12-17, further comprising:applying a transformation to one or more blocks of the at least one tensor to unroll the one or more blocks into at least one two-dimensional (2D) tensor;loading the at least one 2D tensor into a cache; andperforming, using data in the cache, a convolution operation between the convolutional filter and the at least one tensor, via general matrix multiply, to obtain a second output.

19. The method of any of claims 12-18, further comprising:generating a first output using the first technique;generating a second output using the second technique; andcombining the first output and the second output to generate an output tensor.

20. The method of any of claims 12-19, wherein the tensor represents one of: an input layer of a convolutional neural network or a feature map of an inner layer of the convolutional neural network.

21. The method of any of claims 12-20, comprising determining the second one or more portions using a remainder operation.

22. The method of claim 21, comprising dividing the tensor into one or more tiles, and determining the second one or more portions from remainder elements of the tensor that did not evenly divide into a tile.

23. A system, comprisinga memory; andone or more processors, the one or more processors operatively coupled with the memory, to perform operations comprising:determining a first one or more portions of at least one tensor and a second one or more portions of the at least one tensor;accessing, from the memory, the first one or more portions using a first technique to obtain a first output;accessing, from the memory, the second one or more portions using a second technique to obtain a second output; andgenerating an output tensor by combining the first and second outputs.

24. The system of claim 23, wherein the first technique comprises loading data from a plurality of cells corresponding to one of the first one or more portions into a cache, wherein thefirst one or more portions comprises one or more tiles of predetermined dimensions, and wherein the cache is accessible by one or more processing threads of the one or more processors.

25. The system of claim 23 or claim 24, wherein the operations further comprise: performing convolution operations between a plurality of cell patches in the plurality of cells and a convolutional filter to generate the first output, wherein the convolution operations for each cell in the first output is performed by a separate processing thread of the one or more processing threads.

26. The system of claim 25, wherein the convolutional filter comprises a plurality of weight values for a convolution layer of a convolutional neural network model.

27. The system of any of claims 24-26, wherein the operations further comprise: loading padding elements corresponding to the one of the first one or more portions into the cache.

28. The system of any of claims 24-27, further comprising:making a determination that the second one or more portions have smaller dimensions than the predetermined dimensions; andaccessing the second one or more portions of the at least one tensor from the memory responsive to the determination.

29. The system of any of claims 23-28, wherein the operations further comprise: applying a transformation to one or more blocks of the at least one tensor to unroll the one or more blocks into at least one two-dimensional (2D) tensor;loading the at least one 2D tensor into a cache; andperforming, using data in the cache, a convolution operation between the convolutional filter and the at least one tensor, via general matrix multiply, to obtain a second output.

30. The system of any of claims 23-29, wherein the operations further comprise: generating the first output using the first technique;generating the second output using the second technique; andcombining the first output and the second output to generate an output tensor.

31. The system of any of claims 23-30, wherein the tensor represents one of: an input layer of a convolutional neural network or a feature map of an inner layer of the convolutional neural network.

32. The processor of any of claims 23-31, wherein the one or more processors are arranged to determine the second one or more portions using a remainder operation.

33. The processor of claim 32, wherein the one or more processors are arranged to divide the tensor into one or more tiles, wherein the second one or more portions are remainder elements of the tensor that did not evenly divide into a tile.

34. An autonomous vehicle comprising:one or more cameras; andone or more processors according to any of claims 1 to 11, the processors being operatively coupled to the one or more cameras to capture at least one image, and the one or more processors to use one or more trained neural networks to process at least one tensor corresponding to the at least one image by:accessing a first one or more portions of the at least one tensor from a memory using a first technique and a second one or more portions of the at least one tensor from the memory using a second technique in response to an input to combine the first and second techniques.

Images