Communication system

Abstract

Disclosed is a communication system 300 consisting of a host device 302 and a set of peripheral devices 314, 316, 318. The host device has a peripheral addressing terminal 310, and communication bus t

Description

[0001] The present invention is directed towards a communication system comprising a host device and a plurality of peripheral devices. BACKGROUND

[0002] Peripheral devices can communicate with one or more host devices over a serial protocol such as the Serial Peripheral Interface (SPI) protocol or the Inter-Integrated Circuit (I2C) protocol. These protocols enable several peripheral devices (traditionally referred to as slave devices) to be connected to a host device (traditionally referred to as a master device) over one or more shared communication lines.

[0003] In a typical, existing, SPI implementation as shown in FIG. 1, a host device is connected to a plurality (three in this example) of peripheral devices 104, 106, 108. The host device 102 includes a serial clock terminal SCK, a data output terminal MOSI, a data input terminal MISO, and a plurality (three in this example) of chip select terminals CS1, CS2, CS3. The peripheral devices 104, 106, 108 each include a serial clock terminal SCK connected to the serial clock terminal SCK of the host device 102, a data input terminal MOSI connected to the data output terminal MOSI of the host device 102, a data output terminal MISO, connected to the data input terminal MISO of the host device, and a chip select terminal CS1, CS2, CS3.

[0004] The chip select terminal CS1, CS2, CS3 is connected to one of the chip select terminals CS1, CS2, CS3 of the host device 102 such that each peripheral device 104, 106, 108 receives a dedicated chip select signal. The chip select terminal CS1 of peripheral device 104 is connected to chip select terminal CS1 of the host device 102. The chip select terminal CS2 of peripheral device 106 is connected to chip select terminal CS2 of the host device 102. The chip select terminal CS3 of peripheral device 108 is connected to chip select terminal CS3 of the host device 102. The host device 102 selects one of the peripheral devices 104, 106, 108 by toggling one of the chip select terminals CS1, CS2, CS3.

[0005] This SPI implementation requires a dedicated chip select line for each peripheral device. It can be challenging to provide a high number of chip select lines in a communication system both in terms of cost and complexity. This is a particular problem in wearable technology, such as clothing with integrated sensors, where it is advantageous to reduce the number of signal lines in the article to minimise the effect the electronics have on the comfort and appearance of the article.

[0006] An alternative SPI implementation daisy-chains peripheral devices together such that the output of the first peripheral device in the chain connects to the input of the second peripheral device in the chain and so on. A single chip select line connects to all of the peripheral devices and controls all of the peripheral devices to be active at the same time. Only the first peripheral device in the chain is connected to the MOSI line to receive commands from the host device. Every other peripheral device receives data from the preceding peripheral device in the chain. Only the last peripheral device in the chain is connected to the MISO line to send data to the host device.

[0007] Daisy-chaining SPI devices avoids the need for a dedicated chip select line for each peripheral device. However, not all SPI devices support daisy-chaining, making it difficult to implement practically, and it requires that each SPI device uses the clock in the same way. There is also an increased risk of data loss, noise, and reduced data rate as compared to systems which selectively address peripheral devices.

[0008] US Patent Application Publication No. US 2009 / 125657 A1 discloses a serial peripheral interface circuit including a host, a plurality of slaves, and a decoder. A data output terminal, a data input terminal, and a serial clock terminal of the host are connected to a data input terminal, a data output terminal, and a serial clock terminal of each of the slaves. A slave select terminal of the host is connected to a data receive terminal of the decoder. GPIO pins of the host are connected to corresponding input terminals of the decoder. A select terminal of each slave is connected to a corresponding output terminal of the decoder. The address generated by the GPIO pins controls the decoder, so that the select terminal of the host can be connected to a corresponding slave device via the decoder.

[0009] This design reduces the number of chip select terminals on the host device, but still requires chip select lines for each of the peripheral devices.

[0010] US Patent Application Publication No. US2009193165 A1 discloses a communication circuit of SPI devices including a master device and a plurality of slave devices. One of the slave devices includes a plurality of general purpose input / output (GPIO) pins. The chip select terminal of the master device is connected to the control terminal of the slave device having the GPIO pins. The GPIO pins respectively are connected to the control terminals of other slave devices. The slave device having the GPIO pins receives an instruction having an address signal from the master device and compares whether the addresses are identical. If so, the slave device having the GPIO pins communicates with the master device. Otherwise, the slave device transmits the address signal to the control terminals of the other slave devices through the GPIO pins. The other slave devices compare the address signal with their own address. The slave device having the identical address communicates with the master device.

[0011] This design reduces the number ofchip select terminals on the host device, but still requires additional signal lines to enable the address to be transferred from the peripheral device having the GPIO pins to the other peripheral devices. In addition, this design requires that the peripheral devices have microcontrollers.

[0012] UK Patent Application Publication No. GB2391423 A discloses a private branch exchange (PBX) comprising a central processing unit and a plurality of modules connectable to the PBX at selectively addressable primary locations. The modules communicate with the central processing unit through a primary bus using SPI communication protocol. Primary address registered at the primary locations store a primary address code of each primary location which identifies the module connected at the primary location. A comparator compares a primary address code on chip select lines of the primary bus with the stored primary address code in the primary address register for determining if the module is being addressed.

[0013] This design still requires three chip select lines for conveying the 3 bit primary address code and six terminals are required for each peripheral device to receive the stored primary address code from the primary address register and the primary address code from the host device. The design is limited to uniquely addressing only eight devices due to the 3 bit address code used.

[0014] UK Patent Application Publication No. 2589359 A discloses a sensor device, wearable article, system and method. The sensor device comprises a buffer to store time-series sensor data sensed by a sensor module and an input-output interface arranged to send and receive data over a bidirectional line such as a single wire connection. The bidirectional line may be incorporated into a wearable article such as clothes, headwear or footwear whereby the conductor is incorporated into the fibre or yarn and the sensor device or system be removable or incorporated into the wearable article. The sensor device may be provided in a system further comprising multiple sensors and a master device, whereby it is arranged to send time series-data or compressed representation of the data sensed by the sensor. A programmable and erasable non-volatile memory receives and stores an identifier for the sensor device. The sensor module may be a motion, electropotential, electroimpedance, chemical, optical, or bio-sensor module. The sensor device may receive power over the inputoutput interface and store the power in a power source such as a capacitor or rechargeable battery.

[0015] In I2C communication buses, the host device is connected to the peripheral devices by a serial clock line and a data line. Device addressing is achieved by sending an address for the desired peripheral device over the data line. I2C peripheral devices typically have addresses made up of a combination of fixed bits set by the manufacturer and one or more hardware-selectable bits which can be set either to have a value of “0” or “1” by wiring one or more address pins either to ground or the voltage line of the communication system.

[0016] The host device sends message over I2C which are broken up into frames of data. Each message has an address frame that contains the binary address of the peripheral device. The peripheral device with the corresponding address is able to communicate with the host device while the other peripheral devices are disabled from doing so until they are addressed by the host device.

[0017] It can be challenging to incorporate multiple peripheral devices onto the same I2C bus particularly when some or all of the peripheral devices are of the same type and have the same fixed address bits. For example, if an I2C peripheral device has four fixed bits and three hardware-selectable bits then only eight of the same type of I2C peripheral devices can be included on the I2C bus without address conflicts. In practice, many I2C peripheral devices have only 1 or 2 hardware-selectable address bits which even further limits the number of the same I2C peripheral devices that can be incorporated onto the I2C bus to 2 or 4 before address conflicts occur.

[0018] It is known to use I2C switches and multiplexers to resolve address conflict issues. This requires multiple I2C buses making the system more complex. This is a particular problem in wearable technology, such as clothing with integrated sensors, where it is advantageous to reduce the number of signal lines in the article to minimise the effect the electronics have on the comfort and appearance of the article.

[0019] It is also known to use dynamic addressing to resolve address conflict issues in I2C communications. In dynamic addressing, the host device has General Purpose Output (GPO) pins which connect to the addressable hardware pins of the I2C peripheral devices. The host device sets all of the addressable hardware pins to logic ‘0’ except for the peripheral device that is desired to be addressed.

[0020] FIG. 2A and FIG. 2B show an example existing communication system that uses dynamic addressing. A host device 202 is connected to a plurality (four in this example) of peripheral devices 204, 206, 208, 210 by an I2C bus (not shown) and GPO lines.

[0021] All of the peripheral devices 204, 206, 208, 210 in this example have the same fixed address and each have one hardware addressable pin A0 to allow for address configuration. The hardware addressable pins A0 are each connected to one of the GPO pins on the host device 202. The peripheral device 204 is connected to the GPO-O pin of the host device 202. The peripheral device 206 is connected to the GPO-1 pin of the host device 202. The peripheral device 208 is connected to the GPO-2 pin of the host device 202. The peripheral device 210 is connected to the GPO-3 pin of the host device 202.

[0022] In FIG. 2A the host device 202 selects the peripheral device 204 by setting the GPO-O pin to high and the other GPO pins (GPO-1, GPO-2, GPO-3) to low.

[0023] In FIG. 2B the host device 202 selects the peripheral device 208 by setting the GPO-2 pin to high and the other GPO pins (GPO-O, GPO-1, GPO-3) to low.

[0024] A problem with this approach is that it requires multiple GPO pins on the host device as well as multiple signal lines to be added to the communication bus. This solution is similar to SPI addressing which uses a chip select line for each peripheral device to be addressed.

[0025] It is an object of the present disclosure to provide an improved communication system including a host device and a plurality of peripheral devices particularly for use with SPI or I2C communication protocols. SUMMARY

[0026] According to the present disclosure, there is provided a communication system as set forth in the appended independent claim. Other features of the invention will be apparent from the dependent claims, and the description which follows.

[0027] According to a first aspect of the disclosure, there is provided a communication system.

[0028] The communication system comprises a host device comprising a peripheral device addressing terminal, and a plurality of communication bus terminals comprising at least one data terminal and a serial clock terminal.

[0029] The communication system comprises a plurality of peripheral devices.

[0030] Each of the peripheral devices comprises a module comprising at least one data terminal connected to the at least one data terminal of the host device, a serial clock terminal connected to the serial clock terminal of the host device, and a configuration terminal.

[0031] Each of the peripheral devices comprises an addressable switch comprising: a memory storing a primary identifier for the peripheral device, a peripheral device addressing terminal connected to the peripheral device addressing terminal of the host device, and a configuration terminal connected to the configuration terminal of the module.

[0032] The addressable switch is arranged to receive, via the peripheral device addressing terminal, a primary identifier, compare the received primary identifier to the primary identifier stored in the memory, and configure, via the configuration terminal, a communication property of the module based on the comparison, wherein the communication property defines, at least in part, how the module communicates with the host device.

[0033] Advantageously, the peripheral devices comprise addressable switches which store primary identifiers for the peripheral devices. The host device sends a primary identifier to the peripheral devices via the peripheral device addressing terminal. The addressable switches configure communication properties of the modules based on the received primary identifier. This can involve configuring addresses of the modules such as for use in I2C systems to avoid bus address conflicts or configuring the modules to either be enabled to or disabled from communicating with the host device such as for use in SPI systems. This approach enables the host select to individually select a peripheral device without requiring multiple GPO lines (as in the existing dynamic addressing I2C approach) or multiple chip select signal lines (as in existing SPI approaches) connecting the host device to the peripheral devices. Instead, only a single-wire is needed for the selection of individual peripheral devices.

[0034] The communication property of the module may comprise an address of the module. The addressable switch may be arranged to set the address of the module to a first address responsive to the received primary identifier matching the primary identifier stored in the memory. The addressable switch may be arranged to set the address of the module to a second address responsive to the received primary identifier being different to the primary identifier stored in the memory.

[0035] Advantageously, the addressable switches are able to configure address of the modules which are used to communicate with the host device. In Two-Wire Interfaces (TWI) such as I2C, the host device sends messages to the peripheral devices on the communication bus. The messages are broken up into frames of data. Each message has an address frame that contains the binary address of the peripheral device the message is intended for. The messages are sent to all of the devices on the communication bus, but only the device with the corresponding address responds. There is a problem as outlined previously where two or more devices on the bus have the same address. The claimed arrangement advantageously solves this problem by allowing the addresses of the modules to be dynamically changed. The host device can, via the addressable switch, set the address of the module that it wants to communicate with to the first address, the addresses of the other devices can be set to the second address.

[0036] The addresses of the modules may comprise a plurality of fixed bits and at least one hardware-selectable bit. The addressable switches may configure the addresses of the modules by setting the value the at least one hardware-selectable bit. The plurality of peripheral devices may all have the same combination of fixed bits fortheir addresses.

[0037] The plurality of communication bus terminals may comprise a plurality of Inter-Integrated Circuit (I2C) terminals. The module may be an I2C module. The addressable switch may configure the address of the module via the configuration terminal. Other Two-Wire Interface protocols may be used. The configuration terminals in this example are address terminals and the addressable switch sets the logic level of the address terminal of the I2C module. This enables dynamic addressing to avoid address conflicts in an I2C bus such as by setting the hardware-selectable address bits for all but one of the I2C modules with the same fixed address bits to 'O’and setting the hardware-selectable address bit for the remaining I2C module to 'T. The host device can then communicate with the desired I2C modules by sending messages with address frames having the fixed address bits and the hardware-selectable address bit'T.

[0038] The configuration terminals of the module and the addressable switch maybe chip select terminals. The addressable switch may be arranged to send a chip select signal to the module via the chip select terminal to configure the communication property of the module. The chip select signal may have either an enable state to enable the module to communicate with the host device via the at least one data terminal or a disable state to disable the SPI module from communicating with the host device via the at least one data terminal.

[0039] The addressable switch may be arranged to set the chip select signal to the enable state responsive to receiving, via the peripheral device addressing terminal, a primary identifier from the host device that matches the primary identifier stored in the memory.

[0040] Advantageously, the peripheral devices comprise addressable switches which store primary identifiers for the peripheral devices. The host device sends a primary identifier to the peripheral devices via the peripheral device addressing terminal. The addressable switch with the corresponding primary identifier stored in memory enables the module to communicate with the host. This approach enables the host select to individually select a peripheral device without requiring multiple chip select signal lines connecting the host device to the peripheral devices. Instead, only a single-wire is needed for the selection of individual peripheral devices.

[0041] The addressable switch may be arranged to set the chip select signal to the disable state responsive to receiving, via the peripheral device addressing terminal, a primary identifier from the host device that is different to the primary identifier stored in the memory.

[0042] Advantageously, the host device may send a primary identifier for the peripheral device to be selected to all of the peripheral devices (via their addressable switches). The peripheral device with the corresponding primary identifier stored in memory enables their module to communicate with the host device while the other peripheral devices disable their modules from communicating with the host device by setting the chip select signal to the disable state.

[0043] The plurality of communication bus terminals may comprise a plurality of Serial Peripheral Interface, SPI, terminals. The at least one data terminal may comprise a data output terminal and a data input terminal. The module may be an SPI module, and the at least one data terminal comprises a data input terminal connected to the data output terminal of the host device, and a data output terminal connected to the data input terminal of the host device.

[0044] The memory of the addressable switch may be a non-volatile memory. The non-volatile memory may be a read-only memory (ROM). The primary identifier may be lasered onto the ROM by the manufacturer of the addressable switch.

[0045] The host device may communicate with the peripheral devices via the peripheral device addressing terminal using a single-wire communication protocol. The communication via the peripheral device addressing terminal may use a single-wire bus. The host device may comprise only one peripheral device addressing terminal. The addressable switches may each comprise only one peripheral device addressing terminal. Communication between the host device and addressable switches may use only a single-wire bus.

[0046] The host device is connected to the peripheral devices by a communication bus which may comprise an I2C bus (or other two-wire bus) or a SPI bus and is also connected to the peripheral device by a single-wire bus. The modules may be connected to the host device by the communication bus and the addressable switches may be connected to the host device by the single-wire bus. The modules may not be connected to the singlewire bus and the addressable switches may not be connected to the communication bus. The communication bus may comprise a clock line and one data line (for I2C) or two data lines (for SPI). The communication bus may only comprise two or three signal lines. The communication bus is not required to have chip select signal lines. The number of signal lines connecting the host device to the peripheral devices may only be three (e.g., data, clock and single-wire for I2C) or four (e.g., MOSI, MISO, clock, and single-wire for SPI).

[0047] The addressable switch of at least one, some, or each, of the peripheral devices may be arranged to provide a secondary identifier identifying a characteristic of the peripheral device.

[0048] Advantageously, the addressable switch stores a primary identifier that may uniquely identify the peripheral device and also provides a secondary identifier which identifies a characteristic of the peripheral device. The characteristic may identify the location of the peripheral device in the communication system.

[0049] The addressable switch may comprise a plurality of secondary identifier terminals. The logic levels of the secondary identifier terminals may collectively define the secondary identifier. The addressable switch may read the outputs of the plurality of secondary identifier terminals to obtain the secondary identifier. The logic levels of each of the secondary identifier terminals may define 1 bit of the secondary identifier.

[0050] Each of the plurality of secondary identifier terminals may be wired either to a ground line or a power line of the communication system to collectively define the secondary identifier.

[0051] Advantageously, the secondary identifier is hardwired by selectively wiring the secondary identifier terminals either to ground or to the power line. Each of the secondary identifier terminals is set either to a logic LOW or logic HIGH value and represents either a binary value of 0 or 1. The secondary identifier can be formed during the stage of placing components onto a printed circuit board of the peripheral device and does not require bespoke PCB layouts for each peripheral device or for the peripheral devices to be individually programmed.

[0052] At least one of the peripheral devices may comprise a power switch connected to the addressable switch. The addressable switch may be arranged to control the power switch to transition the module between different power states. The power switch may transition the module between on and off states. The module may be switched off when not in use to reduce the power consumption of the communication system. The module may be power cycled.

[0053] The module of at least one of the peripheral devices may comprise a sensor. The sensor may comprise one or more of a temperature sensor, a humidity sensor, a motion sensor, an electropotential sensor, an electroimpedance sensor, an optical sensor, and an acoustic sensor. The temperature sensor may be arranged to measure an ambient temperature, a skin temperature of a human or animal body, or a core temperature of a human or animal body. The temperature sensor may measure the temperature of the peripheral device. The humidity sensor may be arranged to measure humidity or skin-surface moisture levels for a human or animal body. The motion sensor may comprise one or more of an accelerometer, a gyroscope, and a magnetometer. The motion sensor may comprise an inertial measurement unit. The electropotential sensor may be arranged to perform one or more bioelectrical measurements. The electropotential sensor may comprise one or more of an electrocardiography (ECG) sensor, an electrogastrography (EGG) sensor, an electroencephalography (EEG) sensor, and an electromyography (EMG) sensor. The electroimpedance sensor may be arranged to perform one or more bioimpedance measurements. Bioimpedance sensors can include one or more of plethysmography sensors (e.g., for respiration), body composition sensors (e.g., hydration, fat, etc.), and electroimpedance tomography (EIT) sensors. An optical sensor may comprise a photoplethysmography (PPG) sensor. The sensor may comprise a gas sensor (e.g., VOC sensor or CO2 sensor), a noise sensor, a vibration sensor, or a posture sensor.

[0054] The communication system may be incorporated into a wearable article such as a garment or a part thereof. Wearable article refers to any form of article which may be worn by a user such as a smart watch, fitness tracker, necklace, ring, garment, bracelet, or glasses. The wearable article may be a textile article. The wearable article may be a garment. The garment may refer to an item of clothing or apparel. The garment may be a top. The top may be a shirt, t-shirt, blouse, sweater, jacket / coat, or vest. The garment may be a dress, garment brassiere (e.g., sports bra or t-shirt bra), shorts, pants, arm or leg sleeve, vest, jacket / coat, glove, armband, underwear, headband, hat / cap, collar, wristband, armband, chestband, waistband, stocking, sock, or shoe, athletic clothing, personal protective equipment, including hard hats, swimwear, wetsuit, or dry suit.

[0055] The wearable article (e.g., a garment) may be constructed from a woven or a non-woven material. The wearable article may be constructed from natural fibres, synthetic fibres, or a natural fibre blended with one or more other materials which can be natural or synthetic. The yarn may be cotton. The cotton may be blended with polyester and / or viscose and / or polyamide according to the application. Silk may also be used as the natural fibre. Cellulose, wool, hemp, and jute are also natural fibres that may be used in the wearable article. Polyester, polycotton, nylon and viscose are synthetic fibres that may be used in the wearable article.

[0056] The garment may be a tight-fitting garment or a loose-fitting (e.g., freeform garment). A tight-fitting garment helps ensure that the sensor devices of the garment are held in contact with or in proximity to a skin surface of the wearer. The tight-fitting garment may be a compression garment. The tight-fitting garment may be an athletic garment such as an elastomeric athletic garment. A loose-fitting garment is generally more comfortable to wear over extended time periods and during sleep.

[0057] The communication system may further comprise a memory device connected to the host device via the peripheral device addressing terminal. The memory device may be connected to the host device via the single-wire bus of the communication system that also connects the addressable switches to the host device.

[0058] According to a second aspect of the disclosure, there is provided a device comprising: a module comprising at least one data terminal, a serial clock terminal, and a configuration terminal; and an addressable switch comprising: a memory storing a primary identifier for the peripheral device, a peripheral device addressing terminal, and a configuration terminal connected to the configuration terminal of the module. The addressable switch is arranged to receive, via the peripheral device addressing terminal, a primary identifier from a host device, compare the received primary identifier to the primary identifier stored in the memory, and configure, via the configuration terminal, a communication property of the module based on the comparison, wherein the communication property defines, at least in part, how the module communicates with the host device.

[0059] The device may be useable in the communication system of the first aspect of the disclosure. That is, the device may be a peripheral device of the communication system.

[0060] According to a third aspect of the disclosure, there is provided a communication system.

[0061] The communication system comprises a host device comprising a peripheral device addressing terminal, and a plurality of Serial Peripheral Interface, SPI, terminals comprising a data output terminal, a data input terminal, and a serial clock terminal.

[0062] The communication system comprises a plurality of peripheral devices.

[0063] Each of the peripheral devices comprises an SPI module comprising a data input terminal connected to the data output terminal of the host device, a data output terminal connected to the data input terminal of the host device, a serial clock terminal connected to the serial clock terminal of the host device, and a chip select terminal.

[0064] Each of the peripheral devices comprises an addressable switch comprising: a memory storing a primary identifier for the peripheral device, a peripheral device addressing terminal connected to the peripheral device addressing terminal of the host device, and a chip select terminal connected to the chip select terminal of the SPI module.

[0065] The addressable switch is arranged to send a chip select signal to the SPI module via the chip select terminal, the chip select signal having either an enable state to enable the SPI module to communicate with the host device via one or more of the data output terminal and the data input terminal or a disable state to disable the SPI module from communicating with the host device via one or more of the data output terminal and the data input terminal.

[0066] The addressable switch is arranged to set the chip select signal to the enable state responsive to receiving, via the peripheral device addressing terminal, a primary identifier from the host device that matches the primary identifier stored in the memory.

[0067] According to a fourth aspect of the disclosure, there is provided a communication system.

[0068] The communication system comprises a host device comprising a peripheral device addressing terminal, and a plurality of Inter-Integrated Circuit (I2C) terminals comprising a data terminal and a serial clock terminal.

[0069] The communication system comprises a plurality of peripheral devices.

[0070] Each of the peripheral devices comprises an I2C module comprising a data terminal connected to the data terminal of the host device, a serial clock terminal connected to the serial clock terminal of the host device, and address terminal.

[0071] Each of the peripheral devices comprises an addressable switch comprising: a memory storing a primary identifier for the peripheral device, a peripheral device addressing terminal connected to the peripheral device addressing terminal of the host device, and an address terminal connected to the address terminal of the I2C module.

[0072] The addressable switch is arranged to configure an address of the I2C module via the address terminal.

[0073] According to a fifth aspect of the disclosure, there is provided a communication system comprising: a host device; a plurality of wires forming a first communication bus; a single-wire forming a single-wire bus; a plurality of peripheral devices each comprising: a module connected to the host device by the first communication bus; and an addressable switch connected to the host device by the single-wire bus, wherein the addressable switch comprises a plurality of identifier terminals, and wherein the logic levels of the identifier terminals collectively define an identifier, and wherein the addressable switch is arranged to output the identifier to the host device.

[0074] Advantageously, the addressable switch provides an identifier by reading the output of the identifier terminals. The identifier indicates the location of the peripheral device in the communication system.

[0075] In this example, the module is not required to be an SPI module. Other serial communication protocols such as I2C may be supported by the module. The addressable switch is not required to have a memory storing a primary identifier. Addressing of the individual peripheral devices may be achieved using an alternative approach such as the approaches described in the background section of this document.

[0076] Each of the plurality of identifier terminals may be wired either to a ground line or a power line of the communication system to collectively define the secondary identifier.

[0077] The communication system of the fifth aspect of the disclosure may comprise any of the features of the communication system of the first aspect of the disclosure.

[0078] According to a sixth aspect of the disclosure, there is provided a device comprising: a module; and an addressable switch comprising a plurality of identifier terminals, and wherein the logic levels of the identifier terminals collectively define an identifier, and wherein the addressable switch is arranged to o utput the identifier to a host device.

[0079] The device may be useable in the communication system of the fifth aspect of the disclosure. That is, the device may be a peripheral device of the communication system. BRIEF DESCRIPTION OF THE DRAWINGS

[0080] To easily identify the discussion of any particular element or act, the most significant digit or digits in a reference number refer to the figure number in which that element is first introduced.

[0081] FIG. 1 illustrates a prior art communication system.

[0082] FIG. 2A illustrates a prior art communication system.

[0083] FIG. 2B illustrates a prior art communication system.

[0084] FIG. 3 illustrates an example communication system according to aspects of the present disclosure.

[0085] FIG. 4 illustrates an aspect of the communication system of FIG. 3.

[0086] FIG. 5 illustrates an example communication system according to aspects of the present disclosure. DETAILED DESCRIPTION

[0087] The following description with reference to the accompanying drawings is provided to assist in a comprehensive understanding of various embodiments of the disclosure as defined by the claims and their equivalents. It includes various specific details to assist in that understanding but these are to be regarded as merely exemplary. Accordingly, those of ordinary skill in the art will recognize that various changes and modifications of the various embodiments described herein can be made without departing from the scope and spirit of the disclosure. In addition, descriptions of well-known functions and constructions may be omitted for clarity and conciseness.

[0088] The terms and words used in the following description and claims are not limited to the bibliographical meanings but are merely used by the inventor to enable a clear and consistent understanding of the disclosure. Accordingly, it should be apparent to those skilled in the art that the following description of various embodiments of the disclosure is provided for illustration purpose only and not for the purpose of limiting the disclosure as defined by the appended claims and their equivalents.

[0089] It is to be understood that the singular forms “a,” “an,” and “the” include plural referents unless the context clearly dictates otherwise.

[0090] FIG. 3 shows an example communication system 300 according to aspects of the present disclosure.

[0091] The communication system 300 comprises a host device 302. The host device 302 comprises a plurality of Serial Peripheral Interface, SPI, terminals. The SPI terminals comprise a serial clock terminal 304, a data output terminal 306, and a data input terminal 308. The host device 302 further comprises a peripheral device addressing terminal 310. The host device 302 also comprises a controller 312.

[0092] The communication system 300 further comprises a plurality (three in this example) of peripheral devices 314, 316, 318.

[0093] The peripheral devices 314, 316, 318 each comprise an SPI module 320, 322, 324 and an addressable switch 326, 328, 330.

[0094] The SPI module 320, 322, 324 communicates with the host device 302 using the SPI communication protocol. The SPI module 320, 322, 324 comprises a serial clock terminal connected to the serial clock terminal 304 of the host device 302 via the clock signal line (labelled “CLK” in the drawing). The SPI module 320, 322, 324 comprises a data input terminal connected to the data output terminal 306 of the host device 302 via a signal line of the communication bus that enables data to be sent from the host device 302 to peripheral devices in the communication system 300. The signal line is commonly referred to as the Master Out Slave In “MOSI” and is labelled “MOSI” in the drawing. The SPI module 324 comprises a data output terminal connected to the data input terminal 308 of the host device 302 via a signal line of the communication bus that enables data to be received by the host device 302 from the peripheral devices. The signal line is commonly referred to as the Master In Slave Out and is labelled “MISO” in the drawing.

[0095] The addressable switch 326, 328, 330 comprises a peripheral device addressing terminal connected to the peripheral device addressing terminal 310 of the host device 302 via a signal line of the communication bus that enables bidirectional communication between the host device 302 and the peripheral devices 314, 316, 318. The communication over the signal line utilises a single-wire communication protocol such as the 1-Wire communication protocol and is labelled “1-Wire” in the drawing. The 1-Wire communication protocol is not required in all examples, and other protocols such as Local Interconnect Network (LIN) or a proprietary singlewire communication protocol may be used. 1-Wire is generally preferred as it supports a greater number of peripheral devices as compared to a LIN bus which is limited to fifteen nodes. The single-wire communication protocol may support data and power transfer or just data transfer. Just allowing data transfer over the singlewire line can allow for faster data transmission rates due to not required power to be transferred as well.

[0096] The host device 302 is connected to the peripheral devices 314, 316, 318 using a communication bus comprising four signal lines (labelled CLK, MOSI, MISO, 1-Wire in the drawings). The communication bus includes an SPI bus (CLK, MOSI, MISO) for SPI communications between the host device 302 and peripheral devices 314, 316, 318 and a single-wire bus (1-Wire) for communication between the host device 302 and the peripheral devices 314, 316, 318 over a single-wire communication protocol. For convenience, the single-wire bus is generally referred to as a 1-wire bus below as preferred implementations use the 1-wire communication protocol. It is not required that the single-wire bus uses the 1-wire communication protocols and other singlewire communication protocols such as LIN may be used. The SPI module 320, 322, 324 is connected to the host device 302 by the SPI bus. The addressable switch 326, 328, 330 is connected to the host device 302 over the 1-wire bus. The SPI module 320, 322, 324 is not connected to the 1-wire bus and the addressable switch 326, 328, 330 is not connected to the SPI bus.

[0097] Importantly, and unlike existing SPI implementations, one or a plurality of chip select terminals on the host device are not utilised and the SPI bus does not include a chip select signal line. Instead, and as explained below, individual selection of the peripheral devices for communication with the host device is achieved utilising the single-wire bus. The communication system 300 only requires four signal lines to enable individual selection of the peripheral devices and SPI communication between the host device and the selected peripheral device. This reduces the complexity of the communication system as multiple chip select signal lines are not required on the SPI bus and the peripheral devices do not need to be daisy-chained. Moreover, the host device 302 is not required to have multiple chip select terminals which simplifies the construction of the host device 302.

[0098] The addressable switch 326, 328, 330 stores a primary identifier for the peripheral device 314, 316, 318. The addressable switch 326, 328, 330 stores the primary identifier in a memory. The memory is non-volatile and preferably read-only and non-erasable. The primary identifier is a unique code that in preferred implementations is set at manufacture of the addressable switch by lasering the unique code on to the ROM. The primary identifier is a unique code that uniquely identifies the peripheral device.

[0099] The addressable switch 326, 328, 330 further comprises a configuration terminal in the form of a chip select terminal that is connected to a configuration terminal in the form of a chip select terminal of the SPI module 320, 322, 324 by a chip select signal line labelled “CS1”, “CS2”, “CSX” in the drawing. The addressable switch 326, 328, 330 sends a chip select signal to the SPI module 320, 322, 324 via the chip select terminal. The chip select signal configures a communication property of the SPI module and in particular whether the SPI module is enabled or disabled from communicating with the host device. The chip select signal is set either to an enable state to enable the SPI module 320, 322, 324 to communicate with the host device 302 or to a disable state to disable the SPI module 320, 322, 324 from communicating with the host device 302. The SPI module 320, 322, 324 communicates with the host device 302 via one or both of the data output terminal and the data input terminal.

[0100] The chip select terminals of the SPI modules 320, 322, 324 are not connected to chip select terminals of the host device 302. It this therefore not required to provide N chip select signal lines in the communication bus to control the selection of the peripheral devices, where N is the number of peripheral devices in the communication system 300. Instead, individual peripheral device selection is achieved through a single signal line which connects the peripheral device addressing terminal 310 of the host device 302 to the addressable switches 326, 328, 330 of the peripheral devices 314, 316, 318. This reduces the number of signal lines required to individually select peripheral devices.

[0101] For each peripheral device 314, 316, 318, the SPI module 320, 322, 324 and addressable switch 326, 328, 330 are provided in the same hardware package and typically on the same printed circuit board. The chip select signal lines are generally short conductive traces and do not increase the complexity of the communication bus as compared to conventional chip select signals that run throughout the communication bus from the host device to the peripheral devices.

[0102] Peripheral device selection is achieved by the host device 302 sending a primary identifier for the peripheral device 314, 316, 318 it wishes to establish communication with via the peripheral device addressing terminal 310. The primary identifier is sent to all of the peripheral devices 314, 316, 318 over the 1-wire bus and is received by the addressable switches 326, 328, 330. The received primary identifier is compared to the primary identifier stored in the memory of each addressable switch 326, 328, 330.

[0103] If the received primary identifier matches the primary identifier stored in the memory of the addressable switch 326, 328, 330, the chip select signal is set to an enable state to enable the SPI module 320, 322, 324 to communicate with the host device 302 via one or more of the data output terminal and the data input terminal.

[0104] If the received primary identifier is different to the primary identifier stored in the memory of the addressable switch 326, 328, 330, the chip select signal is set to a disable state to disable the SPI module 320, 322, 324 from communicating with the host device 302 via one or more of the data output terminal and the data input terminal.

[0105] For example, the host device 302 sends a primary identifier for peripheral device 314 to the plurality of peripheral devices 314, 316, 318 over the 1-wire bus. As the received primary identifier matches the primary identifier stored in the memory of the addressable switch 326, the addressable switch 326 sets the chip select signal to the enable state to enable the SPI module 320 to communicate with the host device 302. The other addressable switches 328, 330 set the chip select signals to the disable state to disable the SPI module 322, 324 from communicating with the host device 302. Setting the chip select signal to the enable or disable state may mean that the chip select signal is maintained in the enable or disable state.

[0106] In addition, to storing the primary identifier, the addressable switches 326, 328, 330 also provide a secondary identifier. The primary identifier identifies (uniquely) the addressable switch I peripheral device while the secondary identifier identifies a characteristic of the peripheral device 314, 316, 318. In some implementations, the identified characteristic is the location of the peripheral device 314, 316, 318 in the communication system 300.

[0107] In some implementations, the secondary identifier is provided by the addressable switch 326, 328, 330 reading the output of a plurality of secondary identifier terminals. The logic levels of the secondary identifier terminals collectively define the secondary identifier. The output of each of the secondary identifier terminals represents 1 bit of the secondary identifier. The peripheral devices 314, 316, 318 further comprise a hardware address 332, 334, 336 connected to a plurality of secondary identifier terminals of the addressable switch 326, 328, 330. The addressable switch 326, 328, 330 reads the outputs from the plurality of location addressing terminals to determine the secondary identifier. The hardware address 332, 334, 336 is explained in more detail in relation to FIG. 4.

[0108] The addressable switch 326, 328, 330 may be the DS2408 8 channel 1-Wire to GPIO expansion chip manufactured by Analog Devices Inc. Other addressable switches may be used. Other addressable switches may be used. For example, the addressable switch 226, 228, 230 may be the TCA5405 low voltage 5-bit selftimed, single-wire output expander manufactured by Texas Instruments. The addressable switch 226, 228, 230 may be referred to as a single-wire expansion chip.

[0109] The host device 302 comprises a power terminal 338 connected to a power line, a DC voltage line, (labelled “SYS V” in the drawing) of the communication system 300 and a ground terminal 340 connected to a ground line (labelled “GND" in the drawing) of the communication system 300.

[0110] . The peripheral devices 314, 316, 318 are powered by the host device 302 over the power line. The host device 102 provides a system wide (DC) voltage supply to the communication bus. The voltage supply depends on the application but examples range between 1.8 V and 24 V. The peripheral devices 314, 316, 318 are not required to have a battery which simplifies their construction although a secondary power source (such as a capacitor) may be provided. The SPI modules 320, 322, 324 are connected to the power and ground lines. The addressable switches 326, 328, 330 can be connected to the power line but may also or separately be powered over the 1-wire bus. The addressable switches 326, 328, 330 are connected to the ground line.

[0111] The peripheral devices 314, 316, 318 further comprise a power switch 342, 344, 346 that is controlled by the addressable switch 326, 328, 330 to selectively change the power state of the SPI module 320, 322, 324. The power switch 342, 344, 346 can be controlled to switch on / off the SPI module 320, 322, 324 based on an instruction received by the addressable switch 326, 328, 330 via the host device 302. This can be beneficial to prevent the SPI modules 320, 322, 324 from drawing power when not needed and can also be used to power cycle the SPI modules 320, 322, 324 when, for example, an error is detected. An example power switch 242, 244, 246 is the DMG3415U P-channel enhancement mode MOSFET manufactured by Diodes Incorporated.

[0112] On occasion, a peripheral device 314, 316, 318 may enter an erroneous state due to various factors, such as general defects, aging, degradation, spurious voltage fluctuations, or firmware commands that cause sensor malfunctions. To address this, one solution would be to power cycle the entire communication bus. However, this would cause all of the peripheral devices to temporarily switch off which could lead to data being lost. In addition, the peripheral devices may require configuration information from the host device which would have to be resent in the event of all peripheral devices power cycling.

[0113] To mitigate the problem while preserving data integrity, the host device 302 employs a command sent via the 1-wire bus to the malfunctioning peripheral device, instructing it to perform a power reset. The addressable switch controls the power switch to power cycle the SPI module. The other peripheral devices are able to remain in operation while the power cycling of the individual peripheral device is being performed. If needed, the addressable switches can also be power cycled by sending a reset pulse over the 1-wire bus.

[0114] The communication system 300 of the present disclosure is advantageous as the communication bus is only required to have four signal lines even if connection to and independent control of multiple peripheral devices is required. It is not required to daisy-chain peripheral devices or have multiple chip select signal lines extending between the host device and peripheral devices to individually select different peripheral devices. The communication system 300 is particularly advantageous in wearable technology such as smart clothing where it is desirable to limit the number of wires that have to be integrated into the wearable article.

[0115] The communication system of the present disclosure does not require the peripheral devices 314, 316, 318 to have a microcontroller. It is advantageous to avoid including microcontrollers in the peripheral devices 314, 316, 318 for several reasons.

[0116] Firstly, adding a microcontroller to every node of a bus can significantly increase the cost of the system. Microcontrollers include not just the cost of the chip itself, but also additional components like memory, oscillator, and power supply circuitry. This cost can become substantial when multiplied across multiple nodes.

[0117] Secondly, each microcontroller would require power to operate, even when idle or in ‘sleep’. Having a microcontroller on every node can lead to increased power consumption compared to simpler 'passive' nodes. This can be a concern, particularly in a battery-powered systems or when energy efficiency is a priority.

[0118] Thirdly, integrating microcontrollers into each node of a bus network introduces a heightened level of system complexity. Each microcontroller may undergo programming, configuration, and testing to ensure proper functionality within the bus. Consequently, this complexity can result in extended development time, increased challenges during debugging, and extra manufacturing time (and cost) due to program and test procedures.

[0119] While it is technically feasible to perform firmware upgrades in the field on microcontrollers situated on a bus via either wired (existing wired data bus or a dedicated programming bus) or wireless connection, such an approach adds an unnecessary layer of complexity. In the event that an upgrade fails for a specific device while the remainder of the bus has successfully updated, additional code would need to be developed and thoroughly tested to ensure backward compatibility. Failure to address this issue could render the bus inoperable.

[0120] Fourthly, microcontrollers come in various packages, and depending on the chosen microcontroller, they will require additional space on each node. Even if a microcontroller with a physically small package size and low power requirements is used, an external crystal will still typically be required to enable the microcontroller to operate. Crystals can also be problematic components to encapsulate for a wearable application.

[0121] Fifthly, the presence of multiple microcontrollers increases the number of components that need to be maintained and monitored. Failures or malfunctions in individual microcontrollers can impact the functionality of the entire system, making troubleshooting and maintenance problematic. This is amplified in an environment that requires devices to have ATEX certification. For safety reasons, the general rule is that any safety / mission critical devices are controlled by an analogue approach, rather than relying on code. While there are extenuating circumstances where this can apply, the testing to prove this, multiplied across a number of nodes would make the system cost prohibitive.

[0122] Sixthly, when a bus network requires expansion. Adding new nodes with microcontrollers may become complicated. Coordinating the behaviour of additional microcontrollers and ensuring compatibility with existing nodes can be complex, potentially limiting the scalability of the system.

[0123] Finally, in real-time systems, having a microcontroller on every node can introduce variability in the response times of different nodes. Synchronisation and coordination between micros become critical to maintain the required real-time performance, and the overhead introduced by the microcontrollers may affect the overall system. This is even more evident in a system while multiple IMUs are being addressed.

[0124] The communication system 300 of the present disclosure which uses addressable switches in the peripheral devices to enable peripheral devices to be selectively addressed is beneficial in avoiding the need for microcontrollers on the peripheral devices.

[0125] In an example use case, on initialisation of the host device 302, the host device 302, via the controller 312, will initialise the SPI communication bus and the 1 -wire bus.

[0126] If the primary identifiers of the peripheral devices 314, 316, 318 are not already known to the controller 312, the controller 312 will use the 1-wire bus to perform a search for peripheral devices to discover the peripheral devices 314, 316, 318. The search algorithm used may be a binary tree search where branches are followed until a primary identifier (leaf) is found. Subsequent searches then take the other branch paths until all of the peripheral devices 314, 316, 318 on the communication system are discovered. The searching for nodes on a 1-wire bus is already known to the skilled person so a detailed explanation of the search algorithm is omitted.

[0127] Once all peripheral devices are identified, the host device 102 interrogates each peripheral device in turn over the 1-wire bus to obtain the secondary identifiers. The controller 312 of the host device 102 associates each primary identifier with the corresponding secondary identifier.

[0128] The scanning for peripheral devices 314, 316, 318 is not required to be performed every time the host device 302 is activated. The scan for peripheral devices could be performed once (e.g., at the factory), and the details of the peripheral devices (primary identifier, secondary identifier, and other information such as properties of the SPI module such as properties of any sensors of the SPI module) can be stored on a memory device on the 1-wire bus. The host device 302 can read the details from the memory device to identify the peripheral devices in the communication system 300. The host device 302 can use the information stored in the memory device to determine whether any of the peripheral devices are malfunctioning.

[0129] The memory device could be a 1-wire EEPROM. The memory device may have a built-in secure authenticator such as the DS28E35 manufactured by Analog Devices Inc. In this way, the host device 302 can subsequently identify the peripheral devices on the bus by simply reading the details from the memory device. The use of a secure authenticator can help ensure that only approved devices are used in the communication system 300.

[0130] Each addressable switch 326, 326, 328 will obtain their secondary identifier, such as by reading the output of the secondary identifier terminals, and will provide their primary identifier and secondary identifier to the host device 302 over the 1-wire bus.

[0131] By way of example, the communication system 300 can be used in a garment for monitoring the activity of a wearer. The SPI modules 320, 322, 324 of the peripheral devices 314, 316, 318 comprise sensors such as motion sensors. The motion sensors may comprise one or more of an accelerometer, a gyroscope, and a magnetometer.

[0132] The peripheral devices 314, 316, 318 and signal and power lines of the communication bus are attached to the garment and are not intended to be removable in normal use. The host device 102 is releasably coupled to the garment and has an interface (e.g., USB Type C) for releasably electrically connecting to the signal and power lines to bring the host device 102 into communication with the peripheral devices 314, 316, 318. The peripheral devices 314, 316, 318 are distributed around the garment to desired measurement locations such as on the wrist, arm, chest, or back.

[0133] The secondary identifiers identify the location of the peripheral devices 314, 316, 318 on the garment. For example, the secondary identifier for peripheral device 314 identifies that the peripheral device 314 is located on the left wrist region of the garment, the secondary identifier for peripheral device 316 identifies that the peripheral device 316 is located on the left forearm region of the garment, and the second identifier for peripheral device 318 identifies that the peripheral device 318 is located on the left upper arm region of the garment.

[0134] Associating the primary identifier with the secondary identifier enables the host device 302 to determine which location on the body the sensor data received from a particular peripheral device 314, 316, 318 relates to. This is particularly useful for activity tracking using motion sensors as it enables the host device 302 to identify whether the sensor data received relates to hand, wrist, arm (or other body parts) motion. In addition, the host device 302 can identify the location of a malfunctioning peripheral device 314, 316, 318 on the communication system 300 which simplifies maintenance.

[0135] The components (SPI module, hardware address, addressable switch) of each peripheral device 314, 316, 318 are provided in the same hardware package. The SPI module, addressable switch, and other components may be provided on the same printed circuit board (PCB such as a flexible PCB). The chip select signal lines (CS1, CS2, CS3) can be implemented as conductive traces on the printed circuit boards. The peripheral devices 314, 316, 318 may be spaced apart from one another in the communication system 300.

[0136] FIG. 4 shows the addressable switches 326, 328 for two of the peripheral devices 314, 316. Other components are omitted for simplicity.

[0137] The addressable switches 326, 328 each comprise a peripheral device addressing terminal (labelled “1” in the drawing). The peripheral device addressing terminals are connected to the signal line labelled “1 -Wire” to enable the selection of individual peripheral devices as explained above.

[0138] The addressable switches 326, 328 each further comprise a chip select terminal (labelled “16" in the drawing) which enables chip select signals to be sent to the corresponding SPI module as explained above.

[0139] The addressable switches 326, 328 each further comprise a power terminal (labelled “15" in the drawing) which connects the addressable switch 326, 328 to the power line (labelled “3.3V” in the drawing). This is not required in all examples as the addressable switches 326, 328 may be powered over the 1 -wire bus.

[0140] The addressable switches 326, 328 each further comprise a plurality (six in this example) of secondary identifier terminals (labelled “9” to “14” in the drawing) which are connected to the hardware address 332, 334. The hardware address 332, 334 refers to a series of wires and resistors that tie the secondary identifier terminals either to ground or the power line. When the outputs of the secondary identifier terminals are read by the addressable switch 326, 328 they either have a binary value of 0 if tied to ground or 1 if tied to the power line. This provides a 6 bit binary address that allows for up to 64 unique secondary identifiers.

[0141] In this example, the secondary identifier terminals of the addressable switch 326 are all tied to ground giving a secondary identifier of 000000 in binary. Meanwhile, the location addressing terminals 9 to 12 of the addressable switch 328 are tied to ground and the location addressing terminals 13 and 14 are tied to the power line. This gives a secondary identifier of 000011 in binary.

[0142] As explained above, the secondary identifier identifies a characteristic of the peripheral device. This can be location of the peripheral device in the communication system. The following table provides examples of how different secondary identifiers can be used to identify the location of peripheral devices on the body. This is useful particularly when the communication system is incorporated into a garment. BINARY HEX Node Name 000000 0x0 Left Hand 000001 0x1 Left Wrist 000010 0x2 Left Forearm 000011 0x3 Left Elbow 000100 0x4 Left Upper Arm 111100 0x3C Right Shin 111110 0x3E Right Ankle 111111 0x3F Right Heel

[0143] Each of the peripheral devices 314, 316, 318 can comprise the same components and can be manufactured using the same PCB layout. During the pick and place process of assembling the components for the peripheral device on the PCB, the placement of the resistors define the secondary identifier. Unique PCBs are not required for each peripheral device and it is not required to program the secondary identifier onto the peripheral device. This simplifies the manufacturing process for the peripheral devices and reduces costs.

[0144] FIG. 5 shows an example communication system 500 according to aspects of the present disclosure.

[0145] The communication system 500 comprises a host device 502. The host device 502 comprises a plurality of Inter-Integrated Circuit, I2C, terminals. The I2C terminals comprise a serial clock terminal 506, and a data terminal 508. The host device 502 further comprises a peripheral device addressing terminal 510. The host device 502 also comprises a controller 504.

[0146] The communication system 500 further comprises a plurality (three in this example) of peripheral devices 512, 514, 516.

[0147] The peripheral devices 512, 514, 516 each comprise an I2C module 518, 520, 522 and an addressable switch 524, 526, 528.

[0148] The I2C module 518, 520, 522 communicates with the host device 502 using the I2C communication protocol. The I2C module 518, 520, 522 comprises a serial clock terminal connected to the serial clock terminal 506 of the host device 502 via the clock signal line (labelled “SCL” in the drawing). The I2C module 518, 520, 522 comprises a data terminal connected to the data terminal 508 of the host device 502 via a signal line (labelled “SDA” in the drawing) of the communication bus. The signal line SDA enables data to be sent between the host device 502 and the peripheral devices 512, 514, 516.

[0149] The addressable switch 524, 526, 528 comprises a peripheral device addressing terminal connected to the peripheral device addressing terminal 510 of the host device 502 via a signal line of the communication bus that enables bidirectional communication between the host device 502 and the peripheral devices 512, 514, 516. The communication over the signal line utilises a single-wire communication protocol such as the 1-Wire communication protocol and is labelled “1-Wire” in the drawing. The 1-Wire communication protocol is not required in all examples, and other protocols such as Local Interconnect Network (LIN) may be used. Although 1-Wire is generally preferred as it supports a greater number of peripheral devices as compared to a LIN bus which is limited to fifteen nodes.

[0150] The host device 502 is connected to the peripheral devices 512, 514, 516 using a communication bus comprising three signal lines (labelled SCL, SDA, 1-Wire in the drawings). The communication bus includes an I2C bus (SCL, SDA) for I2C communications between the host device 502 and peripheral devices 512, 514, 516 and a single-wire bus (1-Wire) for communication between the host device 502 and the peripheral devices 512, 514, 516 over a single-wire communication protocol. For convenience, the single-wire bus is generally referred to as a 1-wire bus below as preferred implementations use the 1 -wire communication protocol. It is not required that the single-wire bus uses the 1-wire communication protocols and other single-wire communication protocols such as LIN may be used. The I2C module 518, 520, 522 is connected to the host device 502 by the I2C bus. The addressable switch 524, 526, 528 is connected to the host device 502 over the 1 -wire bus. The I2C module 518, 520, 522 is not connected to the 1-wire bus and the addressable switch 524, 526, 528 is not connected to the I2C bus.

[0151] Importantly, and unlike dynamic addressing I2C implementations, individual addressing lines are not required between the host device and the I2C modules. Instead, and as explained below, individual selection of the peripheral devices for communication with the host device is achieved utilising the single-wire bus. The communication system 500 only requires three signal lines to enable individual selection of the peripheral devices and I2C communication between the host device and the selected peripheral device. This avoids address conflicts and reduces the complexity of the communication system as multiple addressing lines and address terminal on the host device 502 are not required.

[0152] The addressable switch 524, 526, 528 stores a primary identifier for the peripheral device 512, 514, 516. The addressable switch 524, 526, 528 stores the primary identifier in a memory. The memory is non-volatile and preferably read-only and non-erasable. The primary identifier is a unique code that in preferred implementations is set at manufacture of the addressable switch by lasering the unique code on to the ROM. The primary identifier is a unique code that uniquely identifies the peripheral device.

[0153] The addressable switch 524, 526, 528 further comprises a configuration terminal in the form of an address terminal that is connected to a configuration terminal (address terminal) of the I2C module 518, 520, 522 by an address line labelled “ADDR” in the drawing. The addressable switch 524, 526, 528 toggles the address terminal of the I2C module 518, 520, 522 to either a logic HIGH or logic LOW state to dynamically configure the address of the I2C module 518, 520, 522.

[0154] For each peripheral device 512, 514, 516, the I2C module 518, 520, 522 and addressable switch 524, 526, 528 are provided in the same hardware package and typically on the same printed circuit board. The address lines are generally short conductive traces and do not increase the complexity of the communication bus as compared to conventional dynamic addressing of I2C devices.

[0155] Each of the I2C modules 518, 520, 522 have address comprising fixed, factory set, address bits and one or more hardware selectable address bits which are configured to have either logic LOW ('0') or logic HIGH ('T) values based on the configuration of the one or more address terminals of the I2C modules 518, 520, 522. In this example, if the I2C modules 518, 520, 522 have a plurality of address terminals, only one of the address terminals needs to be connected to the addressable switch. The other address terminals can either be wired to the power line or ground to have fixed values.

[0156] In an example implementation, the addressable switches 524, 526, 528 initially set each of the address terminals of the I2C modules 518, 520, 522 to logic Low ('0'). If all of the I2C modules 518, 520, 522 have the same fixed address, then this means that all of the I2C modules 518, 520, 522 have the same address (e.g., 0x6A). The host device 502 sends a primary identifier for one of the peripheral devices (e.g., peripheral device 512) it wishes to establish communication with via the peripheral device addressing terminal 510. The primary identifier is sent to all of the peripheral devices 512, 514, 516 over the 1-wire bus and is received by the addressable switches 524, 526, 528. The received primary identifier is compared to the primary identifier stored in the memory of each addressable switch 524, 526, 528.

[0157] The received primary identifier corresponds to the primary identifier of addressable switch 524. The addressable switch 524 sets its address line to logic High (' 1') to change the address of the I2C module 518 to 0x6B. The host device 502 can then communicate with the I2C module 518 using conventional I2C addressing over the I2C bus. As only I2C module 518 has address 0x6B there are no addressing conflicts.

[0158] When the host device 502 has finished communicating with I2C module 518, the host device 502 can revert the address of I2C module 518 back to 0x6A by instructing the addressable switch 524 to toggle the address line to logic Low ('0'). The host device 502 can then configure a different I2C module (e.g., I2C module 520) for addressing by sending the primary address for the addressable switch (e.g., addressable switch 526) via the peripheral device addressing terminal 510. The addressable switch 526 then toggles the address line to logic HIGH ('1') to configure the address for I2C module 520 to 0x6B.

[0159] It will be appreciated that not all peripheral devices in the communication system need to have the addressable switch and other features disclosed herein. This arrangement is beneficial for avoiding addressing conflicts which can occur when a plurality of devices with the same fixed address and a limited number of addressing terminals are provided on the bus. For example, if the communication system comprises seven of the same make and model of motion sensor (each with the same fixed address bits and one address terminal) and one gas sensor (with a different fixed address to the motion sensor), then the peripheral devices with the motion sensors will comprise the addressable switch arrangement while the gas sensor is not required to have the addressable switch arrangement, The addressable switch arrangement may still be beneficial for location identification and power management as explained below.

[0160] In addition, to storing the primary identifier, the addressable switches 524, 526, 528 also provide a secondary identifier. The primary identifier identifies (uniquely) the addressable switch / peripheral device while the secondary identifier identifies a characteristic of the peripheral device 512, 514, 516. In some implementations, the identified characteristic is the location of the peripheral device 512, 514, 516 in the communication system 500.

[0161] In some implementations, the secondary identifier is provided by the addressable switch 524, 526, 528 reading the output of a plurality of secondary identifier terminals. The logic levels of the secondary identifier terminals collectively define the secondary identifier. The output of each of the secondary identifier terminals represents 1 bit of the secondary identifier. The peripheral devices 512, 514, 516 further comprise a hardware address 530, 532, 534 connected to a plurality of secondary identifier terminals of the addressable switch 524, 526, 528. The addressable switch 524, 526, 528 reads the outputs from the plurality of location addressing terminals to determine the secondary identifier. The hardware address 530, 532, 534 is explained in more detail in relation to FIG. 4. In FIG. 4, the configuration terminals 16 are shown as chip select terminals ‘OS’ as this figure shows an SPI-based implementation. For I2C communication the configuration terminals 16 will be address terminals.

[0162] The addressable switch 524, 526, 528 may be the DS2408 8 channel 1 -Wire to GPIO expansion chip manufactured by Analog Devices Inc. Other addressable switches may be used as explained above.

[0163] The host device 502 comprises a power terminal 536 connected to a power line, a DC voltage line, (labelled “SYS V” in the drawing) of the communication system 500 and a ground terminal 538 connected to a ground line (labelled “GND” in the drawing) of the communication system 500.

[0164] The peripheral devices 512, 514, 516 are powered by the host device 502 over the power line. The host device 502 provides a system wide (DC) voltage supply to the communication bus. The voltage supply depends on the application but examples range between 1.8 V and 24 V. The peripheral devices 512, 514, 516 are not required to have a battery which simplifies their construction although a secondary power source (such as a capacitor) may be provided. The I2C modules 518, 520, 522 are connected to the power and ground lines. The addressable switches 524, 526, 528 can be connected to the power line but may also or separately be powered over the 1-wire bus. The addressable switches 524, 526, 528 are connected to the ground line.

[0165] The peripheral devices 512, 514, 516 further comprise a power switch 540, 542, 544 that is controlled by the addressable switch 524, 526, 528 to selectively change the power state of the I2C module 518, 520, 522. The power switch 540, 542, 544 can be controlled to switch on / off the I2C module 518, 520, 522 based on an instruction received by the addressable switch 524, 526, 528 via the host device 502. This can be beneficial to prevent the I2C modules 518, 520, 522 from drawing power when not needed and can also be used to power cycle the I2C modules 518, 520, 522 when, for example, an error is detected.

[0166] On occasion, a peripheral device 512, 514, 516 may enter an erroneous state due to various factors, such as general defects, aging, degradation, spurious voltage fluctuations, or firmware commands that cause sensor malfunctions. To address this, one solution would be to power cycle the entire communication bus. However, this would cause all of the peripheral devices to temporarily switch off which could lead to data being lost.

[0167] To mitigate the problem while preserving data integrity, the host device 502 employs a command sent via the 1-wire bus to the malfunctioning peripheral device, instructing it to perform a power reset. The addressable switch controls the power switch to power cycle the I2C module. The other peripheral devices are able to remain in operation while the power cycling of the individual peripheral device is being performed. If needed, the addressable switches can also be power cycled by sending a reset pulse over the 1 -wire bus.

[0168] The communication system 500 of the present disclosure is advantageous as the communication bus is only required to have three signal lines even if connection to and independent control of multiple peripheral devices is required. The communication system 500 is particularly advantageous in wearable technology such as smart clothing where it is desirable to limit the number of wires that have to be integrated into the wearable article.

[0169] The communication system of the present disclosure does not require the peripheral devices 512, 514, 516 to have a microcontroller. It is advantageous to avoid including microcontrollers in the peripheral devices 512, 514, 516 as explained above.

[0170] The communication system 500 of the present disclosure which uses addressable switches in the peripheral devices to enable peripheral devices to be selectively addressed is beneficial in avoiding the need for microcontrollers on the peripheral devices.

[0171] In an example use case, on initialisation of the host device 502, the host device 502, via the controller 504, will initialise the I2C communication bus and the 1-wire bus.

[0172] If the primary identifiers of the peripheral devices 512, 514, 516 are not already known to the controller 504, the controller 504 will use the 1-wire bus to perform a search for peripheral devices to discover the peripheral devices 512, 514, 516. The search algorithm used may be a binary tree search where branches are followed until a primary identifier (leaf) is found. Subsequent searches then take the other branch paths until all of the peripheral devices 512, 514, 516 on the communication system are discovered. The searching for nodes on a 1-wire bus is already known to the skilled person so a detailed explanation of the search algorithm is omitted.

[0173] Once all peripheral devices are identified, the host device 102 interrogates each peripheral device in turn over the 1-wire bus to obtain the secondary identifiers. The controller 504 of the host device 102 associates each primary identifier with the corresponding secondary identifier.

[0174] The scanning for peripheral devices 512, 514, 516 is not required to be performed every time the host device 502 is activated. The scan for peripheral devices could be performed once (e.g., at the factory), and the details of the peripheral devices (primary identifier, secondary identifier and other information such as properties of the I2C module such as properties of any sensors of the I2C module) can be stored on a memory device on the 1-wire bus. The host device 502 can read the details from the memory device to identify the peripheral devices in the communication system 500. The host device 502 can use the information stored in the memory device to determine whether any of the peripheral devices are malfunctioning.

[0175] The memory device could be a 1-wire EEPROM or an I2C EEPROM with known address. The memory device may have a built-in secure authenticator such as the DS28E35 manufactured by Analog Devices Inc. In this way, the host device 502 can subsequently identify the peripheral devices on the bus by simply reading the details from the memory device. The use of a secure authenticator can help ensure that only approved devices are used in the communication system 500.

[0176] Each addressable switch 524, 526, 528 will obtain their secondary identifier, such as by reading the output of the secondary identifier terminals, and will provide their primary identifier and secondary identifier to the host device 502 over the 1-wire bus.

[0177] By way of example, the communication system 500 can be used in a garment for monitoring the activity of a wearer. The I2C modules 518, 520, 522 of the peripheral devices 512, 514, 516 comprise sensors such as motion sensors.

[0178] The peripheral devices 512, 514, 516 and signal and power lines of the communication bus are attached to the garment and are not intended to be removable in normal use. The host device 502 is releasably coupled to the garment and has an interface (e.g. USB Type C) for releasably electrically connecting to the signal and power lines to bring the host device 502 into communication with the peripheral devices 512, 514, 516. The peripheral devices 512, 514, 516 are distributed around the garment to desired measurement locations such as on the wrist, arm, chest, or back.

[0179] The secondary identifiers identify the location of the peripheral devices 512, 514, 516 on the garment. For example, the secondary identifier for peripheral device 512 identifies that the peripheral device 512 is located on the left wrist region of the garment, the secondary identifier for peripheral device 514 identifies that the peripheral device 514 is located on the left forearm region of the garment, and the second identifier for peripheral device 516 identifies that the peripheral device 516 is located on the left upper arm region of the garment.

[0180] Associating the primary identifier with the secondary identifier enables the host device 502 to determine which location on the body the sensor data received from a particular peripheral device 512, 514, 516 relates to. This is particularly useful for activity tracking using motion sensors as it enables the host device 502 to identify whether the sensor data received relates to hand, wrist, arm (or other body parts) motion. In addition, the host device 502 can identify the location of a malfunctioning peripheral device 512, 514, 516 on the communication system 500 which simplifies maintenance.

[0181] The components (I2C module, hardware address, addressable switch) of each peripheral device 512, 514, 516 are provided in the same hardware package. The I2C module, addressable switch, and other components may be provided on the same printed circuit board (PCB such as a flexible PCB). The address lines (ADDR) can be implemented as conductive traces on the printed circuit boards. The peripheral devices 512, 514, 516 may be spaced apart from one another in the communication system 500.

[0182] The I2C modules 518, 520, 522 should typically support dynamic addressing in order to be useable in the present disclosure.

[0183] The communication system 300, 500 described above is not required to only include peripheral devices with both an SPI module / l2C module and an addressable switch. Additional peripheral devices may be provided on the 1-wire bus without connecting to the host device 302 via the SPI bus. The 1-wire bus may comprise additional devices such as a 1-wire memory device, as described above or a 1-wire temperature sensor. Additionally, or separately, the communication system 300 can comprise a 1 -wire to I2C device bridging device to allow for devices supporting I2C communication to connect to the 1-wire bus. An example 1-wire to I2C device bridging device is the DS28E18 manufactured by Analog Devices Inc.

[0184] In the above example, each peripheral device has only one SPI module / l2C module. This is not required in all examples and the peripheral devices may have two or more SPI modules / l2C modules. Each SPI module / l2C module may comprise a different sensor for example. The addressable switch may have configuration lines (address lines or chip select lines) extending to each of the SPI modules / l2C modules in the peripheral device to enable individual addressing of the SPI modules / l2C modules in the peripheral device. In addition, the peripheral device may have more than one addressable switch.

[0185] The host device 302, 502 can include additional components to the controller 312, 504 and terminals. Example additional components include a power source, such as a rechargeable battery, a wireless communicator for communicating with external devices, a memory for logging data received from the peripheral devices, and a sensor (such as any of the sensors described as being applicable for the peripheral devices).

[0186] The host device 302, 502 may be connected to the communication bus over a USB-type interface for example. A preferred implementation uses the USB Type C interface. USB Type C has 8 pins that are used for high speed data, and some or all (to allow for redundancy and reversibility) of those 8 pins may be used as the terminals of the host device 302, 502 that connect to the communication bus. Some of the pins could be used wired programming / debugging of the host device 302, 502. USB Type C has 4 pins for power and a further 2 for determining which alternative mode of functionality to use (SBU1 / SBU2). This can help with intrinsic safety applications. This arrangement does not utilise the four USB 2.0 pins of the USB Type C interface. This pins are free to be used to connect other devices to the host device 302, 502 on a separate bus if desired. The present disclosure is not limited to the use of a USB Type C interface or a USB interface in general.

[0187] The above examples relate primarily to solutions for SPI and I2C protocols. It will be appreciated that both solutions use addressable switches to simplify addressing of peripheral devices in a communication bus.

[0188] In summary, there is provided a communication system 300. The communication system 300 comprises a host device (302) and a plurality of peripheral devices (314, 316, 318). Each of the peripheral devices (314, 316, 318) comprises a module (320, 322, 324) and an addressable switch (326, 328, 330). The module (320, 322, 324) is connected to the host device (302) over a communication bus (CLK, MOSI, MISO). The addressable switch (326, 328, 330) is connected to the host device (302) over a 1-wire bus (1-Wire). The host device (302) sends a primary identifier for one of the peripheral devices to the addressable switches (326, 328, 330). The addressable switches (326, 328, 330) compares the received primary identifier to a primary identifier stored in memory. If the primary identifiers match, the addressable switch (326, 328, 330) enables the module to communicate with the host device (302) over the communication bus. The communication bus may be an SPI or I2C communication bus.

[0189] At least some of the example embodiments described herein may be constructed, partially or wholly, using dedicated special-purpose hardware. Terms such as ‘component,’ ‘module’ or ‘unit’ used herein may include, but are not limited to, a hardware device, such as circuitry in the form of discrete or integrated components, a Field Programmable Gate Array (FPGA) or Application Specific Integrated Circuit (ASIC), which performs certain tasks or provides the associated functionality. In some embodiments, the described elements may be configured to reside on a tangible, persistent, addressable storage medium and may be configured to execute on one or more processors. These functional elements may in some embodiments include, by way of example, components, such as software components, object-oriented software components, class components and task components, processes, functions, attributes, procedures, subroutines, segments of program code, drivers, firmware, microcode, circuitry, data, databases, data structures, tables, arrays, and variables.

[0190] Although the example embodiments have been described with reference to the components, modules and units discussed herein, such functional elements may be combined into fewer elements or separated into additional elements. Various combinations of optional features have been described herein, and it will be appreciated that described features may be combined in any suitable combination. In particular, the features of any one example embodiment may be combined with features of any other embodiment, as appropriate, except where such combinations are mutually exclusive. Throughout this specification, the term “comprising” or “comprises” means including the component(s) specified but not to the exclusion of the presence of others.

[0191] All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and / or all of the steps of any method or process so disclosed, may be combined in any combination, except combinations where at least some of such features and / or steps are mutually exclusive.

[0192] Each feature disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent, or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.

[0193] The invention is not restricted to the details of the foregoing embodiment(s). The invention extends to any novel one, or any novel combination, of the features disclosed in this specification (including any accompanying claims, abstract and drawings), or to any novel one, or any novel combination, of the steps of any method or process so disclosed.

Claims

1. A communication system comprising:a host device comprising a peripheral device addressing terminal, and a plurality of communication bus terminals comprising at least one data terminal and a serial clock terminal; anda plurality of peripheral devices each comprising:a module comprising at least one data terminal connected to the at least one data terminal of the host device, a serial clock terminal connected to the serial clock terminal of the host device, and a configuration terminal; andan addressable switch comprising: a memory storing a primary identifier for the peripheral device, a peripheral device addressing terminal connected to the peripheral device addressing terminal of the host device, and a configuration terminal connected to the configuration terminal of the module, wherein the addressable switch is arranged to receive, via the peripheral device addressing terminal, a primary identifier, compare the received primary identifier to the primary identifier stored in the memory, and configure, via the configuration terminal, a communication property of the module based on the comparison, wherein the communication property defines, at least in part, how the module communicates with the host device.

2. The communication system of claim 1, wherein the communication property of the module comprises an address of the module, wherein the addressable switch is arranged to set the address of the module to a first address responsive to the received primary identifier matching the primary identifier stored in the memory, and wherein the addressable switch is arranged to set the address of the module to a second address responsive to the received primary identifier being different to the primary identifier stored in the memory.

3. The communication system of claim 2, wherein the plurality of communication bus terminals comprise a plurality of Inter-Integrated Circuit (I2C) terminals, the module is an I2C module, and the addressable switch configures the address of the module via the configuration terminal.

4. A communication system of claim 1, wherein the configuration terminals of the module and the addressable switch are chip select terminals, and wherein the addressable switch is arranged to send a chip select signal to the module via the chip select terminal to configure the communication property of the module, the chip select signal having either an enable state to enable the module to communicate with the host device via the at least one data terminal or a disable state to disable the module from communicating with the host device via the at least one data terminal, and wherein the addressable switch is arranged to set the chip select signal to the enable state responsive to receiving, via the peripheral device addressing terminal, a primary identifier from the host device that matches the primary identifier stored in the memory.

5. The communication system of claim 4, wherein the addressable switch is arranged to set the chip select signal to the disable state responsive to receiving, via the peripheral device addressing terminal, a primary identifier from the host device that is different to the primary identifier stored in the memory.

6. The communication system of claim 4 or 5, wherein the plurality of communication bus terminals comprise a plurality of Serial Peripheral Interface, SPI, terminals, and the at least one data terminal comprises a data output terminal and a data input terminal, and wherein the module is an SPI module, and the at least one data terminal comprises a data input terminal connected to the data output terminal of the host device, and a data output terminal connected to the data input terminal of the host device.

7. The communication system of any preceding claim, wherein the host device communicates with the peripheral devices via the peripheral device addressing terminal using a single-wire communication protocol.

8. The communication system of any preceding claim, wherein the addressable switch of at least one of the peripheral devices is arranged to provide a secondary identifier identifying a characteristic of the peripheral device.

9. The communication system of claim 8, wherein the addressable switch comprises a plurality of secondary identifier terminals, and wherein the logic levels of the secondary identifier terminals collectively define the secondary identifier.

10. The communication system of claim 9, wherein each of the plurality of secondary identifier terminals are wired either to a ground line or a power line of the communication system to collectively define the secondary identifier.

11. The communication system of any preceding claim, wherein at least one of the peripheral devices comprises a power switch connected to the addressable switch, and wherein the addressable switch is arranged to control the power switch to transition the module between different power states.

12. The communication system of any preceding claim, wherein the module of at least one of the peripheral devices comprises a sensor.

13. The communication system of claim 12, wherein the sensor comprises a motion sensor.

14. The communication system of any preceding claim, further comprising a memory device connected to the host device via the peripheral device addressing terminal.

15. A device comprising:a module comprising at least one data terminal, a serial clock terminal, and a configuration terminal; andan addressable switch comprising: a memory storing a primary identifier for the peripheral device, a peripheral device addressing terminal, and a configuration terminal connected to the configuration terminal of the module,wherein the addressable switch is arranged to receive, via the peripheral device addressing terminal, a primary identifier from a host device, compare the received primary identifier to the primary identifier stored in the memory, and configure, via the configuration terminal, a communication property of the module based on the comparison, wherein the communication property defines, at least in part, how the module communicates with the host device.

16. A communication system comprising:a host device;a plurality of wires forming a first communication bus;a single-wire forming a single-wire bus;a plurality of peripheral devices each comprising:a module connected to the host device by the first communication bus; andan addressable switch connected to the host device by the single-wire bus, wherein the addressable switch comprises a plurality of identifier terminals, and wherein the logic levels of the identifier terminals collectively define an identifier, andwherein the addressable switch is arranged to output the identifier to the host device.

17. A communication system as claimed in claim 16, wherein each of the plurality of identifier terminals are wired either to a ground line or a power line of the communication system to collectively define the identifier.

18. A device comprising:a module; andan addressable switch comprising a plurality of identifier terminals, and wherein the logic levels of the identifier terminals collectively define an identifier, and wherein the addressable switch is arranged to output the identifier to a host device.

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