Dynamic ron sensing

Abstract

An III-nitride power semiconductor based heterojunction device comprising a first 101 and second 103 heterojunction transistors comprising first / second drain terminals, first / second source terminals and first / second gate terminals, said first / second drain terminals and said first / second gate terminals separated by a first distance Lgd1; and a third heterojunction transistor 102 comprising a third drain terminal, a third source terminal and a third gate terminal, wherein the third drain terminal and the third gate terminal separated by a second distance Lgd2 that is greater than the first distance. The first drain terminal is operatively connected to the second and third drain terminals, the first gate terminal is operatively connected to the second and third gate terminals, and the second and third heterojunction transistors are scaled to a smaller area or gate perimeter than the first heterojunction transistor. The structure can be a heterostructure AlGaN / GaN high electron mobility transistor or rectifier, and can be used as a Dynamic on resistance (Dynamic RON) change sensor.

Description

Field of the Disclosure The present disclosure relates to power semiconductor devices. Particularly, but not exclusively, the disclosure relates to hetero-structure AIGaN / GaN high electron mobility transistors or rectifiers. Background of the Disclosure Gallium Nitride (GaN) is a wide band gap material with properties that make it a suitable candidate for use in several fields of application (e.g. radio-frequency electronics, opto-electronics, power electronics) which require or benefit from the use of solid-state devices. GaN technology facilitates the design of transistors with a high electron mobility and a high saturation velocity. These properties of GaN have made it a good candidate for high-power and high-temperature microwave applications, for example radar and cellular communications systems. As systems expand in subscribers and desired capacity, interest in increasing their operating frequency and power has grown correspondingly. Higher frequency signals can carry more information (bandwidth) and allow for smaller antennas with relatively high or very high gain. Additionally, GaN with its wide bandgap offers the potential for emitting light at higher frequencies, for example in the green (495-570 nm), blue (380-500 nm), violet (-380 nm), and ultraviolet (10-400 nm) portions of the electromagnetic spectrum. In the last decade, GaN has increasingly been considered as a very promising material for use in the field of power devices. The application areas range from portable consumer electronics, solar power inverters, electric vehicles, and power supplies. The relatively wide band gap of the material (Eg=3.39 eV) results in a relatively high critical electric field (Ec=3.3 MV / cm) compared to alternative materials, which can facilitate the design of devices with a shorter drift region. This in turn may enable a lower on-state resistance compared to e.g. a silicon-based device with the same breakdown voltage. The use of an Aluminium Gallium Nitride (AIGaN) / GaN heterostructure also facilitates the formation of a two-dimensional electron gas (2DEG) at the hetero-interface, where charge carriers can reach very high mobility (p=2000 cm2 / (Vs)) values. In addition, the piezopolarization charge present at the AIGaN / GaN heterostructure can result in a high electron density in the 2DEG layer (e.g. 1*1013 cm-2). These properties allow the development of High Electron Mobility Transistors (HEMTs) and Schottky barrier diodes with very competitive performance parameters. However, the two-dimensional carrier or electron gas (2DEG) which inherently exists at a AIGaN / GaN hetero-interface has been found to be unstable, and may lose electron charge under e.g. a prior high voltage stress. This phenomenon is known as dynamic on resistance (Dynamic Ron) or Current Collapse. When the device is under high voltage stress in the off-state (for example, a high potential is present on the high voltage drain terminal with respect to the source terminal, and the gate voltage is at a potential below the threshold voltage to ensure that the device is off), part of the electrons in the 2DEG may be lost by trapping mechanisms. These trapping mechanisms may be traps in the bulk of the GaN, the transition layer (i.e. the layer placed between the substrate and the GaN buffer) or at the surface of the device. Hot carrier injection in the passivation layer, next to the gate (the control terminal) also may play a role in the current collapse. This loss of charge from the 2DEG layer to the surrounding traps can lead to a subsequent decrease in the conductivity of the device during the on-state, and thus an increase in the on-state resistance. The effect may also be seen e.g. during switching processes, or when the device is in operation in a real system. Dynamic Ron can directly affect the efficiency of e.g. a converter, and can further lead to reliability concerns due to the higher dissipated power than expected from nominal static characteristics of the device. Therefore, characterization of this phenomenon is valuable for the assessment of a device’s performance. This characterization cannot be made with traditional static or small signal measurements, as Ron degradation is triggered by application-like dynamic device excitations. Typically therefore, devices are tested in particular laboratory conditions in order to study Ron variation. One example approach, based on conventional double-pulse measurements, suffers from the problem that (i) the devices are tested far from the switching operation conditions which may occur in a real power converter, namely with a very low duty cycle (<0.01, corresponding to negligible self-heating) and often with resistive load. In addition, (ii) all the stress conditions (e.g. high electric field, temperature etc.) are often applied separately, which is not the case in a real power converter where high temperature, voltage and current levels may be simultaneously present. As the assessment of the real switching operation is crucial for the reliability of GaN-HEMT power devices, it is desirable to characterise the Dynamic Ron during real operation. The Applicant has therefore recognised a need for an on-chip sensor to monitor and measure the Dynamic Ron values of a transistor device during operation, for example with consideration for some or all of the parameters responsible for the Dynamic Ron variation (temperature, off-state bias, switching etc.). Barbato et al (“Fast System to measure the dynamic on-resistance of on-wafer 600 V normally off GaN HEMTs in hard-switching application conditions”, IET Power Electronics, Vol. 13, Issue 11, August 2020, pages 2390-2397) describes a system to investigate the on-wafer level dynamic properties of GaN-based power transistors in hard-switching application conditions. Summary The present disclosure generally relates to a Dynamic Ron change sensor. The sensor may be monolithically integrated with a power device, such as a power HEMT device. The sensor may be configured to provide an accurate and reliable measurement of the Dynamic Ron change values of the power device while the device is in operation. This may be useful in characterisation, and may also be used to provide an in-situ Dynamic Ron change measurement while the device is in operation in its intended application. It will be understood that Static Ron may be defined as the resistance of the device before any ‘stress’ conditions are applied, for example before the application of any high voltage stress. It will be further understood that Dynamic Ron may be defined as the absolute on-state resistance of a device after a period of stress is applied, for example following the application of a high voltage stress. Dynamic Ron Change may be defined as the percentage change of Dynamic Ron compared to Static Ron. Thus, Dynamic Ron Effect may be defined as the phenomenon of the resistance of a device changing after a period of stress as described in the background section. The Dynamic Ron Change is often characterised by an increase in the on state resistance relative to the Static Ron, rather than a decrease. According to one aspect of the present disclosure there is provided an Ill-nitride power semiconductor based heterojunction device comprising: a first heterojunction transistor comprising a first drain terminal, a first source terminal and a first gate terminal, the first drain terminal and the first gate terminal separated by a first distance; a second heterojunction transistor comprising a second drain terminal, a second source terminal and a second gate terminal, wherein the second drain terminal and the second gate terminal separated by the first distance, a third heterojunction transistor comprising a third drain terminal, a third source terminal and a third gate terminal, wherein the third drain terminal and the third gate terminal separated by a second distance that is greater than the first distance, wherein the first drain terminal is operatively connected to the second and third drain terminals, the first gate terminal is operatively connected to the second and third gate terminals; wherein the second heterojunction transistor is scaled to a smaller area or gate perimeter than the first heterojunction transistor by a first scale factor X, where X is larger than 1; and wherein the third heterojunction transistor is scaled to a smaller area or gate perimeter than the first heterojunction transistor by a second scale factor Y, where Y is larger than 1. The heterojunction device according to the present disclosure may provide a Dynamic Ron Change sensor for detecting / measuring a Dynamic Ron Change of the first (e.g. main) transistor during operation. This advantageously facilitates characterisation of the device, e.g. to assist with understanding the behaviour of the device and therefore ultimately the design of reliable and efficient power electronic converters. Furthermore, the Dynamic Ron Change measurement in operation may be useful to observe any degradation of the device during operation, and may facilitate improved estimates of the remaining lifetime of the device, and / or be used to identify the need to replace a component before catastrophic failure. Optionally the first and second scale factors are the same or substantially the same. By scaling the second and third transistors (otherwise called the additional or Dynamic Ron sensing transistors) such that they have a smaller area than the first transistor, the Dynamic Ron Change measurements may be obtained with minimal impact on the operations of the first transistor. For example, the current flow through the second and third transistors may be a relatively small fraction of the current flow through the first transistor. The second and third heterojunction transistors may each have a substantially identical structure to the first heterojunction transistor, scaled based on the respective scaling factors of the devices. The second and third heterojunction transistors may be fabricated using substantially the same process steps as the first heterojunction transistor, and / or in the same process step as the first heterojunction transistor. In implementations, the second distance is between about 1.5 and about 3 times greater than the first distance. The second transistor may have substantially the same structure as the first transistor, such that the Dynamic Ron Change of the second transistor are substantially the same as the first transistor under identical conditions. The third transistor meanwhile may be configured to have a substantially smaller Dynamic Ron Change. For example, by providing the third transistor with a higher drift region length (e.g. gate to drain separation), the surface field between the gate and drain may be lowered relative to the first and second transistors. As a result, the Dynamic Ron Change may be much smaller in the third transistor. Thus, by taking measurements from the second and third transistors during operation, changes to the Static Ron of the second transistor (and therefore also the first transistor) may be detected. Thus, in implementations the second distance is selected such that a Dynamic Ron Change of the third heterojunction transistor under operation conditions is 10% or less of a Dynamic Ron Change of the first and second heterojunction transistors under the same conditions. Any Dynamic Ron Change in the third transistor results in uncertainty or error in the final Dynamic Ron Change measurement for the first transistor device. As such, the third transistor may be configured to reduce or minimise the Dynamic Ron Change, for example to less than 10%, less than 5%, less than 2 or less than 1% of the Dynamic Ron Change of the first transistor under the same conditions, or to have negligible or substantially no Dynamic Ron Change. Additionally or alternatively, the third transistor may be configured to reduce or minimise the Dynamic Ron Change, such that a dynamic on-state resistance (Dynamic Ron) of the third transistor under operation conditions is different by 10% or less of a static on-state resistance (Static Ron) of the third transistor. The heterojunction device may be configured to provide a first current output from the second heterojunction transistor and a second current output from the third heterojunction transistor. The current measurements may be used to determine the Dynamic Ron Change of the first transistor. Optionally, the heterojunction device may be configured to obtain a differential current measurement based on the first and second current outputs. If the first, second and third transistors are positioned relatively close together (for example on a single chip), they will be subject to substantially the same conditions. A differential current measurement may therefore be used to remove or reduce any changes to the Dynamic Ron resulting from environmental conditions. The source terminals of the first, second and third transistors may be electrically connected. Optionally, the heterojunction device may comprise: a first resistive element operatively connected between the first and second source terminals, wherein a resistance of the first resistive element is less than an on-state resistance of the second heterojunction transistor; and a second resistive element operatively connected between the first and third source terminals, wherein a resistance of the second resistive element is less than an on-state resistance of the third heterojunction transistor. The resistance of the first and second resistive elements are at least twenty times less than the resistance of the second and third heterojunction transistors respectively. In addition to or alternatively to the current measurements, the Dynamic Ron Change may be determined via voltage measurements, for example based on the voltage drop across resistors connected in series with the second and third transistors. In implementations therefore, the heterojunction device configured to provide a first potential difference across the first resistor and a second potential difference across the second resistor. As with the current measurements, the device may obtain a differential voltage measurement based on the first and second potential differences. Optionally, a voltage amplifier may be provided to amplify the differential voltage measurement. The amplifier may be e.g. a differential amplifier circuit configured to amplify the difference of the signals applied as inputs to the differential amplifier circuit. The voltage amplifier may be monolithically integrated with the first, second and third transistor. In implementations, a separation between the second source terminal and the second drain terminal is approximately equal to a separation between the third source terminal and the third drain terminal. In other words, the two Dynamic Ron sensing transistors (e.g. the second and third transistors) may have substantially the same total area. This may enable the second and third transistors to have substantially the same on-state resistance before any stresses have been applied (i.e. same Static Resistance). Thus, any difference in on-state resistance between the second and third transistors may be a result of the different Dynamic Ron Change experienced by the two devices after stress. The first, second and third heterojunction transistors are monolithically integrated, such that they are subject to substantially the same stresses and environmental conditions. Optionally, substrate layer of the third heterojunction device is removed at least under the active area of the third heterojunction device. It will be understood that Dynamic Ron Change may arise due to a horizontal component of the electric field (e.g. due to potential sustained between the drain to gate) and a vertical component of the electric field (e.g. due to potential sustained between the drain to substrate). Thus, by removing the substrate under at least the active area of the third transistor, the Dynamic Ron Change of the third transistor may be further reduced. In implementations, the third transistor may comprise a substrate in areas that are not directly below the active area, to improve a mechanical strength of the device and reduce the risk of mechanical failures. In implementations, one or more of the transistor device may be provided with field plates to reduce the Dynamic Ron Change. Optionally, the field plate structure and design of the first and second transistors may be substantially the same, while the field plate structure of the third transistor may be the same or may be different to the first and second transistors. In each case, the field plates may be positioned above the active area of the respective transistor and between the gate and drain terminals. In a further implementation, both the second and third transistors may comprise one or more field plates towards or adjacent to a drain side edge of the gate terminal, and a distance between their respective drain terminals and a drain side edge of their respective field plates may be equal or substantially equal. In implementations, the Dynamic Ron Change sensor may be further configured to sense a current though the first transistor. For example, the current may be determined based on a current through the second transistor. Alternatively, the heterojunction device may comprise a current sensing or fourth heterojunction transistor, the fourth heterojunction transistor comprising a fourth drain terminal, a fourth source terminal and a fourth gate terminal, wherein the fourth drain terminal is operatively connected to the first drain terminal, and the fourth gate terminal is operatively connected to the first gate terminal. A resistive element is operatively connected between the first source terminal and the fourth source terminal. The fourth heterojunction transistor has a substantially identical structure to the first heterojunction transistor, and wherein the fourth heterojunction transistor is scaled to a smaller area or gate perimeter than the first heterojunction transistor by a third scale factor Z, where Z is larger than 1. Optionally, the first, second and third scale factors are all equal. According to a second aspect of the invention, there is provided a (heterojunction) chip comprising a heterojunction device according to any of the implementations of the first aspect. For example, the second aspect may provide a chip comprising an Ill-nitride power semiconductor based heterojunction device comprising: a first heterojunction transistor comprising a first drain terminal, a first source terminal and a first gate terminal, the first drain terminal and the first gate terminal separated by a first distance; a second heterojunction transistor comprising a second drain terminal, a second source terminal and a second gate terminal, wherein the second drain terminal and the second gate terminal separated by the first distance, a third heterojunction transistor comprising a third drain terminal, a third source terminal and a third gate terminal, wherein the third drain terminal and the third gate terminal separated by a second distance that is greater than the first distance, wherein the first drain terminal is operatively connected to the second and third drain terminals, the first gate terminal is operatively connected to the second and third gate terminals; wherein the second heterojunction transistor is scaled to a smaller area or gate perimeter than the first heterojunction transistor by a first scale factor X, where X is larger than 1; and wherein the third heterojunction transistor is scaled to a smaller area or gate perimeter than the first heterojunction transistor by a second scale factor Y, where Y is larger than 1. Thus, the present disclosure may provide an on-chip Dynamic Ron Change sensor. The first, second and third transistors may be monolithically integrated on the chip. Brief Description of the Drawings The present disclosure will be understood more fully from the accompanying drawings, which however, should not be taken to limit the disclosure to the specific embodiments shown, but are provided for aiding in explanation and understanding only. Figure 1 depicts schematically an example circuit diagram for a current sensor. Figure 2 depicts schematically an example circuit diagram for a Dynamic Ron Change sensor according to the present disclosure. Figure 3 depicts schematically example structures for Dynamic Ron Change sensing transistors according to the present disclosure. Figures 4a and 4b depict schematically an example Dynamic Ron Change sensor with an integrated current sensor according to the present disclosure. Figure 5 depicts schematically example structures for Dynamic Ron Change sensing transistors according to the present disclosure. Figure 6 depicts schematically example structures for Dynamic Ron Change sensing transistors according to the present disclosure. Figure 7 depicts schematically example structures for Dynamic Ron Change sensing transistors according to the present disclosure. Detailed Description of the Preferred Embodiments Figure 1 illustrates a schematic circuit diagram of a protection and sensing circuitry. The circuit comprises a current sensing transistor 16 for the main power transistor 19. The current sensing transistor 16 may be a monolithically integrated current sensing transistor, and the circuit may additionally include at least one depletion mode device, such as second transistor 14, and a resistive element 15. The gate terminals 10, drain terminals 9 and source terminals 8 of the current sensing transistor 16 and main power transistor 19 are operably connected. The current sensing transistor 16 has an identical structure to the main power device 19, but is scaled to a known, smaller area when compared to the main power device 19 (e.g. by a scale factor X where X is larger than 1, and may be much larger than 1). The current sensing transistor 16 may therefore provide the ability to detect or sense the current through the main power transistor 19. The detected current may then in turn be used to adjust the gate bias or the gate pulse width / frequency of the main power transistor 19, to thereby avoid or reduce the risk of drain over-current events on the load side, or offer longer endurance time during a short-circuit condition. Figure 2 illustrates a schematic circuit diagram of an example Dynamic Ron Change sensing circuit according to the present disclosure. The circuit comprises a first or main power transistor 101, which may be e.g. a high-voltage Ill-nitride power HEMT 101. Two additional transistors 102,103, which may also be HEMT transistors, are provided for measuring or detecting a Dynamic Ron Change of the main transistor 101. As depicted in Figure 2, the gate, drain and source terminals of the transistors 101, 102, 103 may be connected, optionally via one or more resistive elements such as resistors R2, R3. The two additional transistors may also be referred to as Dynamic Ron Change sensing transistors, or second and third transistors. The two additional or sensing transistors 102, 103 may be monolithically integrated near the main transistor 101. The additional HEMT transistors 102 and 103 may each have a similar or identical structure to the main power device 101, but scaled to a known, smaller area when compared to the main power device 101. For example, the devices may be scaled by a scale factor X, where X is larger or much larger than 1. For example, scale factor X may have a value between 50 and 1000, i.e. such that the devices have an area or gate perimeter that is smaller than the main device by a factor of 50 to 1000 times. In some cases, the scale factor X may be between 100 and 300. In some examples, the scale factor X may refer to device gate width, rather than a device area, such that the additional devices 102, 103 have a similar or identical structure to the main power transistor 101, but with a reduced gate width. It will be understood that the device area may refer to the active area of the device. It will further be understood that each of the additional devices 102, 103 may be scaled by a different scale factor, e.g. such that additional device 102 is scaled by a scale factor Y while additional device 103 is scaled by a scale factor X, where both X and Y are larger or much larger than 1. The main transistor 101 may be a high voltage lateral GaN HEMT. It will be understood that the two additional transistors 102, 103 may also be high voltage lateral GaN HEMTs. To measure the Dynamic Ron Change of the main power transistor 101, one of the additional transistors 101, 102 (referred to henceforth as the first additional transistor) may be designed such that it matches the Dynamic Ron Change performance of the main transistor 101, while the other of the additional transistors 102, 103 (referred to henceforth as the second additional transistor) may exhibit low or negligible Dynamic Ron Change. Any Dynamic Ron Change experienced by the second additional transistor results in an error level in the final Dynamic Ron Change measurements for the main transistor 101. As such, an acceptable Dynamic Ron Change level for the second additional transistor may depend on an acceptable error threshold for the Dynamic Ron Change measurement. For example, the Dynamic Ron Change of the second additional transistor may be less than 10% of the Dynamic Ron Change of the main transistor 101, less than 5% of the Dynamic Ron Change of the main transistor 101, less than 2% of the Dynamic Ron Change of the main transistor 101, less than 1% of the Dynamic Ron Change of the main transistor 101, or the second additional transistor may exhibit approximately zero Dynamic Ron Change. As the additional transistors 102, 103 are connected in parallel with the main transistor 101, they experience the same or substantially the same ‘stress’ conditions as the main transistor 101, and the same or substantially the same voltage across their terminals. For this to be a reasonable assumption when the HEMTs are in the ON-state condition, any additional resistances such as R2 &R3 may be selected to be small in comparison to the resistance of the transistors 102, 103. Under these conditions, the current per unit area (or per unit width, where the scale factor X is a width scale factor) flowing through the additional transistors will be the same or substantially the same as each other. Additionally, by providing the additional transistors 102, 103 on the same chip as the main power transistor 101, they may also have substantially the same temperature as the main power transistor 101. As a result, the first additional transistor can be designed to experience the same or substantially the same Dynamic Ron Change increase as the main transistor 101 in response to the same ‘stress’ conditions as those experienced by the main transistor 101, as discussed above. The second additional transistor can similarly be designed to exhibit zero Dynamic Ron Change (or a significantly smaller Dynamic Ron Change than the main power transistor). Therefore, any resistance difference between the first and second additional resistors 102, 103 will be due to the difference in the Dynamic Ron Change exhibited by the two transistors. Therefore, a differential measurement of the resistance of the two additional transistors 102, 103 during On-state operation, after a high voltage stress has been applied between the drain and source terminals, may represent the Dynamic Ron % change experienced by the main transistor 101 due to the effects of the high voltage stress. These measurements may therefore be used to determine or detect the Dynamic Ron Change of the main power transistor 101. As such, in examples of the present disclosure two Dynamic Ron sensing HEMTs (e.g. 102, 103) are monolithically integrated with a main HEMT (e.g. 101) such that the variation in their parameters due to standard process variations match those of the main HEMT and each other. Dynamic Ron Changes of a GaN HEMT are related to the electric field present in the structure during off-state bias, where a high voltage bias is present. One parameter that may be adjusted to reduce the electric field observed in the HEMT during off-state bias is therefore the gate-to-drain separation distance, also known as the drift region length. A further parameter that may be adjusted is the size or length of any field plate on the source / gate / drain side. Figure 3 illustrates an example design of transistors 102, 103 fulfilling the Dynamic Ron Change conditions described above. In Figure 3, each of the transistors 101, 102, 103 is a GaN / AIGaN HEMT. Figure 3 schematically depicts the cross section structure of the Dynamic Ron Change sensors (DynRonl HEMT 102 and DynRon2 HEMT 103), with respect to the main HEMT 101. In a power HEMT used as the main power transistor 101, the separation between the gate terminal and the drain terminal Lgd1 may be optimised according to a trade-off between the ON-state resistance of the device and OFF-state blocking voltage requirements, or via any other means familiar to the skilled person. In the power HEMT used as the main power transistor, the source-to-gate length of a power HEMT does not contribute towards sustaining the off-state potential, and hence may generally be maintained at the minimum value, to keep the overall resistance of the device to a minimum level. This may assist with the production of a competitive specific on resistance (Ron) for the power HEMT design. However, it will be understood that the source-to-gate length of the main power HEMT may be any length. The two HEMTs 102, 103 may be configured to achieve the same overall resistance in the two HEMTs as in the main HEMT under fresh conditions i.e. before any ‘stress’ which may adjust the resistance of the device is applied. The two H EMTs 102, 103 are further configured to achieve different Dynamic Ron Change behaviours described above, and therefore a difference in their overall resistance, after any ‘stress’ which may adjust the resistance of the device is applied. For one of the two HEMTs, HEMT 103 the Dynamic Ron Change may match or be similar to the Dynamic Ron Change observed in the main HEMT, and for the other HEMT 102, the Dynamic Ron Change may be negligible or otherwise small in comparison to the Dynamic Ron Change in the main HEMT. In the example of Figure 3, this is achieved by adjusting the gate-to-drain separation and source-to-gate separation of the additional HEMTs 102, 103, but maintaining the same or substantially the same source-to-drain separation in the two additional HEMTs 102, 103. As such, the first additional HEMT 103 is provided with a gate-to-drain separation that matches or substantially matches the gate-to-drain separation Lgd1 of the main HEMT 101. The gate-to-drain separation Lgd2 of the second additional HEMT 102, in contrast, is greater than the distance Lgd1 of the main HEMT 101. Lgd2 may be, for example, 1.5 to 3 times greater than Lgd1. It will be understood that the total area of the additional transistors 102, 103 may still be smaller than main transistor 101, for example due to a decreased width of these devices (e.g. by a scale factor X). To assist with increasing the drain-to-source (drift region) length, the overall drain-to-source dimension of the additional HEMTs 102, 103 may be greater than the main HEMT 101. Further, to improve the accuracy of the differential measurement, both of the additional (sensing) devices 102, 103 may have the same overall drain-to-source size, such that they have the same or approximately the same overall resistance in the linear region. As such, the drain-to-source length of the Dynamic Ron Change sensors 102 &103 are increased relative to the drain-to-source length of the main HEMT 101, such that the gate-to-drain drift region length Lgd2 of the second additional transistor 102 may be increased (to thereby reduce the Dynamic Ron Change of this sensor relative to the main transistor). The first additional HEMT 103 is configured to have similar drift region length Lgd1 to the main transistor 101, to thereby sustain the off-state voltage in a similar manner as the main HEMT 101. The electric field distribution at the surface between the gate and drain in the HEMT 103 may therefore also be similar to that in the main power HEMT 101. Generally therefore, the Dynamic Ron Change in HEMT 103 and main HEMT 101 should be similar under similar conditions, due to their similar or identical device structures. In contrast, the higher drift region length of HEMT 102 may lower the surface field between the gate and drain. As a result, the Dynamic Ron Change may be smaller in HEMT 102 than in HEMT 103. The change in the Dynamic Ron in HEMT 103 compared to HEMT 102 may therefore be measured, for example by the voltage difference between the voltage drops across resistors R2 and R3. To assist with this, R2 and R3 may have an equal resistance. The potential differences across R2 and R3 may therefore be indicative of the Dynamic Ron Change of the main HEMT 101. Additionally, the difference in the current flowing through the two HEMTs 102, 103 is also proportional to the difference in the resistance of the two transistors. As previously discussed, the percentage difference in the resistance of the transistors after a ‘stress’ has been applied may represent the percentage change in the resistance of the main HEMT 101 before and after the application of the same ‘stress’. As such, the current output DynRonl from the DynRonl HEMT 102 may generally be expected to represent a zero or small change in Dynamic Ron, while the current output DynRon2 from the DynRon2 HEMT 103 may be expected to represent the percentage change in Dynamic Ron experienced by the main HEMT 101. A differential measurement of these two current output signals may therefore represent the Dynamic Ron Change of the main HEMT 101. Resistors (e.g. R2 and R3) may be placed in series with the sensing HEMTs 102, 103, for example as illustrated in Figure 2 &3. This may assist with the conversion of the current measurement or current differential measurement to a voltage measurement or voltage differential measurement, for implementations or applications utilising the voltage measurements. The resistors R2, R3 may preferably have a resistance that is substantially smaller than the resistance of the sensing HEMTs 102, 103. For example, R2 and R3 may each have a resistance that is 20x less than the on-state resistance of the sensing HEMTs 102, 103. It will be understood that, in implementations or applications utilising the current differential signal, resistors R2 and R3 may be removed. The voltage differential signal may be amplified. For example, a voltage amplifier (not shown) may be included on chip for this purpose. The use of a differential measurement may help to reduce or cancel the effect of temperature on the detected Dynamic Ron Change. The resistance of a device can change significantly with temperature, e.g. due to effect of temperature on the mobility of carriers in the two dimensional electron gas. This can present a challenge for establishing whether the Dynamic increase in resistance observed in operation arises due to the off-state voltage stress (i.e. due to Dynamic Ron) or due to environmental condition such as the device heating up. However, in implementations in which the main and additional transistors 101, 102, 103 are monolithically integrated and / or in close proximity, they will generally experience the same temperature variations. The Dynamic Ron Change sensor as described may therefore reduce or remove the effect of temperature, thereby facilitating a more accurate measurement of the Dynamic Ron Change of the main transistor 101. A further advantage of the Dynamic Ron Change sensor according to the present disclosure is that the integration of these additional HEMTs does not affect the reliability of the overall chip. The high electric field does not affect the source-to-gate region, and hence the increase in the length of the source-to-gate region of first additional HEMT 103 does not degrade the performance of the chip. In addition, the drift region of second additional HEMT 102 is increased, which relaxes the electric field and hence does not introduce a significant reliability risk. Therefore, the integration of the additional sensing HEMTs does not add any additional use constraints, and the overall device reliability may be maintained. Additional fingers (e.g. scaled down compared to the large number of fingers in the main HEMT) can be added in the structure for both of the sensing HEMTs, and would take minimal additional space on the chip (for example <2% of the overall area). It will be understood that the Dynamic Ron Change differential measurement is based on the change in the surface electric field distribution of the first additional device (e.g. HEMT 102) compared to the reference device (e.g. HEMT 103). Nevertheless, the vertical (e.g. drain to substrate) electrical field remains largely the same in the two structures. Figures 4A and 4B illustrate a further example Dynamic Ron Change sensing circuit according to the present disclosure. The circuit and transistors depicted in Figures 4A and 4B are largely identical to those of Figures 2 and 3, except that a third additional transistor 104 is also provided. The third additional transistor 104 may also be referred to as a fourth or current sensing transistor. The current sensing transistor 104 may operate in a similar manner to the current sensing transistor 16 of Figure 1, and the above discussions relating to current sensing transistor 16 apply equally to current sensing transistor 104. The current through transistor 104 is proportional to that through the main transistor 101, and may be measured directly (e.g. via terminal CS) or otherwise determined via a voltage drop across resistor R1. Alternatively, it will be understood that either of the transistors 102, 103 may be configured as a current sensing structure in addition to providing a reference for the Dynamic Ron Change measurements. In some implementations of the present disclosure, field plates may be provided to further reduce the Dynamic Ron and / or change in Dynamic Ron experienced by one or more of the transistors. Field plates in the drift region may facilitate a more optimal surface electric field distribution, which in turn can assist with reducing or minimising Dynamic Ron. Therefore, the first additional transistor may have the same or similar field plate design to the main transistor, while the second additional transistor may have a different field plate design than the main transistor. Figure 5 illustrates a first example field plate design for the sensing transistors (e.g. transistors 102 and 103). The DynRonl HEMT and DynRon2 HEMTs are depicted with different field plate designs. In this example, the field plate structure of DynRon2 HEMT may be the same as the main transistor while the field plate structure of DynRonl HEMT may be different to the main transistor. However, it will be understood that the DynRonl HEMT may also have a field plate structure that is identical to the main transistor. To facilitate a better optimised potential distribution (i.e. that results in a reduced Dynamic Ron) in the off-state for DynRonl HEMT, the field plates FP21 and FP22 may have different dimensions both laterally (e.g. fp21x and fp22x) and vertically (e.g. fp21y and fp22y). In one example, the length (e.g. fp21x) of field plates FP11 and FP21 may be greater than the length of field plates FP12 and FP22, such that the distance from the (drain side) end of the field plate to the drain terminal is the same for both transistors. The increased field plate length may facilitate a reduction in the electric field stress induced by the drain voltage, on the drain edge of the gate region. As a result, a device with a longer field plate length may see a less significant variation of the threshold voltage and / or a less significant shift in the Dynamic Ron when a prior voltage stress is applied between the drain and source terminals (i.e. a reduced Dynamic Ron effect). While Figure 5 shows only the field plates in the two transistors being different by having different lengths, it will be understood that other parameters of the field plates may additionally or alternatively be changed, and / or different voltages may be applied to the corresponding field plates of the transistors. For example, other metal layers could be used within the field plates to differentiate the additional transistor devices 102 and 103, or alternatively one of the devices may have a gate connected field plate rather than a source connected field plate. Further alternatively a height of the field plates above the surface of the active region (e.g. fp21y and fp22y) may be different. Figure 6 depicts a further example field plate design. In the example of Figure 6, DynRonl HEMT comprises a different number of field plates compared to DynRon2 HEMT (and therefore to the main HEMT). Optionally, one of the field plates may be a drain connected field plate (e.g. FP41). Different numbers of field plates may be provided as an alternative or in combination with any of the other field plates designed described above. The examples above have generally described processes and designs to optimise the lateral potential distribution in the off-state operation of the device, in order to reduce or minimise Dynamic Ron. It will be understood that a component of Dynamic changes in the Ron may be due to the vertical potential distribution in the device. The substrate in a GaN HEMT is often connected to a source potential, meaning that the off-state voltage can also be sustained vertically. The contribution of this vertical component to the total Dynamic Ron may be dependent on the choice of substrate, for example whether Silicon, Sapphire, Silicon Carbide, Semi-insulating Silicon Carbide or QST is chosen. As a result, in some examples the substrate may be removed (e.g. through back-etching or any other suitable means) under the transistor intended to demonstrate negligible or small Dynamic Ron changes (e.g. the second additional transistor described above). Figure 7 depicts one such HEMT device where the (Silicon) substrate has been removed (DynRonl HEMT), along with a second HEMT device without a removed substrate (DynRon2) for comparison. It will be understood that the substrate of one or more of the main and additional transistor devices may be removed from any of the embodiments described in the present disclosure. However, while removing the substrate to minimise Dynamic Ron Change is possible, it can also result in increased thermal resistance and reduced wafer robustness during handling. The impact of these disadvantages may be less significant if the area of substrate removal is small compared to the overall chip area. For example, in implementations the substrate under only one of the additional transistors in the Dynamic Ron Change sensor circuit may be removed, while the main transistor and other additional transistor may retain their (entire) substrates. The removal of the substrate from may help to reduce or minimise any Dynamic Ron Changes due to the vertical electric field. In examples, the substrate may be removed only in the drift region of the device. Other concepts which can minimise Dynamic Ron Changes which arise as a consequence of the vertical potential distribution may be used in DynRonl HEMT. In this disclosure, unless explicitly specified, the heterojunction transistors may be any known transistor based on a heterojunction such as a p-Gate HEMT transistor, or a Schottky gate transistor or an insulated gate transistor such as MISFET (Metal Insulating Semiconductor Field Effect Transistor). The diodes can be Schottky diodes, Zener diodes or pn diodes or diodes made of a transistor by connecting the gate terminal with any of its other terminals. The heterojunction chip or the heterojunction power device described in this disclosure can be referred to as a heterojunction smart power device or heterojunction smart chip or heterojunction power integrated circuit or heterojunction integrated circuit. The skilled person will understand that in the preceding description and appended claims, positional terms such as ‘above’, ‘under’, ‘lateral’, etc. are made with reference to conceptual illustrations of a device, such as those showing standard cross-sectional perspectives and those shown in the appended drawings. These terms are used for ease of reference but are not intended to be of limiting nature. These terms are therefore to be understood as referring to a device when in an orientation as shown in the accompanying drawings. Although the disclosure has been described in terms of preferred embodiments as set forth above, it should be understood that these embodiments are illustrative only and that the claims are not limited to those embodiments. Those skilled in the art will be able to make modifications and alternatives in view of the disclosure which are contemplated as falling within the scope of the appended claims. Each feature disclosed or illustrated in the present specification may be incorporated in the disclosure, whether alone or in any appropriate combination with any other feature disclosed or illustrated herein. Many other effective alternatives will occur to the person skilled in the art. It will be understood that the disclosure is not limited to the described embodiments, but encompasses all the modifications which fall within the spirit and scope of the disclosure.

Claims

1. An Ill-nitride power semiconductor based heterojunction device comprising:a first heterojunction transistor comprising a first drain terminal, a first source terminal and a first gate terminal, the first drain terminal and the first gate terminal separated by a first distance;a second heterojunction transistor comprising a second drain terminal, a second source terminal and a second gate terminal, wherein the second drain terminal and the second gate terminal separated by the first distance,a third heterojunction transistor comprising a third drain terminal, a third source terminal and a third gate terminal, wherein the third drain terminal and the third gate terminal separated by a second distance that is greater than the first distance, wherein the first drain terminal is operatively connected to the second and third drain terminals, the first gate terminal is operatively connected to the second and third gate terminalswherein the second heterojunction transistor is scaled to a smaller area or gate perimeter than the first heterojunction transistor by a first scale factor X, where X is larger than 1; andwherein the third heterojunction transistor is scaled to a smaller area or gate perimeter than the first heterojunction transistor by a second scale factor Y, where Y is larger than 1.

2. The heterojunction device according to claim 1, wherein the first and second scale factors are equal.

3. The heterojunction device according to claim 1 or 2, wherein the second distance is between about 1.5 and about 3 times greater than the first distance.

4. The heterojunction device according to claim 3, wherein the second distance is selected such that a dynamic on-resistance change (Dynamic Ron Change) of the third heterojunction transistor under operation conditions is 10% or less of a Dynamic Ron Change of the first and second heterojunction transistors under the same conditions.

5. The heterojunction device according to claim 3, wherein the second distance is selected such that a dynamic on-state resistance (Dynamic Ron) of the thirdheterojunction transistor under operation conditions is different by 10% or less of a static on-state resistance (Static Ron) of the third heterojunction transistor.

6. The heterojunction device according to any preceding claim, configured to provide a first current output from the second heterojunction transistor and a second current output from the third heterojunction transistor.

7. The heterojunction device according to claim 6, configured to obtain a differential current measurement based on the first and second current outputs.

8. The heterojunction device according to any preceding claim, comprising: a first resistive element operatively connected between the first and second source terminals, wherein a resistance of the first resistive element is less than a resistance of the second heterojunction transistor; anda second resistive element operatively connected between the first and third source terminals, wherein a resistance of the second resistive element is less than a resistance of the third heterojunction transistor.

9. The heterojunction device according to claim 8, wherein the resistance of the first and second resistive elements are at least twenty times less than the resistance of the second and third heterojunction transistors respectively.

10. The heterojunction device according to claim 8 or 9, configured to provide a first potential difference across the first resistor and a second potential difference across the second resistor.

11. The heterojunction device according to claim 10, configured to obtain a differential voltage measurement based on the first and second potential differences.

12. The heterojunction device according to claim 10, comprising a voltage amplifier configured to amplify the differential voltage measurement.

13. The heterojunction device according to any preceding claim, wherein a separation between the second source terminal and the second drain terminal is approximately equal to a separation between the third source terminal and the third drain terminal.

14. The heterojunction device according to any preceding claim, wherein the first, second and third heterojunction transistors are monolithically integrated.

15. The heterojunction device according to any preceding claim, wherein a substrate layer of the third heterojunction device is removed at least under the active area of the third heterojunction device.

16. The heterojunction device according to any preceding claim, wherein:the first heterojunction transistor comprises a first set of one or more field plates, each of the first set of field plates positioned between the first gate terminal and the first drain terminal, and wherein each of the first set of field plates is operatively connected to one of the first gate terminal, first source terminal and the first drain terminal; andthe second heterojunction transistor comprises a second set of one or more field plates, each of the second set of field plates positioned between the second gate terminal and the second drain terminal, and wherein each of the second set of field plates is operatively connected to one of the second gate terminal, second source terminal and the second drain terminal.

17. The heterojunction device of claim 16, wherein the positioning and size of the first set of field plates relative to the first gate terminal and first drain terminal is same as the positioning and size of the second set of field plates relative to the second gate terminal and second drain terminal.

18. The heterojunction device according to any preceding claim, wherein the third heterojunction transistor comprises a third set of one or more field plates, each of the third set of field plates positioned between the third gate terminal and the third drain terminal, and wherein each of the third set of field plates is operatively connected to one of the third gate terminal, third source terminal and the third drain terminal.

19. The heterojunction device of claim 18 when dependent upon claim 16, wherein the second set of field plates comprises one or more field plates positioned adjacent to a drain side edge of the second gate terminal, and the third set of field plates comprises one or more field plates positioned adjacent to a drain side edge of the third gate terminal, and wherein a distance between the second drain terminal and a drain side edge of the one or more field plates connected to the second sourceterminal or gate terminal is equal to a distance between the third drain terminal and a drain side edge of the one or more field plates connected to the third source terminal or gate terminal.

20. The heterojunction device according to any preceding claim, comprising:a fourth heterojunction transistor comprising a fourth drain terminal, a fourth source terminal and a fourth gate terminal, wherein the fourth drain terminal is operatively connected to the first drain terminal, and the fourth gate terminal is operatively connected to the first gate terminal;a third resistive element operatively connected between the first source terminal and the fourth source terminal; andwherein the fourth heterojunction transistor has a substantially identical structure to the first heterojunction transistor, and wherein the fourth heterojunction transistor is scaled to a smaller area or gate perimeter than the first heterojunction transistor by a third scale factor Z, where Z is larger than 1.

21. The heterojunction device according to claim 20, wherein the first, second and third scale factors are equal.

22. A chip comprising the heterojunction device according to any preceding claim.

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