Circuitry for touch-sensitive apparatus and method

Abstract

Circuitry 105 determining an indication of capacitive coupling of two drive electrodes of an electrode array of a capacitive touch sensitive device using two signal generators 2,3 to generate a first

Description

BACKGROUND OF THE INVENTION The present invention relates to the field of touch sensors, for example touch sensors for overlying a display screen to provide a touch-sensitive display (touch screen). In particular, embodiments of the invention relate to techniques for measuring the capacitance using drive electrodes and receive electrodes for sensing the presence of one or more touching objects within a two-dimensional sensing area. A capacitive touch sensor can be generalised as one that uses a physical sensor element comprising an arrangement of electrically conductive electrodes extending over a touch sensitive area (sensing area) to define sensor nodes (or intersection points) and controller circuitry connected to the electrodes and operable to measure changes in the electrical capacitance of each of the electrodes or the mutual-capacitance between combinations of the electrodes. The electrodes are typically provided on a substrate. For such capacitive touch sensors, circuitry is arranged to apply an analogue signal (i.e. a time-varying voltage) to the electrodes in order to perform a measurement of the capacitance. Such a signal typically results in an analogue signal (such as a time varying current) that is received or obtained from the electrodes, with this analogue signal including information regarding the measured capacitance for a given electrode or at a given intersection point. Techniques have been developed for analysing the analogue signal and for determining whether a touch (or an object) is present. However, in some respects, these techniques are not optimal and offer certain disadvantages in certain applications. There is therefore a desire to provide circuitry for touch sensors which can offer an improvement processing of received signals from the electrode array. Moreover, in some examples where digital signal processing is used to provide an alternative processing of received signals from the electrode array, some techniques are not optimised for certain applications, and in particular can require relatively long periods of time to perform complete scans of an electrode array while maintaining a suitable signal to noise ratio. There is therefore a desire to provide circuitry for touch sensors which can offer an improvement in speed of processing of received signals from the electrode array. SUMMARY OF THE INVENTION According to a first aspect of the disclosure there is provided circuitry for determining an indication of the capacitive coupling associated with two drive electrodes of an electrode array of a capacitive touch sensitive apparatus, the circuitry including: a first signal generator configured to generate a first drive signal representing a sinusoidal wave having a first frequency; a second signal generator configured to generate a second drive signal representing a sinusoidal wave having the first frequency, wherein the second drive signal is orthogonal in phase to the first drive signal; drive circuitry configured to apply the first drive signal to a first drive electrode of the electrode array and to apply the second drive signal to a second drive electrode of the electrode array at the same time; receiver circuitry configured to receive a first received signal from the electrode array wherein the first received signal is based on the first drive signal and to receive a second received signal from the electrode array wherein the second received signal is based on the second drive signal, wherein the receiver circuitry is configured to sum the first received signal and the second received signal to form a combined received signal; a first multiplier configured to multiply the first drive signal and the combined received signal together; a second multiplier configured to multiply the second drive signal and the combined received signal together; and calculating circuitry configured to provide a first output indicative of the capacitive coupling associated with the first drive electrode based on an adjustment of the output of the first multiplier and to provide a second output indicative of the capacitive coupling associated with the second drive electrode based on an adjustment of the output of the second multiplier. The adjustment of the output of the first multiplier and the adjustment of the output of the second multiplier is performed in accordance with a predetermined relationship that is a function of both the output of the first multiplier and the output of the second multiplier. According to a second aspect of the disclosure there is provided a touch sensitive apparatus including the circuitry according to the first aspect; an electrode array coupled to the circuitry; and control circuitry configured to receive the outputs from the calculating circuitry and configured to sense at least the presence or an absence of a touch in the proximity of the electrode array. According to a third aspect of the disclosure there is provided method for determining an indication of the capacitive coupling associated with two drive electrodes of an electrode array of a capacitive touch sensitive apparatus, the method including: generating a first drive signal representing a sinusoidal wave having a first frequency; generating a second drive signal representing a sinusoidal wave having the first frequency, wherein the second drive signal is orthogonal in phase to the first drive signal; applying the first drive signal to a first drive electrode of the electrode array and applying the second drive signal to a second drive electrode of the electrode array at the same time; receiving a first received signal from the electrode array wherein the first received signal is based on the first drive signal and receiving a second received signal from the electrode array wherein the second received signal is based on the second drive signal; forming a combined received signal by summing the first received signal and the second received signal; multiplying, using a first multiplier, the first drive signal and the combined received signal together, and multiplying, using a second multiplier, the second drive signal and the combined received signal together; and providing a first output indicative of the capacitive coupling associated with the first drive electrode based on an adjustment of the output of the first multiplier and providing a second output indicative of the capacitive coupling associated with the second drive electrode based on an adjustment of the output of the second multiplier. The adjustment of the output of the first multiplier and the adjustment of the output of the second multiplier is performed in accordance with a predetermined relationship that is a function of both the output of the first multiplier and the output of the second multiplier. According to a fourth aspect of the disclosure there is provided a method for calibrating circuitry for determining an indication of the capacitive coupling associated with two drive electrodes of an electrode array of a capacitive touch sensitive apparatus, the method including: applying a first drive signal representing a sinusoidal wave having a first frequency to a first drive electrode of the electrode array; simultaneously applying a second drive signal representing a sinusoidal wave having the first frequency and being orthogonal in phase to the first drive signal to a second drive electrode of the electrode array; identifying the phase of a combined received signal, the combined received signal being a combination of a first received signal from the electrode array and a second received signal from the electrode array, wherein the first received signal is based on the first drive signal and the second received signal is based on the second drive signal; obtaining a value indicative of the phase shift between the first drive signal and the first received signal by subtracting a fixed amount from the determined phase of the combined received signal; obtaining a value indicative of the phase shift between the second drive signal and the second received signal by adding the fixed amount from the determined phase of the combined received signal; and recording the value indicative of the phase shift between the first drive signal and the first received signal and the value indicative of the phase shift between the second drive signal and the second received signal, the values for use in determining an indication of the capacitive coupling associated with the first drive electrode and the second drive electrode. According to a fifth aspect of the disclosure there is provided method for calibrating circuitry for determining an indication of the capacitive coupling associated with two drive electrodes of an electrode array of a capacitive touch sensitive apparatus, the method including: applying a first drive signal representing a sinusoidal wave having a first frequency to a first drive electrode of the electrode array; identifying the difference in phase between the first drive signal and a first received signal from the electrode array, the first received signal based on the first drive signal; recording a value indicative of the phase difference between the first drive signal and the first received signal, the value for use in determining an indication of the capacitive coupling associated with the first drive electrode; applying, at a different time, the first drive signal to a second drive electrode of the electrode array; identifying the difference in phase between the second drive signal and a second received signal from the electrode array, the second received signal based on the first drive signal; and recording a value indicative of the phase difference between the second drive signal and the second received signal, the value for use in determining an indication of the capacitive coupling associated with the second drive electrode. It will be appreciated that features and aspects of the invention described above in relation to the first and other aspects of the invention are equally applicable to, and may be combined with, embodiments of the invention according to other aspects of the invention as appropriate, and not just in the specific combinations described above. BRIEF DESCRIPTION OF THE DRAWINGS The invention is now described by way of example only with reference to the following drawings in which: Figure 1 schematically illustrates a touch sensitive apparatus incorporating measurement circuitry in accordance with certain embodiments of the invention; Figure 2 schematically illustrates a self-capacitance measurement mode of the touch sensitive apparatus of Figure 1, specifically with a view to explaining the principles of selfcapacitance measurement; Figure 3 schematically illustrates a mutual-capacitance measurement mode of the touch sensitive apparatus of Figure 1, specifically with a view to explaining the principles of mutual capacitance measurement; Figure 4 schematically illustrates the measurement circuitry of the touch sensitive apparatus of Figure 1 in accordance with an example for explaining the background behind the present disclosure; Figure 5 schematically illustrates the measurement circuitry of the touch sensitive apparatus of Figure 1 in accordance with certain embodiments of the invention, whereby orthogonal signals are used to simultaneously drive pairs of electrodes of the electrode array; Figure 6 shows a flow chart depicting a method for determining indications of the capacitive couplings associated with respective driven electrodes of the electrode array based on a combined signal received from the electrode array using the circuitry of Figure 5; Figure 7a and 7b schematically illustrate driving patterns for a group of four drive electrodes whereby the electrodes are driven with signals following a combination of the technique of Figures 5 and 6 with a code divisional multiplex technique; Figure 8 schematically illustrates an example arrangement of the measurement circuitry of the touch sensitive apparatus of Figure 1 in accordance with certain embodiments of the invention, whereby a combination of the technique of Figures 5 and 6 is used in conjunction with a code divisional multiplex technique to implement the driving patterns of Figures 7a and 7b; Figure 9 shows a flow chart depicting a method for calibrating the circuitry of Figure 5 for use in determining indications of the capacitive couplings associated with respective driven electrodes of the electrode array according to a first implementation; and Figure 10 shows a flow chart depicting a method for calibrating the circuitry of Figure 5 for use in determining indications of the capacitive couplings associated with respective driven electrodes of the electrode array according to a second implementation. DETAILED DESCRIPTION The present disclosure relates to measurement circuitry for use in a touch sensitive apparatus (which comprises an array of electrodes forming a touch sensitive surface) for determining indications of the magnitude of capacitive couplings associated with a plurality of driven electrodes of the electrode array. The indications may be used for assessing whether a touch (or another object capable of being sensed) is present at or in the proximity of the touch sensitive surface. More specifically, the present disclosure relates to implementing the above measurement circuitry using digital processing and, in particular, ways that allow for calculating the indications of the capacitive couplings more quickly than conventional techniques by simultaneously measuring the capacitive couplings of a plurality of electrodes without compromising signal to noise ratio. Figure 1 schematically shows an example touch-sensitive apparatus 1. The touch-sensitive apparatus 1 is represented in plan view (to the left in the figure) and also in cross-sectional view (to the right in the figure). The touch-sensitive apparatus 1 comprises a sensor element 100, measurement circuitry 105, control (or processing) circuitry 106, and cover 108. The sensor element 100 and cover 108 may, more generally be referred to as a touch screen or touch-sensitive element of the touch-sensitive apparatus 1, while the measurement circuitry 105 and control circuitry 106 may, collectively, be referred to as the controller of the touch-sensitive apparatus 1. The touch screen is primarily configured for establishing the position of a touch (or multiple touches) within a two-dimensional sensing area by providing Cartesian coordinates along an X-direction (horizontal in the figure) and a Y-direction (vertical in the figure). In this implementation, the sensor element 100 is constructed from a substrate 103 that could be glass or plastic or some other insulating material and upon which is arranged an array of electrodes (referred to herein as an electrode array) consisting of multiple laterally extending parallel electrodes, X-electrodes 101 (row electrodes), and multiple vertically extending parallel electrodes, Y-electrodes 102 (column electrodes), which in combination allow the position of a touch 109 to be determined. To clarify the terminology, and as will be seen from Figure 1, the X-electrodes 101 (row electrodes) are aligned parallel to the X-direction and the Y-electrodes 102 (column electrodes) are aligned parallel to the Y-direction. Thus the different X-electrodes allow the position of a touch to be determined at different positions along the Y-direction while the different Y-electrodes allow the position of a touch to be determined at different positions along the X-direction. That is to say in accordance with the terminology used herein, the electrodes are named (in terms of X- and Y-) after their direction of extent rather than the direction along which they resolve position. Furthermore, the electrodes may also be referred to as row electrodes and column electrodes. It will however be appreciated these terms are simply used as a convenient way of distinguishing the groups of electrodes extending in the different directions. In particular, the terms are not intended to indicate any specific electrode orientation. In general the term "row" will be used to refer to electrodes extending in a horizontal direction for the orientations represented in the figures while the terms "column" will be used to refer to electrodes extending in a vertical direction in the orientations represented in the figures. The X-electrodes 101 and Y-electrodes 102 define a sensing (or sense) area, which is a region of the substrate 103 which is sensitive to touch. In some cases, each electrode may have a more detailed structure than the simple "bar" structures represented in Figure 1, but the operating principles are broadly the same. The electrodes of the electrode array are made of an electrically conductive material such as copper or Indium Tin Oxide (ITO). The nature of the various materials used depends on the desired characteristics of the touch screen. For example, a touch screen may need to be transparent, in which case ITO electrodes and a plastic substrate are common. On the other hand a touch pad, such as often provided as an alternative to a mouse in laptop computers is usually opaque, and hence can use lower cost copper electrodes and an epoxy-glass-fibre substrate (e.g. FR4). Referring back to Figure 1, the electrodes 101, 102 are electrically connected via circuit conductors 104 to measurement circuitry 105, which is in turn connected to control circuitry 106 by means of a circuit conductor 107. The measurement circuitry 105 and I or the control circuitry 106 may each be provided by a (micro)controller, processor, ASIC or similar form of control chip. Although shown separately in Figure 1, in some implementations, the measurement circuitry 106 and the control circuitry 106 may be provided by the same (micro)controller, processor, ASIC or similar form of control chip. The measurement circuitry 105 and / or the control circuitry 106 may be comprised of a printed circuit board (PCB), which may further include the various circuit conductors 104, 107. The measurement circuitry 105 and the control circuitry 106 may be formed on the same PCB, or separate PCBs. Note also that the functionality provided by either of the measurement circuitry 105 and the control circuitry 106 may be split across multiple circuit boards and I or across components which are not mounted to a PCB. Generally speaking, the measurement circuitry 105 is configured to perform capacitance measurements associated with the electrodes 101, 102. The measurement circuitry 105 includes elements capable of applying a electrical signals (drive signals) for performing the capacitance measurements and, as described in more detail below, for performing some processing of the raw capacitance measurements. As described in more detail below, the measurement circuitry 105 outputs at least indications of the capacitance measurements to the control circuitry 106. The control circuitry 106 may be configured to perform a number of functions, including controlling the operations of the measurement circuitry 105. For example, the control circuitry 106 may send control signals to the various components forming the measurement circuity 105 for controlling the operation of these components. In the described implementation, the control circuitry 106 is also provided with the capability to determine the presence of a touch 109, caused by an object such a human finger or a stylus coming into contact with (or being adjacent to) the sense area of the sensor element 100, based on an appropriate analysis of relative changes in the electrode array’s measured capacitance / capacitive coupling. The control circuitry 106, may also be configured to, with appropriate analysis of relative changes in the electrode array’s measured capacitance / capacitive coupling, calculate a touch position on the cover’s surface as an XY coordinate 111. As described above, the functions of the control circuitry 106 may be provided across different circuit boards I components, and in the context of the implementation described above, it should be appreciated that dedicate circuit boards / components for the control of the measurement circuitry 105 and for processing of the capacitance measurements may be provided. In the example of Figure 1, a front cover (also referred to as a lens or panel) 108 is positioned in front of the substrate 103 and a single touch 109 on the surface of the cover 108 is schematically represented. Note that the touch itself does not generally make direct galvanic connection to the sensor 103 or to the electrodes 102. Rather, the touch influences the electric fields 110 that the measurement circuitry 105 generates using the electrodes 102 (described in more detail below). A further aspect of capacitive touch sensors relates to the way the measurement circuitry 105 uses the electrodes of the sensor element 100 to make its measurements. There are two main techniques for measuring capacitance, one or both of which may be employed by the measurement circuitry 105 of the described implementation. That is to say, the measurement circuitry 105 is configured to determine capacitances of one or more of the electrodes of the electrode array using one or both of a first technique and a second technique. A first technique is based on measuring what is frequently referred to as “selfcapacitance”. Reference is made to Figure 2. In Figure 2, the measurement circuitry 105 is configured to generate and apply an electrical stimulus (drive signal) to each electrode 101, 102 which will cause an electric field 110 to form around it. This field 110 couples through the space around the electrode back to the measurement circuitry 105 via numerous conductive return paths that are part of the nearby circuitry of the sensor element 100 and the product housing (shown schematically by reference numeral 114), or physical elements from the nearby surroundings 115 etc., so completing a capacitive circuit 116. The overall sum of return paths is typically referred to as the “free space return path” in an attempt to simplify an otherwise hard-to-visualize electric field distribution. The important point to realise is that the measurement circuitry 105 is only driving each electrode from a single explicit electrical terminal 117; the other terminal is the capacitive connection via this “free space return path”. The capacitance measured by the measurement circuitry 105 is the “self-capacitance” of the sensor electrode (and connected tracks) that is being driven relative to free space (or Earth as it is sometimes called) i.e. the “self-capacitance” of the relevant sensor electrode. Touching or approaching the electrode with a conductive element, such as a human finger, causes some of the field to couple via the finger through the connected body 118, through free space and back to the measurement circuitry 105. This extra return path 119 can be relatively strong for large objects (such as the human body), and so can give a stronger coupling of the electrode’s field back to the measurement circuitry 105; touching or approaching the electrode hence increases the self-capacitance of the electrode. The measurement circuitry 105 is configured to sense this increase in capacitance. The increase is strongly proportional to the area 120 of the applied touch 109 and is normally weakly proportional to the touching body’s size (the latter typically offering quite a strong coupling and therefore not being the dominant term in the sum of series connected capacitances). In the described implementation, the electrodes 101, 102 are arranged on an orthogonal grid, generally with a first set of electrodes on one side of a substantially insulating substrate 103 and the other set of electrodes on the opposite side of the substrate 103 and oriented at substantially 90° to the first set. In other implementations, the electrodes may be oriented at a different angle (e.g., 30°) relative to one another. In addition, it should also be appreciated that it is also possible to provide structures where the grid of electrodes is formed on a single side of the substrate 103 and small conductive bridges are used to allow the two orthogonal sets of electrodes to cross each other without short circuiting. However, these designs are more complex to manufacture and less suitable for transparent sensors. Regardless of the arrangement of the electrodes, broadly speaking, one set of electrodes is used to sense touch position in a first axis that we shall call “X” and the second set to sense the touch position in the second orthogonal axis that we shall call “Y”. When the measurement circuitry 105 operates in accordance with the selfcapacitance measuring mode, the measurement circuitry 105 can either drive each electrode in turn (sequential) with appropriate switching of a single control channel (i.e., via a multiplexer) or it can drive them all in parallel with an appropriate number of separate control channels. In the former sequential case, any neighbouring electrodes to a driven electrode are sometimes grounded by the measurement circuitry 105 to prevent them becoming touch sensitive when they are not being sensed (remembering that all nearby capacitive return paths will influence the measured value of the actively driven electrode). In the case of the parallel drive scheme, the nature of the stimulus applied to all the electrodes is typically the same so that the instantaneous voltage on each electrode is approximately the same. The drive to each electrode is electrically separate so that the measurement circuitry 105 can discriminate changes on each electrode individually, but the driving stimulus in terms of voltage or current versus time, is the same. In this way, each electrode has minimal influence on its neighbours (the electrode-to-electrode capacitance is non-zero but its influence is only “felt” by the measurement circuitry 105 if there is a voltage difference between the electrodes). A second technique is based on measuring what is frequently referred to as “mutualcapacitance”. Reference is made to Figure 3. In Figure 3, the measurement circuitry 105 will sequentially stimulate each of an array of transmitter (driven / drive) electrodes, shown as the X electrodes 101 in Figure 3, that are coupled by virtue of their proximity to an array of receiver electrodes, shown as the Y electrodes 102 in Figure 3. (It should be appreciated that the Y electrodes 102 may instead be the transmitting electrodes and the X electrodes 101 may instead be the receiving electrodes in other implementations). The resulting electric field 110 is now directly coupled from the transmitter to each of the nearby receiver electrodes; the “free space” return path discussed above plays a negligible part in the overall coupling back to the measurement circuitry 105 when the sensor element 100 is not being touched. The area local to and centred on the intersection of a transmitter and a receiver electrode is typically referred to as a “node” or “intersection point”. Now, on application or approach of a conductive element such as a human finger, the electric field 110 is partly diverted to the touching object. An extra return path to the measurement circuitry 105 is now established via the body 118 and “free-space” in a similar manner to that described above. However, because this extra return path acts to couple the diverted field directly to the measurement circuitry 105, the amount of field coupled to the nearby receiver electrode 102 decreases. This is measured by the measurement circuitry 105 as a decrease in the “mutualcapacitance” between that particular transmitter electrode and receiver electrodes in the vicinity of the touch 109. The measurement circuitry 105 senses this change in capacitance of one or more nodes. For example, if a reduction in capacitive coupling to a given Y-electrode is observed while a given X-electrode is being driven, it may be determined there is a touch in the vicinity of where the given X-electrode and given Y-electrode cross, or intersect, within the sensing area of the sensor element 100. The magnitude of a capacitance change is nominally proportional to the area 120 of the touch (although the change in capacitance does tend to saturate as the touch area increases beyond a certain size to completely cover the nodes directly under the touch) and weakly proportional to the size of the touching body (for reasons as described above). The magnitude of the capacitance change also reduces as the distance between the touch sensor electrodes and the touching object increases. As described above, the transmitter electrodes and receiver electrodes in the described implementation are arranged as an orthogonal grid, with the transmitter electrodes on one side of a substantially insulating substrate 103 and the receiver electrodes on the opposite side of the substrate 103. This is as schematically shown in Figure 3. As in Figure 2, the first set of transmitter electrodes 101 shown on one side of a substantially insulating substrate 103 and the second set of receiver electrodes 102 is arranged at nominally 90° to the transmitter electrodes on the other side of the substrate 103. In other implementations, the electrodes may be oriented at a different angle (e.g., 30°) relative to one another. In addition, other implementations may have structures where the grid is formed on a single side of the substrate and small insulating bridges, or external connections, are used to allow the transmitter and receiver electrodes to be connected in rows and columns without short circuiting. There are certain advantages and disadvantages associated with both of the two capacitive sensing techniques described above. Mutual capacitance techniques offer the ability to resolve multiple touches at different locations on the touch-sensitive element. While self-capacitance techniques do not, as a matter of course, provide this functionality, self capacitance techniques generally output a much stronger signal thus potentially increasing the sensitivity of the touch-sensitive element. In accordance with the principles of the present invention, the measurement circuitry 105 may be configured to operate in either of the selfcapacitance and / or mutual capacitance techniques depending on the application at hand. Figure 4 schematically shows the measurement circuitry 105 in accordance with an example implementation in more detail. The measurement circuitry 105 of Figure 4 comprises a first signal generator 2, a second signal generator 3, a digital to analogue converter (DAC) 4, an amplifier 5, an analogue to digital converter (ADC) 6, a first multiplier 7, a second multiplier 8, a first accumulator 9, a second accumulator 10, and calculating circuitry 11. Additionally shown in Figure 4, in highly schematic form, is sensor element 100. The sensor element 100 does not form part of the measurement circuitry 105 as such, but instead the measurement circuitry 105 is configured to couple to the sensor element 100. However, in some implementations, the measurement circuitry 105 and the sensor element 100 may be integrally formed. Not shown in Figure 4 is the control circuity 106 which, as described above, may send control signals to the components of the measurement circuitry 105 (such as the first and second signal generators 2, 3, first and second multipliers 7, 8, first and second accumulators 9, 10, and calculating circuitry 11). The control circuitry 106 also receives outputs from calculating circuitry 11, as detailed below. The first signal generator 2 is configured to generate a first signal. In the present implementation, the first signal is a “digital signal”, and hence the first signal generator 2 may be referred to as a first digital signal generator and the first signal may be referred to as a first digital signal. The term “digital signal” as used herein should be understood to encompass a signal which may take one of a plurality of finite levels (or discrete values) at any given time (this is in contrast to an analogue signal which represents a continuous range of values). Each of the discrete values of the digital signal may be represented in an appropriate way, for example each discrete value may be represented by a binary or hex code that is capable of being output by the first digital signal generator 2. Using digital signals enables digital processing to be performed which may have some benefits over analogue processing. The first digital signal is representative of a sinusoidal wave, and in the described implementation, the sinusoidal wave has a single frequency component. Accordingly, in the described implementation, the first digital signal generator 2 generates and outputs a digital representation of the sinusoidal wave as the first digital signal. For example, the first digital signal generator 2 may comprise a continuous digital sequence e.g., of n-bit binary codes, each representing one of a series of discrete values located in a memory or the like (i.e., a pre-stored sequence of codes representing the discrete values as a function of time). The first digital signal generator 2 may comprise n separate output lines (not shown in Figure 4), each able to output one of a “1” (e.g., when a voltage pulse is applied to the output line) or a “0” (e.g., when a voltage pulse is not applied to the output line) at any given time to output binary codes representing one of 2" possible discrete values. The first digital signal generator 2 may be configured to output the coded sequence at a predetermined rate to generate the first digital signal, for example, on the basis of an output from a clock or oscillator (e.g., associated with a (micro)processor or the like). By way of example, the clock cycle may be 32MHz, meaning that one n-bit code is output around once every 30 ns. However, it should be appreciated that the technique used to generate the first digital signal is not significant to the principles of the present disclosure, and any suitable technique may be used. The second signal generator 3 is configured to generate a second signal. In the present implementation, the second signal is similarly a “digital signal”, and hence the second signal generator 3 may likewise be referred to as a second digital signal generator 3 and the second signal may be referred to as a second digital signal. The second digital signal is similarly representative of a sinusoidal wave. More particularly, the second digital signal is representative of the same sinusoidal wave of the first digital signal, but one that is phase shifted. That is, the sinusoidal wave represented by the second digital signal has the same frequency and the same, or similar, amplitude as the sinusoidal wave represented by the first digital signal, but is provided at a different phase. More specifically, the sinusoidal wave represented by the second digital signal is orthogonal in phase to, e.g., 90° out of phase with, the sinusoidal wave represented by the first digital signal. Hence, assuming the sinusoidal waves have an angular frequency of w, the sinusoidal wave represented by the first digital signal can be broadly expressed by the function sin(wt) and the sinusoidal wave represented by the second digital signal can be broadly expressed by the function cos(wt). The first digital signal may be referred to as the “in phase” or “I” signal and the second digital signal may be referred to as the “quadrature” or “Q” signal. Accordingly, in the described implementation, the second digital signal generator 3 generates and outputs a digital representation of the sinusoidal wave as the second digital signal. The second digital signal generator 3 may similarly be provided with suitable components required to generate the second digital signal representing the sinusoidal wave. For example, the second digital signal generator 3 may function in substantially the same way as the first digital signal generator 2, but where the sequence of digital codes is offset (or out of phase) by 90° relative to the sequence used in the first digital generator 2. In such implementations, the second digital signal generator 3 functions largely independently of the first digital signal generator 2. However, in other implementations, such as that shown in Figure 4, the second digital signal generator 3 may be configured to receive information from the first digital signal generator 2 and generate the second digital signal on the basis of the received information from the first digital signal generator 2. For example, the second digital signal generator 3 may receive the first digital signal and use a look up table that maps the discrete values represented by a digital code (i.e., an n-bit binary code) of the first digital signal to a phase shifted discrete value represented by another digital code in accordance with the abovementioned mapping. In other words, the second digital signal generator 3 may effectively shift the received digital code of the first digital signal to another digital code representing a phase shifted value of the sinusoidal wave. Any suitable technique for generating the second digital signal on the basis of the information received from the first digital signal generator 2 may be implemented. In addition, the first and second digital signal generators 2, 3, may be synchronised so as to output the respective signals at substantially the same rate. For example in the described implementation, the control circuitry 106 is configured to cause the first and second digital signal generators 2, 3 to each output a corresponding digital (e.g., binary) code at predetermined times, e.g., based on the clock cycle of the micro(processor) of the control circuitry 106. Although the first and second digital signal generators 2, 3 are shown as separate components in Figure 4, the first and second digital signal generators 2, 3, may be implemented by a single electronic component I circuitry. The first and second digital signal generators 2, 3, may collectively be referred to as a digital signal generator. Referring back to Figure 4, the first digital signal is output from the first digital signal generator 2 and is sent to two different locations or along two different braches of the circuit. The first branch includes the DAC 4, sensor element 100, amplifier 5 and ADC 6, while the second branch bypasses these components and goes directly to the first multiplier 7. Taking the first branch first, the first digital signal is passed to the DAC 4. The DAC 4 is configured to convert the first digital signal to an analogue representation of the first digital signal (herein a first analogue drive signal) that is capable of being applied to an electrode 101, 102 of the electrode array of the sensing element 100. In essence, the DAC 4 is configured to receive the sequence of digital codes output from the first signal generator 2 representing the sequence of discrete values of the first digital signal and convert these discrete values into a smooth analogue signal representing a physical quantity, which in this case is a voltage. That is, the DAC 4 outputs an analogue voltage corresponding to the first digital signal. The DAC 4 may for instance assign each of the discrete values of the digital signal to a given voltage level at a given time in accordance with the timings of the first digital signal. This provides a series of voltage points over time. The DAC 4 may use suitable interpolation techniques, e.g., using a reconstruction filter, to “fill in” the spaces between the series of voltage points to generate a smooth and continuous voltage. Accordingly, the DAC 4 in Figure 4 may comprise any suitable DAC capable of converting the first digital signal to an analogue voltage signal. In some implementations, the DAC 4 may comprise, or operate in association with, a digital noise-shaping sigma-delta converter. The digital noise-shaping sigma-delta converter is used to convert the first digital signal into a one-bit serial digital output, based on the change (the delta) in the first digital signal. The digital noise-shaping sigma delta converter essentially samples the first digital signal at a high frequency (sometimes referred to as oversampling, where the frequency is substantially above the Nyquist rate). The delta is encoded as a series of pulses where the number and frequency of the pulses is proportional to the change. The series of pulses may then be sent to a single-bit DAC having a high bandwidth which converts the single bit-stream into an analogue signal. For example, this may comprise modulating an output voltage on the basis of the one-bit digital signal, akin to a pulse width modulation approach. Such an approach has been found to produce an analogue drive voltage signal with reduced noise in the spectral band occupied by the sinusoidal wave of the first digital signal. It should be appreciated that a single bit DAC 4 is a non-limiting example of a suitable DAC 4 and, depending on the specifics of the application at hand, any suitable DAC may be employed as the DAC 4 in the measurement circuitry 105. The analogue voltage signal output by the DAC 4 is subsequently applied to the sensor element 100, or more specifically, to ones of the electrodes 101 and 102. The analogue voltage signal output by the DAC 4 may be referred to as a first analogue drive signal, while the first digital signal may correspondingly be referred to as the first digital drive signal (although this digital drive signal is not, directly, applied to the electrodes 101, 102). The sensor element 100 represents an impedance to be measured, which may be influenced by a number of factors including the presence of a touch 109. As described above, the technique by which the touch-sensitive apparatus 1 detects changes in capacitive coupling may be the self-capacitance technique and / or the mutual capacitance technique. Accordingly, in the self-capacitance technique, the first analogue drive signal output by the DAC 4 is applied to an electrode of the electrode array and a corresponding parameter indicative of the self-capacitance of the electrode (such as a current) is able to be obtained. For the purposes of this description, the electrode to which the analogue voltage signal is applied is referred to as a driven electrode because it is driven by the first analogue drive signal. Conversely, in the mutual capacitance technique, the first analogue drive signal output by the DAC 4 is applied to an electrode of the electrode array, e.g., a transmission electrode 101, and a corresponding parameter indicative of the mutual capacitance between the transmission electrode 101 and a selected receiver electrode 102 (such as a current) is able to be obtained. For the purposes of this description, the electrode to which the first analogue drive signal is applied is referred to as a driven electrode. The operation of the sensor element 100 is explained in more detail above and is not repeated here for conciseness. As used herein, the DAC 4 and any electrical connections or components between the output of the DAC 4 and the sensor element 100, such as multiplexers or the like, are referred to herein as drive circuitry, and are provided with the purposes of apply the first analogue drive signal to the sensor element 100. The output from the sensor element 100 is a corresponding analogue signal (e.g., a current), which is subsequently based on the first analogue drive signal output by the DAC 4 (which in turn is based on the first digital drive signal). This first received analogue signal from the sensor element 100 therefore, broadly speaking, has the same form as the sinusoidal wave represented by the first digital drive signal. That is, the first received analogue signal is a sinusoidal wave having the same frequency as the sinusoidal wave represented by the first digital drive signal. Although the first received analogue signal is a sinusoidal wave having the same frequency as the sinusoidal wave represented by the first digital drive signal, the amplitude or magnitude between the two may be different. For instance, in the mutual capacitance measurement technique, the first analogue drive signal applied to the transmission electrode 101 induces a response (e.g., a current) in the corresponding receiver electrode 102. There may be a known proportional relationship between the amplitude of the first analogue drive signal applied to the driven (transmission) electrode and the amplitude of the first received analogue signal. As described above, the parameter indicative of a capacitive coupling (e.g., a mutual capacitance) may alter in the presence of a touch 109 and this generally manifests itself as a change in the amplitude of the sinusoidal wave. For example, in the mutual capacitance technique, in the presence of a touch 109, the capacitive coupling between the transmission electrode 101 and the selected receiver electrode 102 would be expected to decrease, and thus a relative decrease in the magnitude of the first received analogue signal in the presence of a touch 109 would be expected. Additionally, although the first received analogue signal is a sinusoidal wave having the same frequency as the sinusoidal wave represented by the first digital drive signal, there may be a difference in phase between the first received analogue signal and the first digital drive signal. Such a phase difference may be present due to the different path lengths of (i.e., the physical distance travelled by) the respective signals. In an ideal scenario, these are the only factors that affect the first received analogue signal. However, in practical terms, there are likely to be sources of noise (typically at different frequencies) from external sources and / or inherent interaction with different components of the touch sensitive apparatus which affect the characteristics of the first received analogue signal, such as the phase and / or amplitude of the received analogue signal. Referring back to Figure 4, the first received analogue signal is first passed through amplifier 5, and from amplifier 5 to ADC 6. As used herein, the amplifier 5 and ADC 6, and any suitable electrical connections or components between the output of the ADC 6 and the multipliers 7, 8 (described below), such as multiplexers or the like, are referred to herein as receiver circuitry, and are provided with the purposes of receiving the first analogue received signal from the sensor element 100. The amplifier 5 may be any suitable amplifier configured to amplify the first analogue received signal. In the described implementation, the amplifier 5 is a transimpedance amplifier (TIA) configured to convert the first received analogue signal, which is a current signal, into a corresponding voltage signal. Commonly, ADCs convert an analogue voltage to a digital signal, and thus the amplifier 5 in this implementation is used primarily to convert the received current signal to a corresponding voltage signal for processing at the ADC 6. In some implementations, the amplifier 5 may not be necessary. The analogue voltage signal output from the amplifier 5 is passed to the ADC 6. The ADC 6 is broadly configured to work in a similar manner to the DAC 4 but in reverse. That is, the ADC 6 converts the first received analogue (voltage) signal into a digital representation of the first received analogue (voltage) signal (herein referred to as the first received digital signal). The output of the ADC 6 is therefore a digital signal representing the first received analogue signal output from the sensor element 100. As should be appreciated in light of the above description, the first received digital signal has encoded within it a sinusoidal component that is related to the sinusoidal wave represented by the first digital drive signal. The ADC 6 may be configured to output any suitable digital signal. The ADC 6 in Figure 4 may comprise any suitable ADC capable of converting the received analogue voltage signal to the first received digital signal. In some implementations, the ADC 6 may output a multi-bit digital signal by assigning discrete values to the received analogue voltage signal. In some examples, the ADC 6 is configured to sample the first received analogue voltage signal at a sampling frequency, and subsequently quantise the sampled values into one of a plurality of discrete values. This general approach to analogue signal processing may more conventionally be known as pulse code modulation. The set of discrete values the ADC 6 may assign may be the same set of discrete values used by the first and second digital signal generators 2, 3. In alternative implementations, however, the number of discrete values used by the ADC 6 (that is, the number of bits of the digital signal output by the ADC 6) may be different to the number of discrete values used by the digital signal generators 2 and 3 (that is, the number of bits of the digital signal output by the digital signal generators 2 and 3). Generally, ADCs that output a lower-bit digital signal are easier and cheaper to implement than ADCs that output a higher bit signal but are generally of a lower resolution. Thus, a balance may be struck between cost / efficiency and resolution of the signal for the specific application at hand. In other implementations, the ADC 6 may output a single or one-bit digital signal. In this regard, the one-bit digital signal may encode the relative magnitude of the first received analogue signal at any given time by the number of single bits output in a given time period of the one-bit digital signal (or in other words, the frequency of the output bits). Using a single-bit converter to output a single or one-bit digital signal may be simpler and cheaper to implement than a multi-bit converter. To improve resolution, the single-bits may be output at a higher frequency. A suitable ADC 6 for the described implementation is a sigma-delta ADC configured to output a serial one-bit signal as the received digital signal. A sigma-delta ADC firstly performs a delta modulation, which encodes the change in the first received analogue signal between two points rather than the absolute value of the received analogue signal. The sigma-delta ADC comprises an analogue modulator that samples the analogue signal and produces a serial stream of bits (a one-bit or one bit level output). This is done at a high sample frequency (sometimes referred to as oversampling, where the frequency is substantially above the Nyquist rate) in order to increase the resolution of the final digital signal output by the ADC. The frequency of the bits in the serial one-bit data stream is proportional to the change in the analogue signal (the delta). More specifically, over a given time period, the frequency of “1”s and “0”s dictates how much the signal increases or decreases from its previous value. For example, for a sequence of six binary outputs, the sequence of “010101” represent no change in the amplitude of an analogue signal, whereas “111111” represents a maximum change in the positive direction of the analogue signal (i.e., an increase in the amplitude form a previous reference point) and “000000” represents a maximum change in the negative direction of the analogue signal (i.e., a decrease in the amplitude form a previous reference point). Hence, the one bit digital signal can be used to represent the received analogue signal. In some sigma-delta ADC converters, the sigma-delta converter comprises a digital filter which converts the stream of bits into a multi-bit output digital signal taking one of a plurality of discrete values in a process known as decimation. However, outputting the serial one-bit data stream as the first received digital signal directly to the first and second digital multipliers 7 and 8 is an alternative configuration. Broadly speaking, the sigma-delta ADC utilises a one-bit converter to produce a high frequency, low resolution bit stream encoding the change in amplitude of the received analogue voltage signal. It is easier and more cost effective to implement a single bit converter rather than a multi-level converter. The sigmadelta ADC 6 is controlled to output one bit at a frequency of once every clock cycle of the (micro)processor of the control circuitry 106. It should be appreciated, however, that in some implementations, the sigma-delta ADC may also be configured to convert the serial one-bit data stream to a multi-bit digital signal before sending to the multipliers 7 and 8 using, e.g., a digital filter. It should also be appreciated that other sigma delta converters, e.g., that output a 3-bit digital signal (instead of a 1-bit digital signal) may also be used in accordance with the principles of the present disclosure. It should be appreciated that a sigma-delta ADC is a non-limiting example of a suitable ADC and, depending on the specifics of the application at hand, any suitable ADC may be employed as the ADC 6 in the measurement circuitry 105. Referring back to Figure 4, the first received digital signal is output from the ADC 6 to the first and second multipliers 7 and 8. The multipliers 7 and 8 may be largely identical and differ only in the inputs received by the multipliers 7 and 8. As shown in Figure 4, the first multiplier 7 is configured to receive the first digital signal output from the first digital signal generator 2 and the first received digital signal output by the ADC 6. The second multiplier 8 is configured to receive the second digital signal output from the second digital signal generator 3 and the first received digital signal output by the ADC 6. Accordingly, the first and second multipliers 7 and 8 are each configured to multiply their corresponding inputs together. That is, the first multiplier 7 is configured to multiply the first digital signal and the first received digital signal, while the second multiplier 8 is configured to multiply the second digital signal with the first received digital signal. Broadly speaking, the multipliers 7, 8 may be configured to multiply corresponding codes of the respective digital signals together. That is, the first multiplier 7 is configured to multiply values of the first digital signal and the first received digital signal together at corresponding points in time and the second multiplier 8 is configured to multiply values of the second digital signal and the first received digital signal together at corresponding points in time. In the example described in Figure 4, the first received digital signal is a serial one-bit digital signal output by the sigma-delta ADC 6 at a frequency of one bit every clock cycle of the (micro)processor of the control circuitry 106. The one-bit digital signal takes values of “0” or “1”, as described above, so for each clock cycle outputs a value of “0” or “1”. As described above, the first digital signal comprises a digital code comprising n-bits (e.g., 16-bits) output for each clock cycle of the (micro)processor. The first multiplier 7 is configured to correspondingly multiply each bit of the n-bits of the digital code of the first digital signal output for a given clock cycle with a multiplication factor based on the corresponding bit output from the sigma-delta ADC 6 for that clock cycle. More specifically, the multiplication factor is either a value of “1” or “-1”, where the value “1” is used when the value “1” is output by the sigma-delta ADC and the value “-1” is used when the value “0” is output by the sigma-delta ADC 6. Additionally, the multiplier 7, 8 incorporates the sign attributed to the digital code as mentioned above in the multiplication process. The result of the multiplication is output to the first accumulator 9. Correspondingly, the second multiplier 8 correspondingly multiplies each bit of the n-bits of the digital code of the second digital signal output for a given clock cycle with a multiplication factor based on the corresponding bit output from the sigma-delta ADC 6 that clock cycle and the sign attributed to the digital code. The result of the multiplication is output to the second accumulator 10. It should be appreciated, however, that this is just an example of how the multiplication of two digital signals is performed, and that any suitable mechanism may alternatively be employed. For example, the multiplication of two, multi-bit digital codes representing discrete values of the first / second digital signals and the first received digital signal may be multiplied together and passed to the accumulators 9, 10. In accordance with the principles of the present disclosure, the multipliers 7, 8 are digital multipliers. Digital multipliers in the context of capacitive touch sensors offers several advantages. For example, in one implementation, the digital multipliers 7, 8 implement a “shift and add” architecture to allow for the relatively rapid multiplication of two binary values using, for example, an interconnected series of adders. Other more advanced techniques, such as the Baugh-Wooley algorithm or Wallace trees, may also be utilised in accordance with the present disclosure. The skilled person will appreciated that any suitable digital multiplier 7, 8 may be used in accordance with the present disclosure and the specific type of digital multiplier selected may depend on a variety of factors including the format of the first received digital signal and the first and second digital signals. With reference back to Figure 4, the first and second multipliers 7, 8 are configured to output the respective plurality of multiplied values to the first accumulator 9 and second accumulator 10 in accordance with each clock cycle. The first accumulator 9 is configured to accumulate (sum) the plurality of multiplied values output by the first multiplier 7. In this regard, the first accumulator 9 sums the plurality of multiplied values output by the first multiplier 7 over a predetermined time period, corresponding to a number (e.g., thousands) of clock cycles, essentially providing a cumulative total of the multiplied values with time. As should be appreciated, in the described implementation, the accumulators may effectively sum each individual multiplication result both for a given clock cycle and for sequential clock cycles. That is, the accumulators 9, 10 may sum each of the n-bits resulting from the multiplication of each of the n-bits of the digital code representing a discrete value of the first / second digital signal with the single-bit output (or multiplication factor associated therewith) from the ADC 6, and adds to this the results from the next subsequent multiplication for the next clock cycle, and so on. The predetermined time period may be any suitable length of time but generally a balance may be struck between the responsiveness of the system (i.e., how long the system takes to perform one complete set of measurements and, ultimately, identify if a touch is present) versus accuracy. In an example, the predetermined time period may be on the order of thousands to tens of thousands of clock cycles. The first accumulator 9 may be implemented in hardware or software and be arranged to perform suitable addition. Equally, the second accumulator 10 is configured in a similar manner to the first accumulator but is instead configured to accumulate the plurality of multiplied values output by the second multiplier 8. In this regard, the second accumulator 10 sums the plurality of multiplied values output by the first multiplier 8 over the predetermined time period, essentially providing a cumulative total of the multiplied values with time. The skilled person will appreciated that any suitable digital accumulator 9, 10 may be used in accordance with the present disclosure and the specific type of digital accumulator selected may depend on a variety of factors including the format and possible number of bits (the available discrete values) of the first received digital signal and the first and second digital signals. It should be appreciated that the outputs from the accumulator modules 9 and 10 can be thought of as representing corresponding baseband signals of the first received digital signal. In principle, any sinusoidal signal can be split (demodulated) into two baseband signals (or conversely any sinusoidal signal can be created using the two baseband signals). As described above, these baseband signals are the in-phase, I, signal and the quadrature, Q, signal, where the quadrature Q signal is 90° out of phase with the in phase I signal. The baseband signals can be thought of as representing a “real” and “imaginary” part of a sinusoidal signal, and indeed, this is how periodic sinusoidal waves are presented in some branches of mathematics. Accordingly, the outputs of the accumulators 9, 10 can be considered to represent a vector which can have any phase between 0 and 360°, when considering the real (I signal) as the x-axis value and the imaginary (Q signal) as the y-axis value on a Cartesian coordinate graph. The process of multiplying the digital signals and accumulating the results performs an IQ demodulation on the first received digital signal. The main purpose for performing the parallel in-phase and quadrature paths is to account for variation in the phase of the first received digital signal relative to the first digital signal, as described above. Although it is shown in Figure 4 that the multipliers 7 and 8 are separate from the respective accumulator modules 9 and 10, it will be appreciated that the multiplier and accumulator modules may be combined. That is, in some implementations the first multiplier 7 and the first accumulator 9 are combined into a first multiplier accumulator (MAC) module. Equally, the second multiplier 8 and the second accumulator 10 are combined into a second multiplier accumulator (MAC) module. Using combined MAC modules may help reduce the complexity of the system as a whole from a control perspective. Again, in accordance with the disclosure above, the MAC modules are configured to receive digital signals and perform processing on the digital signals. The output from the accumulators 9 and 10 are passed to the calculating circuitry 11. In this implementation, the calculating circuitry 11 is configured to take the output from both the first accumulator 9 and the second accumulator 10 and calculate the magnitude of the corresponding vector formed by the outputs of the first accumulator 9 and second accumulator 10. The magnitude of the vector is indicative of a component corresponding to the sinusoidal wave represented by the first digital signal in the first received digital signal. In particular, it is noted that the component of the received digital signal at the same frequency as the first digital signal can be determined irrespective of any phase shifts that the first received digital signal has experienced. In this regard, the measurement of each individual node or intersection point on the sensor element 100 is expected to result in a received digital signal of unique and unknown phase. Despite this, no uniformity or knowledge of the phases of individual nodes is assumed or required. Instead only the magnitude of the received signal is measured as it is found that this is the quantity that is modified when a human finger is brought into close proximity to each node. Broadly speaking, the magnitude of the first received digital signal is represented by the following formula: M = > / (l2 + Q2), where M is magnitude of the vector is indicative of a component corresponding to the sinusoidal wave represented by the first digital signal in the first received digital signal, I represents the accumulated value output by the first accumulator 9 (the in phase accumulated value) and Q represents the accumulated value output by the second accumulator 10 (the quadrature accumulated value). To perform such a calculation, the calculating circuitry 11 implements a suitable digital calculation algorithm. In the described implementation, the calculating circuitry 11 implements a CORDIC algorithm (Coordinate Rotation Digital Computer). This process takes advantage of the fact that the I and Q signals can be thought of to represent “real” and “imaginary” parts of the received digital signal and can be represented as a two-dimensional vector. The basic premise of the algorithm is to perform a series of rotations until the “imaginary” part of the signal tends to zero. The “real” part after the rotations hence represents the magnitude of the vector, and this is what is output by the calculating circuitry 11. This process is particularly effective for calculating magnitudes as it only requires the use of addition I adders to rotate the binary / digital number, rather than multipliers, and hence can reduce the overall footprint of the electronics involved. Accordingly, the calculating circuitry 11 outputs an indication of the magnitude of the associated vector, which is itself an indication of the capacitive coupling associated with the driven electrode of the electrode array 101, 102. As stated above, because the magnitude of the capacitive coupling varies with the presence or absence of a user’s touch 109 (or other object that capacitively couples to the electrode array, such as a stylus), the presence or absence of a touch 109 can be determined based on the magnitude of the vector as determined by the calculating circuitry 11. Accordingly, the magnitude of the vector can be output to the control circuitry 106 which is configured to perform suitable processing to determine if a touch 109 is present at the electrode I intersection point in accordance with conventional techniques. For instance, the magnitude of the vector may be compared to a pre-stored value of the magnitude for the electrode array or for specific electrode I electrode pairs, or the magnitude of the vector may be compared to previously obtained values for the electrode array or specific electrodes. If the difference between the calculated magnitude and the pre-stored or previously obtained value for the magnitude is sufficiently different, this may be interpreted by the control circuitry 106 as corresponding to a sensed touch 109. The circuitry described in Figure 4 applies a first drive signal to one of the plurality of electrodes of the electrode array 101, 102 and is capable of making a determination of the magnitude I strength of the capacitive coupling associated with that driven electrode (which may be the self-capacitance of the driven electrode or the mutual capacitance between the drive electrode and a selected receiver electrode). However, the circuitry is configured to drive only one of the electrodes of the electrode array 101, 102 at any time, and hence to perform a complete scan of the electrode array, each electrode or pairs of electrodes are measured. For example, taking an electrode array 101, 102 of a M x N grid (i.e., M x-electrodes 101 and N y-electrodes 102), in the self-capacitance measurement mode a total of M plus N measurements are made (where each of the M x-electrodes 101 and N y- electrodes are driven individually) while in the mutual capacitance measurement mode a total of M times N measurements are made, corresponding to each of the nodes associated with different pairs of x-electrodes and y-electrodes. Practically speaking, any received signal typically has an element of noise associated with it. Such a received signal may be assessed based on the signal to noise ratio (that is, the ratio of genuine signal to any noise signal within the received signal). The signal to noise ratio generally varies as the square root of n, where n is the number of samples taken of the received signal. In other words, the greater the number of samples taken, n, the higher the signal to noise ratio. A higher signal to noise ratio is generally desirable to help improve the sensitivity of the touch-sensitive apparatus. Assuming that the sampling rate is fixed (that is the number of samples n obtained per second of the received signal), then the signal to noise ratio varies as the square root of the time period that the samples are obtained for. If in the above example of a M x N grid of electrodes each measurement is obtained over a period of T, which provides for a certain signal to noise ratio, then the total time period required to perform a complete scan of the electrode array 101, 102 will be M plus N times T (for self-capacitance) or M times N times T (for mutual capacitance). (Note that this rough calculation assumes that the period T is the same for both mutual capacitance and selfcapacitance measurements, whereas in principle the time T may be different for each of these techniques). The Inventor has found that by adapting the circuitry of Figure 4, the total time required to complete a scan of the electrode array 101, 102 can be reduced. This may impact the touch sensitive apparatus 1 by either allowing for a more rapid response for detecting touches 109 (e.g., if the total scan can be performed more quickly, the control circuitry 106 can subsequently process the data from the complete scan earlier in time in order to detect touches 109 more quickly), or for allowing a higher signal to noise ratio to be obtained by in effect increasing the time period T per measurement while keeping the time to complete the full scan the same. Of course, it should also be appreciated that both of these characteristics (responsiveness and sensitivity) may be improved in other implementations. More specifically, the adaptation to the circuitry of Figure 4 includes driving a second electrode of the electrode array 101, 102 with the second signal generated by the second signal generator 3 simultaneously with driving a first electrode of the electrode array 101, 102 with the first signal generated by the first signal generator 2 (e.g., as described in Figure 4). Consequently, and as will be described in more detail below, measurements associated with capacitive couplings of both the first and second electrodes can be obtained simultaneously. As a result, a total complete scan of the electrode array 101, 102 can be completed, in effect, twice as quickly. Figure 5 schematically shows a modification of the measurement circuitry 105 in accordance with the principles of the present disclosure in more detail. Figure 5 will broadly be understood from Figure 4. Like components are identified with like reference signs and a description thereof will generally be omitted from the foregoing for conciseness. Referring to Figure 5, the measurement circuitry 105 of Figure 5 similarly comprises a first digital signal generator 2 and a second digital signal generator 3. The first and second digital signal generators 2 and 3 are the same as those referred to in Figure 4. That is, the first digital signal generator 2 is configured to generate and output a first digital signal having the form of a sinusoidal wave of a certain frequency, and the second digital signal generator 3 is configured to generate and output a second digital signal having the form of a sinusoidal wave of the same frequency but orthogonal to the first digital signal (e.g., 90° out of phase). The way in which the first digital signal and second digital signal are generated is not significant to the principles of the present disclosure, and any suitable technique may be used, such as any of the techniques described above. In the circuitry of Figure 5, two DACs 4, 44 are provided. The DAC 4 is substantially the same as the DAC 4 described with respect to Figure 4, and is configured to operate in substantially the same manner. That is, the DAC 4 is configured to receive the first digital signal, convert the first digital signal to a first analogue signal (e.g., an analogue voltage signal), and apply the first analogue signal to a first electrode of the electrode array 101, 102. The second DAC 44 is, in principle, the same as DAC 4 in that it is a suitable digital to analogue converter. However, as seen in Figure 5, the DAC 44 is arranged in the circuitry so as to receive the second digital signal and convert the second digital signal to a second analogue signal (e.g., an analogue voltage signal). Again, the DAC 44 may use any suitable technique to convert the second digital signal to the second analogue signal, such as any of the techniques that have been described extensively above. The DAC 44 is positioned so as to apply the second analogue signal to a second electrode of the electrode array 101, 102, where the second electrode of the electrode array is different to the first electrode of the electrode array 101, 102. Hence, broadly speaking, the DACs 4, 44 are provided to respectively convert the first and second digital signals to first and second analogue signals that are used to drive, simultaneously, different electrodes of the electrode array 101, 102. It should be appreciated that as compared to the circuitry of Figure 4, the circuitry of Figure 5 includes an additional DAC 44 that is provided for the purposes of converting the second digital signal into a suitable second analogue drive signal, where previously, the second digital signal was not applied in any form to the sensor element 100. In this implementation, the drive circuitry includes the DAC 4 as well as the DAC 44 along with any electrical connections or components between the output of the DACs 4, 44 and the sensor element 100 (such as multiplexers or the like), and is configured to apply the first analogue drive signal and the second analogue drive signal respective electrodes of the sensor element 100. The receiver circuitry is also configured in a different manner to the receiver circuitry of Figure 4. Primarily, the receiver circuitry of Figure 5 is configured to receive analogue outputs (e.g., of a current) corresponding to each of the applied analogue drive signals. For instance, when operating in the self-capacitance mode, a first received analogue signal from the sensor element 100 corresponds to the self-capacitance of the first electrode and a second received analogue signal from the sensor element 100 corresponds to the selfcapacitance of the second electrode. When operating in the mutual capacitance mode, a first received analogue signal from the sensor element 100 corresponds to the mutual capacitance between the first electrode and a first receiver electrode, and a second received analogue signal from the sensor element 100 corresponds to the mutual capacitance between the second electrode and a second receiver electrode (which may be the same or different to the first receiver electrode). This is schematically shown in Figure 5 where two conductor lines connect from the sensor element 100 to the input of the amplifier 5. Although the receiver circuitry is shown as separately receiving a first received analogue signal and a second received analogue signal, these two received analogue signals are combined by the receiver circuitry to form a combined received analogue signal. In particular, in the example of Figure 5, the two received analogue signals are input to a common input of the amplifier 5, where in effect, these two received analogue signals are summed before being processed by the amplifier 5. This configuration does not require a dedicated component for combining the two analogue received signals and makes use of the natural summation that is present by sending two electrical signals along a common conductor. However, in other implementations, a dedicated component may be implemented between the sensor element 100 and the input of the amplifier to combine the two received analogue signals, or the amplifier 5 may be suitable configured to receive the two received analogue signals and combine the signals before processing. The amplifier 5 is substantially the same as the amplifier 5 used in Figure 4, except in this instance the amplifier 5 is configured to amplify the combined received analogue (current) signal and output a combined received analogue (voltage) signal. The combined received analogue (voltage) signal is passed to the ADC 6. The ADC 6 is substantially the same as the ADC 6 of Figure 4, and may implement any of the analogue to digital conversion techniques as described above. The main function of the ADC 6 is to convert the combined received analogue signal to a combined received digital signal for subsequent processing. The multipliers 7, 8 and accumulators 9, 10 are configured broadly in the same way as for the circuitry of Figure 4, but in this implementation, operate on the basis of the combined received digital signal. In particular, the multiplier 7 is configured to receive the combined received digital signal and the first digital signal from the first digital signal generator 2, and multiply the corresponding signals together before outputting the multiplication result to the accumulator 9 where the accumulator 9 accumulates (sums) the outputs from the multiplier 7 for a predetermined period of time before outputting the accumulated result to the calculation circuitry 111. Similarly, the multiplier 8 is configured to receive the combined received digital signal and the second digital signal from the second digital signal generator 3, and multiply the corresponding signals together before outputting the multiplication result to the accumulator 10 where the accumulator 10 accumulates (sums) the outputs from the multiplier 8 for a predetermined period of time before outputting the accumulated result to the calculation circuitry 111. The multipliers 7, 8 and accumulators 9, 10 may take any suitable form in accordance with their counterparts in the circuitry of Figure 4, including being provided as combined multiplier and accumulator (MAC) modules. The calculation circuitry 111 is configured subtly differently to the calculation circuitry 11 of Figure 4. In this implementation, the calculating circuitry 111 is similarly configured to receive the output from both the first accumulator 9 and the second accumulator 10, but instead of calculating the magnitude of the two-dimensional vector formed by the output from both the first accumulator 9 and the second accumulator 10, the calculating circuitry 111 is instead configured to perform an adjustment of the output from both the first accumulator 9 and the second accumulator 10. In particular, and as will be explained below with reference to an example, the adjustment is performed in accordance with a predetermined relationship that is a function of both the output of the first accumulator 9 and the output of the second accumulator 10. The calculating circuitry 111 may implement a suitable digital calculation algorithm, such as for example a CORDIC algorithm (Coordinate Rotation Digital Computer). As noted above, the premise of the algorithm is to perform rotations of the vector formed by the output of the first and second accumulators 9, 10. The calculating circuitry 11 of Figure 4 performed a series of rotations of the vector until either of the in-phase, I, value or the quadrature, Q, valve, tended to zero, to subsequently determine the magnitude of the vector. However, the calculating circuitry 111 of Figure 5 is instead configured to perform a rotation by a predetermined amount, obtained in advance. In other words, mathematically, the calculation performed by the calculating circuitry 111 can be represented as: Mr where R is a rotation matrix, and the vector X, Y is a vector formed by the output of the first accumulator 9 (i.e., X) and the output of the second accumulator 10 (i.e., Y). The rotation matrix R may take any suitable form, but by way of a concrete example, takes the form below in one implementation: fcas(®) Wn(0) dos(@)7 (2) Accordingly, it can be seen from equations (1) and (2) that the calculation circuitry 111 is configured to perform an adjustment of the output of the first accumulator 9 and the second accumulator 10 by rotating the corresponding vector by an angle, ¢. Consequently, the adjusted values for the first accumulator 9 (herein Xa) and second accumulator 10 (herein Ya) are represented as follows: Xa — X cos(cp) — Y sin(rp) (3) Ya = Y sin(0) + X cos(<b) The calculating circuitry 111 after performing the rotation is configured to output the adjusted values Xa, Ya, to the control circuitry 106 for further processing as a first output and a second output. The adjusted values Xa, Ya as described in more detail below are set to be indicative of the capacitive couplings associated with the driven electrodes. In particular, the adjusted value Xa is associated with the capacitive coupling of the first driven electrode (either the self-capacitance of first driven electrode or the mutual capacitance of the first driven electrode with a selected receiver electrode), while the adjusted value Ya is associated with the capacitive coupling of the second driven electrode (either the self-capacitance of second driven electrode or the mutual capacitance of the second driven electrode with a selected, different, receiver electrode). Accordingly, the two outputs from the calculation circuitry 111 of the adjusted values Xa, Ya are indicative of the capacitive coupling associated with the first and second drive electrodes and subsequently may be processed by the control circuitry 106 accordingly. The angle, ¢, is determined in advance. The angle, ¢, is determined corresponding to the particular drive electrodes (and / or receiver electrodes, if used) that are driven by the drive circuitry to which the combined received digital signal relates. In other words, the angle, ¢, is specific to the electrodes of the electrode array being driven at that particular time. The values of the angle, ¢, may be determined in advance for various combinations of electrodes of the electrode array 101, 102 and, for example, stored in a memory forming part of the calculating circuitry 111 and / or that is accessible by the calculating circuitry 111. The calculating circuitry 111 may be provided with an indication of the electrodes of the electrode array 101, 102 being driven (e.g., from the control circuitry 106), such that the calculating circuitry 111 is able to recall the appropriate value of the angle, ¢, from the memory. The value of the angle, ¢, is selected so as to reduce or reverse (to the extent possible) any phase shift expected between the first digital drive signal and the first digital received signal and between the second digital drive signal and the second digital received signal. As described above, absent any noise, the phase shift between the first / second digital drive signal and the first / second digital received signal, respectively, is dependent on the path length that the first / second digital received signal travels relative to the first / second digital drive signal. Accordingly, the predetermined angle, ¢, is able to be set based on the signal path length associated with the first digital received signal and the second digital received signal. By setting the angle, ¢, to a value that reduces or reverses the phase shifts, it has been found that the adjusted values Xa and Ya can be considered to be largely indicative of the magnitude of the first received digital signal and second received digital signal, respectively, and thus indicative of the corresponding capacitive couplings. In principle, any two electrodes of the electrode array 101, 102 can be selected as the driven electrodes (and equally any two receiver electrodes of the electrode array can be selected as the receiver electrodes). The above equation (3) utilises a single value for the angle, ¢. However, because the phase shift between the first digital drive signal and the first digital received signal is independent of the phase shift between the second digital drive signal and the second digital received signal, the single value for the angle, ¢, for a given pair of drive electrodes (and receiver electrode(s)) may be set as the mean of the phase shift between the first digital drive signal and the first digital received signal and between the second digital drive signal and the second digital received signal. It should also be appreciated that when the phase shift between the first digital drive signal and the first digital received signal is different to the phase shift between the second digital drive signal and the second digital received signal the mean value of the phase shift is subsequently somewhere between the actual values of the phase shift that is experienced in both of these cases (i.e., between the first digital drive signal and the first digital received signal and between the second digital drive signal and the second digital received signal). What this means is that, potentially, the adjusted values (i.e., Xa and Ya) less accurately mirror the respective magnitudes of the first digital received signal and the second digital received signal, respectively. Therefore, to minimise this effect, the phase shifts between the first digital drive signal and the first digital received signal and between the second digital drive signal and the second digital received signal should be equal to, or as close as possible to, one another. As noted above, the phase shift is predominately impacted by the path length, i.e. the physical distance the received signal has to travel through the sensor element 100. Therefore, by driving pairs of electrodes 101, 102 that are spatially adjacent one another in the electrode array (e.g., by driving a first X-electrode 101 with the first analogue drive signal and a second X-electrode 101 with the second analogue drive signal that is the next in the sequence to the first X-electrode in the M x N grid of electrodes) the respective path lengths through the electrode array 101, 102 for the first digital received signal and the second digital received signal are fairly similar, and therefore the expected phase shifts between the first digital drive signal and the first digital received signal and between the second digital drive signal and the second digital received signal are also fairly similar. Accordingly, while in principle any combination of electrodes may be driven using the present technique, by driving electrodes that are spatially close to one another (and also selecting receiver electrodes that are the same or spatially close to one another, if used), the accuracy of the adjusted values Xa and Ya output by the calculation circuitry 111 to the corresponding magnitudes of the first digital received signal and the second digital received signal can be increased when spatially adjacent electrodes are driven. Accordingly, using the circuitry of Figure 5, by adjusting the values output by the accumulators 9, 10 to reverse or minimise the phase shift of the first received digital signal and the second received digital signal relative to the first and second digital drive signals respectively, the calculating circuitry 111 is capable of outputting separate values that are indicative of the capacitive coupling associated with the first drive electrode and the second drive electrode respectively. In this way, the time required to perform a total scan of the electrode array 101, 102 can be reduced as, in effect, two capacitive measurements are being made simultaneously in the same time period that only a single measurement is made using the circuitry of Figure 4. For instance, and with reference to the example M x N electrode array described above, two measurements (corresponding to two driven electrodes) may now be obtained over a period of T, as opposed to a single measurement as in the case of the circuitry of Figure 4. The total time period required to perform a complete scan of the electrode array 101, 102 will now be approximately one half of M plus N times T (for self-capacitance) or approximately one half of M times N times T (for mutual capacitance). Accordingly, the characteristics of the touch sensitive apparatus 1 can be improved by use of the circuitry of Figure 5, and hence, overall, the performance of the touch sensitive apparatus 1 may be improved. It has been described above that the calculating circuitry 111 utilises a CORDIC algorithm (as an example of a digit-by-digit algorithm or shift-and-add algorithm). However, it should be understood that the principles of the present disclosure are not limited to calculating circuitry 111 implementing a CORDIC algorithm and in other implementations the calculating circuitry 111 may implement alternative algorithms to perform the same or similar functions. Moreover, the algorithm implemented by the calculating circuitry 111 may be in hardware, for example through a suitably arranged FPGA, ASIC or the like, or it may be implemented in software. A particular advantage of the CORDIC algorithm is that it is capable of being implemented in hardware, in a relatively low cost and low complexity manner, and therefore may be suitable for particular applications where costs and complexity are to be minimised (in particular, the use of hardware multipliers or expensive processors can be avoided). In particular, it only requires the use of addition I adders to rotate the values, rather than multipliers, and hence can reduce the overall footprint of the electronics involved. It has also been described above that the circuitry of Figure 5 generates first and second digital drive signals that are converted to analogue drive signals, and additionally that the circuitry receives analogue signals from the sensor element that are converted to first and second digital received signals for processing. Performing processing in the digital space can be advantageous for several reasons, particularly in terms of ease of implementation in hardware, an improved control over the digital processing, lower energy requirements and reduce footprint for the electronic components. Thus, the burden of implementing the additional analogue to digital conversion steps outweighs the potential advantages. However, it should be appreciated that the principles of the present disclosure may be suitably applied to an analogue based system. In this regard, components such as the DACs 4, 44 and ADC 6 may be omitted from the circuitry, and suitable adaptations of the remaining components (such as the multipliers 7, 8, accumulators 9, 10 and calculating circuitry 111) may be made in order to handle the analogue signals. Referring now to Figure 6, Figure 6 shows flow diagram depicted an example method in accordance with the principles of the present disclosure. The method starts at step S1 with the generation of the first digital signal using the first digital signal generation module 2, under the control of the control circuitry 106. As specified previously, the first digital signal may be a sequence of digital codes, each digital code corresponding to one of a plurality of finite values. The first digital signal represents a sinusoidal wave of a fixed frequency. The method proceeds to step S2 with the generation of the second digital signal using the second digital signal generation module 3. The second digital signal is largely the same as the first digital signal, but is phase shifted. More specifically, the second digital signal is phase shifted by 90°. The second digital signal generation module 3 may receive the first digital signal from the first digital signal generation module 2 and use a suitable process (such as mapping the received value to a corresponding value that is shifted by 90° relative to the sinusoidal wave) to generate the second digital signal. The method the proceeds to step S3 where the first digital signal is applied to a first electrode of the sensor element 100 and the second digital signal is applied to a second electrode (different from the first electrode) of the sensor element 100. In this step, the first digital signal is converted to a first analogue drive / voltage signal using DAC 4 while the second digital signal is converted to a second analogue drive / voltage signal using DAC 44, as described above. The output from the DACs 4, 44 are relatively smooth, varying voltage signals (simulating the sinusoidal waveform of the first digital signal and second digital signal, respectively). The analogue voltage signals are applied to selected ones of the electrodes of the electrode array in accordance with a particular method for sensing capacitances (as described above). At step S4, the received digital signal is generated. In this step, the analogue drive signals applied to the sensor element 100 are used in a manner to provide a detectable analogue signal representative of the capacitive coupling of (at least a part of) the electrode array in accordance with the chosen method for sensing capacitances. As described above, by virtue of the two orthogonal analogue drive signals being simultaneously applied to different electrodes of the electrode array, in effect, two analogue signals are received from the sensor element 100 (corresponding to the two driven electrodes). These two received analogue signals are combined, to provide a combined analogue received signal, that is first amplified and converted into a voltage via transimpedance amplifier 5, before then being passed to ADC 6 and converted into the combined digital received signal. The received digital signal in some implementations may be a binary one-bit bitstream, as described above. The method then proceeds in parallel along steps S5 and S6, and along steps S7 and S8. At step S5, the first multiplier 7 receives the first digital signal generated in step S1 and the combined digital received signal generated in step S4 and multiplies the two together. More specifically, the first multiplier 7 is configured to use a digital multiplication technique to multiply corresponding portions (digital codes) of the first digital signal and the combined digital received signal, for example using a shift and add technique. The first multiplier 7 is configured to repeat the process and output a plurality of results of the multiplication, for example, corresponding to the multiplication of each digital code and / or each bit of the digital code of the respective digital signals. At step S6, the first accumulator 9 receives the output from the first multiplier 7 and sums consecutive outputs in a cumulative fashion. That is, the first accumulator 9 is configured to perform a digital addition to sum together two consecutive outputs from the first multiplier 7. The first accumulator 9 performs this summation for a predetermined period and, once the predetermined period has elapsed, transmits the result to the calculating circuitry 111. After the predetermined period has elapsed, the first accumulator 9 resets its memory and starts from zero to cumulatively add the results output from the first multiplier 7. At step S7, the second multiplier 8 receives the second digital signal generated in step S2 and the combined digital received signal generated in step S4 and multiplies the two together. More specifically, the second multiplier 8 is configured to use a digital multiplication technique to multiply corresponding portions (digital codes) of the second digital signal and the combined digital received signal, for example using a shift and add technique. The second multiplier 8 is configured to repeat the process and output a plurality of results of the multiplication, for example, corresponding to the multiplication of each digital code and / or each bit of the digital code of the respective digital signals. At step S8, the second accumulator 10 receives the output from the second multiplier 8 and sums consecutive outputs in a cumulative fashion. The second accumulator 10 is also configured to perform a digital addition to sum together two consecutive outputs from the second multiplier 8. The second accumulator 10 performs this summation for a predetermined period and, once the predetermined period has elapsed, transmits the result to the calculating circuitry 111. After the predetermined period has elapsed, the second accumulator 10 resets its memory and starts from zero to cumulatively add the results output from the second multiplier 8. At step S9, the calculating circuitry 111 receives the output from the first and second accumulators 9, 10 at steps S6 and S8, respectively, and under control of the control circuitry 106 (or other suitable control circuitry), is configured to adjust the output of the first and second accumulators 9, 10 using a predetermined relationship that is a function of the both of the outputs of the first and second accumulators 9, 10. More specifically, the calculating circuitry 111 is configured to rotate the vector formed by the outputs of the first and second accumulators 9, 10 using, for example, a CORDIC algorithm. As described above, the CORDIC algorithm can be implemented in hardware or software that does not require digital I binary multipliers and can instead use digital I binary adders. In accordance with the present disclosure, the CORDIC algorithm is arranged to rotate the aforementioned vector by a predetermined angle that is related to the driven electrodes of the electrode array 101, 102. The calculating circuitry 111 then outputs the adjusted values after rotation by the predetermined angle to the control circuitry 106 which is configured to determine the presence or absence of a touch 109 corresponding to either of the first or second driven electrodes on the basis of the adjusted values output by the calculating circuitry 111. More specifically, a first adjusted value output by the calculating circuitry 111 is indicative of the capacitive coupling associated with the first driven electrode and a second adjusted value output by the calculating circuitry 111 is indicative of the capacitive coupling associated with the second driven electrode. It has been found, particularly when the first and second driven electrodes are spatially, directly adjacent one another in the electrode array 101, 102 (and, if used, any corresponding receiver electrodes are either the same or spatially, directly adjacent one another) that the adjusted values output by the calculating circuitry 111, after rotation by a suitable predetermined angle, are largely independent of one another. In this respect, it should be appreciated that “largely independent” of one another means that for a given adjusted value, this is largely unaffected by changes in capacitance associated with the other driven electrode. The degree of cross-talk between the adjacent values (i.e., the degree to which a change in capacitance associated with one driven electrode influences the output of the adjusted value associated with the other driven electrode) is dependent, in part, on the difference in the phase shifts between the first digital drive signal and the combined digital received signal and the second digital drive signal and the combined digital received signal, respective signals. When this difference is minimised, e.g., by selected drive electrodes that are spatially adjacent one another, the cross-talk is subsequently minimised. While cross-talk may not be completely eliminated, e.g., by virtue of the fact the respective path lengths may not be completely identical, therefore making these adjusted values not completely independent from one another, it has been found that the degree of cross-talk is not significantly different from levels that may be expected in conventional touch sensitive apparatuses when driving electrodes in parallel, which may be handled or compensated for by conventional means. Accordingly, changes in the magnitudes of the adjusted values, relative to one or more reference values (e.g., obtained in advance, and in the absence of a touch 109) can be used to determine whether a touch 109 is detected in the vicinity of a given electrode 101, 102. For example, in a mutual capacitance technique, the adjusted value of a node (i.e., an intersection of the driven electrode with a receiver electrode) can be determined in advance and in the absence of a touch 109 to be used as a reference value for that node, and if a corresponding adjusted value for the same node is obtained at a later time that has decreased below a threshold amount from the reference value, the control circuitry 106 can determine that a touch 109 is present at that node. Consequently, based on the adjusted values, the control circuitry 106 is capable of determining whether a touch 109 on the touch sensitive apparatus 1 is present or not. Although not shown in the method of Figure 6, it should be appreciated that steps S1 to S9 are repeated during operation of the touch sensitive apparatus 1. In particular, each drive electrode (and if present, each receiver electrode) is to be measured in order to perform a complete scan of the electrode array 101, 102. Under the self-capacitance measurement technique, an M x N electrode array comprises M plus N electrodes to be driven for a complete scan. According, steps S3 to S9 are first performed while a first and second electrode are driven with the first and second drive signals, before being repeated with a third and fourth electrode being driven by the first and second drive signals, and so on until all electrodes of the array have been driven. Under the mutual capacitance measurement technique, an M x N electrode array comprises M times N nodes of electrodes to be driven for a complete scan. In this case, to perform a complete scan, steps S3 to S9 are first performed while a first and second electrode are driven with the first and second drive signals and a first and second receiver electrode are coupled to the receiver circuitry, before being repeated with a third and fourth receiver electrode coupled to the receiver circuitry while the first and second drive electrodes continue to be driven by the first and second drive signals. Once all receiver electrodes have been measured, this process is repeated for all pairs of drive electrodes in order to perform a complete scan. It should be appreciated that for either measurement technique, step S9 may be performed each time an output from the accumulators 9, 10 is received at the calculating circuitry 111, or the calculating circuitry 111 may wait until a complete (or partial) scan is completed before outputting the adjusted values. Under both measurement techniques, when a complete scan of the electrode array 101, 102 is performed, a subsequent scan may be initiated and the process repeats for the subsequent scan. In other implementations, a further reduction in the time that is required to perform a complete scan may further be realised by implementing a so-called code division multiplex technique. The code division multiplex technique involves driving a group of electrodes simultaneously for a plurality of sequential time periods, and obtaining measurements in each of the time periods that are based on the combinations of the received signals corresponding to the group of electrodes that are driven for that time period. The electrodes of the group are driven with two drive signals, orthogonal to one another but 180° out of phase with one another. For each of the time periods, different drive signals are applied to different ones of the group of drive electrodes. This technique may be applied in combination with the method of Figure 6, as will be described below. Figures 7a to 7b exemplify how a group of, in this case four, electrodes of the electrode array 101, 102 are driven in various scenarios using schematic representations of the electrodes 101 and 102 of Figure 1. Other features of Figure 1 are omitted from Figures 7a to 7b for reasons of clarity. Figures 7a to 7b illustrate a group of four drive electrodes 101 and a single receive electrode 102. For facilitating explanation, each of the drive electrodes has an identifier 1 to 4. In addition, the electrodes are shown artificially grouped in pairs, primarily for ease of explanation in the foregoing (e.g., there is a larger separation between electrodes 2 and 3, than between 1 and 2). In other implementations, the spacing between the electrodes 101 may be uniform. Figure 8 schematically shows an example arrangement of the circuitry used to implement the combined code division multiplexing with the technique of Figure 6. Figure 8 will broadly be understood from Figure 5, as explained in more detail below. In essence, the circuitry of Figure 8 is the same as the circuitry of Figure 5 but includes a set of additional signal generators 2’, 3’ (and additional DACs 4’, 44’). The function of these additional signal generators 2’, 3’ is to provide a further drive signal for driving pairs of the electrodes (as will be explained in more detail below). More particularly, the circuitry of Figure 8 includes a third signal generator 2’, fourth signal generator 3’, third digital to analogue converter (DAC) 4’, and fourth digital to analogue converter (DAC) 44’, in addition to the components of the circuitry of Figure 5. It will be appreciated from the below that Figure 8 represents an example layout for the circuitry only and in other implementations, the circuitry may be arranged different. In particular, certain components may be shared or duplicated amongst the two parts of the circuitry. In accordance with a code division multiplex implementation, the circuitry (e.g., measurement circuity 105) is configured to generate two orthogonal signals, e.g., sine waves, that are 180° out of phase with one another (or the inverse of one another), but which otherwise are substantially the same (e.g., same frequency, same amplitude, etc.). For ease of explanation, we will refer to these signals herein as signal 1 and signal 2. Signal 2 may also correspondingly be referred to as the inverse of signal 1. Signal 1 may, mathematically, be represented as sin(wt) and signal 2 may be represented as sin(wt +tt) or simply -sin(wt). These signals are then applied to the electrode array 101, 102 in certain codes or patterns over a plurality of discrete time periods, and measurements are taken from the electrode array 101, 102 (e.g., from a receiver electrode 102 thereof). Figure 7a shows the way in which the signals 1 and 2 are applied to a plurality of four drive electrodes, labelled 1 to 4, for a first time period, T1. In the example of Figure 7a, electrode 1 is driven with signal 1. Signal 1 is equivalent in this instance to the first analogue drive signal as described above. That is, the first signal generator 2 of Figure 8 generates a first digital drive signal which is converted using the first DAC 4 to the first analogue drive signal (or signal 1) and then applied to electrode 1 of the electrode array 101, 102. Electrode 2 is driven with a signal that is 90° out of phase with signal 1 (shown as signal 1+90° in Figure 7a). In other words, this signal, signal 1+90°, is equivalent to the second analogue drive signal as described above. Correspondingly, the second signal generator 3 of Figure 8 generates a second digital drive signal which is converted using the second DAC 44 to the second analogue drive signal (or signal 1+90°) and then applied to electrode 2 of the electrode array 101, 102. So far, this process is identical to the approach described above, for example with reference to Figures 5 and 6. In addition to the above, electrode 3 and electrode 4 are driven in substantially the same manner as electrodes 1 and 2. That is, electrode 3 is driven with signal 1 (e.g., as generated by signal generator 2 of Figure 8 that generates the first digital drive signal which is converted using the first DAC 4 to the first analogue drive signal (or signal 1) and then applied to electrode 3 of the electrode array 101, 102), and electrode 4 is driven with a signal that is 90° out of phase with signal 1 (e.g., as generated by signal generator 3 of Figure 8 that generates the second digital drive signal which is converted using the second DAC 44 to the second analogue drive signal (or signal 1 +90°) and then applied to electrode 4 of the electrode array 101, 102). In this regard, it should be appreciated that the drive signals as generated by the third and fourth signal generators 2’, 3’ are not applied to any of the drive electrodes 1 to 4 during the first time period T1 (in this particular implementation). In conventional code divisional multiplexing, only electrodes 1 and 3 would be driven using the abovementioned signal 1. Signal 1 is applied to both electrodes for the first time period T1. Because both electrodes are driven with signal 1, which may be considered a reference signal, the code or pattern for this conventional code division multiplexing can be denoted as (+, +), where the symbol '+’ denotes the non-inverted version of signal 1 is applied to electrodes 1 and 3. In conventional code division multiplexing, it would be possible to obtain indications of the capacitive coupling between electrodes 1 and 3 and the receiver electrode 102, respectively. However, by additionally using the abovementioned technique of Figures 5 and 6, however, it is possible to drive electrodes 2 and 4 simultaneously with electrodes 1 and 3, and as will be appreciated from the below, additional information may be extracted from the measurements made (namely, indications of the capacitive coupling between electrodes 1 and 3 and the receiver electrode 102, respectively). With reference back to Figures 7a and 8, during the first time period, T1, a measurement M1 is made from the electrode array 101, 102 which is indicative of the summation of the capacitive coupling of each of the four drive electrodes 1 to 4 with the receiver electrode 102. Figure 8 schematically shows signal lines being coupled to the amplifier 5 representing the transmission of a combined signal comprising components from each of electrodes 1 to 4. In much the same way as Figure 5, this represents a combined received analogue signal, although in this example, the combined received analogue signal is a combination of the output from four drive electrodes, not just two drive electrodes. The combined received analogue signal is passed to the ADC 6 and converted to a combined digital received signal, which is then passed to the respective multipliers 7, 8. In mathematical terms, the combined received analogue signal can be considered to comprise components from corresponding to each of the capacitive couplings between the drive electrodes 1 to 4 and the receiver electrode 102. In particular, in the first time period, the output from the sensor element 100 (i.e., measurement M1), may be represented as follows: M1 = E1sin(wt) + E2cos(wt) + E3sin(wt) + E4cos(cot) (4) where each term / component of equation (4) is indicative of a component corresponding to the capacitive coupling of one of the driven electrodes 1 to 4 with the receiver electrode 102, wherein the component is represented as an amplitude EN (where N is the value 1, 2, 3, or 4) modulated by the drive signal applied to the drive electrode, which in this example is represented either by sin(wt) for signal 1 or cos(wt) for signal 1+90°. The measurement M1 is provided to the multipliers 7, 8 and accumulators 9, 10 in a similar manner to that described above. Namely, the first multiplier 7 receives the first digital signal I signal 1 from the first signal generator 2 and multiplies this with the received combined digital signal output from ADC 6, before passing to the first accumulator 9 to output a value. Similarly, the second multiplier 8 receives the second digital signal I signal 1+90° from the second signal generator 3 and multiplies this with the received combined digital signal output from ADC 6, before passing to the second accumulator 10 to output a value. It should be appreciated that the multipliers 7, 8, in effect, multiply measurement M1 by either signal 1 (i.e., sin(wt)) or signal 1+90° (i.e., cos(wt)), respectively. When the output of this multiplication is summed over a period of time, by the accumulators 9 and 10, the output from the accumulator 9 can be represented as a (E1+E3) and the output from the accumulator 10 can be represented as a (E2+E4), where the parameter a is a feature of the accumulators 9, 10 performing a summation of several outputs from the multipliers 7, 8 over time. Using the terminology above, these two outputs can be identified as the X and Y values, e.g., as follows: Xi = a (E1 + E3) (5) Yi = a (E2 + E4) where the subscript T signifies the values are determined based on measurement M1 (or alternatively, based on the output during the first time period, T1). Figure 7b shows the way in which the signals 1 and 2 are applied to a plurality of four drive electrodes, labelled 1 to 4, for a second time period, T2. In the example of Figure 7b, electrode 1 is driven with signal 1 and electrode 2 is driven with signal 1+90° in a similar manner to as described above. However, the way in which electrodes 3 and 4 are driven in the second time period, T2, is different. In particular, electrode 3 is now driven with a drive signal that is based on the inverse of the first drive signal (i.e., a signal that is 180° out of phase with the first drive signal). As explained above, this can be denoted as signal 2. Accordingly, electrode 3 is driven with signal 2 in the time period T2 (whereby now the third signal generator 2’ of Figure 8 generates and provides what we may call a third digital drive signal, that is 180° out of phase with the first digital drive signal, which is then converted using the third DAC 4’ to the third analogue drive signal (or signal 2) and then applied to electrode 3 of the electrode array 101, 102). Similarly, electrode 4 is driven with a signal that is 90° out of phase with signal 2 (labelled signal 2+90° in Figure 7b). The fourth signal generator 3’ of Figure 8 generates a fourth digital drive signal, that is 90° out of phase with the third digital drive signal, which is converted using the fourth DAC 44’ to a fourth analogue drive signal (or signal 2+90°) and then applied to electrode 4 of the electrode array 101, 102. In this regard, it should be appreciated that the circuitry 105 of Figure 8 may be provided with suitable multiplexers or the like to allow signals 1, 1+90°, 2, and 2+90° to be applied to the corresponding drive electrodes in the relevant time periods T1, T2. In the second time period T2, because electrode 1 is driven by signal 1, and electrode 3 is driven by signal 2, which is the inverse of signal 1, the code or pattern can by which the electrodes are driven can be denoted as (+, -), where now the symbol denotes the inverted version of signal 1, i.e., signal 2, is applied to electrode 3 in this implementation. With reference back to Figure 7b and Figure 8, during the second time period, T2, a measurement M2 is similarly made from the electrode array 101, 102 which is indicative of the summation of the capacitive couplings of each of the four electrodes 1 to 4 with a receiver electrode 102. In mathematical terms, the combined received analogue signal for the measurement M2 can be considered to comprise the summation of components from each of the corresponding drive electrodes. In particular, in the second time period, the output from the sensor element 100 (i.e., measurement M2), may be represented as follows: M2 = E1sin(wt) + E2cos(wt) - E3sin(wt) - E4cos(wt) (6) where each term of equation (6) is indicative of a component corresponding to the capacitive coupling of one of the driven electrodes 1 to 4, wherein the component is indicated as an amplitude EN (where N is the value 1, 2, 3, or 4) modulated by the drive signal applied to the electrode, which in this example is represented either by sin(wt) for signal 1, cos(wt) for signal 1+90°, -sin(wt) for signal 2, and -cos(wt) for signal 2+90°. The measurement M2 is provided to the multipliers 7, 8 and accumulators 9, 10 in a similar manner to that described above. Namely, the first multiplier 7 receives the first digital signal I signal 1 from the first signal generator 2 and multiplies this with the received combined digital signal, before passing to the first accumulator 9 to output a value. Similarly, the second multiplier 8 receives the second digital signal / signal 1+90° from the second signal generator 3 and multiplies this with the received combined digital signal, before passing to the second accumulator 10 to output a value. It should be appreciated that the multipliers 7, 8, in effect, multiply measurement M2 by either signal 1 (i.e., sin(ajt)) or signal 1+90° (i.e., cos(wt)), in substantially the same manner as described above. When the output of this multiplication is summed over a period of time, by the accumulators 9 and 10, the output from the accumulator 9 can be represented as a (E1-E3) and the output from the accumulator 10 takes the form a (E2-E4), where the parameter a is a feature of the accumulators 9, 10 performing a summation of several outputs from the multipliers 7, 8. Using the terminology above, these two outputs can be identified as the X and Y values, e.g., as follows: X2 = a (E1 - E3) Y2 = a (E2 - E4) (7) where the subscript ‘2’ signifies the values are determined based on measurement M2 (or alternatively, based on the output during the second time period). In order to obtain an indication of the magnitudes of the capacitive couplings, EN, for each of the drive electrodes 1 to 4 with the receiver electrode 102, the calculating circuitry 111 is configured to perform a manipulation of the values Xi, 2 and Yi, 2. The specific way in which these values are manipulated will depend on the “codes” used to drive the drive electrodes in the first and second time periods T1, T2. In the present example, the codes are specified above as (+, +) and (+, -) and these codes can be applied to the values Xi,2 and Yi, 2 in order to provide the values EN. Mathematically, for the above example, 2 a E1 = Xi + X2 = a (E1 + E3) + a (E1 - E3) 2 a E2 = Yi + Y2 = a (E2 + E4) + a (E2 - E4) 2 a E3 = Xi - X2 = a (E1 + E3) - a (E1 - E3) 2 a E4 = Yi - Y2 = a (E2 + E4) - a (E2 - E4) (8) Hence, by providing manipulations (i.e., additions and subtractions) of the values Xi,2 and Yi, 2 output from the accumulators 9, 10, it is possible to obtain indications of the magnitudes of the capacitive couplings between the drive electrodes (i.e., drive electrodes 1 to 4) and receiver electrodes 102. However, more significantly, by using a combination of a code division multiplex approach with the technique of Figures 5 and 6 (which, in essence, is the simultaneous driving of a pair of, ideally adjacent, electrodes with signals that are phase-shifted by 90° from one another), a significant further reduction in the time it takes to scan an electrode array 101, 102 can be realised. Using solely the technique of Figure 5, two electrodes may be scanned in a period of time that is equal to T1 plus T2 with a similar signal to noise ratio (noting here that the measurements M1 and M2 in the code divisional multiplex technique both contribute to the overall signal to noise ratio for each driven electrode). Conversely, four electrodes may be scanned in similar overall time period when combining the code division multiplex approach with the technique described in Figure 5 and 6, thereby in effect halving the time required for a total scan of the electrode array 101, 102. As noted above, by being able to reduce the time required to complete a scan of the electrode array, this may impact the touch sensitive apparatus 1 by either allowing for a more rapid response for detecting touches 109 (e.g., if the total scan can be performed more quickly, the control circuitry 106 can subsequently process the data from the complete scan earlier in time in order to detect touches 109 more quickly), or for allowing a higher signal to noise ratio to be obtained by in effect increasing the measurement time period T (e.g., T1 + T2) per measurement while keeping the time to complete the full scan the same. Of course, it should also be appreciated that both of these characteristics (responsiveness and sensitivity) may be improved in other implementations. Code division multiplexing may be implemented with more than four electrodes. For example, conventional code division multiplexing can be implemented using sets of electrodes having 2, 4, 8, 12, 16, 20, etc. groups of electrodes which, when combined with the technique of the present disclosure (i.e., as described in Figure 5), means the sets of electrodes that can be driven are 4, 8, 16, 24, 32, 40, etc. Depending on the number of drive electrodes in a particular group, the number of discrete time periods used and hence measurements, as well as the codes used to drive the electrodes varies. For example, for a conventional group of 4 drive electrodes (or a group of 8 drive electrodes when combined with the technique of Figure 5), a total of four time periods and four different sets of codes can be used to drive the set of electrodes. The codes applied to the driven electrodes may also dictate how the X and Y values are combined in order to provide an indication of the corresponding capacitances EN. The above described example is a simplification which assumes there is no phase difference or phase shift between the drive signals and the received signals. However, as should be appreciated from the techniques described in respect of Figures 5 and 6, in instances where there is a phase difference or phase shift, the calculating circuitry 111 is configured to perform rotations of the vectors formed by the output of the first and second accumulators 9, 10. As described for the technique of Figures 5 and 6, the calculation circuitry 111 is configured to perform an adjustment of the outputs of the first accumulator 9 and the second accumulator 10 by rotating the corresponding vectors by one or more angles, ¢. Similarly to the techniques described above, the values Xi, 2 and Yi, 2 are able to be modified or adjusted based on a rotation to provide adjusted values XiA, 2a and YiA, 2a, for example using a similar rotation to equation (3). The calculating circuitry 111 after performing the rotation is configured to use the adjusted values XiA, 2a and YiA, 2a to obtain indications of the magnitudes of the capacitive couplings between the drive electrodes (i.e., drive electrodes 1 to 4) and receiver electrodes 102, for example using equations (8) but XiA, 2A and YiA, 2A in place of Xi, 2 and Yi, 2. In general, therefore, the combination of code division multiplexing and the technique of Figure 5 and 6, utilises four signals to drive a group of N electrodes for a total of N / 2 discrete time periods, where N is a whole number equal to 4, 8, 16, 24, 32, 40, etc. The four signals used to drive the group of N electrodes may be referred to as a first drive signal, a second drive signal that is 90° (of substantially 90°) out of phase with the first drive signal, a third drive signal which is the inverse of the first drive signal (i.e., 180° out of phase with the first drive signal) and a fourth drive signal which is the inverse of the second drive signal (i.e., 180° out of phase with the second drive signal, or 270° out of phase with the first drive signal). It should be appreciated that the circuitry may comprise any suitable arrangement to generate these signals to drive the group of N drive electrodes (e.g., each electrode may be selectively couplable to one of two signal generators, e.g., via a multiplexer). The group of N drive electrodes may be artificially split into a first group of N / 2 drive electrodes and a second group of N / 2 drive electrodes (where each of the drive electrodes forms either a part of first group of N / 2 or the second group of N / 2). However, each of the group of N drive electrodes are also artificially split into pairs of electrodes, with one of the pair being from the first group of N / 2 electrodes and the other of the pair being from the second group of N / 2 electrodes. For the reasons as explained above, it is beneficial in order to reduce error if the pair of electrodes are spatially adjacent one another (as the expected phase shifts will be approximately the same for both electrodes). Therefore, it can be seen that the group of N electrodes can be considered as comprising a first group of N / 2 electrodes that are spatially interleaved with a second group of N / 2 electrodes. The first group of N / 2 electrodes are capable of being driven with either of the first drive signal or the third drive signal (i.e., the inverse of the first drive signal) and may be considered to represent the electrodes that are driven in accordance with a conventional code division multiplex approach. As described above, for each of the N / 2 discrete time periods, the pattern of first and third drive signals applied to the first group of N / 2 drive electrodes is set to be different. The specific way in which the first group of N / 2 drive electrodes is driven will depend on the number N. However, regardless of the number N, in at least two of the N / 2 discrete time periods, at least one of the first group of N / 2 drive electrodes is driven with a different one of the first or third drive signals (e.g., as in the example above, electrode 3 is driven with the first drive signal in the time period T1, and the third drive signal in the time period T2). The second group of N / 2 electrodes are capable of being driven with either of the second drive signal or the fourth drive signal. Whether the electrodes are driven with the second or fourth signal will depend on the signal that is applied to the corresponding electrode of the pair of electrodes. That is, if the electrode of the pair of electrodes belonging to the first group of N / 2 electrodes is driven with the first drive signal, then the electrode of the pair of electrodes belonging to the second group of N / 2 electrodes is driven with the second drive signal. Conversely, if the electrode of the pair of electrodes belonging to the first group of N / 2 electrodes is driven with the third drive signal, then the electrode of the pair of electrodes belonging to the second group of N / 2 electrodes is driven with the fourth drive signal. Hence, the same pattern or code of drive signals that is applied to the first group of N / 2 electrodes is applied to the second group of N / 2 electrodes, albeit with corresponding signals that are phase shifted by 90°. The combined received signal that is received from the electrode array contains components that correspond to each of the group of N drive electrodes. That is to say, the combined received signal is a function of the capacitive couplings associated with all of the drive electrodes of the group of N drive electrodes. The outputs from the corresponding multipliers / accumulators / MACs are output to the calculating circuitry 111. Each of the outputs from the multipliers / accumulators / MACs is representative of the capacitive couplings of either the first group of N / 2 electrodes or the second group of N / 2 electrodes. Optionally, by using the same process as described in equation (3) above, with a suitable angle, cp, selected for the pair of electrodes, each of the outputs of the multipliers are able to be adjusted to provide the adjusted outputs Xna, Yna by the calculating circuitry 111 as in the manner described above. Note that the angle, (p, may be different for different pairs of the group of N drive electrodes. These adjusted outputs, in essence, represent components in the received signals corresponding to the first or third drive signals (in the values Xna) and to the second or fourth signals (in the values Yna). However, it should be appreciated that each value Xna, Yna includes components from each of the corresponding groups of driven electrodes. That is, any value Xna will contain components from each electrode of the first group of N / 2 drive electrodes. In order to extract the components related to a given drive electrode of the first group of N / 2 drive electrodes, each of the obtained values for Xna derived from each multiplier / accumulator / MAC in all discrete time periods are combined in a certain manner (e.g., through addition or subtraction) to isolate the component corresponding to a given drive electrode of the first group of N / 2 drive electrodes. Correspondingly, any value YNa will contain components from each electrode of the second group of N / 2 drive electrodes. In order to extract the components related to a given drive electrode of the second group of N / 2 drive electrodes, each of the obtained values for Yna derived from each multiplier / accumulator / MAC in all discrete time periods are combined in a certain manner (e.g., through addition or subtraction) to isolate the component corresponding to a given drive electrode of the second group of N / 2 drive electrodes. The precise way in which all of the Xna values in all discrete time periods are combined and the way in which all of the Yna values in all discrete time periods are combined will depend on the number N of the drive electrodes and the patterns I code by which the N drive electrodes are driven. Hence, overall, it should be appreciated that the capacitive couplings associated with any of the first group of N / 2 drive electrodes of the group of N drive electrodes can be determined through combinations of all adjusted outputs of the multipliers I accumulators / MACs corresponding to the first group of N / 2 drive electrodes for all discrete time periods (i.e., the XNa values) and the capacitive couplings associated with any of the second group of N / 2 drive electrodes of the group of N drive electrodes can be determined through combinations of all adjusted outputs of the multipliers I accumulators I MACs corresponding to the second group of N / 2 drive electrodes for all discrete time periods (i.e., the Yna values). As described above, the time required to scan the electrode array 101, 102 can be reduced (e.g., halved) when using a combination of code division multiplexing and the technique described in Figures 5 and 6 above as compared to using solely the technique described in Figures 5 and 6. This can have performance implications on the touch sensitive apparatus 1, namely helping to improve responsiveness and / or sensitivity of the touch sensitive apparatus 1. An important aspect of the present disclosure is the predetermined angle, ¢, which is used to perform the rotation of the vector formed by the outputs of the accumulators 9, 10 in order to provide the adjusted values. As noted above, the predetermined angle, ¢, is dependent on the particular pairs of drive (and receiver) electrodes selected to perform a particular measurement and is also known in advance. For example, a 4 x 4 electrode array 101, 102 operating in the mutual capacitance mode may be considered to have four drive electrodes (drive electrodes 1 to 4) and four receiver electrodes (receiver electrodes 1 to 4). The predetermined angle, ¢, is the mean phase shift that would be experienced by a given set of electrodes used to perform the measurements. Hence, for example, if drive electrode 1 and drive electrode 2 are driven respectively by the first and second drive signals, and receiver electrode 1 and receiver electrode 2 are coupled to the receiver circuitry, then this set of electrodes requires a predetermined angle, 0a, to be known in advance in order to perform the required rotation. Equally, if drive electrode 3 and drive electrode 4 are driven respectively by the first and second drive signals, and receiver electrode 1 and receiver electrode 2 are coupled to the receiver circuitry, then this set of electrodes requires a predetermined angle, 0b, to be known in advance in order to perform the required rotation, where 0a is likely to be different from 0b (although not necessarily). The predetermined angles, ¢, required for the rotation can be determined in advance through a suitable calibration technique. Figure 9 represents a suitable calibration technique according to a first example. In this example, the phase shift for a driven electrode (or the combination of a driven and receive electrode) is determined by applying a drive signal (i.e., either of the first and second digital drive signals) sequentially to electrodes of the electrode array 101, 102. Such a calibration technique is ideally performed in the absence of any external noise or of any touches 109. The method of Figure 9 starts at step S11, where the first digital signal is generated, converted to a first analogue drive signal, and applied to a first electrode of the electrode array. The first digital signal is the same as the first digital signal described previously. It should be appreciated that the second digital signal may alternatively be used. The second electrode (and any other electrodes) of the electrode array 101, 102 is held at a constant potential while the first drive signal is applied to the first electrode. At step S12, a received digital signal is generated from the electrode array 101, 102. Unlike the circuitry of Figure 5 above, because only a single drive electrode is being driven at this time, the received (analogue) signal from the electrode array 101, 102 is only based on the first drive signal and as such there is no combination of received signals (in other words, this step is more similar to what would be expected to be performed in the circuitry as shown in Figure 4). At step S13, the calculating circuitry 111, which receives the output from the first and second accumulators 9, 10 in a similar manner to that described above, now operates in a calibration mode. In this regard, the calculating circuitry 111 is configured to determine the phase shift between the first digital signal and the received digital signal. This can be done by, in effect, determining the inverse tan of the quadrature signal (i.e., the output from accumulator 10, Y) divided by the in-phase signal (i.e., the output from the accumulator 9, X). In other words, the phase shift a may be expressed as: a = tarr1(Y / X) (9) The calculating circuitry 111 may be configured in any suitable way to perform the above calculation. The value for the phase shift, a, is stored for further processing (e.g., in the calculating circuitry 111 or control circuitry 106). At step S14, the first digital signal is generated and applied now to a second electrode of the electrode array (although again it should be appreciated that the second digital signal may alternatively be used). In this instance, it should be appreciated that the second electrode is the only electrode of the electrode array 101, 102 being driven by a drive signal (that is, the first electrode is no longer being driven). As above, the first electrode (and any other electrodes) of the electrode array 101, 102 is held at a constant potential while the first drive signal is applied to the second electrode. At step S15, similarly to step S12, a received digital signal is generated from the electrode array 101, 102, which again is only based on the first drive signal. At step S16, the calculating circuitry 111, which receives the output from the first and second accumulators 9, 10 in a similar manner to that described above, now operates in a calibration mode. In this regard, the calculating circuitry 111 is configured to determine the phase shift between the first digital signal and the received digital signal; however, at step S16 this is the phase shift in respect of the second drive electrode, which for the purposes of ease we refer to herein as p. p may be calculated in substantially the same manner as a using equation (9), but of course using the respective values for X and Y corresponding to the outputs of the accumulators 9, 10 while the second electrode is being driven. The value for the phase shift, p, is similarly stored for further processing (e.g., in the calculating circuitry 111 or control circuitry 106). At step S17, the phase shifts a, p of steps S13 and S16 are stored, for example in a memory of, or a memory accessible to, the calculating circuitry 111. These phase shifts a, p may then be used to adjust the output of the first and second accumulators 9, 10 when measurements indicative of the capacitance of the various electrodes 101, 102 are performed (i.e., when the touch sensitive apparatus 1 is used in a normal manner, for example as described in respect of Figure 6). Note that, at step S9 of Figure 6, the predetermined angle, ¢, for the first drive electrode and the second drive electrode (i.e., of steps S3) may be derived from the outputs of steps S13 and / or S16; that is, on the basis of the values determined for a and / or p. For example, the predetermined angle, ¢, for the combination of the first and second electrodes may be calculated as the mean of the phase shifts a and p, e.g., such as (a + P) / 2. In some other implementations, when the first and second electrodes are spatially close to one another, the values of a and p are likely to be fairly similar, and thus step S9 of Figure 6 may use either of a or p as the predetermined angle (p for a given pair of drive electrodes. It should be appreciated that the method of Figure 9 is repeated for all the electrodes of the electrode array 101, 102. Accordingly, the calculating circuitry 111 is capable of identifying the relevant phase shifts a, p for the electrodes to be used as the predetermined angles, ¢, for different combinations of the drive (and receiver) electrodes, for calculating the adjusted values Xa, Ya in the manner described above. The method of Figure 9 is an example of a calibration technique used to calibrate the circuitry. However, as should be appreciated, this technique requires separate measurements of the all the drive electrodes I pairs of drive electrodes. As only a single electrode is driven at any one time, this can be a time consuming process. Figure 10 represents a suitable calibration technique according to a second example. In this example, the phase shift for a driven electrode (or the combination of a driven and receive electrode) is determined by applying two drive signals (i.e., the first and second digital drive signals) to the electrode array 101, 102 simultaneously. Such a calibration technique is ideally performed in the absence of any external noise or of any touches 109. The method of Figure 10 starts at step S21, where the first digital signal is generated, converted to a first analogue signal, and applied to a first electrode of the electrode array. Similarly, at step S22, the second digital signal is generated, converted to a second analogue signal, and applied to a second electrode of the electrode array. The first and second digital signals are the same as the digital signals described previously. The remaining electrodes of the electrode array 101, 102 may be held at a constant potential while the first drive signal is applied to the first electrode and the second drive signal is applied to the second electrode. At step S23, the outputs from the sensor element are combined to provide a combined received signal (in a similar manner to that described above in respect of Figure 5), which is subsequently passed to the amplifier 5, etc. to generate the combined digital received signal. However, unlike the method of Figure 6, at step S24, the outputs from the accumulators 9, 10 are passed to the calculating circuitry 111 that now operates in a calibration mode. Instead of adjusting the outputs of the accumulators 9, 10 by rotation of the vector formed thereby by a predetermined angle, ¢, the calculation circuitry 111 is configured to determine the phase of the vector (i.e., the combined received signal). This can be done by, in effect, determining the inverse tan of the quadrature signal (i.e., the output from the accumulator 10, Y’) divided by the in-phase signal (i.e., the output from the accumulator 9, X’). In other words, the phase of the vector, y, may be expressed as: y = tan-1(Y7X’) (10) This calibration technique is based on the premise that, if there were no phase shift between the first drive signal and the first received signal and between the second drive signal and the second receive signal, then the combined received signal (which is the summation of the first received signal and the second received signal, which is 90° out of phase with the first received signal) would show a phase shift of 45° with respect to the first / second drive signals. That is, y would be expected to be 45°. This relationship between the received first and second signals is, in effect, maintained even when there is a phase shift between the first drive signal and the first received signal and / or between the second drive signal and the second receive signal. By using this relationship, it is possible to derive the values a, p from the determined phase of the combined received signal from equation (10). For example, if one assumes that y is say, 55°, by subtracting 45° from the value of y, the phase shift, a, between the first drive signal and the first received signal can be identified. In the above example, a would be calculated as 10°. Conversely, by adding 45° to the value of y, the phase shift, p, between the second drive signal and the second received signal can be identified. In this example, p would be 100°. Hence, at step S25, the values a and p, i.e., the relative phase shifts corresponding to the first driven electrode and the second driven electrode, are determined using equation (10) above from the phase shift of the combined received signal. At step S26, the phase shifts a, p of steps S25 are stored, for example in a memory of, or a memory accessible to, the calculating circuitry 111, and are capable of being used in normal use of the touch sensitive apparatus 1 as described above in respect of step S17 for Figure 9. It should be appreciated that the method of Figure 10 is repeated for all the electrodes of the electrode array. Accordingly, the calculating circuitry 111 is capable of identifying the relevant phase shifts a, p for the electrodes to be used as the predetermined angles, ¢, for different combinations of the drive (and receiver) electrodes, for calculating the adjusted values Xa, Ya in the manner described above. The calibration technique of Figure 10 offers an advantage over the calibration technique of Figure 9 in that two electrodes are driven simultaneously, and thus the calibration can be performed in half the time that it would take in respect of the technique of Figure 9. The calibration technique of Figure 10 though is much more dependent on the two driven electrodes being spatially close to one another, as the phase of the vector, y, in effect is representative of the mean phase shift between the first drive signal and the first received signal and between the second drive signal and second received signal. However, provided this difference is sufficiently small (e.g., by ensuring the driven electrodes are spatially close), the calibration technique of Figure 10 can provide suitable values for the phases a and p within acceptable tolerance I error limits. In further implementations, the calibration technique of Figure 10 may be implemented using code divisional multiplexing (e.g., in a similar manner to the technique described above with respect of Figures 7a, b and 8). In such implementations, the method of Figure 10 is modified. In particular, steps S21 and S22 may be replaced with suitable steps that causes the relevant drive signals to be applied to the relevant group of N electrodes over N / 2 time periods, before proceeding to step S24. For example, using the above example of Figures 7a and 7b, for a first time period, T1, the first digital signal of step S21 and the second digital signal of step S22 are applied to the first and second electrodes as per the method of Figure 10, but additionally, the first digital signal of step S21 and the second digital signal of step S22 are applied to the third and fourth electrodes (much like in Figure 7a). For a second time period, T2, the first digital signal of step S21 and the second digital signal of step S22 are applied to the first and second electrodes as per the method of Figure 10, but in this case, the inverse of the first digital signal of step S21 (i.e., signal 2) and the inverse of the second digital signal of step S22 (i.e., signal 2+90°) are applied to the third and fourth electrodes (much like in Figure 7b). The method of Figure 10 may proceed in a suitable manner now using the outputs from the two different time periods T1, T2 in order to determine the relevant angles for the set of driven electrodes. Accordingly, using code division multiplexing with the calibration technique of Figure 10 can further reduce the time required to perform calibration of the electrode array. It should also be appreciated that the principle of code division multiplexing may also be applied to the calibration technique of Figure 9 in a similar manner. It has been described above that the sinusoidal waves on which the first digital signal and second digital signal are based are of a single frequency. In some examples, the single frequency is in the range of 25kHz to 250kHZ, although it should be appreciated that this is an example only and other frequencies may be used in other implementations. A particularly advantageous reason for using sinusoidal signals of a single frequency is that the majority of the energy applied to the electrode array is in the fundamental frequency. Having multiple frequencies means that the electrode array, which essentially acts as a low-pass filter, causes some of the energy in the higher frequencies to be lost to the system as a whole. In other words, more of the energy is retained when using a single frequency which results in a stronger signal obtained from the electrode array. While, as mentioned, there is the possibility of some additional frequency components being introduced as a result of the quantization errors or the like, these generally speaking would only contain a relatively small fraction of the energy of the overall drive signal. In some implementations, the measurement circuitry 105 may optionally include window imparting modules (not shown). These window imparting modules may be arranged to optionally impart a window function to the respective first and second digital signals. A window function is a function which is zero in all areas apart from inside a chosen interval. A suitable window function is the Hann window function, which is approximately a bell curve shape having a maximum value in the middle of the curve and tapering to zero either side of the mid-point. When a window function is applied to a signal, such as the first and second digital signals mentioned above, the window function causes the digital signal to be zero outside of the limits of the window function and provides a packet of the original signal within the limits of the window. The window function may be applied to the first and second digital signals before they are passed to the first and second multipliers 7, 8, respectively. Applying the window function at this point may help to shape or narrow the reception spectrum. This may help prevent any interference by other foreign signals that are spectrally-near to the frequency of the sinusoidal wave that the first digital signal represents in the received analogue signal. When the window imparting modules are employed, the first and second multipliers 7, 8 and first and second accumulators 9, 10 may be controlled (by the control circuitry 106) to operate in accordance with the window imparting modules. Alternatively, or additionally, the window function may be applied to the first and second digital signals before they are passed to the DAC 4, 44 respectively. Applying the window function at this time shapes the spectrum of the voltages and currents driven through the sensor element 100. While this may help in some aspects with the reduction of noise, one main reason for performing windowing at this time is to reduce the amount of electromagnetic emissions (the drive signal is effectively zeroed outside of the limits of the window). Thus there has been described circuitry for determining an indication of the capacitive coupling associated with two drive electrodes of an electrode array of a capacitive touch sensitive apparatus, the circuitry including a first signal generator configured to generate a first drive signal representing a sinusoidal wave having a first frequency; a second signal generator configured to generate a second drive signal representing a sinusoidal wave having the first frequency, wherein the second drive signal is orthogonal in phase to the first drive signal; drive circuitry configured to apply the first drive signal to a first drive electrode of the electrode array and to apply the second drive signal to a second drive electrode of the electrode array at the same time; receiver circuitry configured to receive a first received signal from the electrode array wherein the first received signal is based on the first drive signal and to receive a second received signal from the electrode array wherein the second received signal is based on the second drive signal, wherein the receiver circuitry is configured to sum the first received signal and the second received signal to form a combined received signal; a first multiplier configured to multiply the first drive signal and the combined received signal together; a second multiplier configured to multiply the second drive signal and the combined received signal together; and calculating circuitry configured to provide a first output indicative of the capacitive coupling associated with the first drive electrode based on an adjustment of the output of the first multiplier and to provide a second output indicative of the capacitive coupling associated with the second drive electrode based on an adjustment of the output of the second multiplier. The adjustment of the output of the first multiplier and the adjustment of the output of the second multiplier is performed in accordance with a predetermined relationship that is a function of both the output of the first multiplier and the output of the second multiplier. Also described is a method of operation, and methods of calibration. Further particular and preferred aspects of the present invention are set out in the accompanying independent and dependent claims. It will be appreciated that features of the dependent claims may be combined with features of the independent claims in combinations other than those explicitly set out in the claims.

Claims

1. Circuitry for determining an indication of the capacitive coupling associated with two drive electrodes of an electrode array of a capacitive touch sensitive apparatus, the circuitry comprising:a first signal generator configured to generate a first drive signal representing a sinusoidal wave having a first frequency;a second signal generator configured to generate a second drive signal representing a sinusoidal wave having the first frequency, wherein the second drive signal is orthogonal in phase to the first drive signal;drive circuitry configured to apply the first drive signal to a first drive electrode of the electrode array and to apply the second drive signal to a second drive electrode of the electrode array at the same time;receiver circuitry configured to receive a first received signal from the electrode array wherein the first received signal is based on the first drive signal and to receive a second received signal from the electrode array wherein the second received signal is based on the second drive signal, wherein the receiver circuitry is configured to sum the first received signal and the second received signal to form a combined received signal;a first multiplier configured to multiply the first drive signal and the combined received signal together;a second multiplier configured to multiply the second drive signal and the combined received signal together; andcalculating circuitry configured to provide a first output indicative of the capacitive coupling associated with the first drive electrode based on an adjustment of the output of the first multiplier and to provide a second output indicative of the capacitive coupling associated with the second drive electrode based on an adjustment of the output of the second multiplier,wherein the adjustment of the output of the first multiplier and the adjustment of the output of the second multiplier is performed in accordance with a predetermined relationship that is a function of both the output of the first multiplier and the output of the second multiplier.

2. The circuitry of claim 1, wherein the calculating circuitry is configured to use a CORDIC algorithm to provide the first output and the second output.

3. The circuitry of claim 1 or 2, wherein the predetermined relationship is representative of a rotation of a vector defined in two-dimensional space by the output of the first multiplier and the output of the second multiplier, and wherein the rotation is by a predetermined angle calculated in advance.

4. The circuity of claim 3, wherein the predetermined angle is set based on the signal path length associated with the first received signal and the second received signal.

5. The circuitry of claim 4, wherein the calculating circuitry is configured to store or have access to a plurality of values of the predetermined angle calculated in advance, and wherein the calculating circuitry is configured to select a value for the predetermined angle used to calculate the rotation based on the signal path length associated with the first received signal and the second received signal.

6. The circuitry of any one of claims 3 to 5, wherein the predetermined angle is set as the mean of the phase shift between the first drive signal and the first received signal and between the second drive signal and the second received signal.

7. The circuitry of any one of claims 3 to 6, wherein the calculating circuitry is configured to adjust the output of the first multiplier by multiplying the output of the first multiplier by the cosine of the predetermined angle and subtracting the result of multiplying the output of the second multiplier by the sine of the predetermined angle, and wherein the calculating circuitry is configured to adjust the output of the second multiplier by multiplying the output of the second multiplier by the cosine of the predetermined angle and adding the result of multiplying the output of the first multiplier by the sine of the predetermined angle.

8. The circuitry of any of the preceding claims, wherein the electrode array comprises a plurality of electrodes arranged at spatially distinct positions, and wherein the first drive electrode and the second drive electrode are directly adjacent one another spatially.

9. The circuitry of any of the preceding claims, wherein the electrode array further comprises a first receiver electrode and a second receiver electrode, wherein the first drive electrode is distinct from the first receiver electrode and the second drive electrode is distinct from the second receiver electrode, and wherein the first output indicative of the capacitive coupling associated with the first drive electrode is indicative of the mutual capacitance between the first drive electrode and the first receiver electrode, and wherein the secondoutput indicative of the capacitive coupling associated with the second drive electrode is indicative of the mutual capacitance between the second drive electrode and the second receiver electrode.

10. The circuitry of claim 9, when dependent on claim 8, wherein the first receiver electrode and the second receiver electrode are the same electrode or are directly adjacent one another spatially.

11. The circuitry of any of claims 1 to 8, wherein first output indicative of the capacitive coupling associated with the first drive electrode is indicative of the self-capacitance of the first drive electrode, and wherein the second output indicative of the capacitive coupling associated with the second drive electrode is indicative of the self-capacitance of the second drive electrode.

12. The circuitry of any of the preceding claims, the circuitry further comprising: a first accumulator; and a second accumulator,wherein the first accumulator is configured to sum a plurality of outputs from the first multiplier over a predetermined period of time,wherein the second accumulator is configured to sum a plurality of outputs from the second multiplier over the predetermined period of time, wherein the first and second accumulators are each configured to output the corresponding summations to the calculating circuitry after the predetermined period of time has elapsed, andwherein the calculating circuitry is configured to provide a first output indicative of the capacitive coupling associated with the first drive electrode based on an adjustment of the output of the first accumulator and to provide a second output indicative of the capacitive coupling associated with the second drive electrode based on an adjustment of the output of the second accumulator.

13. The circuitry of any of the preceding claims, wherein the drive circuitry is configured to sequentially drive pairs of electrodes of the electrode array as the first drive electrode and the second drive electrode, wherein the receiver circuitry is configured to sequentially receive pairs of received signals from the electrode array as the first received signal and second received signal, and wherein the calculating circuitry is configured to sequentially provide pairs of outputs as the first output and second output based on the sequentially received pairs of received signals.

14. The circuity of any of the preceding claims, wherein:the circuitry comprises a first inverse signal generator configured to generate a third drive signal that is the inverse of the first drive signal and a second inverse signal generator configured to generate a fourth drive signal that is the inverse of the second drive signal;the drive circuitry is configured to drive a group of N drive electrodes simultaneously, where N is an integer, wherein a first group of N / 2 of the drive electrodes, including the first drive electrode, are driven with either of the first drive signal or the third drive signal, and wherein a second group of N / 2 of the drive electrodes, including the second drive electrode, are driven with either of the second drive signal and the fourth drive signal;the drive circuitry is configured to drive the group of N electrodes for N / 2 discrete time periods, wherein in at least two of the N / 2 discrete time periods, at least one of the first group of N / 2 drive electrodes is driven with a different one of the first or third drive signals; andthe receiver circuitry is configured to form the combined received signal based on the signals received from the electrode array when the group of N electrodes are simultaneously driven with a corresponding drive signal,wherein the first multiplier is configured to receive the combined received signal and multiply the first drive signal with the combined received signal and the second multiplier is configured to receive the combined received signal and multiply the second drive signal with the combined received signal, andwherein the calculating circuitry is configured to provide the first output indicative of the capacitive coupling associated with at least the first drive electrode based on a combination of an adjustment of the outputs of the first multiplier for each of the N / 2 discrete time periods, and to provide the second output indicative of the capacitive coupling associated with at least the second drive electrode based on a combination of an adjustment of the outputs of the second multiplier for each of the N / 2 discrete time periods,wherein the adjustment of the output of the first multiplier and the adjustment of the output of the second multiplier is performed in accordance with the predetermined relationship that is a function of both the output of a first multiplier and a second multiplier corresponding to a pair of the drive electrodes, wherein a pair of drive electrodes includes one drive electrode from the first group of N / 2 drive electrodes and from the second group of N / 2 drive electrodes.

15. The circuitry of claim 14, wherein the group of N drive electrodes are arranged at spatially distinct positions, and wherein the group of N electrodes are arranged such thateach electrode of the first group of N / 2 drive electrodes is directly adjacent at least one electrode of the second group of N / 2 drive electrodes.

16. A touch sensitive apparatus comprising:the circuitry according to any one of claims 1 to 15;an electrode array coupled to the circuitry; andcontrol circuitry configured to receive the outputs from the calculating circuitry and configured to sense at least the presence or an absence of a touch in the proximity of the electrode array.

17. A method for determining an indication of the capacitive coupling associated with two drive electrodes of an electrode array of a capacitive touch sensitive apparatus, the method comprising:generating a first drive signal representing a sinusoidal wave having a first frequency;generating a second drive signal representing a sinusoidal wave having the first frequency, wherein the second drive signal is orthogonal in phase to the first drive signal;applying the first drive signal to a first drive electrode of the electrode array and applying the second drive signal to a second drive electrode of the electrode array at the same time;receiving a first received signal from the electrode array wherein the first received signal is based on the first drive signal and receiving a second received signal from the electrode array wherein the second received signal is based on the second drive signal;forming a combined received signal by summing the first received signal and the second received signal;multiplying, using a first multiplier, the first drive signal and the combined received signal together, and multiplying, using a second multiplier, the second drive signal and the combined received signal together; andproviding a first output indicative of the capacitive coupling associated with the first drive electrode based on an adjustment of the output of the first multiplier and providing a second output indicative of the capacitive coupling associated with the second drive electrode based on an adjustment of the output of the second multiplier,wherein the adjustment of the output of the first multiplier and the adjustment of the output of the second multiplier is performed in accordance with a predetermined relationship that is a function of both the output of the first multiplier and the output of the second multiplier.

18. A method for calibrating circuitry for determining an indication of the capacitive coupling associated with two drive electrodes of an electrode array of a capacitive touch sensitive apparatus, the method comprising:applying a first drive signal representing a sinusoidal wave having a first frequency to a first drive electrode of the electrode array;simultaneously applying a second drive signal representing a sinusoidal wave having the first frequency and being orthogonal in phase to the first drive signal to a second drive electrode of the electrode array;identifying the phase of a combined received signal, the combined received signal being a combination of a first received signal from the electrode array and a second received signal from the electrode array, wherein the first received signal is based on the first drive signal and the second received signal is based on the second drive signal;obtaining a value indicative of the phase shift between the first drive signal and the first received signal by subtracting a fixed amount from the determined phase of the combined received signal;obtaining a value indicative of the phase shift between the second drive signal and the second received signal by adding the fixed amount from the determined phase of the combined received signal; andrecording the value indicative of the phase shift between the first drive signal and the first received signal and the value indicative of the phase shift between the second drive signal and the second received signal, the values for use in determining an indication of the capacitive coupling associated with the first drive electrode and the second drive electrode.

19. The method of claim 18, wherein the fixed amount is a value corresponding to an angle of 45°.

20. A method for calibrating circuitry for determining an indication of the capacitive coupling associated with two drive electrodes of an electrode array of a capacitive touch sensitive apparatus, the method comprising:applying a first drive signal representing a sinusoidal wave having a first frequency to a first drive electrode of the electrode array;identifying the difference in phase between the first drive signal and a first received signal from the electrode array, the first received signal based on the first drive signal;recording a value indicative of the phase difference between the first drive signal and the first received signal, the value for use in determining an indication of the capacitive coupling associated with the first drive electrode;applying, at a different time, the first drive signal to a second drive electrode of the electrode array;identifying the difference in phase between the second drive signal and a second received signal from the electrode array, the second received signal based on the first drive 5 signal; andrecording a value indicative of the phase difference between the second drive signal and the second received signal, the value for use in determining an indication of the capacitive coupling associated with the second drive electrode.

Images