Inverter comprising multi-level and two-level inverter

Abstract

An inverter comprising at least one phase, each phase comprising at least one half bridge circuit, each half bridge circuit comprising a high-side leg and a low-side leg, each of the high-side leg and

Description

TECHNICAL FIELD The present disclosure relates to an inverter. Particularly, but not exclusively, the disclosure relates to an inverter comprising half bridge comprising a parallel switch based on a high-electron-mobility transistor (HEMT) (e.g. a Ill-nitride HEMT) and optionally a high voltage transistor device such as an insulated-gate bipolar transistor (IGBT), a metal-oxide-semiconductor field-effect transistor (MOSFET), or a superjunction. The high voltage transistor device may be a silicon or silicon carbide device. BACKGROUND IGBTs Insulated Gate Bipolar transistors (IGBTs) are silicon devices that employ bipolar conduction while maintaining MOS gate control. The bipolar conduction allows for conductivity modulation of the drift region which in turn results in low on-state resistance. The conductivity modulation depends on the current density level. Above a certain current density level (e.g. 0.1 A / cm2), the excess charged (plasma) brought by the bipolar injection of holes and electrons could be larger than the doping charge level of the drift region and therefore resulting an increase in the conductivity of the drift region. The higher the current density, the larger the plasma created in the drift region and therefore the lower the on-state resistance of the drift region. IGBTs are used as switches in high voltage and high power applications. Their typical blocking voltage range is very wide, from 600 V to 6.5 kV, while typical current range is also very wide and varies from a few Amps to thousands of Amps. The on-state voltage drop across the drift region (the region that blocks the voltage during off-state) is directly proportional to the on-state resistance and therefore a smaller on-state resistance results in a lower voltage drop and a more efficient device in the on-state. The simplest equivalent circuit description of an IGBT is that of a metal-oxide-semiconductor field-effect transistor (MOSFET) device driving the base terminal of a bipolar transistor. Most IGBTs are n-channel devices. For these the MOSFET is an n-channel and the transistor is a pnp transistor. The base region of the pnp transistor is the n-type doped drift region of the IGBT. The total on-state voltage drop of the IGBT is approximately given by the sum of the voltage drop across the base-emitter junction of the pnp transistor, the voltage drop across the drift region and the voltage drop across the n-channel of the MOSFET component. The IGBT conducts no current until the base-emitter junction of the pnp transistor is forward-biased. For this, at room temperature, a minimum voltage drop of 0.7 V (at room temperature) is needed between its main terminals. The collector terminal of the IGBT is defined as the high voltage terminal in the forward conduction, while the emitter terminal is defined as the low voltage terminal in the forward conduction. The gate terminal modulates the channel resistance and therefore modulates the electron injection into the base of the pnp transistor. Note that the collector terminal of the IGBT is in fact the emitter terminal of the pnp transistor and the emitter terminal of the IGBT is in fact both the collector terminal of the pnp transistor and the source terminal of the MOSFET component. The collector junction of the IGBT is the same as emitter-base junction of the PNP transistor. The IGBT has superior on-state characteristics but in general is quite slow due to the need to build and remove the plasma (excess charge of minority carriers, electrons and holes in equilibrium) during the turn-on and turn-off transients. In particular the removal of the plasma is a slow process dictated by (i) the sweeping action of the depletion region, when the voltage builds up in the depletion region and (ii) by the recombination of carriers. The IGBT does not conduct until 0.7 V at room temperature. This voltage level goes down as the temperature is increased. The rate at which it goes down is ~ 1.5 to 2 mV / degC. Nevertheless this is considered a weakness of the IGBT. IGBTs are used extensively in motor control applications and they tend to operate at relatively lower frequencies (e.g. 1 to 30 kHz). One of their important applications is that of inverters in electric cars. Here 6 IGBTs (or 6 sets of IGBTs connected in parallel) are used as three half bridges per each of the three phases driving a motor. IGBTs have an interesting temperature behavior. At relatively low on-state voltage drops (low currents) the IGBTs have a negative temperature coefficient - meaning that their on-state voltage drop decreases with temperature while at relatively higher on-state voltage drops (higher currents) the IGBTs have a positive temperature coefficient - meaning that their on-state voltage drop increases with temperature. At low currents the bipolar effect is prominent while at higher currents and eventually during the channel saturation, the MOSFET effect becomes prominent. For a nominal current the IGBTs are generally designed to have a mild positive temperature coefficient, meaning that their voltage drop increases slightly with temperature. This is a good compromise between avoiding high on-state losses at high temperatures while allowing for easy-paralleling and avoiding runaway thermal effects. The IGBTs have good short-circuit capability and limited avalanche capability. They also have good reliability and most IGBTs are rated for a maximum junction temperature of 175 °C. Silicon Carbide Silicon Carbide MOSFETs are unipolar devices (during forward conduction) and are considered good alternatives to the IGBTs. They are faster and they do not have the IGBTs 0.7 V weakness. Unlike silicon MOSFET and silicon Superjunctions, Silicon Carbide MOSFETs and Silicon Carbide superjunctions do not suffer from a very high positive temperature coefficient and in this way they match the high performance of the IGBTs at high temperatures. While the drift mobility decreases with temperature, the channel mobility remains constant or even slightly increases with temperature. Silicon Carbide MOSFETs and Silicon Carbide Superjunctions are among the state-of-the-art devices today. When compared to Power MOSFET superjunctions, they have a lower specific on-state drift resistance due to the presence of n-type and p-type pillars in the drift region to further reduce the resistivity of the drift region. Nevertheless, the process of making n / p pillars within the drift region is complex leading to further increase in the cost. In general, silicon carbide wafers and device processing are still significantly more expensive than those of silicon. Moreover, Silicon Carbide MOSFETs have lower short-circuit capability than the IGBTs and are vulnerable to threshold voltage instabilities and reliability effects during the bipolar reverse conduction. In applications such as motor control (e.g. inverters in electric cars), the currently preferred devices are vertical switches. Bipolar devices in silicon such as IGBTs or silicon Carbide MOSFETs are the main switches in this market. IGBTs are widely available, have relatively low cost, and they are currently manufactured in 12 inch wafers. As mentioned, their on-state performance is very good especially at high currents and / or high temperature. However, they only conduct forward currents above 0.7V (at room temperature) and therefore tend to be less efficient in low to medium load conditions. Silicon Carbide MOSFETs on the other hand are expensive and their availability is scarcer. To scale-up in current (up to values of 1000 A), chips of IGBTs or SiC are placed in parallel within a module. In this way, very large area chips are avoided. This has the advantage of higher yield and creating multiple heat sources which results in a lower temperature increase. Parallel combinations of Silicon Carbide MOSFETs and IGBTs have also been proposed in the prior art as shown in Figure 1, which shows an IGBT in parallel with Silicon Carbide MOSFET, reproduced from M. Rahimo, IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 30, NO. 9, SEPTEMBER 2015, the contents of which are hereby incorporated by reference. The silicon carbide MOSFET can conduct the forward current up to 0.7 V while both the IGBT and SiC can conduct above 0.7 V. However, the IGBTs and the SiC MOSFETs and superjunctions are vertical devices and therefore cannot integrate any smartness. No monolithic integration of sensing and protection features are present in state-of-the-art IGBTs and SiC MOSFETs. GaN HEMT Gallium Nitride (GaN) has been more recently considered as a very promising material for use in the field of power devices. The application areas range from portable consumer electronics, solar power inverters, electric vehicles, and power supplies. The wide band gap of the material (Eg=3.39eV) results in high critical electric field (Ec=3.3MV / cm) which can lead to the design of devices with a shorter drift region, and therefore lower on-state resistance if compared to a silicon-based device with the same breakdown voltage. The use of an Aluminium Gallium Nitride (AIGaN) / GaN heterostructure also allows the formation of a two-dimensional electron gas (2DEG) at the hetero-interface where carriers can reach very high mobility [p=2000cm2 / (Vs)] values. In addition, the piezopolarization charge present at the AIGaN / GaN heterostructure, results in a high electron density in the 2DEG layer (e.g. 1x1013cm-2). These properties allow the development of High Electron Mobility Transistors (HEMTs) and Schottky barrier diodes with very competitive performance parameters. One common parameter used to compare power semiconductor transistors is Specific ON-state resistance or Specific Rds(ON). The specific Rds(ON) is the product of the resistance of a device times the area of the device on wafer. An extensive amount of research has focused on the development of power devices using AIGaN / GaN heterostructures. Layers which constitute the AIGaN / GaN heterojunction transistor are often epitaxially grown on a substrate from a different material for example Silicon, Silicon Carbide or Sapphire. Epitaxial growth of GaN on different substrates has advantages and disadvantages both in terms of the complexity and cost of growing high quality layers and in terms of device performance. A non-exhaustive list of things to consider when choosing a suitable substrate is: substrate lattice constant mismatch with GaN, substrate thermal expansion coefficient mismatch with GaN, substrate cost, substrate thermal conductivity etc. Today, substrates such as silicon (using a transition layer to adapt the mismatch between GaN layers and silicon), semi-insulating silicon carbide, quartz and sapphire are present in the market or in advanced research. GaN transistors based on a 2DEG are mainly available on a lateral configuration. While this is advantageous from a point of view of integrating additional smart circuits around the main power device, it does pose some limitations in terms of scalability at high currents (in excess of 100A). Moreover, lateral GaN devices tend to be limited today to below 900 V rating, though this limit is expected to grow to 1.2 kV and beyond in the future. There are different types of the gate structure available for GaN HEMTs. The p-Gan Gate features a layer of Magnesium doped GaN above the AIGaN layer. It delivers a positive threshold voltage of 1.3 to 1.7 V and results in an enhancement mode (normally-off) transistor. Currently this is the preferred solution in the market. The p-GaN gate technology has also some major disadvantages. If the gate voltage applied to the gate is in excess of 7 V the leakage current becomes very high leading to failure. Moreover, the relatively low threshold voltage does not give sufficient margin for avoiding retriggering on the transistor during the turn-off if the minimum voltage level is zero (ground). For this reason, often such transistors need negative voltage rails which make the driving more cumbersome and could result in some reliability issues such as the dynamic increase in the Rds(ON). Other alternative technologies are based on an insulated gate or Schottky gate. The insulated gate is problematic for GaN due to traps in the insulated material and at the interface between the GaN or AIGaN and the insulated material. While this could deliver a higher threshold voltage, the reliability and reproducibility are currently poor and therefore there are no devices of this type in the market. The Schottky gate results in normally-on devices (depletion mode devices), which could only be used in a Cascode configuration or direct drive mode to deliver a normally-off solution. The Cascode relies on placing a silicon MOSFET in series with a depletion mode HEMT (based on Schottky gate technology) with the gate of the HEMT connected to the source of the silicon MOSFET and the drain of the Silicon MOSFET connected to the source of the depletion mode HEMT. The main advantage of this solution is the gate of the Cascode device is the insulated gate of the MOSFET which has a high degree of reliability, ease of use and can be easily tailored for a higher threshold voltage and extended voltage range. No negative voltage rail is needed. However, both the Cascode and direct drive configurations are based on two chip solution. Moreover, adjusting the slew rate in the Cascode configuration is not straightforward, as the gate of the depletion mode HEMT has a fixed potential (connected to the source of the MOSFET and not to the driver). While these solutions (i.e. direct drive and Cascode) are present in the market, they have a strong competition from enhancement gate GaN solutions. It would be of interest to parallel GaN HEMTs with vertical devices such as IGBTs or SiC devices such as Power MOSFETs or Superjunctions. A simple, but problematic combination is shown in Figure 2. GaN HEMTs are especially efficient at low on-state voltage drops, low on-state currents and lower temperatures, while devices such as IGBTs are inefficient at low currents (due to the forward voltage drop on the base-emitter junction of the pnp transistor) but have superior on-state characteristics at high currents and higher temperatures. However, enhancement GaN devices cannot be easily paralleled with vertical devices such as IGBTs and / or SiC MOSFETs and / or SiC superjunctions. The gate voltage range for vertical devices is not aligned to that of the p-GaN HEMTs. P-GaN HEMTs tend to have a threshold voltage of around 1.5 V while IGBTs and SiC power MOSFETs and superjunctions have threshold voltages in excess of 3V (e.g. 4V). The maximum drive voltage for the p-GaN HEMT (to turn-on of the device and maintain it in the on-state) is limited to 7V, before the leakage current through the gate becomes too large. In contrast, IGBTs, SiC MOSFETs and Superjunctions are driven with a maximum voltage in excess of 10 V, and often in excess of 15 V (e.g. 20V). If the HEMT could be done with an insulated gate instead of a p-GaN gate, the threshold could be adjusted and the voltage range could be extended. However, insulated gate HEMTs are not currently available and the technology is not ready for the market as explained above. Another approach in paralleling a HEMT with a vertical switch (in this case an IGBT) has been described by L. Molnar, 2018 IEEE 24th International Symposium for Design and Technology in Electronic Packaging (SIITME), 2018, the contents of which is hereby incorporated by reference (Figure 3). The circuit implementation provided in Figure 3 is however very complex with each of the GaN HEMT and the IGBT having a separate gate driver and a common digital control circuit. Furthermore, a monitor feedback circuit is also added for better sharing of current between the two components. The solution is too complex and not cost effective in high power applications. Three Level Inverter Technology The multi-level (e.g. three level) inverter, often referred to as Neutral Point Clamped (NPC) technology, has several advantages over the traditional two level inverter. The more levels present in the technology, the smaller the output voltage steps, resulting in cleaner waveforms, lower output current ripple, higher efficiency and smaller harmonic distortions. Figures 4 and 5 show the circuit configuration of a two level inverter using IGBTs and the three-level NPC inverter respectively. In the two-level inverter (Figure 4) each phase contains a half-bridge with an IGBT in the low-side leg and an IGBT in the high side leg. The output of the two-level inverter can be connected to either the DC+ bus voltage level when the IGBT on the high side is ON and the IGBT on the low-side is OFF or to the DC-bus voltage level, when the opposite, the IGBT on the high side is OFF and the IGBT on the low-side is ON. In the three-level NPC inverter (Figure 5), each phase contains a half bridge with each leg of the half bridge having two IGBTs connected in series. In this case, the applied voltage on each of the IGBTs is half of that of the traditional two-level inverter. This allows the use of IGBTs with shorter drift regions to be used. The DC bus voltage is split in two (or more for more than three levels) with a intermediate level (DC MID) which sits at a voltage given by the potential divider of the two capacitors in series. This DC MID voltage level is typically half of that between the DC+ and DC- voltage levels. Depending on the status (ON or OFF) of the four IGBTs and given the action of the additional clamping diodes placed as shown in Figure 2, the output voltage can be in steady-state at any of the three level DC voltages (DC+, DC MID, and DC -) and switching between these states when the IGBTs are switched. The clamping diodes are connected between the series devices on each of the high-side and low-side legs to the DC MID (between the series capacitors). The IGBTs connected to the output voltage could be in the on-state for a longer period of the cycle, resulting in greater conduction loss. On the opposite, the transistors connected to the DC- and DC+ busses could incur less conduction losses but higher switching losses. The IGBTs could handle well the high power and high temperatures, because of their mild positive temperature coefficient. However, IGBTs are particularly inefficient at light loads, when the current is low due to the voltage drop on the collector junction. This voltage drop is around 0.7V at room temperature. IGBTs are also bipolar devices and as a result are slower and have higher switching losses than unipolar devices. In both two-level and multi-level topologies the IGBTs could be replaced by unipolar devices such as power MOSFETs, superjunctions or HEMTs and for increased efficiency, power density and higher switching frequency of operation such devices could be made of wide bandgap (WBG) materials such as Silicon Carbide (SiC), Gallium Nitride (GaN) or heterojunctions based on Gallium Nitride and Aluminium GaN Nitride (GaN / AIGaN). Such devices could have a vertical geometry (such as SiC power MOSFETs) or lateral geometry such as GaN / AIGaN HEMTs. Nevertheless, such WBG devices are more expensive and some of them have lower ability to handle very high power levels (high currents) or surge current reliably and efficiently. A review of modern traction inverter systems is provided in: Sambhavi and Ramachandran, “A technical review of modern traction inverter systems used in electric vehicle application”, Energy Reports 10 (2023), 3882-3907, the contents of which are hereby incorporated by reference. SUMMARY Aspects and preferred features are set out in the accompanying claims. The present disclosure provides a semiconductor switch combining a high-electron-mobility transistor (HEMT), and another transistor device that may be, for example, an insulated-gate bipolar transistor (IGBT), a metal-oxide-semiconductor field-effect transistor (MOSFET), or a superjunction. The HEMT may be a lateral device, made in Ill-nitride material while the transistor device may be a vertical device, preferably made in silicon or silicon-carbide. Alternatively, the vertical device may be made in Vertical GaN, GaN on GaN or ultra wide bandgap materials such as Gallium Oxide (GaO) or Aluminium Nitride (AIN). While the HEMT and the other transistor device can be based on different material systems, the semiconductor switch according to the present disclosure can enable both devices to be driven using a single control terminal, rather than requiring a dedicated driver for each device. Moreover, given the lateral configuration, other devices or circuits can be monolithically integrated with the HEMT, for sensing and protection, for voltage regulation and for enhanced reliability. Described herein is a semiconductor switch comprising: a first branch comprising a first lateral semiconductor transistor device and a second lateral semiconductor transistor device, the first lateral semiconductor transistor device and the second lateral semiconductor transistor device being connected in series; and a second branch comprising a vertical semiconductor transistor device; wherein the first branch and the second branch are connected in parallel; and wherein a maximum voltage rating of the vertical semiconductor transistor device is greater than a maximum voltage rating of the first and second lateral semiconductor transistor devices. In some examples, the voltage rating of the vertical semiconductor transistor device is greater than the maximum voltage rating of the first and second lateral semiconductor transistor devices by a factor of at least 1.5, or at least 2. The semiconductor switch may comprise a first control terminal configured to receive the first control signal. The semiconductor switch may comprise a second control terminal configured to receive the second control signal. The semiconductor switch may comprise a third control terminal configured to receive the third control signal. As described herein, the first control terminal may correspond to, or be connected to, a gate terminal of the first lateral semiconductor transistor device. The second control terminal may correspond to, or be connected to, a gate terminal of the second lateral semiconductor transistor device. The third control terminal may correspond to, or be connected to, a gate terminal of the vertical semiconductor transistor device. Additionally, the semiconductor switch may also have a mid terminal connected to the mid-point between the first lateral semiconductor transistor device and the second lateral semiconductor transistor device. The semiconductor switch may comprise an interface circuit. The interface circuit may be connected between one or both of the first and second control terminals and their respective transistor devices. That is, the interface circuit may be connected between at least one of: the first control terminal and the first lateral semiconductor transistor device; and the second control terminal and the second lateral semiconductor transistor device. In an example, the interface circuit may comprise at least one of: a first auxiliary HEMT operatively connected between the first control terminal and the first lateral semiconductor transistor device, and a second auxiliary HEMT operatively connected between the second control terminal and the second lateral semiconductor transistor device. The first and / or second lateral semiconductor transistor device(s) may comprise one or more Ill-nitride transistors. The first and / or second lateral semiconductor transistor device(s) may comprise one or more HEMTs. The first and / or second lateral semiconductor transistor device(s) may comprise one or more Ill-nitride HEMTs. The vertical semiconductor transistor device may comprise one or more silicon or silicon carbide transistors, one or more IGBTs, one or more MOSFETs, and / or one or more superjunctions. The first lateral semiconductor transistor device may be configured to be driven by a first control signal. The second lateral semiconductor transistor device may be configured to be driven by a second control signal. The vertical semiconductor transistor device may be configured to be driven by a third control signal. An apparatus according to the present disclosure may comprise a semiconductor switch as described herein, and a driver. One or more of the transistor devices may be operatively connected to the driver, the driver being configured to provide one or more of the first, second, and third control signals. The first, second, and third control signals may be a same signal, or may be different signals. Alternatively, the semiconductor switch may comprise only one control terminal to receive a control signal from a driver / controller. The semiconductor switch may further comprise an interface circuit. The interface circuit may be connected between the control terminal and the three transistor devices - first and second lateral semiconductor transistor devices and the vertical semiconductor transistor device. The interface circuit may be configured to internally generate the first control signal and provide to the gate of the first lateral semiconductor transistor device, generate the second control signal and provide to the gate of the second lateral semiconductor transistor device and generate the third control signal and provide to the gate of the vertical semiconductor transistor device. The interface circuit may comprise additional circuits and components such as auxiliary HEMTs, level shifter, slew rate control circuit, logic circuits, voltage regulator to generate the first, second and third control signals. Also described herein is a semiconductor switch comprising: a first branch comprising a first wide bandgap semiconductor transistor device, and a second wide bandgap semiconductor transistor device, the first wide bandgap semiconductor transistor device and the second wide bandgap semiconductor transistor device being connected in series; and a second branch comprising a silicon-based semiconductor transistor device; wherein the first branch and the second branch are connected in parallel; and wherein a maximum voltage rating of the silicon semiconductor transistor device is greater than a maximum voltage rating of the first and second wide bandgap semiconductor transistor devices. The voltage rating of the silicon-based semiconductor transistor device may be greater than the maximum voltage rating of the first and second wide bandgap semiconductor devices by a factor of at least 1.5, or at least 2. The semiconductor switch may comprise a first control terminal configured to receive the first control signal. The semiconductor switch may comprise a second control terminal configured to receive the second control signal. The semiconductor switch may comprise a third control terminal configured to receive the third control signal. As described herein, the first control terminal may correspond to, or be connected to, a gate terminal of the first wide bandgap semiconductor transistor device. The second control terminal may correspond to, or be connected to, a gate terminal of the second wide bandgap semiconductor transistor device. The third control terminal may correspond to, or be connected to, a gate terminal of the silicon-based semiconductor transistor device. Additionally, the semiconductor switch may also have a mid terminal connected to the mid-point between the first lateral semiconductor transistor device and the second lateral semiconductor transistor device. The semiconductor switch may comprise an interface circuit. The interface circuit may be connected between one or both of the first and second control terminals and their respective transistor devices. That is, the interface circuit may be connected between at least one of: the first control terminal and the first wide bandgap semiconductor transistor device; and the second control terminal and the second wide bandgap semiconductor transistor device. At least one of the first and second wide bandgap semiconductor transistor devices may comprise one or more Ill-nitride transistors, and / or one or more silicon carbide transistors. The silicon-based semiconductor transistor device may comprise one or more IGBTs, one or more MOSFETs, and / or one or more superjunctions. The first wide bandgap semiconductor transistor device may be configured to be driven by a first control signal. The second wide bandgap semiconductor transistor device may be configured to be driven by a second control signal. The silicon-based semiconductor transistor device may be configured to be driven by a third control signal. An apparatus according to the present disclosure may comprise a semiconductor switch as described herein, and a driver. One or more of the transistor devices may be operatively connected to the driver, the driver being configured to provide one or more of the first, second, and third control signals. The first, second, and third control signals may be a same signal, or may be different signals. Alternatively, the semiconductor switch may comprise only one control terminal to receive a control signal from a driver / controller. The semiconductor switch may further comprise an interface circuit. The interface circuit may be connected between the control terminal and the three transistor devices - first and second wide bandgap semiconductor transistor devices and the silicon-based semiconductor transistor device. The interface circuit may be configured to internally generate the first control signal and provide to the gate of the first wide bandgap semiconductor transistor device, generate the second control signal and provide to the gate of the second wide bandgap semiconductor transistor device and generate the third control signal and provide to the gate of the silicon-based semiconductor transistor device. The interface circuit may comprise additional circuits and components such as auxiliary HEMTs, level shifter, slew rate control circuit, logic circuits, voltage regulator to generate the first, second and third control signals. Also described herein is a half bridge circuit comprising a low-side leg and a high-side leg, each of the low-side leg and the high-side leg comprising a semiconductor switch comprising: a first branch comprising a first wide bandgap semiconductor transistor device, and a second wide bandgap semiconductor transistor device, the first wide bandgap semiconductor transistor device and the second wide bandgap semiconductor transistor device being connected in series; and a second branch comprising a silicon-based semiconductor transistor device; wherein the first branch and the second branch are connected in parallel; and wherein a maximum voltage rating of the silicon semiconductor transistor device is greater than a maximum voltage rating of the first and second wide bandgap semiconductor transistor devices. Also described herein is a half bridge circuit comprising a low-side leg and a high-side leg, each of the low-side leg and the high-side leg comprising a semiconductor switch comprising: a first branch comprising a first lateral semiconductor transistor device, and a second lateral semiconductor transistor device, the lateral semiconductor transistor device and the second lateral semiconductor transistor device being connected in series; and a second branch comprising a vertical semiconductor transistor device; wherein the first branch and the second branch are connected in parallel; and wherein a maximum voltage rating of the vertical semiconductor transistor device is greater than a maximum voltage rating of the first and second lateral semiconductor transistor devices. Also described herein is an inverter comprising at least one phase, each phase comprising at least one half bridge circuit, each half bridge circuit comprising a low-side leg and a high-side leg, each of the low-side leg and the high-side leg comprising a semiconductor switch comprising: a first branch comprising a first wide bandgap semiconductor transistor device, and a second wide bandgap semiconductor transistor device, the first wide bandgap semiconductor transistor device and the second wide bandgap semiconductor transistor device being connected in series; and a second branch comprising a silicon-based semiconductor transistor device; wherein the first branch and the second branch are connected in parallel; and wherein a maximum voltage rating of the silicon semiconductor transistor device is greater than a maximum voltage rating of the first and second wide bandgap semiconductor transistor devices. Also described herein is an inverter comprising at least one phase, each phase comprising at least one half bridge circuit, each half bridge circuit comprising a low-side leg and a high-side leg, each of the low-side leg and the high-side leg comprising a semiconductor switch comprising: a first branch comprising a first lateral semiconductor transistor device, and a second lateral semiconductor transistor device, the first lateral semiconductor transistor device and the second lateral semiconductor transistor device being connected in series; and a second branch comprising a vertical semiconductor transistor device; wherein the first branch and the second branch are connected in parallel; and wherein a maximum voltage rating of the vertical semiconductor transistor device is greater than a maximum voltage rating of the first and second lateral semiconductor transistor devices. Also described herein is a multi-level inverter comprising at least one phase, each phase comprising at least one half-bridge circuit. The half bridge circuit may comprise a low side and a high side. Each side of each half bridge circuit may comprise: a first wide bandgap semiconductor transistor device; and a silicon-based semiconductor transistor device; wherein the wide bandgap semiconductor transistor device and the silicon-based semiconductor transistor device are connected in series. The first wide bandgap semiconductor transistor device may comprise one or more Ill-nitride transistors, and / or one or more silicon carbide transistors. The silicon-based semiconductor transistor device may comprise one or more IGBTs, one or more MOSFETs, and / or one or more superjunctions. The multi-level inverter may comprise an output terminal. The silicon-based semiconductor transistor device may be arranged closer in proximity to the output terminal than the first wide bandgap semiconductor transistor device. That is, the silicon-based semiconductor transistor device may be connected between the first wide bandgap semiconductor transistor device and the output terminal. In other words, the output terminal may be connected at a mid-point of the high-side and the low-side of the half bridge circuit. In some examples of the multi-level inverter according to the present disclosure, each side of each half bridge circuit may further comprise a second wide bandgap semiconductor transistor device connected in parallel with the silicon-based semiconductor transistor device. A maximum voltage rating of the silicon-based semiconductor transistor device may be greater than a maximum voltage rating of the first wide bandgap semiconductor transistor device. For example, the maximum voltage rating of the silicon-based semiconductor transistor device may be greater than the maximum voltage rating of the first wide bandgap semiconductor transistor device by a factor of at least 1.5, or at least 2. The multi-level inverter may comprise a first control terminal configured to receive a first control signal to drive the first wide bandgap semiconductor device. The multi-level inverter may comprise an interface circuit operatively connected between the first control terminal and the first wide bandgap semiconductor device. The interface circuit may comprise a first auxiliary HEMT operatively connected between the first control terminal and the first wide bandgap semiconductor device. In some examples described herein, the semiconductor switch is referred to as a “combined switch”. In some examples, as already mentioned, the HEMT may be a Ill-nitride based device, and the high voltage transistor device may be a silicon or silicon carbide based device. The silicon device may be an Insulated Gate Bipolar Transistor (IGBT) while the silicon carbide based device may be a Power MOSFET or a superjunction. A “Ill-nitride” transistor, device, or integrated circuit, as used herein, may refer generally to a transistor or device based on the group Ill-nitride family of materials, including GaN, AIN, InN, and alloys thereof. BRIEF DESCRIPTION OF THE DRAWINGS The present invention will now be described by way of example with reference to the following drawings: Figure 1 illustrates a prior art example of an IGBT in parallel with a silicon carbide MOSFET, reproduced from M. Rahimo, IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL 30, NO. 9, SEPTEMBER 2015; Figure 2 illustrates a parallel combination between a discrete GaN HEMT and an IGBT; Figure 3 illustrates a prior art solution for paralleling IGBTs with a GaN HEMT, reproduced from L. Molnar, 2018 IEEE 24th International Symposium for Design and Technology in Electronic Packaging (SIITME), 2018; Figure 4 illustrates a prior art circuit configuration of a two level inverter using IGBTs; Figure 5 illustrates a prior art circuit configuration of a three level NPC inverter; Figure 6 illustrates an example of a semiconductor switch according to the present disclosure; Figure 7 illustrates an example of a semiconductor switch according to the present disclosure in which the transistor device gate terminal is operatively connected to an output of the interface circuit; Figure 8 illustrates an example of a semiconductor switch featuring a lateral GaN HEMT, an auxiliary low voltage HEMT and a high voltage IGBT placed in parallel with the lateral high voltage GaN HEMT according to the present disclosure; Figure 9 illustrates an example of a semiconductor switch featuring a lateral GaN HEMT, an auxiliary low voltage HEMT, a pull down device and a high voltage IGBT placed in parallel with the lateral high voltage GaN HEMT, according to the present disclosure; Figure 10 illustrates an example of a semiconductor switch featuring a lateral high voltage GaN HEMT, an auxiliary low voltage HEMT, a pull down device and a high voltage SiC MOSFET (or superjunction) in parallel with the lateral high voltage GaN HEMT, according to the present disclosure; Figure 11 illustrates an example of a semiconductor switch wherein the interface circuit comprises an auxiliary low voltage HEMT and a pull down device connected to the gate of a GaN HEMT; Figure 12 illustrates the schematic shapes of on-state output l-V characteristics of the high voltage lateral GaN HEMT and the vertical IGBT at room and high temperatures; Figure 13 illustrates the schematic shapes of output on-state l-V characteristics of the combined GaN HEMT and IGBT switch according to the present disclosure; Figure 14 illustrates an example of a semiconductor switch comprising a silicon companion chip, or integrated circuit; Figure 15 illustrates an example of a semiconductor switch wherein a control terminal and a transistor device gate terminal are configured to be driven by a driver; Figure 16 illustrates an example of a semiconductor switch wherein a control terminal and a transistor device gate terminal are configured to be driven by a driver; Figure 17 illustrates an example of a semiconductor switch wherein a control terminal and a transistor device gate terminal are configured to be driven by a driver; Figure 18 illustrates an example of a semiconductor switch wherein a control terminal and a transistor device gate terminal are configured to be driven by a driver along with a feedback control circuit; Figure 19 illustrates an example of a semiconductor switch wherein a control terminal and a transistor device gate terminal are configured to be driven by a driver along with a feedback control circuit, wherein a current sensing HEMT acts as a feedback control circuit; Figure 20 illustrates an example of a semiconductor switch wherein the transistor device gate terminal is driven via an interface circuit; Figure 21 schematically illustrates an example of a method of operating a semiconductor switch according to the present disclosure; Figure 22 illustrates an example of a semiconductor switch suitable as part of an inverter according to the present disclosure; Figure 23 illustrates an example of a semiconductor switch comprising first and second interface circuits suitable as part of an inverter; Figure 24 illustrates an example of a semiconductor switch comprising an interface circuit comprising first and second auxiliary HEMTs suitable as part of an inverter; Figure 25 illustrates an example of a semiconductor switch comprising a single, or common, control terminal; Figure 26 illustrates an example of an interface circuit that may be used as part of a semiconductor switch; Figure 27 illustrates an example of a half bridge circuit suitable as part of an inverter according to the present disclosure; Figure 28 illustrates an example of a one phase inverter according to the present disclosure; Figure 29 illustrates an example of a three phase inverter according to the present disclosure Figure 30 illustrates an example of a multi-level inverter comprising at least one phase according to the present disclosure; Figure 31 illustrates another example of a multi-level inverter comprising at least one phase according to the present disclosure; Figure 32 illustrates an example of a semiconductor switch comprising a feedback element according to the present disclosure; Figure 33 illustrates a further example of a semiconductor switch comprising a feedback element according to the present disclosure; and Figure 34 illustrates an example of a semiconductor switch comprising temperature sensors for monitoring the temperatures of the transistor devices. DETAILED DESCRIPTION In the illustrative examples described herein, a semiconductor switch comprises a (high voltage) high-electron-mobility transistor (HEMT), such as a Ill-nitride HEMT, and optionally a high voltage transistor device such as an insulated-gate bipolar transistor. While the examples of HEMTs described herein are predominantly GaN-based, it will be appreciated that HEMTs based on other Ill-nitride materials such as InN, AIN, and alloys of InN, AIN, and GaN may also be suitable. Similarly, it will be appreciated that the high voltage transistor device described herein may alternatively comprise a metal-oxide-semiconductor field-effect transistor (MOSFET), and / or a superjunction. The high voltage transistor device may be a silicon or silicon carbide device. In addition to the examples described herein, examples of semiconductor switches suitable for use with embodiments of the present invention are described in WO 2025 / 062120 A1, the contents of which are hereby incorporated by reference in their entirety. Figure 6 illustrates a combined switch according to some examples, featuring a lateral GaN HEMT (10), an interface circuit (207) and a high voltage transistor (30). The interface circuit (207) is placed in front of the gate of the lateral GaN HEMT to adapt the driving voltage of the control terminal to that suitable and allowable for the GaN HEMT. This interface could be preferably monolithically integrated with the power HEMT for providing lower parasitics, ease of manufacturing and fast reaction time. Alternatively, this interface could be part of a separate chip (such as a silicon companion chip, or a driver chip). The interface circuit may additionally include clamping circuits, sensing and protection functions, pull-down devices to ensure a fast and safe turn-off, to enhance immunity against dV / dt and to absorb any transient voltage peaks on the gate. Figure 7 illustrates another example according to the present disclosure, featuring the high voltage transistor (30) to be connected to another output of the interface circuit. The interface circuit can provide functionality of clamping, voltage limiting, sensing and protection and other control functions for the high voltage transistor (30). As shown in Figure 8, the interface circuit may additionally comprise a voltage limiter 201. The voltage limiter may be a circuit block which can limit (or clamp) the maximum voltage at the gate of the auxiliary low voltage HEMT. Through this manner of operation the voltage limiter may overall act to provide a limit on the maximum voltage on the gate terminal of the GaN HEMT. In operation, the voltage applied to the control terminal may be divided between a voltage drop between the drain and source terminal of the aux HEMT (20) and a voltage drop between the gate and source terminal of the GaN HEMT (10). The auxiliary HEMT and the voltage limiter may be monolithically integrated with the GaN HEMT. Figure 8 illustrates an example of a combined switch featuring a lateral GaN HEMT (10) placed in parallel with a high voltage IGBT (40) and an example of the interface circuit comprising an auxiliary low voltage HEMT (20) and a voltage limiter (201). The voltage limiter may be a circuit block which can limit (or clamp) the maximum voltage at the gate of the auxiliary low voltage HEMT. Through this manner of operation the voltage limiter may overall act to provide a limit on the maximum voltage on the gate terminal of the GaN HEMT. In operation, the voltage applied to the control terminal may be divided between a voltage drop between the drain and source terminal of the aux HEMT (20) and a voltage drop between the gate and source terminal of the GaN HEMT (10). The auxiliary HEMT and the voltage limiter may be monolithically integrated with the GaN HEMT. Figure 9 illustrates another example of a combined switch according to the present disclosure, featuring a lateral GaN HEMT (10), an auxiliary low voltage HEMT (20), a pull down device (Miller clamp, 50) and a high voltage IGBT (40) placed in parallel with the lateral high voltage GaN HEMT (20). The driving circuit for the Miller Clamp (50) is not shown here. For simplicity the Miller clamp may be an active device, for example it may switch according to a signal applied to the control terminal. The signal to the gate of the Miller clamp may be adjusted in relation to the signal at the control terminal for example it may inverted and / or level shifted. The Miller clamp may be monolithically integrated with the GaN HEMT (10), aux HEMT (20) and Voltage limiter (201). Figure 10 illustrates a combined switch according to another example, featuring a lateral high voltage GaN HEMT (10), an auxiliary low voltage HEMT (20), a pull down device (Miller clamp, 50) and a high voltage SiC MOSFET (or superjunction MOSFET) (60) in parallel with the lateral high voltage GaN HEMT (10). Figure 11 illustrates an example of an interface circuit comprising an auxiliary low voltage HEMT (20a) and a pull down device (Miller clamp, 50a) connected to the gate of the GaN HEMT (10) and an additional auxiliary low voltage HEMT (20b) and an additional pull down device (Miller clamp, 50b) connected between the control terminal and the gate of the high voltage IGBT (40). The additional low voltage HEMT (20b) and the additional pull down device (Miller clamp, 50b) enable on-chip regulation or pull-down of the gate voltage of the IGBT. The driving / control circuits of the auxiliary HEMTs and Miller clamps are not shown here for simplicity. It will be appreciated that the high voltage transistor device described herein as an IGBT may alternatively comprise a metal-oxide-semiconductor field-effect transistor (MOSFET), and / or a superjunction. The high voltage transistor device may be a silicon or silicon carbide device. The silicon carbide device may be preferred in terms of performance and efficiency while the silicon transistor such as a superjunction may be preferred in terms of price. For higher power applications (e.g. more than 10kW), the high voltage transistor may preferably be an IGBT or a Silicon Carbide power MOSFET or a Silicon Carbide Superjunction device. Figure 12 illustrates the schematic shapes of on-state output l-V characteristics of the high voltage lateral GaN HEMT and the vertical IGBT at room and high temperatures. Note that the HEMT has a linear shape of the characteristics at low currents, while the IGBT does not have any current until 0.7 V and growing super-linearly initially and linearly after 0.7 V (followed by saturation). Note that the HEMT has a severe drop in the current (increased on-state resistance) at high temperatures. Figure 13 illustrates the schematic shapes of output on-state l-V characteristics of the combined GaN HEMT and IGBT switch according to the present disclosure. Note that the HEMT current dominates at lower currents / lower on-state voltage drops (below 0.7V) - low load, while the IGBT currents dominates at higher currents (higher on-state voltage drops). At high temperatures, the IGBT compensates the loss in the current of the HEMT. The two parallel devices offer a complementary behavior with improved performance than either the IGBT or the GaN HEMT. Figure 14 illustrates an example of the present disclosure where a silicon companion chip (2000) can be co-packaged with the Power HEMT (10). The Miller clamp (50) can be monolithically integrated with the GaN HEMT (10). The silicon companion chip can provide an interface allowing a compatible voltage range for driving the GaN HEMT (10) and the IGBT (40). The companion chip (2000) can provide voltage clamping action, slew rate control, high side drive and other sensing and protection features. It can have programmable functions and can be made in mix-signal processes which allow both digital and analogue components to be integrated. A BCD (Bipolar CMOS DMOS) process can be used as an example. The symbol for the high voltage switch in Figure 14 is that of an IGBT, but the high voltage switch could be another type of power semiconductor device, such as a power MOSFET or a superjunction MOSFET preferably comprising a wide band-gap (such as Silicon Carbide) or ultra-wide bandgap (such as Aluminium Nitride) material, or silicon. Figure 15 illustrates an example according to the present disclosure, featuring a multiple input Ill-nitride (e.g. GaN) power HEMT with individual connections for driving the gates of the GaN power HEMT (10) and high voltage switch (40). In the example illustrated in Figure 15, the HEMT is part of a GaN power integrated circuit (IC). The symbol for the high voltage switch in Figure 15 is that of an IGBT, but the high voltage switch could be another type of power semiconductor device, such as a power MOSFET or a superjunction MOSFET preferably comprising a wide band-gap (such as Silicon Carbide) or ultra-wide bandgap (such as Aluminium Nitride) material. An optional interface circuit (207) may be placed in front of the gate of the lateral GaN power HEMT (10) to adapt the driving voltage from the driver to that suitable and allowable for the GaN power HEMT (10). This interface could be preferably monolithically integrated with the power HEMT for providing lower parasitics, ease of manufacturing and fast reaction time. Alternatively, this interface could be part of a separate chip (such as a silicon companion chip, or a driver chip). Alternatively, this interface could be integrated within the driver. The interface circuit may additionally include pass transistors (e.g. a low power HEMT), diodes, voltage regulators, voltage limiters, clamping circuits, sensing and protection functions, pull-down devices, such as a Miller clamp, to ensure a fast and safe turn-off, to enhance immunity against dV / dt and to absorb any transient voltage peaks on the gate. Multiple inputs of the GaN power IC are configured to have different driving voltage levels and / or slew rates and / or timing sequences when the power IC is in the on-state, off-state, turn-on and turn-off modes. This may enable dynamic control of the IGBT slew rate and turn on and turn off curves while GaN power IC has its own input from the driver. The resistors RG1, RG2, RG3 can be provided externally or inserted before the interface circuit for the power HEMT (10) and the gate of the IGBT (40) to adjust individually the turn-on and turn-off speed of the two devices. The VDD voltage needed as a DC rail for the interface circuit, could be provided internally via a start-up structure (not shown) or could be the same as the VDD supplied to the driver. In the example shown in Figure 15, the turn-on and turn-off of the GaN Power IC are driven by gate G1 through the same path OUT1. Gate G2 of IGBT may receive driving signal from two outputs of the driver OUT 1 and OUT2 which can be configured for turnon and turn-off signals, respectively. This helps in controlling the slew rate of the IGBT by adjusting the resistor values and delaying the gate driving signals. The resistors RG1, RG2 etc. can help dynamically control and modulate the turn-on speeds of the switches. During the turn-on, the GaN power HEMT can take higher current than during the on-state or steady state (as much as the saturation current) until the IGBT turns-on fully and the current is redistributed (part of the current from the GaN power HEMT would be redistributed in the IGBT). As a result, the turn-on losses in a combined switch may be smaller than in an IGBT or a first transistor alone. Alternatively, the connections between the outputs (e.g. OUT 1, OUT2, OUT3) of the driver and the inputs of the interface circuit or the gate of the high voltage switch (e.g. G1, G2) may contain resistors in parallel with series branches of resistors and diodes to differentiate between turn-on and turn-off speeds. In Figure 33a only one power HEMT 10 and one high voltage switch 40 are shown. It may be understood that multiple HEMT devices in parallel could replace the HEMT 10, or multiple high voltage switches (e.g. vertical IGBTs or Silicon Carbide MOSFETs) could replace the high voltage switch 40. It may also be understood that the semiconductor switch may comprise the combination of a cascode device with a high voltage switch or other alternative configurations as illustrated in previous embodiments. For example, a module or a package can house a combined switch which could comprise multiple vertical IGBTs in a combination with a single Power HEMT. A multiple output driver can drive the module as described above. Figure 16 illustrates a further example of the aspect depicted in Figure 15 featuring a multiple input semiconductor switch power IC with individual connections for driving the gates of the GaN power HEMT (10) and high voltage switch (40), wherein the high voltage switch may be a SiC MOSFET (60). Figure 17 illustrates a further example of the aspect depicted in Figure 15 featuring a multiple input semiconductor switch power IC, wherein the GaN HEMT is replaced by a Cascode device. The Cascode device comprises a MOSFET (93) (an n-channel MOSFET made preferably in silicon or silicon carbide technology) in series with a high voltage depletion mode HEMT (95) (made in Ill-Nitride material). The gate of the depletion mode GaN HEMT is connected to the source of the MOSFET. The symbol for the high voltage switch in Figure 17 is that of an IGBT, but the high voltage switch could be another type of power semiconductor device, such as a power MOSFET or a superjunction MOSFET preferably comprising a wide band-gap (such as Silicon Carbide) or ultra-wide bandgap (such as Aluminium Nitride) material, or silicon. Figure 18 illustrates a further example according to the present disclosure, featuring a multiple input semiconductor switch power IC with individual connections for driving the gates of the GaN power HEMT (10) and high voltage switch (40). Compared to Figure 15, Figure 18 shows an additional feedback control circuit (301) preferably integrated within the GaN Power IC. The role of this circuit is to provide a feedback signal to the driver about the state of the combined switch. The feedback control circuit could comprise sensing circuits such as current sensing or short-circuit sensing and provide this information to the driver. The driver could utilize this information to adjust the voltage levels on OLIT1, OLIT2, OLIT3, or the time sequence or the slew-rates to provide (i) increased performance (ii) enhanced reliability. The decision regarding the feedback can come from an additional controller or can be embedded within the driver. As an example, the feedback control may detect the voltage across the combined switch and at higher voltages (e.g. above 5V) it may lower the voltage level applied to the gate of the GaN Power HEMT 10. The switching frequency or time sequences could also change as a function of the feedback loop control. Another scenario can be when the feedback control circuit detects the current or the temperature in the GaN Power HEMT 10 exceed a certain level, the driver output voltage is configured to take certain actions such as either lower the gate voltage applied to the gate of the Power HEMT 10 or shut off the GaN Power HEMT for a period of time or depending on other threshold levels for current or temperature. In this period, the vertical switch 40 driving signal may not be affected, and the vertical switch may handle the extra load current. The feedback loop circuit can be monolithically integrated with the Power HEMT, 10. It can also be a part of or regarded as being a part of the interface circuit. The feedback loop circuit can gather certain information regarding the status of the GaN Power IC, such as the current in the Power HEMT 10 or the voltage across the drain-source terminals of Power HEMT 10 or the temperature within the GaN Power IC, however not limiting to only these conditions. As an additional control, the feedback signal may also be provided to the interface circuit to internally control the GaN power HEMT while the driver controls the device externally. The feedback control circuit may be provided in the subsequent embodiments of the invention, however it is not shown for simplicity. This aspect is also applicable to the examples shown in Figure 16 and Figure 17. The symbol for the high voltage switch in Figure 18 is that of an IGBT, but the high voltage switch could be another type of power semiconductor device, such as a power MOSFET or a superjunction MOSFET preferably comprising a wide band-gap (such as Silicon Carbide) or ultra-wide bandgap (such as Aluminium Nitride) material, or silicon. Figure 19 illustrates a further example of the first aspect of the present disclosure, featuring a multiple input semiconductor switch power IC with individual connections for driving the gates of the GaN power HEMT (10) and high voltage switch (40). In this embodiment, the feedback control circuit 301 shown in Figure 18 is exemplified by a Sense HEMT 104. The Sense HEMT 104 is a scaled down, identical version of the Power HEMT (e.g. by an area of 10 to 1000x). The Sense HEMT could be integrated monolithically with the Power HEMT. The Sense HEMT can directly sense the current of the Power HEMT and this information can be communicated directly or indirectly to the driver. The driver (or a separate controller - not shown) could decide to change the driving voltages, time sequence, slew rates or frequency of the output pins to the combination switch, function of the feedback provided. As an additional control, the feedback signal may also be provided to the interface circuit to internally control the GaN power HEMT while the driver controls the device externally. The symbol for the high voltage switch in Figure 19 is that of an IGBT, but the high voltage switch could be another type of power semiconductor device, such as a power MOSFET or a superjunction MOSFET preferably comprising a wide band-gap (such as Silicon Carbide) or ultra-wide bandgap (such as Aluminium Nitride) material, or silicon. Figure 20 illustrates another example according to the present disclosure, where the gate of the high voltage switch 40 (e.g. IGBT) is also driven through the interface circuit 207, preferably incorporated within the GaN Power IC. The interface circuit 207 can internally control the lead / lag and slew rates of the operation of the switches through additional circuits such as logic circuits, signal conditioning circuits, latch circuits, delay circuits, networks of resistors and capacitors etc. Additionally, the interface circuit can provide functionality of clamping, voltage limiting, voltage regulation, sensing and protection and other control functions for the high voltage transistor (40), and / or for the GaN Power HEMT (10). The symbol for the high voltage switch in Figure 20 is that of an IGBT, but the high voltage switch could be another type of power semiconductor device, such as a power MOSFET or a superjunction MOSFET preferably comprising a wide band-gap (such as Silicon Carbide) or ultra-wide bandgap (such as Aluminium Nitride) material, or silicon. Figure 21 illustrates an example of a method 470 of operating a semiconductor switch according to the present disclosure. The semiconductor switch may comprise any of the example semiconductor switches (also referred to as ‘combined switches’) illustrated and described herein, and may comprise a high voltage HEMT (e.g. a GaN HEMT) comprising a high voltage HEMT terminal operatively connected to a control terminal, and a high voltage transistor device (e.g. a vertical device such as an IGBT), the high voltage transistor device comprising a transistor device gate terminal. For example, in a step S472, the method 470 comprises driving the control terminal, by a driver via a first driver output, at a first driving voltage. In a step S474, the method 470 comprises diving the transistor device gate terminal, by the driver via a second driver output, at a second driving voltage. Examples of semiconductor switches that may be suitable for use in phase inverters will now be described. For example, described herein is a parallel combination between a 3-level inverter based on a HEMT (e.g. a Ill-nitride HEMT) and a two-level inverter based on a high voltage transistor device such as an IGBT, a MOSFET, or a superjunction. The high voltage transistor device may be a silicon or silicon carbide device. Figure 22 illustrates a simplified example of a semiconductor switch 101 suitable for use as part of an inverter as described herein. The semiconductor switch 101 comprises a first branch comprising a first lateral semiconductor transistor device 12 (e.g. a GaN HEMT) and a second lateral semiconductor transistor device 11 (e.g. a GaN HEMT) connected in series. A second branch comprises a high voltage vertical semiconductor transistor device 40 (e.g. a Si IGBT). The first branch and the second branch are connected in parallel. A maximum voltage rating of the high voltage vertical semiconductor transistor device 40 is significantly greater (e.g. by a factor of 1.5 or more, or a factor of 2 or more) than the maximum voltage ratings of the lateral semiconductor transistor devices 12, 11. Further, it may be understood that the high voltage vertical semiconductor transistor device 40 (e.g. a Si IGBT) may comprise a body diode between its main terminals (emitter, collector). Each of the lateral semiconductor transistor devices 12, 11, and the high voltage vertical semiconductor transistor device 40, may have gates that are each operatively connected to distinct control terminals (first control terminal G1, second control terminal G2, and third control terminal G3) that are operable by a driver or controller. For example, the driver or controller may provide at least one of a first control signal, a second control signal, and a third control signal to at least one of the control terminals G1, G2, G3 to drive the transistor devices 12,11,40. Additionally, the semiconductor switch may also have a mid terminal M1 connected to the mid-point between the first lateral semiconductor transistor device 12 and the second lateral semiconductor transistor device 11 to access the DC mid-point between the two lateral semiconductor transistor devices. Figure 23 illustrates an additional example of a semiconductor switch 101a. The semiconductor switch 101a illustrated in Figure 23 is similar to the semiconductor switch 101 illustrated in Figure 22, but additionally comprises a first interface circuit 207_2 operatively connected between the first control terminal G1 and the first lateral semiconductor transistor device 12, and a second interface circuit 207_1 operatively connected between the second control terminal G2 and the second lateral semiconductor transistor device 11. In some examples (not shown) an interface circuit (e.g. a third interface circuit) may be connected between the third control terminal G3 and the vertical semiconductor transistor device 40. Various examples of interface circuits have been described herein, for example the interface circuit 207 illustrated in Figure 6 and its variations in Figures 7, 8, and 9,, and may be suitable as the first 207_2, second 207_1, and / or third interface circuit(s) of the semiconductor switch 101a. Figure 24 illustrates a further example of a semiconductor switch 101b, similar to the semiconductor switch 101 illustrated in Figure 22. The semiconductor switch 101b illustrated in Figure 24 includes an example of an interface circuit (e.g. a GaN interface circuit) that may be connected between the first control terminal G1 and the first lateral semiconductor transistor device 12, and between the second control terminal G2 and the second lateral semiconductor transistor device 11. Similarly to other examples described herein, the interface circuit may comprise a first auxiliary HEMT 20_1 connected between the first control terminal G1 and the first lateral semiconductor transistor device 12, and a second auxiliary HEMT 20_2 connected between the second control terminal G2 and the second lateral semiconductor transistor device 11. The connections of the gate terminal for auxiliary HEMTs are not shown for simplicity. The interface circuits may comprise additional circuitry connected to the different terminals of the auxiliary HEMTs and the lateral semiconductor transistor devices. For example, the interface circuits may each additionally comprise a voltage limiter connected between the gate of an auxiliary HEMT and the source of respective lateral semiconductor transistor device with an input from the respective control terminal. The voltage limiter may be a circuit block which can limit (or clamp) the maximum voltage at the gate of respective auxiliary HEMT. Through this manner of operation, the voltage limiter may overall act to provide a limit on the maximum voltage on the gate terminal of the lateral semiconductor transistor device. In operation, the voltage applied to the control terminal may be divided between a voltage drop between the drain and source terminal of the auxiliary HEMT (20_1, 20_2) and a voltage drop between the gate and source terminal of the lateral semiconductor transistor device (12, 11). The auxiliary HEMT and the voltage limiter may be monolithically integrated with the lateral semiconductor transistor device. Figure 25 illustrates a further example of a semiconductor switch 101c. The semiconductor switch 101c may comprise only one control terminal (which may be referred to as a common control terminal) to receive a control signal from a driver / controller. The semiconductor switch may further comprise an interface circuit 207. The interface circuit 207 may be connected between the control terminal and the three transistor devices 12, 11 and 40. The interface circuit 207 may be configured to internally generate the first control signal and provide to the gate G1 of the first lateral semiconductor transistor device 12, generate the second control signal and provide to the gate G2 of the second lateral semiconductor transistor device 11 and generate the third control signal and provide to the gate G3 of the vertical semiconductor transistor device 40. Figure 26 illustrates an example of the interface circuit that may be used in the semiconductor switch illustrated in figure 25 and Figure 6. The interface circuit may comprise additional circuits and components such as auxiliary HEMTs, level shifter, slew rate control circuit, logic circuits, voltage regulator to generate the first, second and third control signals. Additionally, the interface circuit may comprise sensing and protection circuits for both the lateral and vertical semiconductor devices and may also be configured to receive feedback from the lateral and vertical semiconductor devices. The interface circuit may be implemented on the same substrate as the lateral semiconductor switches such as a GaN chip or it may be implemented on an additional companion chip for example a silicon companion chip. Figure 27 illustrates an example of a half bridge circuit according to the present disclosure. The half bridge circuit comprises at least one switch operated on the low-side leg of the half bridge and one switch operated on the high-side leg of the half bridge; wherein each of the switches comprises a first branch of two or more lateral semiconductor transistor devices Q1, Q2, Q3, Q4 (e.g. GaN transistors) and a second branch comprising a high voltage vertical semiconductor transistor device S1, S2 and wherein the first and second branch are in parallel. Each of the semiconductor transistor devices may comprise control terminals which are operated through a driver / controller, as described herein. The rated maximum voltage of the high voltage vertical device is significantly larger (e.g. by a factor or 1.5 or 2) than the rated maximum voltage of the lateral semiconductor transistor device. Additionally, each high voltage vertical semiconductor transistor device S1, S2 (e.g. Si IGBT) may comprise a body diode between its main terminals (emitter, collector). Figure 28 illustrates an example of a one phase inverter according to the present disclosure. In other examples, an inverter may comprise more than one phase. Each phase of the inverter comprises at least one half bridge circuit. Each half bridge circuit may comprise a high side (e.g. a high-side leg) and a low side (e.g. a low-side leg). Each side of the half bridge circuit comprises a first branch of two or more lateral semiconductor transistor devices Q1, Q2, Q3, Q4 (e.g. GaN transistors) and a second branch comprising a high voltage vertical semiconductor transistor device S1, S2 and wherein the first and second branch are in parallel. Additionally, each high voltage vertical semiconductor transistor device S1, S2 (e.g. Si IGBT) may comprise a body diode between its main terminals (emitter, collector). Each of the semiconductor transistor devices may comprise control terminals which are operated through a driver / controller, as described herein. Alternatively, the control terminals may be operated though an internal interface circuit as illustrated in figure 25. The rated maximum voltage of the high voltage vertical device is significantly larger (e.g. by a factor or 1.5 or 2) than the rated maximum voltage of the lateral semiconductor transistor device. The inverter additionally comprises two DC link capacitors connected in series between the high voltage and the low voltage terminals. The mid-point of the DC link capacitors is referred to as a DC Mid point or also referred as neutral point in the literature. Each leg of the half-bridge has a DC point at the mid of the two lateral semiconductor switches denoted as point A in the high-side leg of the half-bridge and point B in the low-side leg of the half-bridge in Figure 28. The inverter further comprises two clamping diodes over the neutral point, that is connected between the DC mid-point and the mid point of the first branch of each leg of the half-bridge. Figure 29 illustrates an example of a three phase inverter according to the present disclosure. The three phase inverter comprises a first half bridge circuit comprising a first 101_1 and a second 101_2 semiconductor switch, a second half bridge circuit comprising a third 101_3 and a fourth 101_4 semiconductor switch, and a third half bridge circuit comprising a fifth 101_5 and a sixth 101_6 semiconductor switch as described herein. The DC bus voltage is split in two (or more for more than three levels) with an intermediate level (DC MID) which sits at a voltage given by the potential divider of the two capacitors in series. This DC MID voltage level is typically half of that between the DC+ and DC- voltage levels. Depending on the status (ON or OFF) of low-side and high-side legs of the half-bridge circuits and given the action of the additional clamping diodes placed as shown in Fig. 29, the output voltage can be in steady-state at any of the three level DC voltages (DC+, DC MID, and DC -) and switching between these states when the switches are switched. The clamping diodes are connected between the series devices on each of the high-side and low-side legs to the DC MID (between the series capacitors). It will be understood that a lateral semiconductor transistor device has terminals (e.g. source and drain terminals) on a same surface of the semiconductor. A vertical semiconductor transistor device has terminals (e.g. collector and emitter) on opposite surfaces. Each lateral semiconductor transistor device may comprise, e.g. one or multiple Ill-nitride (e.g. GaN) transistors, such as discrete HEMTs, Cascode HEMTs, smart GaN HEMTs such as those described in US11217687 and US11404565B2, the contents of which are hereby incorporated by reference. The transistors (e.g. HEMTs) may comprise monolithically integrated interface circuits, or the lateral semiconductor transistor device may comprise additional companion or interface circuits (e.g. fabricated from silicon). Preferably, where the device comprises multiple transistors, the multiple transistors have similar specifications and are arranged in parallel. The high voltage vertical semiconductor transistor device may comprise, e.g., one or more parallel IGBTs, MOSFETs, or superjunctions. The vertical semiconductor transistor device may comprise silicon and / or silicon carbide transistors. The maximum voltage rating refers to the maximum voltage supported between the main terminals when the device is in blocking mode. The main terminals are referred to as drain and source terminals for HEMTs, MOSFETs, and superjunctions, and emitter and collector terminals for IGBTs. The control terminal(s) described herein correspond to gate terminals of the transistor devices. When two branches are in parallel, a first terminal of a first branch is electrically connected to a first terminal of the second branch and a second terminal of the first branch is electrically connected to a second terminal of the second branch. Drivers can feature multiple outputs and some outputs of the drivers can be connected to the gate terminals of devices commonly via resistors and diodes to adjust turn-on and turn-off slew rates. All half bridges are connected between a DC+ voltage level and a DC- level and feature a mid AC output point (e.g. output terminal). Any low side leg of the half bridge is connected between DC- (or ground) and mid point. Any high side leg of the half bridge is connected between the DC+ and the mid point. A three phase or multiple phase inverter could be provided as part of the invention. The inverter according to the present disclosure could be viewed as a parallel combination between a two-level component of an inverter comprising high voltage switches such as IGBTs, Power MOSFETs, or superjunctions and multi-level (such as three level) component of an inverter comprising two or more series GaN lateral devices such as HEMTs or MISFETs. The mid points are outputs from the inverter and can be connected to a motor. The inverter described could be used as a traction inverter in automotive or other motor control applications. The inverter according to this aspect of the invention could be referred to as a “combo inverter”. Different control schemes could be applied to the combo inverter. The multi-level (such as three level) component (comprising e.g. two or more series GaN lateral devices) could be active or dominant in light load conditions, when the currents are relatively small. The two-level component (comprising e.g. IGBTs, Power MOSFETs, or superjunctions) could be active or dominant in high load conditions surge conditions, when the currents are relatively high or very high. Different control schemes could be applied to the control terminal to optimize the efficiency and robustness of the combo inverter. The drive frequency could also change when driving the two-level component (preferably lower frequency) compared to the multi-level component (preferably higher frequency). In another example according to the present disclosure, a semiconductor switch may comprise a first branch comprising a first wide bandgap semiconductor transistor device, and a second wide bandgap semiconductor transistor device, the first wide bandgap semiconductor transistor device and the second wide bandgap semiconductor transistor device being connected in series; and a second branch comprising a high voltage silicon- based semiconductor transistor device; wherein the first branch and the second branch are connected in parallel; and wherein a maximum voltage rating of the silicon semiconductor transistor device is greater than a maximum voltage rating of the first and second wide bandgap semiconductor transistor devices. The two or more series wide bandgap semiconductor transistor devices could comprise one or more Ill-nitride (e.g. GaN) transistors such as discrete HEMTs, Cascode HEMTs, or smart GaN HEMTs such as those described in US11217687 and US11404565B2, the contents of which are hereby incorporated by reference. The transistors (e.g. HEMTs) may comprise monolithically integrated interfaces, or HEMTs with additional silicon companion / interface circuits, or could comprise one or multiple silicon carbide transistors such as SiC power MOSFETs or SiC superjunctions. The multiple GaN transistors or the multiple SiC transistors could preferably have similar specifications and placed in parallel. The high voltage silicon-based semiconductor transistor device could comprise one or multiple parallel silicon IGBTs, silicon MOSFETs, or silicon superjunctions. A half bridge circuit may comprise at least two semiconductor switches as described herein, and an inverter may comprise at least one phase, each phase comprising at least one half bridge, as described herein in relation to other examples. Figure 30 illustrates an example of a multi-level inverter comprising at least one phase according to the present disclosure. Each phase comprises at least one half bridge, each half bridge comprising at least a branch of two or more series devices wherein at least one of the series devices is a wide bandgap device WBG1, WBG2, and at least one of the other series devices is a (high voltage) silicon-based semiconductor transistor device. Each of the devices may have control terminals which are operated through a driver / controller as described herein. The wide bandgap semiconductor transistor device WBG1, WBG2 could comprise one or more Ill-nitride (e.g. GaN) transistors such as discrete HEMTs, Cascode HEMTs, or smart GaN HEMTs such as those described in US11217687 and US11404565B2, the contents of which are hereby incorporated by reference. The transistors (e.g. HEMTs) may comprise monolithically integrated interfaces, or HEMTs with additional silicon companion / interface circuits, or could comprise one or multiple silicon carbide transistors such as SiC power MOSFETs or SiC superjunctions. The multiple GaN transistors or the multiple SiC transistors could preferably have similar specifications and placed in parallel. The high voltage silicon-based device could be one or multiple parallel silicon IGBTs, silicon MOSFETs, or silicon superjunctions. The devices with one terminal connected to the output voltage (i.e. the output terminal OUT) would be mostly in the on-state while the devices with one terminal connected to the DC- or DC+ buses would be switching more. Preferably, the devices with one terminal connected to the output voltage could be a silicon device. Such a device could be in the on-state for a longer period of the cycle, resulting in greater conduction loss. The devices with one terminal connected to the DC- and DC+ buses could be wide bandgap devices and could incur less conduction losses but higher switching losses. Alternatively, when one of the devices in series is a GaN transistor then the other transistor device may be a high voltage silicon-carbide based semiconductor transistor device. In this scenario, the SiC device would be connected to the output voltage as it can be in the on-state for longer and incur lower conduction losses relative to the GaN device. The GaN devices could be connected to the DC- and DC+ buses and could incur less conduction losses but higher switching losses. However, switching losses of GaN devices would be lesser than SiC devices. As shown in Figure 30, the output terminal OUT is operatively connected at a mid-point of the high-side leg and the low-side leg of the half bridge circuit, that is between a transistor device (e.g. silicon-based transistor device) on the high-side leg and a transistor device (e.g. silicon-based transistor device) on the low-side leg. This aspect of the invention is advantageous as IGBTs (as the silicon devices) are efficient in steady-state, especially at high temperatures and high power levels, while wide bandgap devices (e.g. GaN or SiC) can switch faster and therefore have lower switching losses. Also described herein is a multi-level inverter comprising at least one phase; each phase comprising at least one half bridge, each half bridge comprising at least a branch of two or more series devices wherein at least one of the series devices is a first wide bandgap device and at least one of the other series devices comprises a parallel combination between a silicon device and a second wide bandgap device wherein each of the devices may have control terminals which are operated through a driver / controller. The parallel combination of the silicon device and the second wide bandgap device may be similar to the combined switch illustrated in Figure 6 and its various implementations / variations described earlier. Figure 31 illustrates another example of a multi-level inverter comprising at least one phase according to the present disclosure. Each phase comprises at least one half bridge, each half bridge comprising at least a branch of two or more series devices wherein at least one of the series devices is a first wide bandgap semiconductor transistor device WBG1, WBG2 and at least one of the other series devices comprises a parallel combination between a silicon-based semiconductor transistor device and a second wide bandgap semiconductor transistor device WBG3, WBG4. Each of the devices may have control terminals which are operated through a driver / controller. The parallel combination of the silicon-based semiconductor transistor device and the second wide bandgap semiconductor transistor device may be similar to any of the combined switches described and illustrated herein, such as in Figures 6 to 11 and their subsequent variations. The example illustrated in Figure 31 is similar to the example illustrated in Figure 30. To address the light load condition in the on-state, preferably, the devices with one terminal connected to the output voltage could comprise a combination between a silicon device and a wide bandgap device. Such devices could be in the on-state for a longer period of the cycle, resulting in greater conduction loss. At light load the wide bandgap device WBG3, WBG4 will take most of the current, reducing the conduction losses while at high load (or high temperature) the silicon device could take most of the current. The devices with one terminal connected to the DC- and DC+ buses WBG1, WBG2 could be wide bandgap devices and could incur less conduction losses but higher switching losses as they would be switching more. As shown in Figure 31, the output terminal OUT is operatively connected at a mid-point of the high-side leg and the low-side leg of the half bridge circuit, that is between the parallel combination on the high-side leg and the parallel combination on the low-side leg. It will be understood that combinations of the examples described and illustrated herein are possible. In some examples, feedback control of adjusting the driving scheme of a combined switch comprising at least one GaN transistor and at least a vertical power device (IGBT or SiC power MOSFET) may be enabled. Feedback control may be provided in a similar manner to that illustrated in Figures 18 and 19 and described herein. A semiconductor switch may comprise a parallel combination between a high-electron-mobility transistor (HEMT) (e.g. a Ill-nitride HEMT) and a high voltage transistor device such as an insulated-gate bipolar transistor (IGBT), a metal-oxide-semiconductor field-effect transistor (MOSFET), or a superjunction. The semiconductor switch may comprise at least one feedback element (e.g. feedback control circuit 301_2 as illustrated in Figure 32) based on a current or temperature sensor incorporated alongside the HEMT and / or the high voltage transistor device, wherein the voltage levels provided to the control terminal(s) may be adjusted depending on the output from the at least one feedback element. The high voltage transistor device may be a silicon or silicon carbide device. The temperature feedback may be provided from both the IGBT and the GaN transistor to drive each differently. Examples of temperature sensor include an enhanced 2DEG with pGaN shielding the edges. Figure 33 illustrates another example of the feedback control for adjusting the driving scheme of a combined switch comprising at least one GaN transistor and at least a vertical power device (IGBT or SiC power MOSFET). Here, the semiconductor switch may comprise a parallel combination between a high-electron-mobility transistor (HEMT) (e.g. a Ill-nitride HEMT) and a high voltage transistor device such as an insulated-gate bipolar transistor (IGBT), a metal-oxide-semiconductor field-effect transistor (MOSFET), or a superjunction. The semiconductor switch may additionally comprise an interface circuit that would provide control signals to the gates of the HEMT and the high voltage transistor device. The semiconductor switch may comprise at least one feedback element (e.g. feedback control circuit 301_1, 301_2 as illustrated in Figure 33) based on a current or temperature sensor incorporated alongside the HEMT and / or the high voltage transistor device, wherein the voltage levels provided to the control terminal(s) may be adjusted depending on the output from the at least one feedback element. The high voltage transistor device may be a silicon or silicon carbide device. The temperature feedback may be provided from both the IGBT and the GaN transistor to drive each differently. Examples of temperature sensor include an enhanced 2DEG with pGaN shielding the edges. The feedback may be provided internal to the semiconductor switch to the interface circuit to adjust the driving signals and / or the feedback may be provided externally to the driver / controller to adjust the control signal from the driver / controller. In any of the examples described herein, current or junction temperature feedback from the wide bandgap device (e.g. a GaN transistor or a SiC transistor) and / or the silicon-based device (e.g. IGBT) could be used by a controller or driver or the interface circuit to modify the driving schemes of the switch. The temperature sensor for a GaN device (lateral device), could comprise a resistive temperature detector (RTD) in some examples (see Figure 34, Sensorl). A RTD is a device that modifies its resistance with the temperature in a known manner. By monitoring the resistance, the temperature could be monitored. The RTD could comprise a 2DEG resistor, a 2DEG resistor with edges covered by p-GaN, to give better uniformity, metal resistor or a HEMT used in a resistive mode. Sensing bridges or differential schemes as known in state-of-the art of such RTDs could be used to increase the sensitivity and accuracy of temperature reading. Alternatively, the temperature could be monitored by monitoring the voltage drop on a diode incorporated in GaN or its leakage during reverse blocking. The GaN diode could be made using a similar structure to the pGaN gate diode, or could be done by using Schottky metallization. The temperature sensor for the vertical device (e.g. SiC MOSFET or IGBT), could be in the form of a polysilicon diode (see Figure 34, Sensor2). The voltage drop on a polysilicon diode at a constant current decreases with temperature linearly. This could be used to monitor the temperature. The diode could be the sensing element in a VPTAT or IPTAT circuit (the rest of the circuit could be external) or could be used as part of differential measurement or in a bridge configuration. The feedback in the form of current or junction temperatures could be used to adjust the driving scheme for the combinational switch. For example, if either of the GaN lateral device or the IGBT hit a certain temperature level, the devices could be switched off made inactive, or the other device could be actively operated. Continuous adjustment of the driving scheme could be performed as a function of the current / temperature information from the vertical and the lateral device to (i) increase efficiency or (ii) enhance reliability. It will be appreciated that terms such as "top" and "bottom", "above" and "below", "lateral" and "vertical", and “under” and “over”, “front” and “behind”, “underlying”, etc. may be used in this specification by convention and that no particular physical orientation of the device as a whole is implied. It will be further appreciated that specific examples described herein may be equivalently applicable to any suitable type of high voltage transistor device, for example IGBTs, MOSFETs (e.g. high voltage Si or SiC MOSFETs), and / or superjunctions. Although the disclosure has been described in terms of preferred embodiments as set forth above, it should be understood that these embodiments are illustrative only and that the claims are not limited to those embodiments. Those skilled in the art will be able to make modifications and alternatives in view of the disclosure, which are contemplated as falling within the scope of the appended claims. Each feature disclosed or illustrated in the present specification may be incorporated in the disclosure, whether alone or in any appropriate combination with any other feature disclosed or illustrated herein.

Claims

1. An inverter comprising at least one phase, each phase comprising at least one half bridge circuit, each half bridge circuit comprising a high-side leg and a low-side leg, each of the high-side leg and the low-side leg comprising a semiconductor switch, the semiconductor switch comprising:a first branch comprising a first lateral semiconductor transistor device configured to be driven by a first control signal, and a second lateral semiconductor transistor device configured to be driven by a second control signal, the first lateral semiconductor transistor device and the second lateral semiconductor transistor device being connected in series; anda second branch comprising a vertical semiconductor transistor device configured to be driven by a third control signal;wherein the first branch and the second branch are connected in parallel; andwherein a maximum voltage rating of the vertical semiconductor transistor device is greater than a maximum voltage rating of the first and second lateral semiconductor transistor devices;wherein:the first branch of the low-side leg and the first branch of the high-side leg form a first multi-level component; andthe second branch of the low-side leg and the second branch of the high-side leg form a second multi-level component;wherein the first multi-level component is configured to be dominant when a current through the inverter is below a threshold level; andwherein the second multi-level component is configured to be dominant when the current through the inverter is above the threshold level.

2. The inverter according to claim 1, wherein the maximum voltage rating of the vertical semiconductor transistor device is greater than the maximum voltage rating of the first and second lateral semiconductor transistor devices by a factor of at least 1.5, or at least 2.

3. The inverter according to claim 1 or 2, wherein at least one of the first and second lateral semiconductor transistor devices comprises one or more Ill-nitride transistors, one or more HEMTs, and / or one or more Ill-nitride HEMTs.

4. The inverter according to any one of the preceding claims, wherein the vertical semiconductor transistor device comprises one or more silicon or silicon carbide-based IGBTs, MOSFETs, and / or superjunctions.

5. The inverter according to any one of the preceding claims, comprising:a first control terminal configured to receive the first control signal;a second control terminal configured to receive the second control signal; andan interface circuit connected between at least one of:the first control terminal and the first lateral semiconductor transistor device; andthe second control terminal and the second lateral semiconductor transistor device.

6. The inverter according to claim 7, wherein the interface circuit comprises at least one of:a first auxiliary HEMT operatively connected between the first control terminal and the first lateral semiconductor transistor device; anda second auxiliary HEMT operatively connected between the second control terminal and the second lateral semiconductor transistor device.

7. The inverter according to any one of claims 1 to 4, comprising:a common control terminal configured to receive a common control signal; andan interface circuit connected between at least one of:the common control terminal and the first lateral semiconductor transistor device;the common control terminal and the second lateral semiconductor transistor device; andthe common control terminal and the vertical semiconductor transistor device;wherein the interface circuit is configured to generate at least one of the first control signal, the second control signal, and the third control signal.

8. The inverter according to any one of the preceding claims, wherein each phase comprises an output terminal connected at a mid-point of the high-side leg and the low-side leg of the half bridge circuit.

9. The inverter according to any one of the preceding claims comprising three phases, each phase comprising an output, the outputs being configured to drive a three-phase motor.

10. The inverter according to any one of claims 5 to 7, wherein the interface circuit comprises a sensing and protection circuit configured to:sense at least one of current, voltage, and temperature for one more of the first lateral semiconductor transistor device, the second lateral semiconductor transistor device, and the vertical semiconductor transistor device; andmodify, in response to the sensing, one or more of the first, second, and third control signals.

11. An apparatus comprising:the inverter according to any one of the preceding claims; andat least one driver operatively connected to at least one of the first lateral semiconductor transistor device, the second lateral semiconductor transistor device, and the vertical semiconductor transistor device;wherein the at least one driver is configured to output at least one of the first control signal, the second control signal, and the third control signal.

12. An inverter comprising at least one phase, each phase comprising at least one half bridge circuit, each half bridge circuit comprising a high-side leg and a low-side leg, each of the high-side leg and the low-side leg comprising a semiconductor switch, the semiconductor switch comprising:a first branch comprising a first wide bandgap semiconductor transistor device configured to be driven by a first control signal, and a second wide bandgap semiconductor transistor device configured to be driven by a second control signal, the first wide bandgap semiconductor transistor device and thesecond wide bandgap semiconductor transistor device being connected in series; anda second branch comprising a silicon-based semiconductor transistor device configured to be driven by a third control signal;wherein the first branch and the second branch are connected in parallel; andwherein a maximum voltage rating of the silicon semiconductor transistor device is greater than a maximum voltage rating of the first and second wide bandgap semiconductor transistor devices;wherein:the first branch of the low-side leg and the first branch of the high-side leg form a first multi-level component; andthe second branch of the low-side leg and the second branch of the high-side leg form a second multi-level component;wherein the first multi-level component is configured to be dominant when a current through the inverter is below a threshold level; andwherein the second multi-level component is configured to be dominant when the current through the inverter is above the threshold level.

13. The inverter according to claim 12, wherein the maximum voltage rating of the silicon-based semiconductor transistor device is greater than the maximum voltage rating of the first and second wide bandgap semiconductor transistor devices by a factor of at least 1.5, or at least 2.14 The inverter according to claim 12 or 13, wherein at least one of the first and second wide bandgap semiconductor transistor devices comprises one or more Ill-nitride transistors, and / or one or more silicon carbide transistors.

15. The inverter according to any one of claims 12 to 13, wherein the silicon-based semiconductor transistor device comprises one or more IGBTs, one or MOSFETs, and / or one or more superjunctions.

16. The inverter according to any one of claims 12 to 15, comprising:a first control terminal configured to receive the first control signal;a second control terminal configured to receive the second control signal; andan interface circuit connected between at least one of:the first control terminal and the first wide bandgap semiconductor transistor device; andthe second control terminal and the second wide bandgap semiconductor transistor device.

17. The inverter according to claim 16, wherein the interface circuit comprises at least one of:a first auxiliary HEMT operatively connected between the first control terminal and the first wide bandgap semiconductor transistor device; anda second auxiliary HEMT operatively connected between the second control terminal and the second wide bandgap semiconductor transistor device.

18. The inverter according to any one of claims 12 to 15, comprising:a common control terminal configured to receive a common control signal; andan interface circuit connected between at least one of:the common control terminal and the first wide bandgap semiconductor transistor device;the common control terminal and the second wide bandgap semiconductor transistor device; andthe common control terminal and the silicon-based semiconductor transistor device.wherein the interface circuit is configured to generate at least one of the first control signal, the second control signal, and the third control signal.

19. The inverter according to any one of claims 12 to 18, wherein each phase comprises an output terminal connected at a mid-point of the high-side leg and the low-side leg of the half bridge circuit.

20. The inverter according to any one of claims 12 to 19 comprising three phases, each phase comprising an output, the outputs being configured to drive a three-phase motor.

21. The inverter according to any one of claims 18 to 20, wherein the interface circuit comprises a sensing and protection circuit configured to:sense at least one of current, voltage, and temperature for one more of the first lateral semiconductor transistor device, the second lateral semiconductor transistor device, and the vertical semiconductor transistor device; andmodify, in response to the sensing, one or more of the first, second, and third control signals.

22. An apparatus comprising:the inverter according to any one of claims 12 to 21; andat least one driver operatively connected to at least one of the first wide bandgap semiconductor transistor device, the second wide bandgap semiconductor transistor device, and the silicon-based semiconductor transistor device;wherein the at least one driver is configured to output at least one of the first control signal, the second control signal, and the third control signal.

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