SEMICONDUCTOR MEMORY DEVICE HAVING TWO MEMORY MATRICES PERFORMING MUTUAL TRANSMISSION AND RECEPTION OF DATA

Description

Ml 91 A / 03 O 8B MITSUBISHI DENKI KABUSHIKI KAISHA based in Chiyoda-ku, Tokyo (Japan) ***** DESCRIPTION The present invention relates to semiconductor memory devices and, more particularly, to a semiconductor memory device such as a dual-port memory comprising two types of memory arrays performing data transmission / reception between them. In accordance with the multifunctional and high performance of video equipment, high performance is also required from semiconductor memory devices to store video signals as digital data, such as video semiconductor memory devices such as video RAM (Random Access Memory). A dual-port memory is a semiconductor memory device having the ability to read and write multiple data in parallel and sequentially, used as a semiconductor memory device for video applications. Figure 6 is a block diagram schematically illustrating the entire structure of a conventional dual-port memory. The structure and operation of the conventional dual-port memory are illustrated below with reference to Figure 6. In the following description, the H level and the L level correspond to the supply potential and the ground potential respectively. With reference to figure 6, a conventional dual-port memory 1 comprises a memory matrix 2 having a plurality of memory cells MC each formed by a MOS-type transistor TR and by n capacitor C arranged in a row and column array; a sensor amplifier portion 3, a serial register 4, a serial bus line 5, a serial decoder 6, a counter 7, a serial data output terminal SDO, and a serial data input terminal SD1, all provided for writing to and reading from the memory array 2 a plurality of data in parallel; a row address buffer 11, a column address buffer 12, a row decoder 13, a column decoder 14, a data bus line 15, a parallel data output terminal PDO, and a parallel data input terminal PDI, all provided for writing to and reading from the memory array 2 a plurality of data in parallel. Row address buffer 11 buffers 8-bit address data AXO « AX7, for example, forming an external row address signal AX for supplying the same to row decoder 13. Similarly, column address buffer 12 buffers 8-bit address data AYO - AY7, for example forming the external column address signal AY for supplying the same to row decoder 14. Row decoder 3 is connected to all word lines WL included in memory array 2. Column decoder 14 is connected to all bit lines BL included in memory array 2 via data bus line 15. In memory array 2, the gates of the respective transistors TR of the memory cells MC arranged along one row are connected to the same word line WL. The wells of the respective transistors TR of the memory cells MC arranged along a column are connected to the same bit line BL. \! Row decoder 13 applies an H-level potential only to the word line WL corresponding to the row specified by the row address signals AX7 - AX7 from row address buffer 11 (hereinafter referred to as the selected word line) among all word lines WL in memory array 2. This causes transistor TR in each memory cell MC located in the row selected by the external row address signal AX to conduct, so capacitor C is electrically connected to the bit line BL corresponding to the relevant memory cell MC.The column decoder 14 electrically connects a plurality of BL bit lines corresponding to the column selected by the column address signals AYQ AY7 from the column address buffer 12 (hereinafter referred to as the selected bit line) between the BL bit lines in the memory array 2 to the parallel data output terminal PDO and the parallel data input terminal PDI via the data bus line 15. The parallel data input terminal PDI applies parallel data of a predetermined bit length as the write data from an external source at the time of data writing. The parallel data output terminal PDO provides the output of the parallel data bus line 15 to an external source as the read data at the time of data reading. By the previously described operations of the row decoder 13 and the column decoder 14, each capacitor C of the memory cell MC is connected to the selected word line WL and the selected bit line BL and is charged or discharged accordingly. to the write data supplied in parallel to the data input terminal PDI at the time of data writing. As a result, the node potential of transistor TR and capacitor C in each memory cell MC connected to the selected word line WL and the selected bit line BL obtains a potential of level Η or level L in accordance with the write data. In other words, data is simultaneously written to all memory cells MC of a row connected to the selected word line WL. At the time of data readout, the potential of the PDO parallel data output terminal is determined in accordance with the node potential of transistor TR and capacitor C of each MC memory cell connected to the selected word line WL and the selected bit line BL. In other words, the data stored in the MC memory cells connected to the selected bit line BL and the selected word line WL appears on the PDO parallel data output terminal through the corresponding bit line BL and the corresponding data bus line 15. Therefore, at the time of data readout, the data stored in the MC memory cells of a row connected to the selected word line WL are simultaneously supplied from the PDO parallel data output terminal. The preceding illustrates the operation for writing and reading data in parallel in dual-port memory. The operation for reading and writing data serially in dual-port memory will be explained later. The row address buffer 11 and the row decoder 13 operate in a manner similar to the case of writing and reading data in parallel. Therefore, the potential of only one word line WL selected by word lines WL in memory array 2 obtains a level H. Column address buffer 12 responds to external column address signals AYO - AY7 to provide 8-bit serial signals SAO - SA7, for example, to specify each of the column pluralities specified by the column address signals AYO - AY7. Then, counter 7 responds to serial address signals SAO-SA7 to provide the serial decoder 6 8-bit serial column address signals SYO - SY7, for example, to sequentially specify one by one the columns of the address specified by the external column address signal AY. When reading data, the sensor amplifier portion 3 amplifies the potential change generated on each BL bit line in the memory array 2 and simultaneously supplies it to the serial register 4. The serial register 4 temporarily stores the amplified output of the sensor amplifier portion 3 when reading data. The serial decoder 6 controls the electrical connection between the serial bus line 5 and the serial register 4 so that the line 5 is provided with only the amplified output of the potential change generated on the BL bit lines corresponding to the columns selected by the serial column address signals SYO - SY7 from the counter 7, from the amplified output temporarily stored in the serial register 4. The serial column address signals SYO - SY7 supplied by the counter 7 specify in sequence The columns in the memory matrix are temporally sorted one by one. This causes the amplified outputs of the sensor amplifier portion 3, temporarily stored in the serial register 4, to be transferred one at a time to the serial data output terminal SDO via the serial bus line 5, when the data is read. When the data is read, a potential change corresponding to the node potential between the transistor TR and the capacitor C in each memory cell MC connected to the selected word line WL and the selected bit line BL is generated at the corresponding bit line BL. Therefore, the data stored in the memory cells MC along a line connected to the selected WL word line are supplied one at a time from the SDO serial data output terminal sequentially to an external source. When reading data, a plurality of data to be written to all memory cells MC connected to a word line WL in memory array 2 is serially applied from an external source such as a voltage signal Η or L to the serial data input terminal SD1. This plurality of data is supplied to serial bus line 5 one at a time in temporal sequence. Serial decoder 6 controls the electrical connection between serial bus line 5 and the respective bit lines BL in memory array 2, so that each data supplied to serial bus line 5 is applied only to one bit line BL specified by serial column address signals SYO - SY7 from counter 7 via serial register 4 and sensor amplifier portion 3, when writing data. The signals SYO - SY7 serial column addresses supplied by counter 7 specify the columns in memory array 2 one at a time in temporal sequence. When writing data, a plurality of data applied to the serial data input terminal SDÌ from an external source is supplied to the bit line BL to which are connected MC memory cells that will store the data. Accordingly, external data is written to MC memory cells of a row connected to the selected word line. In addition to the functional components described above, the dual-port memory includes a clock generator circuit 16. The clock generator circuit 16 generates various clock signals controlling the operational timing of the previously described components such that the previously described circuit operations for reading and writing parallel data and serial data are correctly implemented, in accordance with external control signals RAS, CAS, SC, DT. For example, the circuit operation for reading and writing serial data is controlled by the internal serial clock signal SC generated by the clock generator circuit 16 in response to an external serial clock signal SC. Figure 7 shows the circuit configuration of memory array 2, sensor amplifier portion 3, serial register 4 and serial bus line 5. Referring to Figure 7, the sensor amplifier portion 3 comprises the differential amplification type sensor amplifiers 30. The number of sensor amplifiers 30 is half the numbers of BL bit lines in memory array 2. Each sense amplifier has two BL bit lines of memory array 2 connected. In memory array 2, the two BL bit lines connected to each sense amplifier 30 form a pair of bit lines obtaining complementary potentials when reading and writing data. The MC memory cells connected to one BIT bit line between the two bit lines forming a pair of bit lines, and the MC memory cells connected to the other BIT bit line are connected to different WL word lines. When reading serial data, the sense amplifier 30 amplifies the potential difference between one BIT bit line and the other BIT bit line. Figure 8 is a circuit illustrating one structure of the sensor amplifier 30. Referring to Figure 8, the sensor amplifier 30 includes a P-channel MOS transistor 310 and an N-channel MOS transistor 320 whose gates are connected to the bit line BIT; and a P-channel MOS transistor 330 and an N-channel MOS transistor 340 having their gates connected to the bit line BIT. Transistors 310 and 320 are connected in series between signal lines 350 and 360. Similarly, transistors 330 and 340 are connected in series between signal lines 350 and 360. When reading and writing serial data, power potential and ground potential are applied to signal lines 350 and 360, respectively.Therefore, when reading serial data, if the memory cell MC connected to the selected word line WL is connected to the bit line BIT, and the node potential of the transistor TR of the capacitor C in this memory cell. When MC reaches a level H, a small charge is applied from capacitor C to the BIT bit line, causing the potential of the BIT bit line to increase in accordance with this small charge. When starting to read data, the BIT bit line and the BIT bit line are equalized such that the potentials of the BIT bit line and the BIT bit line are identical. The increase in potential in the BIT bit line causes a small potential difference to be generated between the BIT bit line and the BIT bit line. The sensing amplifier 30 operates to increase this potential difference between the BIT and BIT bit lines. More specifically, the increase in potential of the bit line BIT causes transistor 320 to become slightly conductive. Consequently, there are potential drops at the gate node of transistors 330 and 340 and the d-node. In response to this potential drop, transistor 330 also becomes slightly conductive to generate a potential increase at the gate node of transistors 310 and 320 and the c-node. Transistor 320 becomes highly conductive by this potential increase to lower the gate node potentials of transistors 330 and 340 and the d-node to the ground potential applied to the signal line 360. Since transistor 330 also becomes highly conductive in response, the c-node potential increases to the supply potential applied to the signal line 350. The d-node potential of transistors 310 and 320 and the c-node potential of transistors 330 and 340 are the output of the sense amplifier 30.Therefore, the potential of the bit BIT line is brought to the supply potential by the sense amplifier 30 and applied to the serial register 4. cK 7** f LB§> ;or; The potential of the bit line ΒΪT is brought or lowered to ground potential by the sense amplifier 30 and applied to the serial register 4. Conversely, if the memory cell MC connected to the selected word line WL is connected to the bit BIT line, and the node potential of transistor TR of capacitor C of this memory cell MC reaches a level L, a small charge is supplied to that capacitor C from the bit BIT line. Therefore, the potential of the bit BIT line decreases in accordance with this small charge. This causes transistor 310 to become slightly conductive in sense amplifier 30 to raise the gate node potential of transistors 330 and 340. In response, transistor 340 also becomes slightly conductive to lower the gate node potential of transistors 310 and 320. Consequently, transistors 310 and 340 become highly conductive, whereby the C node potential is lowered to ground potential and the d node potential is raised to supply potential. Then, the small potential difference between the BIT and BIT lines is amplified to the differential voltage between the supply potential and ground potential by the sense amplifier 30. When memory cells MC connected to the selected word line WL are connected to the BIT bit lines, the potential difference between the BIT and BIT bit lines is amplified either by the transistor 330 or by the transistor 340 made conductive in each sense amplifier since there is a small rise or fall in potential in the BIT line. QNÌ Referring again to Figure 7, the serial register 4 comprises a plurality of flip-flops 40 each provided corresponding to each sensor amplifier 30. The flip-flop 40 is connected to the corresponding sensor amplifier 30 via two N-channel MOS transistors 150 and 160. The flip-flop 40 comprises two inverters 410 and 420 each having their own input and output terminals mutually connected. As shown in Figure 8, the sensor amplifier 30 comprises an output end (node ​​c) of the bit-bit BIT line side and an output end (node ​​d) of the bit-bit BIT line side. The output end of the bit BIT line side is connected to the input end of inverter 420 through transistor 150, and the output end of the bit BIT line side is connected to the input end of inverter 410 through transistor 160.The gates of transistors 150 and 160 connected to all flip-flops 40 in serial register 4 have the same trigger applied. When reading or writing serial data, this trigger signal reaches a level H to cause transistors 150 and 160 to conduct. Upon serial data reading, the outputs of the BIT line side and the BIT line side of the sensor amplifier 30 are latched at node a of the input end of the inverter 420 and output end of the inverter 410, and node b of the input end of the inverter 410 and output end of the inverter 420, respectively, in the corresponding latching circuit 40. The serial bus line 5 includes two data lines 100 and 110. The re serial register 4 and connected to serial bus line 5 through separate N-channel MOS transistors 120 and 130 for each flip-flop 40. Data line 100 is connected to the input end of inverter 420 through transistor 120. Data line 110 is connected to the input end of inverter 410 through transistor 130. The gates of transistors 120 and 130 provided corresponding to each flip-flop 40 are connected to serial decoder 6 through a common serial memory cell trigger signal line 140. Upon reading and writing serial data, serial decoder 6 sequentially supplies a Ξ-level potential to each serial memory cell trigger signal line 140.Therefore, upon serial data read, the potential latched on node a and the potential latched on node b are transferred to data lines 100 and 110 respectively for each flip-flop 40 in serial register 4. The circuit operation of this transfer will be illustrated more specifically with reference to Figure 9. Figure 9 is a circuit diagram specifically illustrating the structure of flip-flop 40. Referring to Figure 9, inverter 410 in flip-flop 40 includes a P-channel MOS transistor 410a and an N-channel MOS transistor 410b connected in series between the VC supply and GND. Similarly, inverter 420 includes a P-channel MOS transistor 420a and an N-channel MOS transistor 420b connected in series between the VC supply and GND. When serial data is read, transistors 120 and 130 are conducting when H-level potential is applied to signal line 140. Lines 100 and 110 data lines are equalized to present mutually identical potential, until an H-level potential is applied to signal line 140. Data lines 100 and 110 are unequalized when the H-level potential is applied to signal line 140. Therefore, if an H-level potential and an L-level potential are locked at nodes a and b, respectively, discharge is initiated from data line 110 to ground (GND) through transistors 130 and 420b. This reduces the potential of data line 110 from the equalized potential (the H-level). The potential of data line 110 is maintained at the potential (the H-level) by the H-level potential of node a. Therefore, there is a potential difference between data lines 100 and 110. If an L-level potential and an H-level potential are locked at nodes a and b, respectively, discharge is initiated in data line 100 to GND through transistors 120 and 410b. There is no discharge in data line 100. Therefore, the potential of data line 100 is maintained at the H-level, and the potential of data line 110 decreases from the H-level to generate a potential difference between lines 100 and 110. Therefore, when serial data is read, a potential difference exists between data lines 100 and 110 in accordance with the latched data of flip-flop 40. When serial data is read, a potential difference is sequentially generated between data lines 100 and 110 in accordance with the data temporarily stored in the respective flip-flop 40 in serial register 4. This potential difference is detected and amplified by a sensor amplifier (not shown). The detected and amplified signal of this sensor amplifier is provided by the serial data output SDO terminal in Figure 6, named Read Data. The description of the operation of the circuit in Figure 7 when serial data is read is essentially included in the previous description. Therefore, the operation of the circuit in Figure 7 when serial data is written will be explained below. When writing serial data, each data serially applied to the serial data input terminal SDÌ in Figure 6 as write data is supplied to the data lines 100 and 110 as two complementary level potentials. For example, when an H-level potential is applied to data line 100 and an L-level potential is applied to data line 110, the potentials of nodes a and b reach an H-level and an L-level through the potentials of data lines 100 and 110, respectively, in the flip-flop 40 corresponding to the conductive ones of transistors 120, 130. In other words, one of the write data serially applied to the serial data input terminal SD1 is latched into a flip-flop 40. The latched potentials at nodes a and b in this flip-flop 40 are applied to the sensor amplifier 30 provided corresponding to this flip-flop 40 through transistors 150 and 160, respectively. Since the sensor amplifier operates as a latching circuit, the two potentials temporarily stored in the corresponding flip-flop 40 are ap16 ,ΟK_; applied to BIT and BIT bit lines respectively without level variation. Consequently, the H level potential and the L level potential latched at nodes a and b respectively, in flip-flop 40 corresponding to the conducting transistors 120 and 130 are supplied to BIT and BIT bit lines connected to the sense amplifier 30 provided corresponding to this flip-flop 40. If memory cells MC connected to the selected word line WL are connected to the BIT bit lines at this point, the capacitor C of one of these MC memory cells is charged by the H level potential supplied to this BIT bit line. This causes an H level to be written to the node of transistor TK and capacitor C in this MC memory cell.Similarly, if MC memory cells connected to the selected word line WL are connected to the bit lines BIT, the capacitor C of one of these MC memory cells is discharged by the potential of a level L supplied to the BIT line. This causes the level L to be written to the node of the transistor TR and the capacitor C of this MC memory cell. Conversely, if an L-level potential and an H-level potential are supplied to data lines 100 and 110, respectively, an L-level potential and an H-level potential are latched at nodes a and b, respectively, in flip-flop 40 corresponding to the conductive ones of transistors 120, 130. In this case, if MC memory cells connected to the selected WL word line are connected to BIT bit lines, an L-level is written to one of these MC memory cells. Similarly, if MC memory cells connected to the selected WL word line are connected to BIT lines, an H-level is written to one of these MC memory cells. When serial data is written, an H-level potential is applied to all serial memory cell activation signal lines 140, as is the case when serial data is read. During the time that data to be written to the memory cell MC connected to the selected word line WL and the BIT or arbitrary bit line BΪT is applied to data lines 100 and 110, an H-level potential is applied to the serial memory cell activation signal line 140 connected to the gates of transistors 120 and 130 provided correspondingly to the sense amplifiers 30 connected to the BIT or arbitrary bit line BIT. Therefore, when serial data is read, each of the plurality of write data serially applied to the serial data input terminal SD1 is written to one of the memory cells MC along a line connected to the selected word line WL.As a result, a plurality of data is written to the MC memory cells of a row connected to the selected WL word line. Therefore, at the time of serial data writing, the write data temporarily stored in each flipflop 40 in the serial register 4 is transferred to the memory array 2 through large if icg.sensors 30. At the time of serial data reading, the data read from the MC memory cells of a row in the memory array 2 is transferred to all the flipflops 40 in the shift register 4. In other words, each flipflop 40 in the serial register 4 functions as a memory cell storing the stored data of an MC memory cell. in memory array 2. Therefore, serial register 4 functions as a memory array having a plurality of memory cells arranged only in the row direction. The number of memory cells is identical to the number of memory cells MC of a row in memory array 2. In the following description, serial register 4 and flip-flop 40 are referred to as serial memory array and serial memory cell, respectively. The timing of the potential change in the signal lines and nodes at the time of data transfer from memory array 2 to serial memory array 4 will be illustrated later with reference to Figure 10. Figure 10 is a timing diagram to explain the operation of the dual port memory for transferring data from memory array 2 to serial memory array 4. Data reading from the serial memory array 2 is conducted during the time period when the external control signal RAS (Fig. 10(a)) is at an L level. More specifically, an H level potential is applied to the selected word line WL as shown in Fig. 10(b), after the external control signal RAS drops out. in the memory array 2. Then, a supply potential and a ground potential are applied to signal lines 350 and 360, as shown in Fig. 10(c) and 10(d), respectively, in the sense amplifier 30. This causes all the sense amplifiers 30 in the sense amplifier portion 3 to be turned on. Each potential of the BIT (or BIT) lines of bits connected to cells of MC memory cells connected to the selected word line WL ^increases or decreases slightly in accordance with the data stored in the MC memory cell connected to them as shown in Figure 10(e). This slight change in potential is amplified by the sensing amplifier 30 which is activated. In other words, the potential of the bit line BIT (or BIT), rising slightly in response to the increase in potential of the selected word line WL, rises to ground potential in response to the increase in potential of the signal line 350, as shown in curve 1 of Figure 10(e). Conversely, the potential of the bit line BIT (or BIT), decreasing in response to the increase in potential of the selected word line WL, falls to ground potential in response to the drop in potential of the signal line 360, as shown in curve 2 of Figure 10(e). The potential of the bit BIT (or BIT) line, which is the pair of the above-mentioned bit BIT (ο ΒΪΤ ) lines having a small increase in potential, is brought to ground potential in response to activation of the sensor amplifier 30. The potential of the bit BIT (or BIT) line, which is the pair of bit BIT (p BIT) lines where the potential decreases slightly, is brought to the supply potential in response to activation of the sensor amplifier. The trigger signal applied to the gates of transistors 150 and 160 (hereinafter referred to as the data transfer signal) is at a level H for a constant, short period of time, as shown in FIG. 10(f). In other words, transistors 150 and 160 conduct only during this period of time, so each output of all sense amplifiers 30 in sense amplifier portion 3 is fed to the corresponding serial memory cell 40. Therefore, stored data of each serial memory cell 40 in serial memory array 4 is switched to new data applied by sense amplifier 30 during the period of time that the data transfer signal is at a level O as shown in FIG. 10(g). When writing of the output of sense amplifier 30 to the corresponding serial memory cell 40 is completed, the potential of the selected word line WL reaches a level L.In response, the two BIT and BIT bit lines forming a bit line pair are equalized, so that the potentials of all BIT, BIT bit lines return to a potential intermediate between the power potential and the ground potential. At the same time, the potentials of the signal lines 350 and 360 of Figure 8 reach the ground potential and the power potential, respectively, to deactivate the sensor amplifier 30. The timing of the potential change in the signal lines and nodes at the time of data transfer from serial memory array 4 to memory array 2 will be illustrated later with reference to figure 11. Figure 11 is a timing diagram to explain the operation of the dual port memory to transfer data from serial memory array 4 to memory array 2* The data transfer from the serial memory array 4 to the memory array 2 is also conducted during the time period in which the The external control signal RAS (Figure 11(a)) is at a level L. The data transfer signal is at a level H for a short, constant period of time after the external control signal ES§ has dropped, as shown in Figure 11(f). The write data stored in each serial memory cell 40 is applied to the corresponding sensor amplifier 30 during this period of time. The sensing amplifier 30 is activated upon increasing the data transfer signal. More specifically, the signal lines 350 and 360 of FIG. 8 are energized with the supply potential and ground potential as shown in FIGS. 11(c) and 11(d), respectively. The write data applied to the sensing amplifier 30 from the serial memory cell 40 is latched in the sensing amplifier 30. The potentials of the two lines BIT and BIT forming each pair of bit lines vary complementarily in accordance with the data latched at the sensing amplifier 30 connected as shown in FIG. 11(e).In other words, one potential between the two bit lines BIT and BIT forming a pair of bit lines (curve of Figure 11(e)) goes to the supply potential in response to increasing the potential of the signal line 350 and the other potential about 2 of Figure 11(e)) goes to the ground potential in response to decreasing the potential of the signal line 360. An H-level potential is supplied to the selected word line WL, as shown in Figure 11(b). Consequently, each of the MC memory cells of a row connected to the selected word line WL has data written to it in accordance with the potential of the BIT line or Corresponding bit BIT. When data writing to memory array 2 is complete, the potential of the selected word line WL returns to the L level. In response, the two lines BIT and BIT bit forming a bit line pair are equalized, so that the potentials of all lines BIT and BIT return to the aforementioned intermediate potential. At the same time, the potentials of the signal lines 350 and 360 of Figure 8 return to ground potential and power potential, respectively, to deactivate the sensing amplifier 30. The timing of the potential change in the signal lines and nodes at the time of data transfer from data bus line 5 to serial memory array 4 will be explained later with reference to Figure 12. Figure 12 is a timing diagram to explain the operation of the dual port memory for transferring data from data bus line 5 to serial memory array 4. When transferring data from data bus line 5 to serial memory array 4, an H-level potential is applied by serial decoder 6 to one of the serial memory cell activation signal lines 140 for a short constant time period as shown in FIG. 12(b). During this short time period, data lines 100 and 110 are electrically connected to nodes a and b in serial memory cell 40 provided correspondingly to transistors 120 and 130 having their gates connected to the aforementioned signal line 140. Consequently, the potentials of nodes a and b reach potentials corresponding to the data applied to data lines 100 and 110 (FIG. 12(a)). In other words, data stored in serial memory cell 40 is switched to new data from data bus line 5 during ±1 of the aforementioned short time period as shown in FIG. 12(c). The timing of the potential change in the signal lines and nodes at the time of data transfer from the serial memory array 4 to the serial bus line 5 will be explained later with reference to Figure 13. Figure 13 is a timing diagram to explain the operation of the dual port memory for transferring data from the serial memory array 4 to the data bus line 5. An H-level potential is applied to one of the serial memory cell activation signal lines 140 for a short, constant time period, also corresponding to the time of data transfer from the serial memory array 4 as shown in FIG. 13(b). The data lines 100 and 110 are equalized as long as an H-level potential is applied to any one signal line 140. Therefore, the potentials of the data lines 100 and 110 are both at an H-level, as long as the potential of said signal line 140 is applied, as shown in FIG. 13(a). As the potential of the signal line 140 increases, the data lines 100 and 110 are unequalized.Therefore, in response to data stored in the serial memory cell 40 provided correspondingly with transistors 120 and 130 having their gates connected to the signal line 140 (Figure 13(c)), one potential (curve 2) of either data line 100 and 110 decreases from the H level and the other potential (curve 1) is maintained at the H level. The potential variation of data lines 100 and 110 and of the nodes a and b in the serial memory cell 40 generated when data is transferred between data lines 100 and 110 and the serial memory cell 40 and the potential change of nodes a and b in the serial memory cell 40 generated when data is transferred between the serial memory cell 40 and the sensor amplifier 30 will be explained in more detail with reference to FIG. 14. Figure 14 is a circuit diagram illustrating the structure of the circuit portions provided corresponding to an arbitrary pair of bit lines for reading and writing serial data. The sensor amplifier 30 and the serial memory cell 40 in Figure 14 are represented by the circuit diagrams of Figures 8 and 9, respectively. It will be assumed that an H-level potential and an L-level potential are latched at nodes a and b, respectively, in serial memory cell 40 of FIG. 14 just before data is transferred from data lines 100 and 110 to serial memory cell 40. In this case, the following phenomenon is generated when transistors 120 and 130 become conductive when an L-level potential and an H-level potential are applied to data lines 100 and 110, respectively, as data is written. Since transistors 410a and 410b are conducting just before transistors 120 and 130 start conducting, current flowing from data line 110 to ground GND through transistors 420b and current flowing from power supply VC to data line 100 through transistor 410a are started just after transistors 120 and 130 start conducting. This causes the potential of data line 110 to decrease from the level— the H, and that the potential of the data line 100 is to rise from the L level. It should be noted that the current capacity of the data line 110 and the sizes of the transistors 420a and 420b are set in advance so that the magnitude of the current applied from the H level data line 110 to the L level node b is sufficiently greater than the current flowing from the ground node b to GND through the conducting transistor 420a, and that the magnitude of the current applied from the H level node b to the L level data line 110 is sufficiently greater than the current flowing from the power supply VC to the node b through the conducting transistor 420a.Furthermore, the current capacity of data line 100 and the sizes of transistors 410a and 410b are set in advance such that the magnitude of the current applied from the H-level data line 100 to the L-level node is sufficiently greater than the current flowing from node a to ground GND through the conducting transistor 410b, and the magnitude of the current supplied from the H-level node a to the L-level data line 100 is sufficiently greater than the current flowing from the VC power supply to node a through the conducting transistor 410a. Therefore, although the potential of data line 110 decreases slightly from the H level just after transistors 120 and 130 become conductive, the potential of data line 110 returns to the H level because the potential of node b immediately reaches an H level through the current supplied by data line 100. Similarly, the potential of data line 100 increases slightly from the L level just after transistors 120 and 130 become conductive, and returns to then at level L because the potential of node a immediately reaches level L through the current drawn by node a on data line 110. A similar phenomenon occurs when an L-level potential and an H-level potential are locked at nodes a and b, respectively, just before transistors 120 and 130 conduct, and when the potentials of data lines 100 and 110 reach the H- and L-levels, respectively. More specifically, just after transistors 120 and 130 conduct, the potential of data line 110 decreases slightly due to current flowing from data line 100 to GND through transistors 120 and 410b, and the potential of data line 110 increases slightly due to current flowing from power supply VC to data line 110 through transistors 420a and 130. Then, the potential of data line 110 returns to the H level, due to the potential of node a reaching the H level via the current applied from data line 100 to node a. Simultaneously, the potential of data line 110 returns to the L level due to the potential of node b reaching the L level via the current drawn from node b to data line 110. When writing serial data, if the potential levels of data lines 100 and 110 differ from those already latched into nodes a and b (i.e., the writing data externally applied to data lines 100 and 110 differ from the data already stored in serial memory cells 40), the potential (curve 1) of data line 100 or 110 will be data found at the H level decreases slightly in response to increasing the potential of the signal line 140 and the potential (curve 2) of the data line level L increases slightly in response to increasing the potential of the signal line 140. The transfer of data from serial memory cell 40 to data lines 100 and 110 will now be illustrated. If H-level and L-level potentials are locked early at nodes a and b in Figure 14, for example, current flows from data line 110 to node b through transistor 130 during the time that transistors 120 and 130 are conducting. Therefore, the potential of node b is maintained at an a level slightly above an L level during this time. This current causes the potential of data line 110 to decrease, thereby establishing a potential difference between data lines 100 and 110. When transistors 120 and 130 return to the non-conducting state, the current path is interrupted, so the potential difference between data lines 100 and 110 is maintained. The potential of node b returns to the L level due to the current flowing from node b to GND through transistor 420b. Conversely, if an L-level potential is clamped at node a, the potential at node a is maintained at a level slightly above the L-level, due to the current flowing from data line 100 to node a through transistor 120 during the conduction time of transistors 120 and 130. The potential at data line 110 gradually decreases. Therefore, when transistors 120 and 130 return in the non-conducting state, the potential of node a returns to the L level due to the current flowing to transistor 410b, and the potential of data line 100 is maintained at the decreased potential. Thus, at the time of data transfer from serial memory cell 40 to data lines 100 and 110, the potential of node a or b having a temporarily locked L-level potential increases during the time period in which signal line 140 is at an H-level potential as shown in curve 1 of Figure 13(c). The transfer of data from the serial memory cell 40 to the corresponding sensor amplifier 30 will be explained later. In Figure 14, the following phenomenon will occur just after transistors 150 and 160 conduct, when an H-level potential and an L-level potential are locked at nodes a and b, respectively, e.g., just prior to data transfer from serial memory cell 40 to sense amplifier 30. The sensing amplifier 30 is activated after the data transfer signal increases as shown in FIG. 11. This means that the signal lines 350 and 360 reach ground potential and power potential just after transistors 150 and 160 conduct. Therefore, just after transistors 150 and 160 conduct, transistors 330 and 320 temporarily conduct in the sensing amplifier 30. Consequently, current flows from node a to signal line 350 through transistors 150 and 330, and current flows from signal line 360 ​​to node b through transistors 320 and 160. This causes the potential of node a to decrease slightly and the potential of ' node b to increase slightly. It should be noted that the sensor amplifier 30 is activated during the period of time in which the data transfer signal reaches a level H. Therefore, the current flowing from node a to the lower potential side and the current flowing from the higher potential side to node b are interrupted just after the potentials of nodes a and b begin to decrease or increase, respectively. Consequently, the potentials of nodes a and b return to the H and L levels, respectively. Conversely, if an L-level potential and an H-level potential are locked at nodes a and b, respectively, just before data is transferred from the serial memory cell 40 to the sensor amplifier 30, a phenomenon opposite to the phenomenon that was previously described occurs. More specifically, just after transistors 150 and 160 conduct, the potential of node a temporarily increases slightly due to current flowing from signal line 360 ​​to node a through transistors 340 and 150, and the potential of node b temporarily decreases slightly due to current flowing from node b to signal lines 350 through transistors 160 and 310. Therefore, at the time of data transfer from the serial memory cell 40 to the corresponding sensor amplifier 30, the potential (curve 2) of the node a or b having a locked H level temporarily decreases just after the increase of the data transfer signal and the potential (curve 1) of the other node slightly temporarily increases just after the increase of the data transfer signal as shown in Fig. 11(g). The value in parentheses in Figure 14 is the ratio of each channel width W of the transistors forming the serial memory cell 40 and the transistors forming the sense amplifier 30 to the channel width of other transistors. The channel width ratio W set in Figure 14 is only an example of the channel width setting of the transistors forming the sense amplifier and the serial memory cell 40 in a conventional dual-port memory. As described above, in a conventional semiconductor memory device having serial data read / write function, data is transferred between two types of memory arrays and between one of these two memory arrays and a data input / output bus line. The following problems were encountered in a similar conventional semiconductor memory device. To improve the serial data read speed in the dual port memory of FIG. 6, the data transfer speed from Hall1-ατη~ sensor amplifier 30 to the corresponding serial memory cell 40 and the data transfer speed from serial memory cell 40 to the data lines 100 and 110 of FIG. 7 must be improved. In the case of data transfer from the sensor amplifier 30 to the serial memory cell 40, the potentials of the nodes c and d obtain complementary logic levels corresponding to the data read from the memory cell MC in the memory array 2 at the BIT or BIT bit line. The po31 The potentials of nodes a and b are maintained at the potentials applied by data lines 100 and 110 or by the sensor amplifier 30. Therefore, the potentials of nodes a and b may differ from those of nodes c and d, respectively. The case will be considered next where transistors 150 and 160 conduct when an H-level potential and an L-level potential are locked at nodes a and b, respectively, and when the potentials of nodes c and d are at the L- and H-levels, respectively. When transistors 150 and 160 conduct, node a has current drawn from transistors 340 to the signal line 360 ​​which is at the supply potential and current applied from the VC supply through transistor 410a. Simultaneously, node b has current supplied from the signal line 350 which is at the supply potential through transistor 310 and current drawn from transistor 420b to ground GND. Therefore, the potentials of nodes a and b will immediately fall and rise, respectively, but will not be equal to the potential level of nodes c and d. The potentials of nodes a and b are applied to the gate node of transistors 420a and 420b, and to the gate node of transistors 410a and 410b, so that transistors 410a and 410b will become non-conducting and subsequently conducting, respectively, in response to the increase in potential of node b.Transistors 420a and 420b will become conducting and non-conducting, respectively, successively in response to the drop in potential at node a. Thus, the potentials at nodes a and b eventually stabilize at the H level and L level, respectively. Therefore, in order to speed up the data transfer from the sensor amplifier 30 to the serial memory cell 40, the current flowing to node a from the power supply VC through transistor 410a and the current flowing from node b to ground GND through transistor 420b will be reduced to achieve a faster potential drop at node a and a faster potential rise at node b. The case will be considered where transistors 150 and 160 conduct when an L-level potential and an H-level potential are locked at nodes a and b, and when nodes c and d are at the H-level and the L-level respectively. When transistors 150 and 160 conduct, the current flowing to GND from node a through transistor 410b prevents the potential of node a from being immediately raised to an H level, and the current flowing to node b from the VC supply through transistor 420a prevents the potential of node b from being immediately raised to the L level. To transfer data from the sense amplifier 30 to the serial memory cell 40 at high speed, therefore, the current flowing from node a to GND through transistor 410a and the current flowing from the VC supply to node b through transistor 420a will need to be reduced to improve the rate of rise of the potential of node a by the current supplied to node a by the signal line 350 and to improve the rate of fall of the potential of node b by the current flowing from node b to the signal line 360. It can be understood from the above, that the current flowing between the source and drain of each of the transistors 410a, 410b, 420a, 420b at the time of conduction will have to be reduced to improve the data transfer rate from the sensor amplifier 30 to the serial memory cell 40. To this end, the dimensions, such as the channel width W of each of the transistors 410a, 410b, 420a, and 420b, must be reduced. The intensity of the current flowing between the source and drain of a switched-on MOS transistor increases in accordance with the channel width W of the MOS transistor. The driving capacitance of a MOS transistor is the amount of current that can flow between its source and drain. Figure 15 is a cross-sectional view and a plan view of a MOS transistor. Figures 15(a) and (b) show related MOS transistors having a short channel length and a long channel length, respectively. Referring to Figure 15, the MOS transistor comprises a conducting layer (dashed in the drawing) as a gate G with a constant width L on a semiconductor substrate 500 and two impurity diffusion layers (dashed in the drawings) at right angles to the conducting layer, as the source S and the drain D. The channel of the MOS transistor is formed in the conducting layer sandwiched between two impurity diffusion layers. The channel current flows through this portion. The channel length of the MOS transistor corresponds to the width of the conducting layer, i.e., the gate width L. The channel width of the MOS transistor corresponds to the width of the diffusion layer. 5,( Ji of impurities, i.e. the width W of the source / sink. The cross-sectional area in the direction (indicated by a dashed catenary line B in the figure) at right angles to the channel current flow of the channel region (enclosed in the bold Ί-line in the figure) increases in accordance with the increase in channel width W. Therefore, if the voltage between the source and the drain is constant, the intensity of the current flowing between the source and the drain is proportional to the channel width W. It can be seen by comparing Figures 15(a) and (b), that the resistance in the direction parallel to the channel current flow in the channel region increases in accordance with the length L of the channel. Therefore, if the voltage between the gate and the source is constant, the intensity of the current flowing through the source and the drain is inversely proportional to the length L of the channel. Figure 16 is a graph illustrating the relationship between a current IqS through the source and the gate and a voltage Vgg across the gate and the source of two MOS transistors having different channel lengths L (i.e., different gate widths). Curves 1 and 2 show an N-channel MOS transistor having a small gate width L and an N-channel MOS transistor having a large gate length L, respectively. It can be seen from Figure 16 that a transistor with a smaller gate width L has a larger change in the current Ipg flowing between the source and the drain when the gate potential is increased while the source is connected to ground in an N-channel MOS transistor. Comparing35 )§' two arbitrary MOS transistors having the same source-to-gate voltage, the current between the source and the drain of a MOS transistor with a small gate width L is greater than that of a MOS transistor with a large gate width L. This means that the driving capacitance of the MOS transistor is adjustable by varying the gate width L. When comparing two MOS transistors with different G-gate thicknesses T, the electric field generated in the channel region of the transistor with a thin G-gate thickness T is greater than that of the transistor with a large G-gate thickness T, if the voltage VGS applied between the gate and the source is identical. This means that the current between the source and the drain increases when the G-gate thickness T is smaller. The driving capacitance of a MOS transistor can also be adjusted by varying the G-gate thickness T. If the data operating speed of the transistors from the sensor amplifier 30 to the serial memory cell 40 is improved in accordance with the reduction in the driving capacitance of the transistors 410a, 410b, 420a and 420b, then the data transfer from the serial memory array to the serial bus line 5 cannot be implemented in an appropriate manner. The case is considered where transistors 120 and 130 conduct when an H-level potential and an L-level potential are locked at nodes a and b, respectively. When transistors 120 and 130 conduct, the potential of data line 110 begins to drop due to current flowing from the 1-in^n H0 data line to GND through transistors 130 and 420b. Consequently, the potential difference generated between data lines 100 and 110 is amplified by a sensing amplifier as data is read. To read data temporarily stored in the serial memory cell 40 to data lines 100 and 110 at high speed, the current flowing from data line 110 to GND through transistors 130 and 420b must be increased to increase the rate of potential drop of data line 100. In other words, the current flowing through the 420b transistor will need to be increased. In the case where transistors 120 and 130 conduct when an L-level potential and an H-level potential are locked at nodes a and b, respectively, the potential of data line 100 begins to decrease due to the current flowing from data line 110 to GND through transistors 120 and 130b, opposite to the previously described case. Therefore, the rate of potential decrease of data line 110 must be improved by increasing the current flowing to GND through transistor 410b in order to transfer data at high speed from the serial memory cell to data lines 100 and 110. It can be understood from the foregoing that the dimensions, e.g. the channel width W of the N-channel transistors 410b and 420b in the serial memory cell 40 will need to be increased to improve the data transfer rate from the serial memory cell 40 to the serial bus line 5. However, if the 410b and 420b transistors are designed with small dimensions in order to accelerate the transfer of data from the sensor amplifier 30 to the serial memory cell 40, the rate of potential drop of the data line 100 or 110 becomes slower because the current flowing through the transistors 410b and 420b is small at the time of data transfer from the serial memory cell 40 to the data lines 100 and 110. As a result, the rate of data transfer from the serial memory cell 40 to the data lines 100 and 110 is decreased, and the data cannot be read properly due to the fact that the potential difference between the data lines 100 and 110 is small. If the sizes of transistors 410b and 420b are seeded to facilitate data transfer from serial memory cell 40 to serial bus line 5, then the transfer rate from sense amplifier 30 to serial memory cell 40 is decreased and data transfer from data lines 100 and 101 to serial memory cell 40 can be performed properly. In Figure 14, if transistors 120 and 130 conduct when the potentials of data lines 100 and 110 are at an L level and an H level, respectively, by writing data and the potentials of nodes a and b are at an H level and an L level by previously latched data at serial memory cell 40, current flows from data line 110 to GND through transistors 130 and 420b, and current flows from power supply VC to data line 100 through transistors 410a and 120. Therefore, current flowing from power supply VC to node a through transistor 410a prevents the potential of node a from decreasing to the L level. Similarly, current flowing from node b to GND through transistor 420b prevents the potential of node b from increasing to the H level.Therefore, in order to facilitate data transfer from data lines 100 and 110 to serial memory cell 40, the current flowing from power supply VC to node a through transistor 410a and the current flowing from node b to ground GND through transistor 420b must be minimized. In other words, the dimensions, such as the channel width W, of transistors 410a and 420b must be as small as possible. In the case where transistors 120 and 130 conduct when the potentials of data lines 100 and 110 are at the H and L levels, respectively, and the potentials of nodes a and b are at the L and H levels, respectively, the current flowing from node a to GND through transistor 410b prevents the potential of node a from rising to the H level by the potential of data line 100, and the current flowing from the VC power supply to node b through transistor 420a prevents the potential of node b from falling to the L level by the potential of data line 110. In order to facilitate the transfer of data from data lines 100 and 110 to the serial memory cell 40, therefore, the current flowing from node a to GND through transistor 410b and the current flowing from the VC power supply to the node through transistor 420a must be as small as possible.In other words, the dimensions, e.g. the channel width W of transistors 410a and 420b, must be as small as possible. It can be understood from the above that the dimensions, for example The channel width W of transistors 410a, 410b, 420a, and 420b forming serial memory cell 40 must be reduced in order to facilitate data transfer from data lines 100 and 110 to serial memory cell 40. Such a size setting is opposite to facilitating data transfer from serial memory cell 40 to data lines 100 and 110. If the transistor sizes in serial memory cell 40 are set to facilitate data transfer from serial memory cell 40 to serial bus line 5, data transfer from serial bus line 5 to memory cell 40 may not be implemented properly.This creates the problem that the data transfer rate from serial bus line 5 to serial memory cell 40 decreases, and that the potentials of nodes a and b will not reach the potential levels of data lines 100 and 110, respectively, so that data will not be transferred from serial bus line 5 to serial memory cell 40. Therefore, data transfer from the sensor amplifier 30 to the corresponding serial memory cell 40 and data transfer from the serial memory cell 40 to the serial bus line 5 cannot be easily realized for serial data reading. Furthermore, data transfer from the serial bus line 5 to the serial memory cell 40 for serial data writing and data transfer from the serial memory cell 40 to the serial bus line 5 for serial data reading cannot be easily realized together. In a conventional semiconductor memory device comprising the serial data reading / writing function, therefore, it was difficult to mi- improve serial data reading speed and both serial data reading / writing speed. In a conventional semiconductor memory device, two data lines (data lines 100 and 110 in Figure 14) are used for data input from an external source and data output to an external source. This will increase the footprint of the serial bus line 5 on the dual-port memory chip 1 in Figure 6, for example, thus reducing the area allocated for other functional components in chip 1. Therefore, increasing the memory capacity of semiconductor memory devices is hampered. An object of the present invention is to provide a semiconductor memory device enabling improvement in serial data read speed. Another object of the present invention is to provide a semiconductor memory device enabling the m-1 gl-ί n-rnm^nt-n in serial data writing speed. A further object of the present invention is to provide a semiconductor memory device having both serial data writing speed and improved serial data reading speed. A still further object of the present invention is to provide a dual port memory in which both data transfer from a sensor amplifier to a serial memory cell and data transfer from a serial memory cell to a serial bus line are conveniently conducted. Still another object of the present invention is to provide a dual port memory in which both serial bus transfer to a serial memory cell and data from a serial memory cell to a bus can be transferred with ease. An additional object of the present invention is to provide a dual port memory in which data transfer between a serial bus line and a serial memory cell and data transfer from a sense amplifier to a serial memory cell are both readily implemented. Another object of the present invention is to provide a semiconductor memory device in which the area occupied on a semiconductor substrate by data lines provided for applying data to and from an external source is small. To achieve the foregoing objects, according to one aspect of the present invention, a semiconductor memory device includes a first memory array comprising a plurality of first memory cells arranged in a plurality of columns, a second memory array for temporarily storing a data signal stored in the first memory array and a write data signal to be written to the first memory array, a read circuit for reading a data signal from the first memory cell, a limiter circuit, a data bus for supplying the data signal stored by the first memory array to an external source and for receiving the write data signal from an external source. The second memory array includes a plurality of second memory cells provided correspondingly. corresponding to the plurality of columns of the first memory matrix. Each of the second memory cells includes a complementary first and second storage node, and a bidirectional inverter circuit interconnecting the first and second storage nodes. The limiter circuit limits the current flowing through the inverter circuit in one direction to be less than that flowing through the inverter circuit in the opposite direction. The semiconductor device further includes an amplifier circuit for detecting and amplifying data signals read by the readout circuits and data signals temporarily stored in the second memory cells, a first connecting circuit, a second connecting circuit, and a third connecting circuit. The first connecting circuit electrically connects the amplifier circuit and the first storage node when reading and writing data. The second connecting circuit electrically connects the second storage node to the data bus, after the first storage node and the amplifier circuit have been connected to the err-rf ran, when reading data.The third connecting circuit electrically connects the data bus to the first storage node, before the first storage node and the amplifier circuit have been connected via the first connecting circuit, at the time of writing the data. In a semiconductor memory device having the structure presently described according to the present invention, a data read signal from a first memory cell of an arbitrary column is amplified by an amplifier circuit and is then applied to the first storage node of the second memory cell corresponding to that column. At this point, if the current flowing from the first storage node to the inverter circuit is 1-Invitara at a small value, the potential of the first storage node increases rapidly due to the current flowing from the amplifier circuit to the first storage node. If the current flowing from the inverter circuit to the first storage node is limited to a small value, the potential of the first storage node decreases rapidly due to the current flowing from the first storage node to the amplifier circuit. Therefore, the potential of the first storage node quickly becomes a potential corresponding to the read data signal if the current flowing between the first storage node and the inverter circuit is limited to a small value. Subsequently, by operating the inverter circuit, complementary voltage signals corresponding to the read data signal are temporarily stored in the first and second storage nodes. Then, the data signal temporarily stored in the first storage node is transferred to the data bus through the inverter circuit as the read or read data of the first memory cell. At this point, if the current flowing from the inverter circuit to the second storage node is large, the data bus potential increases rapidly. If the current flowing from the second storage node to the inverter circuit is large, the data bus potential decreases rapidly. Therefore, the data bus potential varies rapidly and in accordance with the potential of the first storage node when the current flowing between the second storage node and the inverter circuit is large. Conversely, when data is written, the write data signal supplied to the data bus is applied to the first storage node of the second memory cell. At this point, if the current flowing from the inverter circuit to the first storage node is limited to a small value, then the potential of the first storage node decreases rapidly in accordance with the current flowing from the first storage node to the data bus. If the current flowing from the first storage node to the inverter circuit is limited to a small value, the potential of the first storage node increases rapidly in accordance with the current flowing from the data bus to the first storage node.Therefore, the potential of the first storage node quickly reaches a potential corresponding to the write data signal when the current flowing between the first storage node and the inverter circuit is limited to a small value. Subsequently, by operating the inverter circuit, complementary voltage signals corresponding to the write data signal are temporarily stored in the first and second storage nodes. Then, the data signal temporarily stored in the first storage node is amplified by the amplifier circuit to be written to the first memory cell. According to another aspect of the invention, a semiconductor memory device according to the present invention includes a first memory array comprising a plurality of first memory cells arranged in a plurality of columns, a second memory array temporarily storing a data signal stored in the first memory array and a write data signal for writing to the first memory array, a read circuit for reading a data signal from the first memory cell, and a data bus for providing the data signal stored by the first memory array to an external source and for receiving the write data signal from an external source. The second memory array includes a plurality of second memory cells provided corresponding to the plurality of columns of the first memory array.Each of the second memory cells includes a , ✓ first node, a second node, a first inverter circuit for inverting the potential of the first node and supplying the same to the second node, and a second inverter circuit for inverting the potential of the second node and supplying the same to the first node. The driving capacitance of the first inverter circuit is greater than that of the second inverter circuit. The semiconductor memory device further includes an amplifier circuit for detecting and amplifying data signals read by the read circuits and data signals temporarily stored in the second memory cells, a first connecting circuit, a second connecting circuit, and a third connecting circuit. The first connecting circuit electrically connects the amplifier circuit and the first node when reading and writing data. you. The second connection circuit electrically connects the second node to the data bus after the first node and the amplifier circuit have been electrically connected when reading data. The third connection circuit electrically connects the data bus to the first node before the first node and the amplifier circuit are connected via the first connection circuit when writing data. In a semiconductor memory device having the structure described above according to the present invention, a read data signal from a first memory cell of an arbitrary column is amplified by an amplifier circuit and then applied to the first node of the second memory cell corresponding to that column. Since the driving capacitance of the second inverter circuit is low, the potential of the first node is not affected by the output of the second inverter circuit and quickly becomes a potential corresponding to the read data signal. By inverting the first and second inverter circuits, complementary voltage signals corresponding to the read data signal are temporarily stored in the first and second nodes.Then, the data signal temporarily stored in the first node is transferred to the data bus via the first inverter circuit, as is the data read from the first memory cell. The driving capacitance of the first inverter circuit is high, so the data bus potential varies rapidly in accordance with the potential of the second node. At the time of. To write data, the write data signal supplied to the data bus is applied to the first node of the second memory cell. The driving capacitance of the second inverter circuit is low, so the potential of the first node is not affected by the output of the second inverter circuit and quickly becomes a potential corresponding to the write data signal. Then, complementary voltage signals corresponding to the write data signals are temporarily stored in the first and second nodes by inverting the first and second inverter circuits. Then, the data signal temporarily stored in the first node is amplified by the amplifier circuit and written to the first memory cell. According to a preferred embodiment, the first inverter circuit in each second memory cell includes first and second field-effect semiconductor elements of complementary polarity connected in series between a high-potential power supply and a low-potential power supply. The second inverter circuit includes third and fourth field-effect semiconductor elements connected in series between the high-potential and low-potential power supplies, and having polarity identical to that of the first and second field-effect semiconductor elements, respectively. The dimensions of the first field-effect semiconductor element are larger than those of the third field-effect semiconductor element. The dimensions of the second field-effect semiconductor element are larger than those of the fourth field-effect semiconductor element. According to another preferred embodiment, each of the second memory cell comprises a first inverter circuit having a plurality of inverters connected in parallel between the first storage node and the second storage node, and a second inverter circuit having a single inverter connected between the first and second storage nodes in antiparallel to the plurality of inverters. The first memory array further includes first and second bit lines corresponding to each of a plurality of columns. Each data signal stored in the plurality of first memory cells is read by the readout circuit at the first and second bit lines corresponding to the column in which they are arranged. The amplifier circuit includes a sense amplifier provided corresponding to each of the plurality of columns.Each sensor amplifier includes a fifth and sixth field-effect semiconductor element of complementary polarity provided between the corresponding first bit line and the first signal line and between the corresponding first bit line and the second signal line, respectively, and having their conducting state controlled in accordance with the potential of the second bit line; and a seventh and eighth field-effect semiconductor element of complementary polarity provided between the corresponding second bit line and the first signal line and between the corresponding second bit line and the second signal line, respectively, and having their conducting state controlled in accordance with the potential of the first bit line. The polarity of the seventh field-effect semiconductor element is identical to that of the fifth semiconductor element. Field-effect semiconductor. The polarity of the eighth field-effect semiconductor element is identical to that of the sixth field-effect semiconductor element. When writing data, a first and second signal line have applied high and low potentials, respectively, after the first node and the amplifier circuit are electrically connected via the first connecting circuit. When reading data, the first and second signal lines have applied high and low potentials, respectively, before the first node and the amplifier circuit are electrically connected via the first connecting circuit. The first connection circuit includes data transfer MOS transistors, each connected between the sensor amplifier and the second memory cell corresponding to each column. The data transfer MOS transistor is controlled to conduct only when data is being written and read. The second connection circuit includes a plurality of data readout MOS transistors, each connected between the relevant second node and the data bus. This readout MOS transistor is controlled to conduct after the corresponding transfer MOS transistor becomes conductive when the data is read. The third connection circuit includes a plurality of data write MOS transistors, each connected between its respective first node and the data bus. The write MOS transistor is controlled to conduct before the corresponding transfer MOS transistor conducts when data is written. The data bus consists of a single signal line. Preferably, all transfer MOS transistors conduct simultaneously, and the read and write MOS transistors conduct sequentially in time. Each first memory cell includes, for example, a MOS transistor and a capacitor connected in series between the first and second bit lines and the low-voltage power supply. The MOS transistors of the first memory cells arranged in the same row are connected to the same word line. One MOS transistor, for example, is matched to each of the first through eighth field-effect semiconductor elements. In this case, the aspect ratio of the first through eighth field-effect semiconductor elements can be varied by adjusting their channel width, for example. According to another aspect of the present invention, a semiconductor memory device includes a memory array having a plurality of memory cells arranged in a plurality of columns, a data bus enabling reception / transmission of data signals between the memory cell and an external source, an amplifier circuit for amplifying a data signal from the memory cell, a first electrical path provided corresponding to each of the plurality of columns for enabling transfer of data signal from a memory cell arranged in the corresponding column from the amplifier circuit to the data bus, and a second electrical path different from the first electrical path provided corresponding to each of the plurality of columns, for enabling transfer of a data signal to be written to a memory cell arranged in the corresponding column from the data bus to the amplifier circuit. As illustrated in the present invention described above, the path through which the data signal read from the first memory array is transferred to the data bus and the path through which the data signal written to the data bus is transferred to the first memory array differ from each other in the data signal transfer between the data bus and the second memory array. Therefore, the problem of not being able to transfer data from the data line to the second memory cell properly is ρ»Ί indnat-n even if the driving capability of an inverter circuit between the first and second inverter circuits included in the second memory cell is increased. Furthermore, the problem of not being able to transfer data from the second memory cell to the data bus properly is solved even if the driving capability of the other inverter circuit is reduced. Consequently, the data reading speed is improved because data is easily transferred from the first memory array to the second memory array and from the second memory array to the data bus when reading data. The data writing speed is also improved because data is easily transferred from the data bus to the first memory array when writing data. The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings in which: Figure 1 is a block diagram schematically illustrating the component structure of a dual-port memory according to one embodiment of the present invention. Figure 2 is a circuit diagram detailing the structure of a serial memory cell 40 of Figure 1. Figure 3 is a circuit diagram detailing the structural configuration for reading and writing serial data provided corresponding to a pair of arbitrary bit lines in Figure 1; Figure 4 is a timing diagram to illustrate the circuit operation for transferring data from an arbitrary serial memory array to the data lines of Figure 1. Figure 5 is a timing diagram to illustrate the circuitry for transferring data from data lines to an arbitrary serial memory cell. Figure 6 is a block diagram of the entire structure of a conventional dual-port memory. Figure 7 is a circuit diagram of a conventional dual-port memory proportional structure. Figure 8 is a circuit diagram detailing a structure of a sensor amplifier 30 of Figure 7. Figure 9 is a circuit diagram detailing the structure of a serial memory cell of Figure 7. Figure 10 is a timing diagram to illustrate the circuit operation for transferring data from a sensor amplifier to the corresponding serial memory cell. Figure 11 is a timing diagram to illustrate the circuit operation for transferring data from a serial memory cell to the corresponding sensor amplifier of Figure 7. Figure 12 is a timing diagram to illustrate the circuit operation for transferring data from data lines to a serial memory cell in Figure 7. Figure 13 is a timing diagram to illustrate the circuit operation for transferring data from a serial memory cell to the data lines in Figure 7. Figure 14 is a circuit diagram detailing a circuit structure for reading and writing serial data corresponding to a pair of arbitrary bit lines in Figure 7. Figure 15 is a plan view and a section view of the structure of a MOS transistor. Figure 16 is a graph illustrating the relationship between the gate-to-source voltage and the current through the drain and source of a MOS transistor. Figure 17 is a circuit diagram of a serial memory cell structure in a dual port memory according to another embodiment of the present invention. Figure 18 is a circuit diagram detailing the structure of the inverter 440 of Figure 17. The present invention is generally applicable to a device a semiconductor integrated circuit that reads data from a memory array to transfer the temporarily stored data to another circuit. The present invention will be illustrated in detail according to the preferred embodiments. Figure 1 is a circuit diagram illustrating the component structure of a dual-port memory according to an embodiment of the present invention. The overall structure of this dual-port memory is similar to that shown in Figure 6. The structures of the memory array 2, sense amplifier portion 3, serial register 4, and serial bus line 5 of Figure 6 are mainly illustrated in Figure 1. In Figure 1, the memory array 2 and the sensor amplifier 3 have structures similar to conventional ones so their descriptions will not be repeated. Comparing Figures 1 and 7, the dual-port memory according to the present embodiment differs from a conventional dual-port memory in that the serial bus line 5 consists of a single data line 130, and only one of the two outputs of the sense amplifier 30 is connected to the corresponding serial memory cell 40 through the N-channel MOS transistor 150. Each serial memory cell 40 is connected to the data line 130 through two N-channel MOS transistors 220 and 230. The gates of the transistors 220 and 230 are connected to the serial decoder 6 through a different read select signal line 240 and a write select signal line 250. The significant difference between this dual-port memory and a conventional dual-port memory is that each serial memory cell 40 consists of two inverters 430 and 440 having different drive capacities. The drive capacity of an inverter refers to the current intensity that the inverter can supply to and sink from the node connected to it. Therefore, the drive capacity of an inverter depends on the drive capacity of the transistor forming this inverter. For example, in the conventional dual-port memory of Figure 14, the dimensions of the P-channel transistor 410a included in inverter 410 are the same as those of the P-channel transistor 420a included in inverter 420, and the dimensions of the N-channel transistor 410b included in inverter 410 are the same as those of the N-channel transistor 420b included in inverter 420.Therefore, when the sizes of transistors of the same polarity are the same between two inverters, the driving capacities of the two inverters are the same. Figure 2 is a circuit diagram specifically illustrating one structure of an arbitrary serial memory cell 40 of Figure 1. Referring to Figure 2, an inverter 430 includes a P-channel MOS transistor 430a and an N-channel MOS transistor 430b connected in series between the supply voltage VC and ground GND in the serial memory cell 40. Similarly, inverter 440 includes a P-channel MOS transistor 440a and an N-channel MOS transistor 440b connected in series between the supply voltage VC and ground GND. The dimensions of the P-channel transistor 430a included in inverter 430 are smaller than those of the trans- P-channel transistor 440a included in inverter 440, and the size of the N-channel transistor 430b included in inverter 430 is smaller than that of the N-channel transistor 440b included in inverter 440. Analogously to a conventional case, the two inverters 430 and 440 of the serial memory cell 40 have respective input ends connected to respective output ends of each other to form a flip-flop. Referring again to FIG. 1, sense amplifier 30 is connected to the input end of inverter 440 in the corresponding serial memory cell 40 through transistor 150. The output end of inverter 430 is connected to data line 130 through transistor 230. The output end of inverter 440 is connected to data line 130 through transistor 220. The operation of the dual-port memory according to the present invention will be explained later. The operation for reading and writing data in parallel is similar to that of a conventional dual-port memory, and the description will not be repeated. The serial data reading and writing operation will be explained later. The row address buffer 11 and the row decoder 13 of Figure 6 operate in a conventional manner whereby the potential of all BIT or BIT bit lines increases or decreases in accordance with a datum stored in memory cells MC of a row connected to an arbitrary word line WL in the memory array 2 of Figure 1. This causes the potential difference generated between the two BIT and BIT bit lines forming each pair of bit lines to be amplified to the voltage between the ground potential supply potential by conventional sensor amplifier operation 30. More specifically, in Figure 8, when there is a potential increase in the bit line BIT due to data stored in the memory cell MC connected to the selected word line WL, the potential of node c increases to the supply potential applied to the signal line 350, and the potential of node d decreases to the ground potential applied to the signal line 360. The read or read data amplified by the sense amplifier 30, i.e., data from node c and node d in FIG. 8, is applied to the serial memory cell 40 through the transistor 150 of FIG. 1 as the output of the sense amplifier 30. The circuit operation for transferring data from the sense amplifier 30 to the serial memory cell 40 will be illustrated below with reference to FIG. 3. Figure 3 is a circuit diagram of a circuit portion structure for reading and writing serial data, which is provided corresponding to a pair of arbitrary bit lines in Figure 1. The sensor amplifier 30 and the serial memory cell 40 are both illustrated in Figure 3 in more detail than in Figure 1. Referring to Figure 3, data transfer from the sensor amplifier 30 to the corresponding serial memory cell 40 is implemented by driving the data transfer signal supplied to the gate of transistor 150 to a level H for a constant period of time with a timing similar to that of a conventional case. This causes transistor 150 to conduct for the period of time previously mentioned. Upon conduction in transistor 150, nodes b and d are electrically connected. Therefore, in the case where transistor 150 conducts when the potentials of nodes c and d are at the H level and the L level, respectively, and the potentials of nodes a and b are at the L level and the H level, respectively, node b has current drawn from signal line 360 ​​which is at ground potential through transistors 150 and 320, and the current is supplied from the VC power supply through transistor 430a. More specifically, the current flowing from the VC power supply to node b through transistor 430a prevents the potential of node b from reaching the L level. However, in the present embodiment, the dimensions of transistor 430a are smaller than those of transistor 440a and also sufficiently smaller than those of transistor 320.Consequently, the current flowing from the VC power supply to node b through transistor 430a is sufficiently smaller than that flowing from node b to signal line 360 ​​through transistors 150 and 320. Therefore, the potential of node b quickly reaches an L level in response to the conduction of transistor 150. Therefore, the potential of node a quickly reaches an H level. In the case where transistor 150 conducts when the potentials of nodes c and d are at the L and H levels, respectively, and the potentials of nodes a and b are at the H and L levels, respectively, the current flowing from node b to ground GND through transistor 430b prevents the potential of node b from reaching an H level. However, in the present In this embodiment, the dimensions of transistor 430b are smaller than those of transistor 440b, and also sufficiently smaller than those of transistor 310. The current flowing from node b to ground GND through transistor 430b is sufficiently smaller than that flowing from signal line 350 which is at supply potential to node b through transistors 310 and 150. Therefore, the potential of node b quickly reaches an H level in response to conduction in transistor 150. Therefore, the potential of node a quickly reaches an L level. It can be understood from the above description that, in the present embodiment, the data read from the memory array 2 to the sensor amplifier 3 is efficiently transferred to the serial memory cell 40 independently of the data previously stored in the serial memory cell 30. Referring to FIG. 1, data transferred from the sense amplifier portion 3 to all serial memory cells 40 in serial memory array 4 is respectively transferred to data line 130 through a single transistor 220. The data transfer from serial memory cell 40 to data line 130 is accomplished by all transistors 220 becoming conductive one at a time sequentially in time. More specifically, shift register 6 applies an H-level potential for a constant period of time to all signal lines 240 one at a time sequentially in time. FIG. 4 is a timing diagram indicating the change in potential in signal lines and nodes at the time of data transfer. you from serial memory cell 40 to data line 130. The circuit operation for transferring data from serial memory cell 40 to data line 130 will be illustrated more specifically with reference to FIGS. 3 and 4. From the following description, the signal applied to signal line 240 from serial register 6 is referred to as the serial register read select signal. Data line 130 is clamped at a potential intermediate between the supply potential and ground potential as long as the switching element (transistor 220 in the present embodiment) provided between serial memory cell 40 and data line 130 conducts, similar to a conventional one. This clamping is released when the switching element becomes conductive. Therefore, as long as the serial register read select signal applied to signal line 240 of Figure 3 is raised to an H level for a constant period of time, as shown in Figure 4(c), the potential of data line 130 is at a potential intermediate between the L level and the H level, as shown in Figure 4(a). As the serial register read select signal increases, data line 130 and node a are electrically connected.At this point, the output of inverter 440 is applied to node a which receives the potential of node b latching the data transferred from the sensor amplifier 30. Thus, inverter 440 functions to transfer data from the serial memory cell 40 to the data line 130. More specifically, when the potential of node a is at a level61 The conduction of transistor 220 causes the potential of data line 130 to rise to an H level by current flowing from the power supply VC to data line 130 through transistors 440a and 220, as shown in curve 1 of FIG. 4(a). When the potential of node a is at an L level, the potential of data line 130 decreases to an L level by current flowing from data line 130 to ground GND through transistors 220 and 440b, in response to the conduction of transistor 220, as shown in curve 2 of FIG. 4(a). Since the size of transistor 440a is large in the present embodiment, the current flowing from the VC power supply to the data line 130 through transistors 440a and 220 is large when the potential of node a is at an H level. Furthermore, since the size of transistor 440b is large, the current flowing from the data line 130 to ground GND through transistors 220 and 440b is large when the potential of node a is at the L level. Therefore, the potential of the data line 130 varies easily in accordance with the data temporarily stored in the serial memory cell 40 (Figure 4(d)). Therefore, data is easily transferred from the serial memory cell 40 to the data line 130. When the serial register read select signal decreases, the potential of data line 130 will not change because transistor 220 returns to the non-conducting state. In the present embodiment, a sense amplifier (not shown) detects and amplifies the change in potential in data line 130 by the potentiometer 62. the intermediate signal just after the serial register read select signal drops, i.e., just after transistor 220 returns to the non-conducting state. The signal detected and amplified by the sensor amplifier (not shown) is supplied to an external source by the serial data output terminal SDO of Figure 6 as read data. Therefore, when reading serial data, data read from the memory array 2 is easily transferred from the sensor amplifier 30 to the serial memory cell 40 and from the serial memory cell 40 to the data line 130. Therefore, the time for reading serial data is reduced compared to the conventional one. The data temporarily stored in all serial memory cells 40 in serial memory array 4 is read from data line 130 one by one sequentially since the potential of signal line 240 of FIG. 1 actually reaches an H level sequentially in time as described previously. Transistor 230 is always in the non-conducting state because the potential of all signal lines 250 is always at the H level at the time of serial data readout (FIG. 4(b)). The circuit operation for writing serial data to the dual-port memory of the present embodiment will be explained below with reference to Figures 1, 3 and 5. Figure 5 is a timing diagram illustrating the potential change of signal lines and nodes upon transfer of data from the data line 130 to the serial memory cell 40. In the description that follows, gue, the signal applied from the serial register to signal line 250 is called the serial register write select signal. Upon serial data writing, a potential in accordance with the logic value of each write data item (a Η or L level potential) is applied to data line 130 from serial data input terminal SD1 of FIG. 6. Transfer of the applied write data from data line 130 to the serial memory array is accomplished by transistor 230 becoming conductive. More specifically, shift register 6 applies an H level potential for a constant period of time to all signal lines 250 one at a time sequentially in time. Accordingly, each write data item is temporarily stored in the serial memory cell provided corresponding to the BIT or BIT line to which the memory cell MC to be written is connected, among the serial memory cells 40 in serial memory array 4.The circuit operation for transmitting data from the data line 130 to the serial memory array 4 will be illustrated in more detail. The case is considered where the potential of data line 130 is at the H level and the potential of node b is at the L level, for example in Figure 3. When transistor 230 conducts in this state, the current flowing from node b to ground GND through transistor 430b prevents the potential of node b from reaching the H level in accordance with the current flowing from data line 130 to node b through transistor 230. However, the dimensions of transistor 430b are, in the present embodiment, small. Therefore, the current flowing from node b to ground GND through transistor 430b is small enough so that it does not prevent the potential of node b from changing to the H level. Therefore, the potential of node b immediately reaches an H level in response to the conduction of transistor 230b. In response, the potential of node a reaches an L level. In the case where transistor 230 conducts when the potential of data line 130 is at the L level, and the potential of node b is at the H level, current flowing from the VC supply to node b through transistor 430a prevents the potential of node b from reaching the L level in response to current flowing from node b to data line 130 through transistor 230. However, because in the present embodiment the dimensions of transistor 430a are small, the current flowing from the VC supply to node b through transistor 430a is small enough that it does not prevent the potential of node b from changing to an L level. Therefore, the potential of node b quickly reaches an L level in response to transistor 230 conducting. In response, the potential of node a reaches an H level. In the present embodiment, the potentials of nodes a and b vary rapidly in accordance with the level of data line 130, regardless of the data previously stored in serial memory cell 40. In other words, the data stored in serial memory cell 40 switches to data in accordance with the potential applied to data line 130 (curves 1 or 2 in Fig. 5(a)), rapidly in response to the increase in the write select signal (Fig. 5(b)) of the serial register as shown in figure 5(d)). In FIG. 1, each of the write data transferred from data line 130 to serial memory cell 40 is transferred to sense amplifier 30 through a single transistor 150. The circuit operation for transferring data from serial memory cell 40 to the corresponding sense amplifier 30 will be illustrated in more detail below. Figure 3, data transfer from serial memory cell 40 to sense amplifier 30 is accomplished by making transistor 150 conducting for a constant period of time by the data transfer signal reaching an H level for a constant period of time. Therefore, the smaller inverter 430 of the two inverters 430 and 440 forming serial memory cell 40 functions to transfer data from serial memory cell 40 to sense amplifier 30. When writing serial data, transistor 220 is always in the non-conducting state since the serial register read select signal (Figure 5(c)) is always at the L level. Similar to a conventional case, the sensing amplifier 30 is activated after the conduction of the transistor 150. More specifically, the potentials (Figures 11(c) and 11(d)) of the signal lines 350 and 360 reach the supply potential and the ground potential respectively after the increase of the data transfer signal (Figure 11(f). Therefore, if the potential of the node b is at the H level just before the conduction of the transistor 150, the current flows to the node d from the supply VC through the transistors 430a and 150 during the pe66 time period from the conduction of transistor 150 until the activation of the sensing amplifier 30. Therefore, the potential of node d increases from the potential of the equalized bit signal BIT. However, since the dimensions of transistor 430a are small in the present embodiment, the current flowing from the VC supply to node d through transistors 430a and 150 is small. Consequently, the increase in potential at node d during the aforementioned time period is small. If the d-node potential is at the L level just prior to transistor 150 conduction, current flows from the d-node to GND through transistors 150 and 430b during the time period from transistor 150 conduction until sensing amplifier 30 turns on. Therefore, the d-node potential decreases from the potential of the equalized bit signal ΒΪT. However, because the dimensions of transistor 430b are small in this embodiment, the current flowing from the d-node to GND through transistors 150 and 430b is small. Therefore, the d-node potential drop during the previously mentioned time period is small. During the time period until the sensing amplifier 30 is activated, the amount of potential change according to the write data temporarily stored in the serial memory cell 40 is small at the node d. The threshold voltage and the sizes of the transistors 310, 320, 330 and 340 forming the sensing amplifier 30 are set such that the small potential change generated in the BIT or BIT bit lines by the data stored in the MC memory cell can be amplified by the sensing amplifier 30. This change The potential variation generated in the BIT or BIT of bit line is less than the overall potential variation in the node d during the time period from conduction in the transistor 150 until the activation of the sense amplifier 30. By the activation of the sense amplifier 30, the potential variation generated in the node d is amplified sufficiently by the sense amplifier 30. In other words, the write data temporarily stored in the serial memory array 40 is easily transferred to the sense amplifier 30 regardless of the small size of the inverter 430. When the write data has been transferred to all the sense amplifiers 30 in the sense amplifier portion 3 of FIG. 1, a level potential H is applied to the selected word line WL, similar to the conventional case.This causes the write data transferred to the sensor amplifiers 30 to be written to memory cells MC of a row connected to the selected word line WL. Therefore, the dual-port memory of the present embodiment performs data transfer from the data line 130 to the serial memory cell 40 smoothly for serial data writing without preventing the data from being hindered to the sensor amplifier 30 by the serial memory cell 40. Therefore, the time for serial data writing is reduced compared to a conventional dual-port memory. The transient phenomenon such as the small potential variation generated at nodes a and b of the serial memory cell 40 at the time of data transfer from the serial memory cell 40 to the data line 130 and the small potential change generated in data line 30 upon transfer of data from data line 130 to serial memory cell 40 is similar to that generated in nodes a and b upon transfer of data from serial memory cell 40 to data lines 100 and 110 in the dual-port memory shown in FIG. 7, and generated in data lines 100 and 110 upon transfer of data from data lines 100 and 110 to serial memory cell 40 in the dual-port memory shown in FIG. 7. In other words, upon data transfer from serial memory cell 40 to data line 130, current flows to data line 130 from node a or b which latches onto the H-level potential. Therefore, the potential of node a or b latching onto the H-level potential is slightly below the H-level as shown in curve 1 of Figure 4(d), during the time period when the serial register read select signal is at the H-level. Upon data transfer from data line 130 to serial memory cell 40, current flows from data line 130 to node a or b latching onto an L-level potential, when the potential of data line 130 reaches an H-level; and current flows from node a or b latching onto an H-level potential to data line 130 when the potential of data line 130 reaches an L-level.As shown in Figure 5(a), therefore, the potential of data line 130 increases slightly (when the potential of data line 130 is at level L, curve 2) or decreases slightly (when the potential. of data line 130 is at the Ξ level: curve 1) in response to the increase of the serial register write select signal. Thus, referring to FIG. 1, when reading serial data into the dual-port memory of the present embodiment, the read data applied to node L of the sensor amplifier 30 is temporarily stored by inverters 430 and 440 and then transferred from node a to data line 130 in FIG. 1. When writing serial data, the write data applied from data line 130 to node b is temporarily stored by inverters 430 and 440 and then supplied from node b to the sensor amplifier 30. Thus, the data output from the serial memory cell 40 to data line 130 and the data output from the serial memory cell 40 to the sensor amplifier 30 are implemented by different inverters 430 and 440, respectively. When reading serial data, the output of amplifier 30 will collide with the output of inverter 430. When writing serial data, the output of data line 130 will collide with the output of inverter 430. Therefore, by decreasing the drive capacitance of inverter 430, data transfer from data line 130 to serial memory cell 40 and from sensor amplifier 30 to serial memory cell 40 can both be performed easily. At the same time, the drive capacitance of inverter 440 can be set taking into account only the data transfer from serial memory cell 40 to data line 130. In other words, if the drive capacitance of inverter 440 is increased, data can be easily transferred from serial memory cell 40 to data line 130. Therefore, as in the present embodiment, serial data read and write speeds can both be improved by setting the drive capacitance of inverters 430 and that of inverter 440 in a complementary manner. In practice, the dimensions of transistors 430a and 430b forming inverter 430 and the dimensions of transistors 440a and 440b forming inverter 440 must be determined by considering the dimensions of transistors 310, 320, 330, and 340 forming sensor amplifier 30. The value in the parenthesis in Figure 3 indicates a βββπψίο of the ratio of the dimensions (channel width W) of each of the eight transistors 310, 320, 330, 340, 430a, 430b, 440a, 440b to the dimensions (channel width W) of the other seven transistors. The size ratios of these eight transistors are not limited to those shown in Figure 3. Adjustment of the size (driving capability) of each transistor forming the inverters 430 and 440 can be achieved not only by varying the channel width W, but also by varying other factors, e.g., the channel length, i.e., the gate width L and the gate thickness T. In this embodiment, the two data lines required in conventional dual-port memory are reduced to a single data line, thereby reducing the area occupied by the serial bus line 5 for the dual-port memory chip 1 of Figure 6. This will help increase the storage capacity of a dual-port memory. 7ΐ ο I )ς In each serial memory cell 40 of the above embodiment, the driving capacitance of the P-channel MOS transistor and the N-channel MOS transistor forming the inverter 40 is set to be greater than that of the P-channel MOS transistor and the N-channel MOS transistor forming the inverter 430, so that the driving capacitance of the inverter 440 for transferring the output data of the sense amplifier 30 to the I / O line 130 is greater than that of the inverter 430 for transferring the signal on the I / O line 130 to the sense amplifier 30. However, the method for setting the driving capacitance of the inverter 440 to be greater than that of the inverter 430 is not limited to the method described above. Figure 17 is a diagram illustrating another method of setting the drive capacitance of inverter 440 to be greater than that of inverter 430. Figure 17 shows a structure of a serial memory cell 40. All other serial memory cells 40 have a structure identical to that shown in Figure 17. Referring to Figure 17, a serial memory cell 40 comprises the inverter 440 formed by a circuit for connecting in parallel a plurality of inverters 441 and 442. Figure 18 is a circuit diagram detailing the inverter 440 of Figure 17. Referring to Figure 18, the inverter 440 includes an inverter 441 implemented with the P-channel MOS transistors 441a and the N-channel MOS transistor 441b connected in series between the supply VC and ground GND, and an inverter 442 implemented with the P-channel MOS transistor 442a and the N-channel MOS transistor 442b connected in parallel with the transistors 441a and 441b, respectively. The gates of the transistors 441a and 441b and of the transistors 442a and 442b are connected to node b. The nodes of the transistors 441a and 441b and of the transistors 442a and 442b are connected in common to node a. When a high level potential is transferred to node b from sense amplifier 30 through transistor 150 when serial data is read, the two N-channel MOS transistors 441b and 442b are turned on. When a low level potential is transferred to node b from sense amplifier 30 through transistor 150, the two P-channel MOS transistors 441a and 442a in inverter 440 are turned on. Therefore, the current drawn through inverter 440 from data line 130 through node a and transistor 220 to bring the potential of data line 130 low, and the current that inverter 440 supplies to data line 130 through node a and transistor 220 to bring the potential of data line 130 high are both driven by the two MOS transistors.If the driving capacitance of the P-channel MOS transistor 430a and the N-channel MOS transistor 430b forming the inverter 430 are identical to those of the P-channel MOS transistors 441a and 442a and the N-channel MOS transistors 441b and 442b forming the inverter 440 are similar, then the driving capacitance of the inverter 440 becomes double that of the inverter 430. While in each of the previously mentioned and described embodiments the present invention is applied to a dual-port memory, the present invention is applicable to any semiconductor memory device in which data is transferred between at least two types of memory arrays and between these memory arrays and a data array. While the present invention has been described and illustrated in detail, it will be clearly understood that this has been done by way of illustration and example only and is not to be construed as limiting, the spirit and scope of the present invention being limited only by the terms of the appended claims.

Claims

CLAIMS 1. A semiconductor memory device comprising: a first memory array (2) having a plurality of first memory cells (MC) arranged in a plurality of columns, a second memory array (4) for temporarily storing a read data signal from said first memory array (2) and a write data signal to be written into said first memory array (2), said second memory array (4) including a plurality of second memory cells (40) provided corresponding to said plurality of columns, wherein each of said second memory cells (40) includes a complementary first and second storage node (a, b), bidirectional inverting means (430, 440) interconnecting said first and second storage node, means for limiting the intensity of the current flow within said inverting means (430,440) in one direction (430) to be less than that within said inverting means in the opposite direction (440), data bus means for receiving a data signal read from said second memory cell (40) and an externally applied data signal, reading means (13, 14) for reading a data signal from one of said plurality of first memory cells (MC), amplifying means (3) for reading and amplifying a data signal read by said reading means (13, 14) and a data signal temporarily stored in each of said second memory cells (40), first connecting means (150) for electrically connecting one node of said complementary storage nodes (b) to said amplifying means (3) at the time of reading data and writing data thereto, second connecting means (220) for electrically connecting the other of said complementary storage nodes (a) to said data bus means (5),after said node (b) has been electrically connected to said amplifying means (3) by said first connecting means (150) at the time of said data reading, and third connecting means (230) for electrically connecting said other node (a) to said data bus means (5) before said node (b) is electrically connected to said amplifying means (3) by said first connecting means (150) at the time of said data writing., 2. A semiconductor memory device comprising: a first memory array (2) having a plurality of first memory cells (MC) arranged in a plurality of columns, a second memory array (4) for temporarily storing a read data signal from said first memory array (2) and a write data signal to be written into said first memory array (2), said second memory array (4) including a plurality of second memory cells (40) provided corresponding to said plurality of columns, wherein each of said second memory cells 40 includes a first node (b), a second node (a), first inverting means for inverting the potential of said first node (b) to provide the same to said second node (a), second inverting means (430) for inverting the potential of said second node (a) to provide the same to said first node (b),wherein the driving capacity of said first inverting means (440) is greater than that of said second inverting means (430), data bus means for receiving a data signal read from said second memory cell (40) and an externally applied data signal, reading means (13, 14) for reading a data signal from one of said plurality of first memory cells (MC), amplifying means (3) for detecting and amplifying a data signal read by said reading means (13, 14) and a data signal temporarily stored in each of said second memory cells (40), first connecting means (150) for electrically connecting each of said first nodes (b) to said amplifying means (3) at the time of reading data and writing data,second connecting means (220) for electrically connecting each of said second nodes (a) to said data bus means after each said first node (b) has been electrically connected to said amplifying means (3) by said first connecting means (150) at the time of said data reading, and third connecting means (230) for electrically connecting each said first node (b) to said data bus means (5), before each first node (b) is electrically connected to said amplifying means (3) by said first connecting means (150) at the time of said data writing., 3. A semiconductor memory device according to claim 2, wherein said first inverting means (440) comprises a first and second field-effect semiconductor element (440a, 440b) connected in series between a high potential supply (VC) and a low potential supply (GND), and having complementary polarities, said second inverting means comprising a third and fourth field-effect semiconductor element (430a, 430b) connected in series between said high potential supply (VC) and said low potential supply (GND), and having a polarity identical to that of said first field-effect semiconductor element (440a) and a polarity identical to that of said second field-effect semiconductor element (440b), respectively,the driving capacity of said first field-effect semiconductor element (440a) being greater than that of said third field-effect semiconductor element (430a), the size of said second field-effect semiconductor element (440b) being greater than that of said fourth field-effect semiconductor element (430b)., 4. A semiconductor memory device according to claim 2, wherein said first inverting means (440) comprises a plurality of inverters (441, 442) connected between said first node (b) and said second node (a) in parallel with each other, and said second inverting means (430) comprises a single inverter connected between said first node (b) and said second node (a) in antiparallel with respect to said plurality of inverters (441, 442).

5. Semiconductor memory device according to claim 2, wherein said first memory matrix (2) further comprises a first and second bit line (BIT, BIT) provided corresponding to each of said plurality of columns, said data signals stored in each of said plurality of first memory cells (MC) being read by said reading means (13, 14) at said first and second bit line (BIT, BIT) corresponding to said column in which they are arranged, said amplifying means (3) comprising a plurality of differential amplifying means (30) provided corresponding to said plurality of columns.

6. A semiconductor memory device according to claim 5, wherein each of said plurality of differential amplifier means (30) comprises a first and second signal line (350, 360), a fifth and sixth field-effect semiconductor element (330, 340) of complementary polarity, provided between said first signal line (350) and the corresponding said first bit line (BIT), and between said second signal line (360) and the corresponding said first bit line (BIT), respectively, and controlled in accordance with the potential of the corresponding said second bit line (BIT), a seventh and eighth field-effect semiconductor element (310, 320) of complementary polarity, provided between the corresponding said second bit line (BIT) and said first signal line (350) and between the corresponding said second bit line (BIT) and said second signal line (360), respectively,and controlled in accordance with the potential of the corresponding said first bit line (BIT), the polarity of said seventh field-effect semiconductor element (310) being identical to that of said fifth field-effect semiconductor element (330), the polarity of said eighth field-effect semiconductor element (320) being identical to that of said sixth field-effect semiconductor element (340), said first and second signal lines (350, 360) having applied a high potential and a low potential respectively, after said first node (b) and said amplifying means (30) have been electrically connected by said first connecting means (150), at the time of said data writing, said first and second signal lines (350, 360) having applied said high potential and said low potential respectively,before said first node (b) is electrically connected to said amplifying means (3) at the time of said data reading., 7. A semiconductor memory device according to claim 6, wherein said first connecting means (150) comprises a plurality of ninth field-effect semiconductor elements (150) provided corresponding to said plurality of columns, each of said plurality of ninth field-effect semiconductor elements 150 being connected between the corresponding said differential amplifier means (30) and said first node (b) of the corresponding said second memory cell (40) and controlled to conduct only at the time of said data writing and said data reading.

8. A semiconductor memory device according to claim 7, wherein said second connecting means (220) comprises a plurality of tenth field-effect semiconductor elements (220) provided corresponding to said plurality of columns, each of said plurality of tenth field-effect semiconductor elements (220) being provided between said second node (a) of the corresponding said second memory cell (40) and said data bus means (5), and controlled to conduct after the corresponding said ninth field-effect semiconductor elements (150) have become conductive upon said data readout.

9. A semiconductor memory device according to claim 8, wherein said third connecting means (230) comprises a plurality of eleventh field-effect semiconductor elements (230) provided corresponding to said plurality of columns, each of said plurality of eleventh field-effect semiconductor elements (230) being provided between said first node (b) and the corresponding said second memory cell (40) and said data bus means (5), and controlled to conduct before the corresponding said ninth field-effect semiconductor element (150) is conducting, at the time of said data writing.

10. A semiconductor memory device according to claim 7, wherein said third connecting means (230) comprises a plurality of eleventh field-effect semiconductor elements (230) provided corresponding to said plurality of columns, each of said plurality of eleventh field-effect semiconductor elements (230) being provided between said first node (b) of the corresponding said second memory cell (40) and said data bus means (5), and controlled to conduct before the corresponding said ninth field-effect semiconductor element (150) is conducting, at the time of said data writing.

11. A semiconductor memory device according to claim 7, wherein said plurality of ninth field-effect semiconductor elements (150) conduct simultaneously.

12. A semiconductor memory device according to claim 8, wherein each of said plurality of tenth field-effect semiconductor elements (220) conducts sequentially in time.

13. A semiconductor memory device according to claim 9, wherein each of said plurality of eleventh field-effect semiconductor elements 230 conducts sequentially in time.

14. A semiconductor memory device according to claim 10, wherein each of said plurality of eleventh field-effect semiconductor elements (230) conducts sequentially in time.

15. A semiconductor memory device according to claim 1, wherein said data bus means (5) comprises a single signal line (150).

16. Memory device in claim 2, wherein said semiconductor bus means according to claim 5 comprises a single signal line (150).

17. A semiconductor memory device according to claim 9, wherein said data bus means (5) comprises a single signal line (150).

18. Semiconductor memory device according to claim 1, wherein said plurality of first memory cells (MC) are also arranged in a plurality of rows in said first memory array (2), said first memory array (2) further comprises a plurality of word lines (WL) provided corresponding to said plurality of rows, each of said first memory cells (MC) comprises a twelfth field effect semiconductor element (TR) and a capacitive coupling element (C), connected in series between one of said first and said second lines (BIT, BIT) corresponding to said column in which it is arranged and to the low potential power supply, each of said twelfth field effect semiconductor elements (TR) of said first memory cells (MC) arranged along the same said row and controlled by the potential of said word line (WL) corresponding to said same row.

19. Semiconductor memory device according to claim 2, wherein said plurality of first memory cells (MC) are also arranged in a plurality of rows in said first memory array (2), X / ·< said first memory array (2) further comprises a plurality of word lines (WL) provided corresponding to said plurality of rows, each of said first memory cells (MC) comprises a twelfth field effect semiconductor element (TR) and a capacitive coupling element (C) connected in series between one of said first and second bit lines (BIT, BIT) corresponding to said column in which it is arranged and to the low potential supply, each of said twelfth field effect semiconductor elements (TR) of said first memory cells (MC) arranged along the same said row and controlled by the potential of said word line (WL) corresponding to said same row.

20. Semiconductor memory device according to claim 17, wherein said plurality of first memory cells (MC) are also arranged in a plurality of rows in said first memory matrix (2), said first memory matrix (2) further comprises a plurality of word lines (WL) provided corresponding to said plurality of rows, each of said first memory cells (MC) comprises a twelfth field-effect semiconductor element (TR) and a capacitive coupling element (C), connected in series between one of said first and said second bit lines (BIT, BIT) corresponding to said column in which it is arranged and to the low potential supply, each of said twelfth field-effect semiconductor elements (TR) of said first memory cells (MC) arranged along said first memory matrix (2) further comprises a plurality of word lines (WL) provided corresponding to said plurality of rows,20. A semiconductor memory device according to claim 17, wherein said plurality of first memory cells (MC) are also arranged in a plurality of rows in said first memory array (2), said first memory array (2) further comprises a plurality of word lines (WL) provided corresponding to said plurality of rows,each of said first memory cells (MC) comprises a twelfth field-effect semiconductor element (TR) and a capacitive coupling element (C), connected in series between one of said first and said second line (BIT, BIT) of bits corresponding to said column in which it is arranged and to the low potential power supply, each of said twelfth field-effect semiconductor elements (TR) of said first memory cells (MC) arranged along the same said row is controlled by the potential of said line (WL) of words corresponding to said same row., 21. A semiconductor memory device comprising: a memory array (2) including a memory cell (MC) arranged in a plurality of columns, data bus means enabling said transmission / reception of data signals between said memory array (2) and an external source, amplifying means (3) for amplifying a data signal read from said memory cell (MCO), a plurality of first electrical path means (220, 440) provided corresponding to said plurality of columns for enabling the transfer of a data signal read from said memory cell (MC) arranged in the corresponding said column, from said amplifying means (3) to said data bus means (5), and a plurality of second electrical path means (230) provided corresponding to said plurality of columns, independently controlled by said plurality of first electrical path means (440, 440).220) to enable the transfer of a data signal to be written into said memory cell (MC) arranged in the corresponding said column from said data bus means (5) to said amplifying means (3)., 22. A method for operating a semiconductor memory device comprising: a first memory array (2) having a plurality of first memory cells (MC) arranged in a plurality of columns, a second memory array (4) for temporarily storing a read data signal from said first memory array (2) and a write data signal to be written to said first memory array (2), said second memory array (4) including a plurality of second memory cells (40) provided corresponding to said plurality of columns, wherein each of said second memory cells (40) includes a mutually complementary first and second storage node, data bus means for receiving a data signal read from said second memory cell (40) and an externally applied data signal, read means (13, 14) for reading a data signal from one of said plurality of first memory cells (MC),amplifying means (3) for detecting and amplifying a data signal read by said reading means (13, 14) and a data signal temporarily stored in each of said second memory cells (40), the method comprising the steps of: in a data reading mode, (a) electrically connecting each of said first nodes (b) to said amplifying means (3), and (b) electrically connecting each of said second nodes (a) to said data bus means (5) after each said first node (b) has been electrically connected to said amplifying means (3), wherein current flow from said first node (b) to said second node (a) has a particular current value, and in a data writing mode, (a) electrically connecting each of said first nodes (b) to said amplifying means (3), and (b) electrically connecting each said first node (b) to said data bus means (5) before each said first node (b) is connected electrically to said means,amplifiers (3) while limiting the current flow from said second node (a) to said first node (b) to be less than said particular current value. The Agent Dr. I CTtdoMODIANO,