Image sensor

Abstract

To provide an image sensor with improved electric and optical characteristics.SOLUTION: An image sensor that is provided includes a semiconductor substrate having a first surface and a second surface facing each other, a first pixel separation structure provided in a first trench extending vertically from the first surface of the semiconductor substrate and defining a plurality of pixel regions, and a second pixel separation structure provided in a second trench extending vertically from the second surface of the semiconductor substrate and overlapping with the first pixel separation structure. The first pixel separation structure can include a liner semiconductor pattern that defines a gap region in the first trench and includes side wall parts and a bottom wall part that connects the side wall parts, a liner insulating pattern disposed between the liner semiconductor pattern and the semiconductor substrate, and a capping insulating pattern provided in the gap region of the liner semiconductor pattern.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to an image sensor, and more particularly to an image sensor having improved electrical and optical characteristics. [Background technology]

[0002] Image sensors convert optical images into electrical signals. Recently, with the development of the computer and communication industries, the demand for image sensors with improved performance is increasing in various fields such as digital cameras, video cameras, PCS (Personal Communication Systems), game machines, security cameras, and medical micro cameras.

[0003] Image sensors include charge coupled devices (CCDs) and CMOS image sensors. Among these, CMOS image sensors have a simple driving method and can integrate signal processing circuits on a single chip, allowing for product miniaturization. CMOS image sensors also consume very little power, making them easy to apply to products with limited battery capacity. In addition, CMOS image sensors can be used interchangeably with CMOS process technology, reducing manufacturing costs. Therefore, the use of CMOS image sensors is rapidly increasing as technology develops and higher resolutions become possible. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Patent No. 10,079,259 Summary of the Invention [Problem to be solved by the invention]

[0005] SUMMARY OF THE PRESENT EMBODIMENT An object of the present invention is to provide an image sensor having improved electrical and optical characteristics.

[0006] The problems to be solved by the present invention are not limited to those mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0007] In order to achieve the above object, an image sensor according to an embodiment of the present invention includes a semiconductor substrate having a first surface and a second surface facing each other, a first pixel isolating structure provided in a first trench extending vertically from the first surface of the semiconductor substrate and defining a plurality of pixel regions, and a second pixel isolating structure provided in a second trench extending vertically from the second surface of the semiconductor substrate and overlapping the first pixel isolating structure, wherein the first pixel isolating structure may include a liner semiconductor pattern defining a gap region in the first trench, the liner semiconductor pattern including sidewall portions and a bottom portion connecting the sidewall portions, a liner insulating pattern disposed between the liner semiconductor pattern and the semiconductor substrate, and a capping insulating pattern provided in the gap region of the liner semiconductor pattern.

[0008] In order to achieve the above object, an image sensor according to an embodiment of the present invention includes a semiconductor substrate having a first surface and a second surface facing each other, a first pixel isolating structure extending vertically from the first surface of the semiconductor substrate to surround each pixel region, the first pixel isolating structure including a liner semiconductor pattern having sidewall portions and a bottom portion connecting the sidewall portions, a second pixel isolating structure extending vertically from the second surface of the semiconductor substrate to overlap the first pixel isolating structure, and a back contact plug penetrating a portion of the second pixel isolating structure to be connected to the liner semiconductor pattern of the first pixel isolating structure.

[0009] In order to achieve the above object, an image sensor according to an embodiment of the present invention includes a semiconductor substrate of a first conductivity type having a first surface and a second surface facing each other, a first pixel isolating structure extending vertically from the first surface of the semiconductor substrate to surround each of pixel regions, the first pixel isolating structure including a liner semiconductor pattern including a sidewall portion and a bottom portion connecting the sidewall portion, a liner insulating pattern between the semiconductor substrate and the liner semiconductor pattern, and a capping insulating pattern on the liner semiconductor pattern, a second pixel isolating structure extending vertically from the second surface of the semiconductor substrate and overlapping the first pixel isolating structure, and the pixel region includes a photoelectric conversion region provided in a semiconductor substrate and including impurities of a second conductivity type; an isolation film defining an active portion on the first surface of the semiconductor substrate in each of the pixel regions, the isolation film being adjacent to the first surface of the semiconductor substrate; a transfer gate electrode disposed in the active portion of each of the pixel regions; a back contact plug penetrating a portion of the second pixel isolation structure and connected to the liner semiconductor pattern of the first pixel isolation structure; a color filter corresponding to the pixel region on the second surface of the semiconductor substrate; a lattice structure disposed between the color filters and overlapping the second pixel isolation structure; and a microlens on the color filter. Effect of the Invention

[0010] According to an embodiment of the present invention, the amount of conductive semiconductor material having high light absorption in the pixel separating structure can be minimized. Therefore, it is possible to reduce the absorption of incident light in the semiconductor material of the pixel separating structure, and it is possible to reduce dark current caused by defects at the interface between the semiconductor substrate and the pixel separating structure by applying a negative voltage to the semiconductor material of the pixel separating structure. Therefore, it is possible to simultaneously improve the electrical and optical characteristics of the image sensor. [Brief description of the drawings]

[0011] [Figure 1]FIG. 2 is a plan view illustrating a portion of an image sensor according to an embodiment of the present invention. [Diagram 2] 2 is a cross-sectional view of an image sensor according to an embodiment of the present invention, taken along line II' of FIG. [Figure 3A] 3 is an enlarged view of a portion of an image sensor according to various embodiments of the present invention, in particular, an enlarged view of a portion P1 of FIG. 2; [Figure 3B] 3 is an enlarged view of a portion of an image sensor according to various embodiments of the present invention, in particular, an enlarged view of a portion P1 of FIG. 2; [Figure 3C] 3 is an enlarged view of a portion of an image sensor according to various embodiments of the present invention, in particular, an enlarged view of a portion P1 of FIG. 2; [Figure 3D] 3 is an enlarged view of a portion of an image sensor according to various embodiments of the present invention, in particular, an enlarged view of a portion P1 of FIG. 2; [Figure 3E] 3 is an enlarged view of a portion of an image sensor according to various embodiments of the present invention, in particular, an enlarged view of a portion P1 of FIG. 2; [Figure 3F] 3 is an enlarged view of a portion of an image sensor according to various embodiments of the present invention, in particular, an enlarged view of a portion P1 of FIG. 2; [Figure 3G] 3 is an enlarged view of a portion of an image sensor according to various embodiments of the present invention, in particular, an enlarged view of a portion P1 of FIG. 2; [Figure 3H] 3 is an enlarged view of a portion of an image sensor according to various embodiments of the present invention, in particular, an enlarged view of a portion P1 of FIG. 2; [Figure 3I] 3 is an enlarged view of a portion of an image sensor according to various embodiments of the present invention, in particular, an enlarged view of a portion P1 of FIG. 2; [Figure 4] 3 is an enlarged view of a portion of an image sensor according to various embodiments of the present invention, in which a portion P2 of FIG. 2 is enlarged. [Diagram 5]1 is a cross-sectional view taken along line II' of FIG. 1, illustrating a method of manufacturing an image sensor according to an embodiment of the present invention. [Figure 6] 1 is a cross-sectional view taken along line II' of FIG. 1, illustrating a method of manufacturing an image sensor according to an embodiment of the present invention. [Figure 7] 1 is a cross-sectional view taken along line II' of FIG. 1, illustrating a method of manufacturing an image sensor according to an embodiment of the present invention. [Figure 8] 1 is a cross-sectional view taken along line II' of FIG. 1, illustrating a method of manufacturing an image sensor according to an embodiment of the present invention. [Figure 9] 1 is a cross-sectional view taken along line II' of FIG. 1, illustrating a method of manufacturing an image sensor according to an embodiment of the present invention. [Figure 10] 1 is a cross-sectional view taken along line II' of FIG. 1, illustrating a method of manufacturing an image sensor according to an embodiment of the present invention. [Figure 11] 1 is a cross-sectional view taken along line II' of FIG. 1, illustrating a method of manufacturing an image sensor according to an embodiment of the present invention. [Figure 12] 1 is a cross-sectional view taken along line II' of FIG. 1, illustrating a method of manufacturing an image sensor according to an embodiment of the present invention. [Figure 13] 1 is a cross-sectional view taken along line II' of FIG. 1, illustrating a method of manufacturing an image sensor according to an embodiment of the present invention. [Figure 14] 1 is a cross-sectional view taken along line II' of FIG. 1, illustrating a method of manufacturing an image sensor according to an embodiment of the present invention. [Figure 15] 1 is a schematic plan view of an image sensor including a semiconductor device according to an embodiment of the present invention; [Figure 16] 16 is a cross-sectional view of an image sensor according to an embodiment of the present invention taken along the line in FIG. 15. [Figure 17] 16 is a cross-sectional view of an image sensor according to an embodiment of the present invention taken along the line in FIG. 15. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an image sensor and a method for manufacturing the same according to embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0013] FIG 1 is a plan view showing a portion of an image sensor according to an embodiment of the present invention. FIG 2 is a cross-sectional view of an image sensor according to an embodiment of the present invention, taken along line I-I' in FIG 1. FIGs 3A to 3I are enlarged views of a portion of an image sensor according to various embodiments of the present invention, which are enlarged views of a portion P1 in FIG 2. FIG 4 is an enlarged view of a portion of an image sensor according to various embodiments of the present invention, which is an enlarged view of a portion P2 in FIG 2.

[0014] 1 and 2, an image sensor according to an embodiment of the present invention may include, from a vertical perspective, a photoelectric conversion layer 10, a readout circuit layer 20, and a light-transmitting layer 30.

[0015] The photoelectric conversion layer 10 may be disposed between the readout circuit layer 20 and the light transmission layer 30 from the vertical perspective. Light incident from the outside may be converted into an electrical signal in the photoelectric conversion region PD. The photoelectric conversion layer 10 may include a semiconductor substrate 101, first and second pixel isolation structures PIS1 and PIS2, and a photoelectric conversion region PD.

[0016] In detail, the semiconductor substrate 101 may have a first surface 100a (or front surface) and a second surface 100b (or back surface) facing each other. The semiconductor substrate 101 may be a substrate in which a first conductive type (e.g., p-type) epitaxial layer is formed on a first conductive type (e.g., p-type) bulk silicon substrate, and may be a substrate in which the bulk silicon substrate is removed and only the p-type epitaxial layer remains in the image sensor manufacturing process. Alternatively, the semiconductor substrate 101 may be a bulk semiconductor substrate 101 including a first conductive type well.

[0017] The semiconductor substrate 101 may include a central region CR and an edge region ER around the central region CR. The central region may include a plurality of pixel regions PR defined by first and second pixel separating structures PIS1, PIS2, and the edge region may include a plurality of dummy pixel regions DPR defined by the first and second pixel separating structures PIS1, PIS2.

[0018] The device isolation layer 105 may be disposed adjacent to the first surface 100a of the semiconductor substrate 101 in each of the pixel regions PR. The device isolation layer 105 may be provided in a first trench T1 formed by recessing the first surface 100a of the semiconductor substrate 101. The device isolation layer 105 may be made of an insulating material. For example, the device isolation layer 105 may include a liner oxide layer and a liner nitride layer conformally covering a surface of the first trench T1, and a buried oxide layer filling the first trench T1 on which the liner oxide layer and the liner nitride layer are formed. The device isolation layer 105 may define an active portion on the first surface 100a of the semiconductor substrate 101.

[0019] The first pixel separating structure PIS1 may be provided in the semiconductor substrate 101 by extending in a direction perpendicular to the first surface 100a of the semiconductor substrate 101 (i.e., the third direction D3). The first pixel separating structure PIS1 may be provided in a second trench T2 recessed from the first surface 100a of the semiconductor substrate 101.

[0020] The first pixel isolating structure PIS1 may penetrate a portion of the device isolation layer 105. The first pixel isolating structure PIS1 may define a plurality of pixel regions PR in the central region CR and a plurality of dummy pixel regions DPR in the edge region ER. Here, the first pixel isolating structure PIS1 may include a first portion extending side by side along a first direction D1 and a second portion extending side by side along a second direction D2 across the first portion. The first pixel isolating structure PIS1 may be continuously extended from the central region CR to the edge region ER along the first and second directions.

[0021] The first pixel separating structure PIS1 may surround each of the pixel regions PR and each of the dummy pixel regions DPR in a plan view. The pixel regions PR may be separated from each other in the first direction D1 and the second direction D2 by the first and second pixel separating structures PIS1, PIS2 in a central region CR. The dummy pixel regions DPR may be separated from each other in the first direction D1 and the second direction D2 by the first and second pixel separating structures PIS1, PIS2 in an edge region ER. That is, the pixel regions PR and the dummy pixel regions DPR may be two-dimensionally arranged along the first direction D1 and the second direction D2.

[0022] An upper surface of the first pixel isolating structure PIS1 may be substantially coplanar with the first surface 100a of the semiconductor substrate 101. An upper surface of the first pixel isolating structure PIS1 may be substantially coplanar with an upper surface of the device isolation film 105.

[0023] The first pixel separating structure PIS1 may have a bottom surface between the first surface 100a and the second surface 100b of the semiconductor substrate 101. The first pixel separating structure PIS1 may be spaced apart from the second surface 100b of the semiconductor substrate 101. The first pixel separating structure PIS1 may have a first top width at the first surface 100a of the semiconductor substrate 101 and a first bottom width at the bottom surface thereof. The first bottom width may be smaller than or substantially equal to the first top width. For example, the width of the first pixel separating structure PIS1 may gradually decrease from the first surface 100a to the second surface 100b of the semiconductor substrate 101. The first pixel separating structure PIS1 may have a first length in a direction perpendicular to the surface of the semiconductor substrate 101 (i.e., a third direction D3).

[0024] According to an embodiment, the first pixel separating structure PIS1 may include a liner insulating pattern 111, a liner semiconductor pattern 113, and a capping insulating pattern 115.

[0025] 3A in detail, the liner insulating pattern 111 may conformally cover an inner wall of the second trench T2 recessed from the first surface 100a of the semiconductor substrate 101. The liner insulating pattern 111 may be provided between the liner semiconductor pattern 113 and the semiconductor substrate 101. The liner insulating pattern 111 may be in direct contact with the semiconductor substrate 101. A bottom surface of the liner insulating pattern 111 may be in contact with the second pixel isolating structure PIS2. The bottom surface of the liner insulating pattern 111 may be in contact with a portion of the second pixel isolating structure PIS2.

[0026] The liner insulating pattern 111 may include a material having a lower refractive index than the semiconductor substrate 101. The liner insulating pattern 111 may include, for example, a silicon-based insulating material (e.g., silicon nitride, silicon oxide, and / or silicon oxynitride) and / or a high-k material (e.g., hafnium oxide and / or aluminum oxide). As another example, the liner insulating pattern 111 may include multiple layers, each of which may include different materials.

[0027] The liner semiconductor pattern 113 may fill a portion of the second trench T2 in which the liner insulating pattern 111 is provided. The liner semiconductor pattern 113 may conformally cover a portion of the liner insulating pattern 111. That is, the liner semiconductor pattern 113 may not be provided on an upper sidewall of the liner insulating pattern 111.

[0028] The liner semiconductor pattern 113 may include a sidewall portion and a bottom portion connecting the sidewall portion, and a gap region may be defined in the second trench T2 by the sidewall portion and the bottom portion. The bottom portion of the liner semiconductor pattern 113 may be adjacent to the second surface 100b of the semiconductor substrate 101. The upper surface of the sidewall portion of the liner semiconductor pattern 113 may be vertically spaced apart from the first surface 100a of the semiconductor substrate 101. For example, as shown in FIG. 3A, the upper surface of the sidewall portion of the liner semiconductor pattern 113 may be located at a lower level than the bottom surface of the device isolation layer 105 with respect to the first surface 100a of the semiconductor substrate 101. For another example, as shown in FIGS. 3H and 3I, the upper surface of the sidewall portion of the liner semiconductor pattern 113 may be located at a higher level than the bottom surface of the device isolation layer 105 with respect to the first surface 100a of the semiconductor substrate 101.

[0029] According to the embodiment, the sidewall of the liner semiconductor pattern 113 may have a first thickness D1 on the liner insulating pattern 111. Furthermore, an upper portion of the sidewall of the liner semiconductor pattern 113 may have a thickness that decreases toward the first surface 100a of the semiconductor substrate 101. That is, an upper portion of the sidewall of the liner semiconductor pattern 113 may have a sharp spacer shape.

[0030] The bottom of the liner semiconductor pattern 113 may have a second thickness D2 on the liner insulating pattern 111. Here, the second thickness D2 may be substantially equal to or smaller than the first thickness D1. Meanwhile, according to the embodiment illustrated in FIG 3B, the bottom of the liner semiconductor pattern 113 may have a second thickness D2 that is greater than the first thickness D1 of the sidewall portion.

[0031] A bottom of the liner semiconductor pattern 113 may be in contact with the liner insulating pattern 111. That is, a portion of the liner insulating pattern 111 may be disposed between a bottom of the liner semiconductor pattern 113 and the second pixel separating structure PIS2. Alternatively, referring to FIG 3C, a bottom of the liner semiconductor pattern 113 may be in contact with the second pixel separating structure PIS2.

[0032] 3E, the first pixel separating structure PIS1 may be vertically spaced apart from the second pixel separating structure PIS2. Thus, a bottom portion of the liner insulating pattern 111 may contact the semiconductor substrate 101. That is, a portion of the semiconductor substrate 101 may be present between the bottom surface of the liner insulating pattern 111 and the second pixel separating structure PIS2.

[0033] The liner semiconductor pattern 113 may include an undoped polysilicon layer or a polysilicon layer doped with impurities. The impurities in the liner semiconductor pattern 113 may have the same conductivity type as the semiconductor substrate 101. The impurities in the liner semiconductor pattern 113 may include at least one of boron (B), phosphorus (P), arsenic (As), gallium (Ga), indium (In), antimony (Sb), and aluminum (Al).

[0034] The liner semiconductor pattern 113 may be separated from the semiconductor substrate 101 by the liner insulating pattern 111. Therefore, the liner semiconductor pattern 113 may be electrically isolated from the semiconductor substrate 101 when the image sensor is in operation.

[0035] The liner semiconductor pattern 113 may have a single body provided over the entire pixel array region, i.e., the liner semiconductor pattern 113 may have a single body commonly provided over the central region and the edge region.

[0036] The liner semiconductor pattern 113 may be connected to a rear contact plug PLG at the edge region ER. A negative bias may be applied to the liner semiconductor pattern 113 through the contact pattern CT and the rear contact plug PLG. Therefore, dark current generated at the boundary between the first pixel isolation structure PIS1 and the semiconductor substrate 101 may be reduced.

[0037] The capping insulating pattern 115 may be disposed in a gap region defined by the liner semiconductor pattern 113. The capping insulating pattern 115 may cover the liner semiconductor pattern 113 and may cover an upper sidewall of the liner insulating pattern 111. The capping insulating pattern 115 may have an upper surface at substantially the same level as an upper surface of the device isolation layer 105. The capping insulating pattern 115 may include at least one of a silicon oxide layer, a silicon oxynitride layer, and a silicon nitride layer.

[0038] In addition, a potential barrier region PBR including impurities of a second conductivity type may be provided in the semiconductor substrate 101 adjacent to a sidewall of the first pixel isolation structure PIS1. The potential barrier region PBR may include impurities of the same conductivity type (e.g., p-type) as the semiconductor substrate 101. The concentration of the impurities doped in the potential barrier region PBR may be higher than the concentration of the impurities in the semiconductor substrate 101. The potential barrier region PBR may reduce generation of dark current due to electron-hole pairs (EHPs) generated by surface defects of the second trench T2 when the second trench T2 is formed.

[0039] According to the embodiment illustrated in Figures 3F, 3G, and 3I, the first pixel separating structure PIS1 may further include an air gap AG or a void defined within the gap region of the liner semiconductor pattern 113.

[0040] 3F in detail, a bottom surface of the capping insulating pattern 115 may be vertically spaced apart from a bottom portion of the liner semiconductor pattern 113 to define an air gap AG in a gap region of the liner semiconductor pattern 113. That is, a part of a sidewall portion and a bottom portion of the liner semiconductor pattern 113 may define the air gap AG. The bottom surface of the capping insulating pattern 115 may be located at a lower level or a higher level than an upper surface of the sidewall portion of the liner semiconductor pattern 113 based on the first surface 100a of the semiconductor substrate 101. Also, the bottom surface of the capping insulating pattern 115 may be rounded.

[0041] Referring to FIG. 3G, the capping insulating pattern 115 may cover the liner semiconductor pattern 113 with a non-uniform thickness, and an air gap AG surrounded by the capping insulating pattern 115 may be defined in the gap region of the liner semiconductor pattern 113.

[0042] 1 and 2, the second pixel isolating structure PIS2 may be provided in the semiconductor substrate 101 by extending in the vertical direction D3 from the second surface 100b of the semiconductor substrate 101. The second pixel isolating structure PIS2 may be provided in a third trench T3 recessed from the second surface 100b of the semiconductor substrate 101.

[0043] The second pixel separating structure PIS2 may have a bottom surface between the first surface 100a and the second surface 100b of the semiconductor substrate 101. That is, the second pixel separating structure PIS2 may be spaced apart from the first surface 100a of the semiconductor substrate 101. The second pixel separating structure PIS2 may be in contact with the first pixel separating structure PIS1.

[0044] The second pixel separating structure PIS2 may have a second upper width at the second surface 100b of the semiconductor substrate 101 and a second lower width at its bottom surface. The second lower width may be smaller than or substantially the same as the second upper width. The width of the second pixel separating structure PIS2 may gradually decrease from the second surface 100b to the first surface 100a of the semiconductor substrate 101.

[0045] The second pixel separating structure PIS2 may have substantially the same planar structure as the first pixel separating structure PIS1. The second pixel separating structure PIS2 may overlap the first pixel separating structure PIS1 in a planar view. That is, the second pixel separating structure PIS2 may include a first portion extending in the first direction D1 and a second portion intersecting the first portion and extending along the second direction D2.

[0046] The second pixel separating structure PIS2 may have a second length in the vertical direction D3, and the second length may be different from the first length of the first pixel separating structure PIS1. In one example, the second length of the second pixel separating structure PIS2 may be less than or substantially the same as the first length.

[0047] The second pixel isolation structure PIS2 may be formed of at least one high dielectric film having a higher dielectric constant than a silicon oxide film. For example, the second pixel isolation structure PIS2 may include a surface dielectric film 121 and a gap-fill dielectric film 123.

[0048] The surface dielectric layer 121 may cover the inner wall of the third trench T3 and the second surface 100b of the semiconductor substrate 101 with a uniform thickness. The gap-fill insulating layer 123 may fill the third trench T3 in which the surface dielectric layer 121 is formed, and may have a substantially flat upper surface on the second surface of the semiconductor substrate 101. The surface and gap-fill dielectric layers 121 and 123 may include a metal oxide or a metal fluoride including at least one metal selected from the group consisting of hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), titanium (Ti), yttrium (Y), and lanthanoid (La). For example, the surface dielectric layer 121 may include an aluminum oxide layer, and the gap-fill dielectric layer 123 may include a hafnium oxide layer.

[0049] 3A and 3B, the surface dielectric layer 121 of the second pixel isolating structure PIS2 may be in contact with the liner insulating pattern 111 of the first pixel isolating structure PIS1.

[0050] Referring to FIG. 3C, the surface dielectric layer 121 of the second pixel separating structure PIS2 may contact the bottom of the liner semiconductor pattern 113 of the first pixel separating structure PIS1.

[0051] 3D, the second pixel separating structure PIS2 may be disposed offset from the first pixel separating structure PIS1, in which case the second pixel separating structure PIS2 may contact a portion of a bottom surface of the first pixel separating structure PIS1.

[0052] 3E, the second pixel separating structure PIS2 may overlap and be vertically spaced apart from the first pixel separating structure PIS1, that is, a portion of the semiconductor substrate 101 may be present between the first pixel separating structure PIS1 and the second pixel separating structure PIS2.

[0053] 1 and 2, a photoelectric conversion region PD may be provided in the semiconductor substrate 101 of each pixel region PR. The photoelectric conversion region PD generates photocharges in proportion to the intensity of incident light. The photoelectric conversion region PD may be formed by ion-implanting impurities having a second conductivity type opposite to that of the semiconductor substrate 101 into the semiconductor substrate 101. A photodiode may be formed by a junction between the semiconductor substrate 101 of the first conductivity type and the photoelectric conversion region of the second conductivity type.

[0054] According to some embodiments, the photoelectric conversion region PD may have an impurity concentration difference between a region adjacent to the first surface 100a and a region adjacent to the second surface 100b so as to have a potential gradient between the first surface 100a and the second surface 100b of the semiconductor substrate 101. For example, the photoelectric conversion region PD may include multiple impurity regions vertically stacked.

[0055] In each of the pixel regions PR and the dummy pixel regions DPR, a transfer gate electrode TG may be disposed on the first surface 100a of the semiconductor substrate 101. The transfer gate electrode TG may be located in a central portion of each pixel region PR in a plan view. A portion of the transfer gate electrode TG may be disposed in the semiconductor substrate 101, and a gate insulating film GIL may be interposed between the transfer gate electrode TG and the semiconductor substrate 101.

[0056] A floating diffusion region FD may be provided in the semiconductor substrate 101 on one side of the transfer gate electrode TG. The floating diffusion region FD may be formed by ion-implanting an impurity of the opposite type into the semiconductor substrate 101. For example, the floating diffusion region FD may be an n-type impurity region.

[0057] A readout circuit layer 20 may be disposed on the first surface 100a of the semiconductor substrate 101. The readout circuit layer 20 may include a readout circuit coupled to the photoelectric conversion layer 10. The electrical signal converted by the photoelectric conversion layer 10 may be processed by the readout circuit layer 20.

[0058] In particular, the readout circuit layer 20 may include MOS transistors (eg, a reset transistor, a source follower transistor, and a select transistor).

[0059] An interlayer insulating film 210 can be stacked on the first surface 100a of the semiconductor substrate 101, and the interlayer insulating film 210 can cover the MOS transistor and the transfer gate electrode TG that configure the readout circuit. The interlayer insulating film 210 can include, for example, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0060] Wiring structures 221 and 222 connected to a read circuit may be disposed in the interlayer insulating film 210. The wiring structures 221 and 222 may include metal wirings 222 and contact plugs 221 connecting the metal wirings 222.

[0061] The light-transmitting layer 30 may be disposed on the second surface 100b of the semiconductor substrate 101. The light-transmitting layer 30 may include a lattice structure 310, a protective film 320, a color filter 330, a microlens 340, and a passivation film 350 in a central region CR. The light-transmitting layer 30 may include a light-shielding pattern OBP, a rear contact plug PLG, a contact pattern CT, an organic film 345, and a passivation film 350 in an edge region ER.

[0062] In detail, in the central region CR, the lattice structure 310 may be disposed on the upper surface of the gap-fill insulating film 123. The lattice structure 310 may have a lattice shape in a plan view, similar to the first and second pixel separating structures PIS1 and PIS2. The lattice structure 310 may overlap the first and second pixel separating structures PIS1 and PIS2 in a plan view. That is, the lattice structure 310 may include a first portion extending in a first direction D1 and a second portion extending in a second direction D2 across the first portion. The width of the lattice structure 310 may be substantially the same as or smaller than the minimum width of the first and second pixel separating structures PIS1 and PIS2.

[0063] The grating structure 310 may include a conductive pattern and / or a low refractive pattern. The conductive pattern may include a metal material such as titanium, tantalum, or tungsten. The low refractive pattern may be made of a material having a lower refractive index than the conductive pattern. The low refractive pattern may be made of an organic material and may have a refractive index of about 1.1 to 1.3. For example, the grating structure may be a polymer layer containing silica nanoparticles.

[0064] In the central region CR, the protective layer 320 may cover the surface of the lattice structure 320 with a substantially uniform thickness on the upper surface of the gap-fill insulating layer 123. The protective layer 320 may include at least one single layer or multiple layers selected from, for example, an aluminum oxide layer and a silicon oxycarbide layer.

[0065] In the central region CR, a color filter 330 may be provided on the protective film 320 corresponding to each of the pixel regions PR. The color filter 330 may include blue, red, and green color filters. As another example, the color filter 330 may include magenta, cyan, and yellow color filters. As another example, some of the color filters 330 may include a white color filter or an infrared filter.

[0066] A microlens 340 may be disposed on the color filter 330 corresponding to each pixel region PR. As another example, at least one of the microlenses 340 may be disposed on at least two color filters.

[0067] The microlenses 340 may be two-dimensionally arranged along first and second directions D1 and D2 intersecting each other. The microlenses 340 may have an upwardly convex shape and a predetermined radius of curvature. The microlenses 340 may change the path of light incident on the image sensor to condense the light. The microlenses 340 may be formed of a light-transmitting resin.

[0068] A passivation film 350 may conformally cover the upper surface of the microlens 340. The passivation film 350 may be formed of, for example, an inorganic oxide.

[0069] In the edge region ER, a back contact plug PLG may be connected to the liner semiconductor pattern 113 of the first pixel separating structure PIS1 by penetrating a portion of the second pixel separating structure PIS2 and a portion of the semiconductor substrate 101. When the image sensor operates, a negative bias voltage may be applied to the back contact plug PLG.

[0070] The back contact plug PLG may have a width greater than the width of the second pixel separating structure PIS2. The back contact plug PLG may penetrate a portion of the first portion and a portion of the second portion of the second pixel separating structure PIS2 that intersect with each other. A bottom surface of the back contact plug PLG may be spaced farther from the second surface 100b of the semiconductor substrate 101 than a bottom surface of the second pixel separating structure PIS2. That is, with reference to the second surface 100b of the semiconductor substrate 101, the bottom surface of the back contact plug PLG may be located at a lower level than a bottom surface of the second pixel separating structure PIS2.

[0071] The back contact plug PLG may include a metal and / or a metal nitride, for example, the back contact plug may include titanium and / or titanium nitride.

[0072] 4, the back contact plug PLG may conformally cover an inner wall of a contact hole formed by recessing the second surface 100b of the semiconductor substrate 101. The back contact plug PLG may contact a sidewall portion of the liner semiconductor pattern 113. In addition, when the first pixel separating structure PIS1 includes an air gap AG, a portion of the back contact plug PLG may be inserted into a portion of the gap region of the liner semiconductor pattern. Thus, the back contact plug PLG may contact a portion of an inner wall of the sidewall portion of the liner semiconductor pattern 113.

[0073] The contact pattern CT may be embedded in a contact hole in which the back contact plug PLG is formed. The contact pattern CT may include a different material from the back contact plug PLG. For example, the contact pattern CT may include aluminum (Al).

[0074] The contact pattern CT may be electrically connected to the liner semiconductor pattern 113 of the first pixel separating structure PIS1. A negative bias may be applied to the semiconductor pattern of the first pixel separating structure PIS1 through the contact pattern CT, and the negative bias may be transferred from the edge region ER to the center region CR.

[0075] In the edge region ER, the light-shielding pattern OBP may be continuously extended from the back contact plug PLG and disposed on an upper surface of the gap-fill insulating film 123 of the second pixel isolation structure PIS2. That is, the light-shielding pattern OBP may include the same material as the back contact plug PLG. The light-shielding pattern OBP may include metal and / or metal nitride. For example, the light-shielding pattern OBP may include titanium and / or titanium nitride. The light-shielding pattern OBP does not have to be extended to the central region ER of the pixel array.

[0076] A protective film 320 can cover the upper surface of the light blocking pattern OBP and the upper surface of the contact pattern CT.

[0077] An organic layer 345 and a passivation layer may be provided on the protective layer 320 in the edge region ER. The organic layer 345 may include the same material as the microlenses 340.

[0078] 5 to 14 are cross-sectional views taken along line II' of FIG. 1, illustrating a method of manufacturing an image sensor according to an embodiment of the present invention.

[0079] 1 and 5, a semiconductor substrate 101 of a first conductivity type (e.g., p-type) may be provided. The semiconductor substrate 101 may have a first surface 100a and a second surface 100b facing each other. The semiconductor substrate 101 may include a first conductivity type epitaxial layer formed on a first conductivity type bulk silicon substrate 100. Alternatively, the semiconductor substrate 101 may be a bulk semiconductor substrate including a well of the first conductivity type. As another example, the semiconductor substrate 101 may be a silicon on insulator (SOI) substrate, a germanium substrate, a germanium on insulator (GOI) substrate, or a silicon-germanium substrate.

[0080] The semiconductor substrate 101, i.e., the epitaxial layer, may be formed by selective epitaxial growth (SEG) using the bulk silicon substrate 100 as a seed, and may be doped with impurities of a first conductivity type during the epitaxial growth process. For example, the epitaxial layer may include p-type impurities.

[0081] A first trench T1 may be formed by patterning the first surface 100a of the semiconductor substrate 101. The first trench T1 may define active portions in each of the pixel regions PR and the dummy pixel region DPR.

[0082] The first trench T1 may be formed by forming a buffer layer BFL and a first mask pattern MP1 on the first surface 100a of the semiconductor substrate 101, and anisotropically etching the semiconductor substrate 101 using the first mask pattern MP1 as an etching mask.

[0083] The buffer layer BFL may be formed on the first surface 100a of the semiconductor substrate 101 by performing a deposition process or a thermal oxidation process. The buffer layer BFL may include a silicon oxide layer. The first mask pattern MP1 may include a silicon nitride layer or a silicon oxynitride layer. A bottom surface of the first trench T1 may be spaced apart from the first impurity region 110a.

[0084] Then, a buried insulating layer 103 may be formed to fill the first trench T1. The buried insulating layer 103 may be formed by thickly depositing an insulating material on the semiconductor substrate 101 in which the first trench T1 is formed. The buried insulating layer 103 may fill the first trench T1 and cover the first mask pattern MP1.

[0085] 1 and 6, a second trench T2 defining a pixel region PR and a dummy pixel region DPR may be formed by patterning a buried insulating layer 103 and a first surface 100a of a semiconductor substrate 101.

[0086] In detail, a second mask pattern MP2 is formed on the buried insulating layer 103, and the semiconductor substrate 101 is anisotropically etched using the second mask pattern MP2 as an etching mask, thereby forming the second trench T2.

[0087] The second trench T2 may be extended vertically from the first surface 100a to the second surface 100b of the semiconductor substrate 101 to expose a sidewall of the epitaxial layer. The second trench T2 may be formed deeper than the first trench T1 and may penetrate a portion of the first trench T1.

[0088] The second trench T2 may include a plurality of first regions extending in a first direction D1 in a planar view and having a uniform width, and a plurality of second regions extending in a second direction D2 intersecting the first direction D1 and having a uniform width.

[0089] By performing an anisotropic etching process to form the second trench T2, the width of the second trench T2 may gradually decrease from the first surface 100a to the second surface 100b of the semiconductor substrate 101. That is, the second trench T2 may have inclined sidewalls. The bottom surface of the second trench T2 may be spaced apart from the second surface 100b of the semiconductor substrate 101.

[0090] After forming the second trench T2, the second mask pattern MP2 may be removed. In addition, after forming the second trench T2, a potential barrier region (see PBR in FIG. 3A) containing a first conductivity type impurity may be formed along an inner wall of the second trench T2. As an example, the potential barrier region may contain p-type impurities.

[0091] 1 and 7, a liner insulating film 110 may be formed to conformally cover an inner wall of the second trench T2. The liner insulating film 110 may conformally cover an upper surface of the buried insulating film 103. The liner insulating film 110 may be deposited using a deposition method having excellent step coverage characteristics. The liner insulating film 110 may include, for example, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0092] 1 and 8, a liner semiconductor pattern 113 may be formed on a liner insulating film 110. Forming the liner semiconductor pattern 113 may include performing a liner semiconductor layer deposition process and a liner semiconductor layer etching process in-situ.

[0093] The liner semiconductor film may be formed using at least one of low pressure chemical vapor deposition (LP-CVD), plasma enhanced chemical vapor deposition (PE-CVD), or atomic layer deposition (ALD) techniques.

[0094] According to the embodiment, a source gas containing impurities of a first conductivity type may be used during the deposition process of the liner semiconductor layer. The source gas may include a first gas containing a silane-based compound and a second gas containing a compound containing the impurity, for example, boron (B). The first gas and the second gas may chemically react to form the liner semiconductor layer. The liner semiconductor layer thus formed may have a uniform impurity concentration regardless of position. The liner semiconductor layer may include polycrystalline silicon or amorphous silicon containing impurities of the first conductivity type.

[0095] For example, during the deposition process of the liner semiconductor film, SiH 4 (or Si 2 H 6 ) and BCl 3 (or B 2 H 6 ) can be used, and the deposition process can be performed at a low temperature of about 300 to 530°C.

[0096] During the etching process of the liner semiconductor layer, an etchant gas containing chlorine may be used. During the etching process of the liner semiconductor layer, the etching rate may be faster on the first surface 100a of the semiconductor substrate 101 than on the inner wall of the second trench T2. Therefore, the liner semiconductor layer may be etched on the first surface 100a of the semiconductor substrate 101 to expose the liner insulating film 110, and the liner semiconductor layer may remain in the second trench T2.

[0097] The deposition and etching process of the liner semiconductor layer may be repeatedly performed until the top surface of the liner semiconductor pattern 113 is positioned at a level lower than the bottom surface of the first trench T1. Alternatively, the deposition and etching process of the liner semiconductor layer may be repeatedly performed until the top surface of the liner semiconductor pattern 113 is positioned at a level lower than the first surface 100a of the semiconductor substrate 101 and higher than the bottom surface of the first trench T1.

[0098] The liner semiconductor pattern 113 thus formed may include a sidewall portion on the inner sidewall of the second trench T2 and a bottom portion on the bottom surface of the second trench T2. In addition, the sidewall portion of the liner semiconductor pattern 113 may have a spacer shape that is sharper toward the first surface 100a of the semiconductor substrate 101.

[0099] 1 and 9, a capping insulating layer 114 may be formed to fill the second trench T2 in which the liner semiconductor pattern 113 is formed.

[0100] The capping insulating film 114 may cover the liner insulating film 110 on the first surface 100a of the semiconductor substrate 101. The capping insulating film 114 may include, for example, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0101] The capping insulating layer 114 may be formed using a film-forming technique having aproperty of step coverage, such as chemical vapor deposition (CVD) or atomic layer deposition (ALD), etc. In this case, the capping insulating layer 114 may cover the sidewalls and bottom of the liner semiconductor pattern 113 in the second trench T2.

[0102] Alternatively, the capping insulating layer 114 may be formed using a deposition method having poor step coverage. For example, the capping insulating layer 114 may be formed using a physical vapor deposition method. In this case, the capping insulating layer 114 may be separated from the bottom of the liner semiconductor pattern 113 in the second trench T2 to form an air gap in the second trench T2, as shown in Figures 3F and 3G. By using a deposition process having poor step coverage, a portion of the bottom and sidewall of the liner semiconductor pattern 113 may be exposed to the air gap, as shown in Figure 3F.

[0103] Next, the liner insulating layer 110 and the capping insulating layer 114 are planarized to expose an upper surface of the first mask pattern MP1, so that a liner insulating pattern 111, a liner semiconductor pattern 113, and a capping insulating pattern 115 may be formed in the second trench T2 as shown in Fig. 10. Thus, a first pixel isolating structure PIS1 may be formed in the second trench T2.

[0104] After forming the first pixel isolation structure PIS1, the first mask pattern MP1 may be removed, and the buried insulating film 103 may be planarized to expose the first surface 100a of the semiconductor substrate 101, thereby forming the isolation film 105 in the first trench T1. Due to the planarization process that exposes the first surface 100a of the semiconductor substrate 101, the top surface of the first pixel isolation structure PIS1 and the top surface of the isolation film 105 may be substantially coplanar.

[0105] Next, referring to FIG. 10, a MOS transistor constituting a readout circuit may be formed on a first surface 100a of a semiconductor substrate 101.

[0106] In detail, the transfer gate electrode TG may be formed in each of the pixel region PR and the dummy pixel region DPR. Forming the transfer gate electrode TG includes patterning the semiconductor substrate 101 to form a gate recess region in each of the pixel region PR and the dummy pixel region DPR, forming a gate insulating film conformally covering an inner wall of the gate recess region, forming a gate conductive film filling the gate recess region, and patterning the gate conductive film.

[0107] Furthermore, when the gate conductive layer is patterned to form the transfer gate electrode TG, the gate electrode of the readout transistor may be formed in each of the pixel regions PR.

[0108] After forming the transfer gate electrode TG, a floating diffusion region FD may be formed on one side of the transfer gate electrode TG in the semiconductor substrate 101. The floating diffusion region FD may be formed by ion-implanting impurities of a second conductivity type. Furthermore, when forming the floating diffusion region FD, a source / drain impurity region of a read transistor may be formed.

[0109] An interlayer insulating film 210 , a contact plug 221 , and a connecting wire 223 may be formed on a first surface 100 a of the semiconductor substrate 101 .

[0110] The interlayer insulating film 210 may cover the transfer gate electrode TG and the first surface 100a of the semiconductor substrate 101. The interlayer insulating film 210 may be formed of a material having excellent gap fill properties and may be formed to have a planarized upper surface. For example, the interlayer insulating film 210 may be made of high density plasma (HDP), tonen silazane (TOSZ), spin on glass (SOG), undoped silica glass (USG), etc.

[0111] A contact plug 221 connected to the floating diffusion region FD or the read transistor may be formed in the interlayer insulating film 210. A connection wiring 223 may be formed between the interlayer insulating films 210. The wiring for electrical connection of the read transistor may be arranged without positional restrictions. The contact plug 221 and the connection wiring 223 may be formed of, for example, copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), molybdenum (Mo), tantalum (Ta), titanium nitride film (TiN), tantalum nitride film (TaN), zirconium nitride film (ZrN), tungsten nitride film (WN), and an alloy formed of a combination thereof.

[0112] 1 and 11, a thinning process for removing a portion of the semiconductor substrate 101 may be performed to reduce the vertical thickness of the semiconductor substrate 101. The thinning process includes grinding or polishing the second surface 100b of the semiconductor substrate 101 and anisotropic and isotropic etching. In order to thin the semiconductor substrate 101, the semiconductor substrate 101 may be turned upside down. A portion of the semiconductor substrate 101 may be removed by the grinding or polishing process, and then an anisotropic or isotropic etching process may be performed to remove surface defects of the remaining semiconductor substrate 101.

[0113] For example, the bulk silicon substrate 100 may be removed and a p-type epitaxial layer may remain by performing a thinning process on the semiconductor substrate 101. In an embodiment, the thickness of the semiconductor substrate 101 remaining after the thinning process may be about 8 μm to 15 μm.

[0114] Then, the second surface 100b of the semiconductor substrate 101 may be patterned to form a third trench T3.

[0115] The third trench T3 may be formed by forming a buffer layer BFL and a third mask pattern MP3 on the second surface 100b of the semiconductor substrate 101, and anisotropically etching the semiconductor substrate 101 using the third mask pattern MP3 as an etching mask.

[0116] The buffer layer BFL may be formed by performing a deposition process or a thermal oxidation process on the third surface 300a of the semiconductor substrate 101. The buffer layer BFL may include a silicon oxide layer. The third mask pattern MP3 may include a silicon nitride layer or a silicon oxynitride layer.

[0117] The third trench T3 may expose the first pixel isolating structure PIS1. The third trench T3 may expose the liner insulating film 110 or the liner semiconductor pattern 113 of the first pixel isolating structure PIS1.

[0118] 1 and 12, a surface dielectric layer 121 and a gap-fill dielectric layer 123 may be sequentially stacked in the third trench T3. By forming the surface dielectric layer 121 and the gap-fill dielectric layer 123, a second pixel isolation structure PIS2 may be formed in the third trench T3.

[0119] The surface dielectric film 121 may be conformally deposited on the surface of the third trench T3 and the second surface 100b of the semiconductor substrate 101. The surface dielectric film and the gap-fill dielectric film 121, 123 may be formed by performing an atomic layer deposition (ALD) process. The gap-fill dielectric film 123 may fill the third trench T3 in which the surface dielectric film 121 is formed, and may have a substantially flat upper surface on the second surface 100b of the semiconductor substrate 101. The surface and gap-fill dielectric films 121, 123 may include a metal oxide such as aluminum oxide and / or hafnium oxide. Furthermore, in the pad region R2, the surface and gap-fill dielectric films 121, 123 may conformally cover the inner wall of the pad trench PT.

[0120] 1 and 13, a contact hole may be formed in the edge region ER, penetrating a portion of the semiconductor substrate 101 and a portion of the second pixel separating structure to expose a portion of the semiconductor pattern of the first pixel separating structure PIS1.

[0121] A conductive layer may be deposited on the inner walls of the contact holes and on the top surface of the gap-fill dielectric layer 123. After depositing the conductive layer, a patterning process may be performed on the conductive layer to remove the conductive layer in the center region CR. Thus, a light-shielding pattern OBP and a back contact plug PLG may be formed in the edge region ER. The conductive layer may include a metal such as copper, tungsten, aluminum, titanium, tantalum, or an alloy thereof.

[0122] Then, a contact pattern CT may be filled into the contact hole in which the back contact plug PLG is formed. The contact pattern CT may include a conductive material different from that of the back contact plug PLG. For example, the contact pattern CT may include aluminum.

[0123] 1 and 14, a lattice structure 310 may be formed on an upper surface of the gap-fill dielectric layer 123. The lattice structure 310 may extend in a first direction D1 and a second direction D2 and have a lattice shape. The lattice structure 310 may be formed by sequentially depositing and patterning a conductive film and a low refractive index film. The lattice structure 310 may include a conductive pattern and / or a low refractive index pattern. The conductive pattern may include a metal material such as titanium, tantalum, or tungsten. The low refractive index pattern may be made of a material having a lower refractive index than the conductive pattern.

[0124] The protective layer 320 may be formed on the upper surface of the gap-fill dielectric layer 123 to cover the surface of the lattice structure 310 with a substantially uniform thickness. The protective layer 320 may extend from the central region CR to the edge region ER and cover the upper surface of the light-blocking pattern OBP and the upper surface of the contact pattern CT in the edge region ER. The protective layer 320 may include at least one single layer or multiple layers of, for example, an aluminum oxide layer and a silicon oxycarbide layer.

[0125] After forming the protective layer 320, a color filter 340 may be formed corresponding to each of the pixel regions PR. The color filter 340 may include blue, red, and green color filters.

[0126] 2, microlenses 340 may be formed on the color filters 330. The microlenses 340 may have a convex shape and a predetermined radius of curvature. The microlenses 340 may be formed of a light-transmitting resin.

[0127] After forming the microlens 340, a passivation film 350 may be formed to conformally cover the upper surface of the microlens 340. The passivation film 350 may be formed of, for example, an inorganic oxide.

[0128] 15 is a schematic plan view of an image sensor including a semiconductor device according to an embodiment of the present invention, and FIGS. 16 and 17 are cross-sectional views of the image sensor according to the embodiment of the present invention taken along the line of FIG.

[0129] 15 and 16, the image sensor may include a sensor chip 1 and a logic chip 2. The sensor chip 1 may include a pixel array region R1 and a pad region R2.

[0130] The pixel array region R1 may include a plurality of unit pixels P two-dimensionally arranged along a first direction D1 and a second direction D2 intersecting each other. Each of the unit pixels P may include a photoelectric conversion element and a readout element. An electrical signal generated by incident light may be output from each of the unit pixels P of the pixel array region R1.

[0131] The pixel array region R1 may include a light receiving region AR and a light blocking region OB. The light blocking region OB may surround the light receiving region AR in a plan view. In other words, the light blocking region OB may be disposed above, below, to the left and right of the light receiving region AR in a plan view. A reference pixel to which light is not incident is provided in the light blocking region OB, and the amount of charge sensed in the unit pixel P of the light receiving region AR may be compared with the amount of reference charge generated in the reference pixel P to calculate the size of an electrical signal sensed in the unit pixel P.

[0132] A plurality of conductive pads CP used for inputting and outputting control signals, photoelectric signals, etc. may be arranged in the pad region R2. The pad region R2 may surround the pixel array region R1 in a plan view to facilitate electrical connection with an external device. The conductive pads CP may input and output electrical signals generated in the unit pixels P to and from an external device.

[0133] The sensor chip 1 may include, in the vertical direction, a photoelectric conversion layer 10 between a readout circuit layer 20 and a light transmitting layer 30, as previously described.

[0134] As described above, the photoelectric conversion layer 10 of the sensor chip 1 may include a semiconductor substrate 101, first and second pixel isolation structures PIS1 and PIS2 defining a pixel region, and a photoelectric conversion region PD provided within the pixel region. Here, the semiconductor substrate 101 may correspond to the epitaxial layer of the embodiment described above.

[0135] In the light receiving area AR, the sensor chip 1 can include the same technical features as the image sensor described above.

[0136] First and second pixel separating structures PIS1 and PIS2 may be disposed in the light-shielding region OB in the semiconductor substrate 101. A portion of the first pixel separating structure PIS1 may be connected to the contact plug PLG in the light-shielding region OB.

[0137] The gap-fill dielectric layer 123 may extend from the light receiving region AR to the light blocking region OB and the pad region R2.

[0138] In the light-shielding region OB, a light-shielding pattern OBP may be disposed on the gap-fill dielectric layer 123. The light-shielding pattern OBP may block light from being incident on the photoelectric conversion region PD provided in the light-shielding region OB. In a reference pixel region of the light-shielding region OB, the photoelectric conversion region PD may output a noise signal instead of outputting a photoelectric signal. The noise signal may be generated by electrons generated by heat generation, dark current, or the like. The light-shielding pattern OBP may include a metal such as tungsten, copper, aluminum, or an alloy thereof.

[0139] The passivation layer 320 may extend from the active pixel sensor array region R1 to the pad region R2 and cover an upper surface of the light blocking pattern OBP.

[0140] A filtering film FL may cover the protective film 320 in the light-shielding region OB. The filtering film FL may block light of a different wavelength than the color filter 330. For example, the filtering film FL may block infrared light. The filtering film FL may include, but is not limited to, a blue color filter.

[0141] In the light-shielding region OB, the first through conductive pattern 510 may penetrate the semiconductor substrate 101 and be electrically connected to the metal wiring 221 of the readout circuit layer 20 and the wiring structure 1111 of the logic chip 2. The first through conductive pattern 510 may have a first bottom surface and a second bottom surface located at different levels. A first buried pattern 511 may be provided inside the first through conductive pattern 510. The first buried pattern 511 may include a low refractive index material and have insulating properties.

[0142] A conductive pad CP may be provided on the second surface 100b of the semiconductor substrate 101 in the pad region R2. The conductive pad CP may be embedded in the second surface 100b of the semiconductor substrate 101. As an example, the conductive pad CP may be provided in a pad trench formed on the second surface 100b of the semiconductor substrate 101 in the pad region R2. The conductive pad CP may include a metal such as aluminum, copper, tungsten, titanium, tantalum, or an alloy thereof. In a mounting process of the image sensor, a bonding wire may be bonded to the conductive pad CP. The conductive pad CP may be electrically connected to an external device through the bonding wire.

[0143] In the pad region R2, the second through conductive pattern 520 may penetrate the semiconductor substrate 101 and be electrically connected to the wiring structure 1111 of the logic chip 2. The second through conductive pattern 520 may extend onto the second surface 100b of the semiconductor substrate 101 and be electrically connected to the conductive pad CP. A portion of the second through conductive pattern 520 may cover a bottom surface and a sidewall of the conductive pad CP. A second buried pattern 521 may be provided inside the second through conductive pattern 520. The second buried pattern 521 may include a low refractive index material and have insulating properties. In the pad region R2, first and second pixel separating structures PIS1 and PIS2 may be provided around the second through conductive pattern 520.

[0144] The logic chip 2 may include a logic semiconductor substrate 1000, a logic circuit TR, a wiring structure 1111 connected to the logic circuit, and a logic interlayer insulating film 1100. The top layer of the logic interlayer insulating film 1100 may be bonded to the readout circuit layer 20 of the sensor chip 1. The logic chip 2 may be electrically connected to the sensor chip 1 through a first conductive through pattern 510 and a second conductive through pattern 520.

[0145] In the above embodiment, the sensor chip 1 and the logic chip 2 are electrically connected to each other through the first and second through conductive patterns, but the present invention is not limited thereto.

[0146] According to the embodiment shown in FIG. 17, the first and second through conductive patterns shown in FIG. 16 may be omitted, and the sensor chip and the logic chip may be electrically connected to each other by directly bonding bonding pads provided on the top metal layers of the sensor chip and the logic chip.

[0147] In detail, the sensor chip 1 of the image sensor may include a first bonding pad BP1 provided on the top metal layer of the readout circuit layer 20, and the logic chip 2 may include a second bonding pad BP2 provided on the top metal layer of the wiring structure 111. The first and second bonding pads BP1 and BP2 may include at least one of, for example, tungsten (W), aluminum (Al), copper (Cu), tungsten nitride (WN), tantalum nitride (TaN), and titanium nitride (TiN).

[0148] The first bonding pad BP1 of the sensor chip 1 and the second bonding pad BP2 of the logic chip 2 may be directly and electrically connected to each other by a hybrid bonding method. Hybrid bonding refers to bonding in which two components containing the same material are fused at their interface. For example, if the first and second bonding pads BP1 and BP2 are made of copper (Cu), they may be physically and electrically connected to each other by copper (Cu)-copper (Cu) bonding. In addition, the insulating film surface of the sensor chip 1 and the insulating film surface of the logic chip 2 may be joined by dielectric-dielectric bonding.

[0149] Although the embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention can be embodied in other specific forms without changing the technical concept or essential features of the present invention. Therefore, it should be understood that the embodiments described above are illustrative in all respects and are not limiting. [Explanation of symbols]

[0150] 10 Photoelectric conversion layer 20 Readout circuit layer 30 Light transmission layer 101 Semiconductor substrate 105 Element isolation film 310 Lattice structure 320 Protective film 330 Color Filter 340 Micro Lens 350 Passivation film 350 AG Air Gap CR center area DPR Dummy Pixel Area ER Edge Area FD Floating diffusion region GIL Gate insulating film PD Photoelectric conversion area PIS1, PIS2 pixel isolation structures PR Pixel Area TG Transfer gate electrode

Claims

1. a substrate having a first surface and a second surface opposed to each other; a first isolation structure disposed within a first trench extending perpendicularly from the first surface of the substrate and defining a plurality of pixel regions; a second isolation structure provided in a second trench extending perpendicularly from the second surface of the substrate and overlapping the first isolation structure in a first direction perpendicular to the first surface of the substrate; The first isolation structure is a first liner pattern defining a gap region in the first trench, the first liner pattern including a sidewall portion and a bottom portion connecting the sidewall portion in a first direction perpendicular to the first surface of the substrate; a second liner pattern disposed between the first liner pattern and the substrate; a capping insulating pattern provided in the gap region of the first liner pattern.

2. The image sensor of claim 1 , wherein the first isolation structure further comprises an air gap defined in the gap region by the capping insulating pattern.

3. the first isolation structure includes a plurality of first portions extending along a second direction in a plan view and a plurality of second portions intersecting the first portions in the plan view and extending along a third direction in the plan view; The image sensor of claim 1 , wherein the first liner pattern is continuously extended along the second direction and the third direction.

4. The image sensor of claim 1 , wherein a thickness of the bottom portion of the first liner pattern is substantially the same as or greater than a thickness of the sidewall portion.

5. the bottom of the first liner pattern is adjacent to the second isolation structure; The image sensor of claim 1 , wherein an upper portion of the sidewall of the first liner pattern has a thickness that decreases toward the first surface.

6. an isolation layer adjacent to the first surface of the substrate in each of the pixel regions; The image sensor of claim 1 , wherein an upper surface of the sidewall portion of the first liner pattern is located at a level between a bottom surface of the device isolation film and the second isolation structure.

7. an isolation layer adjacent to the first surface of the substrate in each of the pixel regions; The image sensor of claim 1 , wherein an upper surface of the sidewall portion of the first liner pattern is located at a level between a bottom surface of the isolation film and the first surface of the substrate.

8. The image sensor of claim 1 , wherein the first liner pattern contains impurities of a first conductivity type that is the same as that of the substrate.

9. a photoelectric conversion region provided in each of the pixel regions and including impurities of a second conductivity type; The image sensor according to claim 1 , wherein the sidewall portion of the first liner pattern surrounds each of the photoelectric conversion regions in a plan view.

10. the bottom of the first liner pattern is adjacent to the second isolation structure; The image sensor of claim 1 , further comprising a back contact plug penetrating a portion of the second isolation structure and connected to the first liner pattern.

11. 11. The image sensor of claim 1, wherein a portion of the second liner pattern is disposed between the second isolation structure and the bottom of the first liner pattern.

12. the first isolation structure has a maximum width at the first surface of the substrate in a second direction; The image sensor of claim 1 , wherein the second isolation structure has a maximum width at the second surface of the substrate in the second direction.

13. An image sensor as described in any one of claims 1 to 12, wherein a first vertical length of the first isolation structure in the first direction is greater than or substantially the same as a second vertical length of the second isolation structure in the first direction.

14. a substrate having a first surface and a second surface opposed to each other; a first isolation structure extending perpendicularly from the first surface of the substrate to surround each of the pixel regions, the first isolation structure including a first liner pattern having sidewall portions and a bottom portion connecting the sidewall portions; a second isolation structure extending perpendicularly from the second surface of the substrate and overlapping the first isolation structure in a first direction perpendicular to the first surface of the substrate; a back contact plug penetrating a portion of the second isolation structure and connected to the first liner pattern of the first isolation structure.

15. The image sensor of claim 14 , wherein the back contact plug contacts the sidewall of the first liner pattern.

16. 16. The image sensor of claim 14, wherein the back contact plug has a width in a second direction perpendicular to the first direction that is greater than a maximum width of the second isolation structure in the second direction.

17. the first isolation structure further includes a capping insulating pattern filling a gap region defined by a second liner pattern provided between the first liner pattern and the substrate and the bottom and sidewall portions of the first liner pattern, 17. The image sensor of claim 14, wherein a portion of the second liner pattern is disposed between the second isolation structure and the bottom of the first liner pattern.

18. an isolation layer adjacent to the first surface of the substrate in each of the pixel regions; The image sensor of claim 14 , wherein a top surface of the sidewall of the first liner pattern is vertically spaced apart from a bottom surface of the device isolation layer.

19. the first isolation structure includes a plurality of first portions extending along a second direction in a plan view and a plurality of second portions intersecting the first portions in the plan view and extending along a third direction in the plan view; The image sensor of claim 14 , wherein the first liner pattern is continuously extended along the second direction and the third direction.

20. a substrate of a first conductivity type having a first surface and a second surface opposed to each other; a first isolation structure extending vertically from the first surface of the substrate to surround each of the pixel regions, the first isolation structure including a first liner pattern including sidewall portions and a bottom portion connecting the sidewall portions, a second liner pattern between the substrate and the first liner pattern, and a capping insulating pattern on the first liner pattern; a second isolation structure extending perpendicularly from the second surface of the substrate and overlapping the first isolation structure; a photoelectric conversion region provided in the substrate in each of the pixel regions and including impurities of a second conductivity type; an isolation layer defining an active portion on the first surface of the substrate in each of the pixel regions and adjacent to the first surface of the substrate; a transfer gate electrode disposed in the active portion of each of the pixel regions; a back contact plug penetrating a portion of the second isolation structure and connected to the first liner pattern of the first isolation structure; a color filter corresponding to the pixel area on the second surface of the substrate; a grating structure disposed between the color filters and overlapping the second isolation structure; and a microlens over the color filter.

Images