Silicon carbide power device with integrated resistor and method of manufacturing the same

Abstract

To provide a silicon carbide power device which eliminates the problems of the prior art and includes integrated resistor having improved characteristics, and a method of manufacturing the same.SOLUTION: A silicon carbide power device (100) includes: a die (2) having a functional layer (4) of silicon carbide, an edge area (2a), and an active area (2b) surrounded by the edge area (2a); gate structures (3') formed on a top surface (4a) of the functional layer (4) in the active area (2b); and a gate contact pad (18) for biasing the gate structures (3'). The device also has an integrated resistor (30) including a doped region (32), of a first conductivity type (N+), arranged at the front surface (4a) of the functional layer (4) in the edge area (2a), and the integrated resistor (30) defines an insulation resistance value in the functional layer (4), interposed between the gate structures (3') and the gate contact pad (18).SELECTED DRAWING: Figure 2B

Description

[Technical Field]

[0001] The present invention relates to a silicon carbide power device with integrated resistors and a method for fabricating the same. [Background technology]

[0002] Electronic semiconductor devices are known, in particular MOSFET (Metal-Oxide Semiconductor Field Effect Transistor) transistors for power electronic applications, which are manufactured starting from silicon carbide substrates.

[0003] These devices are beneficial due to the favorable chemical and physical properties of silicon carbide. For example, silicon carbide has a wider bandgap than silicon, which is typically used in electronic devices. As a result, even at relatively small thicknesses, silicon carbide has a higher breakdown voltage than silicon, and can therefore be used effectively in high-voltage, high-power, and high-temperature applications.

[0004] In particular, silicon carbide having the hexagonal polytype (4H-SiC) can be used for power electronic applications due to its crystallographic properties and its large scale applicability.

[0005] In known manner, when using devices, in particular MOSFET transistors, for high power applications, the usual solution is to reduce the on-state resistance (so-called R ON The goal is to parallelize multiple devices to reduce the overall processing time.

[0006] However, this approach can create imbalances between parallel devices, resulting in a loss of efficiency.

[0007] To avoid such imbalance, it has been proposed to insert a resistor of appropriate value in series with the gate contact of the MOSFET device to add controlled resistance when biasing the gate structure of the MOSFET device.

[0008] In particular, the first known solutions contemplate the use of discrete resistors (i.e., not fabricated with integrated technology within the die of the MOSFET device during manufacturing) mounted separately on the printed circuit to which the MOSFET device is coupled.

[0009] Another known solution aims to integrate the series resistor within the die of the MOSFET device by fabricating it by photolithographic definition of a corresponding gate layer of polycrystalline silicon near the gate contact pad.

[0010] However, both of these solutions are not entirely satisfactory.

[0011] Introducing a series resistor before the gate contact with a discrete resistor has the disadvantage of higher manufacturing costs and loss of efficiency.

[0012] Solutions that aim to add photolithographically defined polysilicon resistors encounter problems of high variability between fabricated wafers and with operating temperature. Summary of the Invention [Problem to be solved by the invention]

[0013] SUMMARY OF THE INVENTION It is an object of the present invention to provide a silicon carbide power device with an integrated resistor having improved characteristics and a method for manufacturing the same, which overcomes the above-mentioned problems. [Means for solving the problem]

[0014] According to the present invention there is provided a silicon carbide device and method of manufacture as defined in the claims.

[0015] In order that the invention may be better understood, preferred embodiments thereof will now be described, purely by way of non-limiting example and with reference to the accompanying drawings, in which: [Brief explanation of the drawings]

[0016] [Figure 1A] 1 is a schematic plan view of a portion of a silicon carbide device of a known type; [Figure 1B] 1B is a cross-sectional view of a portion of the device of FIG. 1A taken along line II. [Figure 2A] 1 is a schematic plan view of a silicon carbide device according to one embodiment of the present invention. [Figure 2B] 2B is a cross-sectional view of a portion of the device of FIG. 2A taken along the line II-II. [Figure 3] 4 is a cross-sectional view of a portion of a silicon carbide device according to another embodiment of the present invention. [Figure 4] 3 is a cross-sectional view of a portion of a silicon carbide device according to another embodiment of the present invention. [Figure 5A] 2A and 2B at various steps in a manufacturing method of the present invention. [Figure 5B] 2A and 2B at various steps in a manufacturing method of the present invention. [Figure 5C] 2A and 2B at various steps in a manufacturing method of the present invention. [Figure 5D] 2A and 2B at various steps in a manufacturing method of the present invention. [Figure 5E] 2A and 2B at various steps in a manufacturing method of the present invention. [Figure 5F] 2A and 2B at various steps in a manufacturing method of the present invention. [Figure 5G]2A and 2B at various steps in a manufacturing method of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0017] As will be explained in detail below, one aspect of the present invention is directed to utilizing the special characteristics of the silicon carbide device manufacturing process for the integrated fabrication of the aforementioned series resistors.

[0018] In particular, the implanted doped regions in the silicon carbide substrate are fabricated prior to the definition of the active areas and the formation of the gate structures (and corresponding contact structures and metallization) because activation of the implanted doped regions occurs at high temperatures (approximately 1800°C) that are incompatible with any of the materials fabricated on the substrate.

[0019] This property allows doped regions to be positioned virtually anywhere desired within the silicon carbide substrate.

[0020] In accordance with one aspect of the present invention, this property is utilized to place appropriately doped regions at the edge regions of the device that are configured to provide an isolated resistor within the silicon carbide substrate.

[0021] In particular, this resistor is used as an integrated series resistor inserted before the gate contact of the device.

[0022] Referring to FIGS. 1A and 1B, a silicon carbide device is first shown (in a schematic and simplified plan view and corresponding cross-sectional view, respectively), and in particular a power MOSFET device of the standard type lacking the integrated series resistor discussed above, where the series resistor is provided in a manner not shown here, for example as a discrete component on a printed circuit board to which the MOSFET device is coupled.

[0023] The power MOSFET device 1 is constructed in a die 2 of semiconductor material made of silicon carbide. In plan view, the die 2 has a generally rectangular or square shape in the horizontal plane xy, the edges and corners of which correspond to the so-called scribe lines (one of which is indicated by LT in FIG. 1A) along which a starting wafer of semiconductor material is diced.

[0024] The die 2 has a top surface 4a and comprises a functional layer 4 (substrate or epitaxial layer formed on said substrate layer) of silicon carbide (SiC) having a first conductivity type, for example N-type.

[0025] A peripheral or edge area 2a adjacent the scribe line LT is configured in a functional layer 4 and is configured to house the edge termination structure of the power MOSFET device 1, and a central or active area 2b is also configured in the same functional layer 4 within which the power MOSFET device 1 is physically fabricated, comprising, in a known manner, a plurality of basic units or cells 3, in particular MOSFET transistors (for simplicity, only one of these basic cells 3 is shown in FIG. 1B).

[0026] In the case of a vertical conduction configuration, the functional layer 4 constitutes a common drain region for a plurality of basic units 3 forming the power MOSFET device 1. The edge termination structure described above includes a ring-shaped edge termination region 5 (hereinafter simply referred to as ring region 5), specifically a region lightly doped with a second conductivity type of P-type, formed within a surface portion of functional layer 4. Ring region 5 is configured within edge area 2a and completely surrounds (precisely forms a ring around) active area 2b.

[0027] A plurality of body wells 6 having the second conductivity type of P type, one for each basic unit 3 of the power MOSFET device 1, are provided in the active area 2b and on the surface of the functional layer 4.

[0028] Within each body well 6 are a plurality of source regions 8 having a first conductivity type of N-type and disposed below respective gate structures 3' and further configured to provide electrical contact to a common body and source metallization of the power MOSFET device 1. + A doped enhanced region 7 of the type (having a high dopant concentration) is provided.

[0029] In particular, in the overlap region between the active area 2b and the end area 2a, an outermost body well (designated 6') is formed. + It is connected to the ring region 5 by a doped connection region 9 which is highly doped in the type.

[0030] The power MOSFET device 1 further comprises a first thin dielectric layer 12 (e.g. made of silicon oxide) on the front surface 4a of the functional layer 4, starting from which the basic units 3 of the power MOSFET device 1 are formed in the active area 2b, and a thick oxide region 13 in the end area 2a above the ring region 5.

[0031] A gate layer 14 (made of polysilicon or other conductive material) present on the aforementioned first dielectric layer 12 and thick oxide region 13 is defined on the gate oxide region to provide an electrode region for the gate structure (designated 3') of the basic unit 3 of the power MOSFET device 1. The same gate layer 14 extends in a continuous manner over the thick oxide region 13 in the end area 2a.

[0032] A second dielectric layer 15 (e.g., made of field oxide) covers the aforementioned gate layer 14. This second dielectric layer 15 has openings 15' in the edge region 2a and is covered by gate contact pads 18 made of a metallic material, which contact the gate layer 14 through these openings 15'. The gate contact pads 18 are accessible from outside the power MOSFET device 1 and are electrically coupled by soldering to gate lines 17 for biasing the gate structure 3' of the power MOSFET device 1 and for carrying signals to and from it.

[0033] Furthermore, the second dielectric layer 15 and the aforementioned first dielectric layer 12 are overlapped and crossed in the active area 2b by a source metallization 16, which contacts and shorts out the body well 6 and the source regions 8 of the various basic units 3 of the power MOSFET device 1 to each other.

[0034] In particular, contact regions 19 , eg, silicide, provide electrical contact between source metallization 16 and source region 8 and body well 6 .

[0035] As particularly highlighted in FIG. 1A , the power MOSFET device 1 has a gate metallization 20, which is connected to the gate contact pad 18 in the edge area 2 a and has a linear extension in the active area 2 b (in the illustrated example, along the axis x of the horizontal xy plane), where it crosses the second dielectric layer 15 and contacts the gate structure 3′ of the basic unit 3 (in a manner not shown in detail, the same basic unit 3 typically has an extension orthogonal to the linear extension of the gate metallization 20, in the illustrated example, along the second axis y of the horizontal xy plane).

[0036] Referring now to Figures 2A and 2B, there is shown a silicon carbide device (again shown in schematic and simplified plan and cross-sectional views, as in Figures 1A and 1B above), and in particular a power MOSFET device 100 with an integrated series resistor before the gate contact.

[0037] Power MOSFET device 100 is generally constructed in a manner similar to that of power MOSFET device 1 described above (and therefore corresponding elements are given the same corresponding numerals), except that device 100 includes an integrated resistor 30 at and within end region 2 a, interposed between gate contact pad 18 and gate structure 3′ (which is also disposed in series with gate contact pad 18).

[0038] In detail, this integrated resistor 30 is produced by implanting dopant atoms, for example, N in the illustrated example, in the front surface 4a of the functional layer 4. + The doped region 32 is of the same type (having a high dopant concentration).

[0039] As shown in FIG. 2A, in one possible implementation, this doped region 32 may have a ring-like shape in plan view (in the aforementioned horizontal plane xy) with a horizontal extension that surrounds the aforementioned gate contact pad 18.

[0040] 2B, this doped region 32 is configured within an isolation well 34, which in the illustrated example has a P-type doping (similar to the previously described body well 6), located within ring region 5. In the illustrated embodiment, the thickness of isolation well 34 (along axis z, orthogonal to the previously described horizontal plane xy) is smaller than the corresponding thickness of ring region 5.

[0041] According to one aspect of the present invention, the aforementioned gate contact pad 18 does not in this case make direct contact with the gate layer 14, and the same gate contact pad 18 does not make direct connection with the gate metallization 20.

[0042] In fact, the gate contact pad 18 contacts the first ends of the integrated resistors 30 and of the corresponding doped regions 32 via respective first contact regions 36a, e.g., made of silicide, in openings 13' formed through the thick oxide region 13.

[0043] A second end of the same integrated resistor 30 and the corresponding doped region 32 are electrically connected to the aforementioned gate metallization 20 by respective second contact regions 36b, e.g., made of silicide, located in the same opening 13'.

[0044] The same gate metallization 20 contacts, in this case, the gate layer 14 through a single opening 15' that crosses the second dielectric layer 15 in the illustrated embodiment.

[0045] The gate line 17 is in this case in contact with the gate contact pad 18, underneath which the gate layer 14 is absent, but only the second dielectric layer 15 and the thick residue layer 13. In other words, the gate contact pad 18 is located directly on the dielectric region formed by the thick oxide region 13 and the second dielectric layer 15 for the entire horizontal extension of said dielectric region.

[0046] In fact, the aforementioned gate layer 14 stops in this embodiment in the initial region of the end section 2a before the aforementioned second end of the integrated resistor 30.

[0047] Furthermore, the gate contact pad 18 and the gate metallization 20 are electrically isolated and separated on the upper surface 4a of the substrate 4, in this case by the separating portion 38 of the second dielectric layer 15 previously described.

[0048] In this embodiment, the resistance value of the integrated resistor 30 can be, for example, in the range of 0.1 to 200 Ω.

[0049] As shown in FIG. 3, in an alternative embodiment of the power MOSFET device 100, the aforementioned doped regions 32 of the integrated resistor 30 are doped with P + A highly doped outermost body well 6' is formed in the aforementioned doped connection region 9 connecting the outermost body well 6' to the ring region 5.

[0050] In this case, this doped connection region 9 extends within the ring region 5 (in this example, along the first axis x) until it reaches the area dedicated for the formation of the integrated resistor 30.

[0051] In this embodiment, the resistance of integrated resistor 30 can be much higher than 200 ohms.

[0052] As shown in FIG. 4, in a further variant of the power MOSFET device 100, the doped region 32 of the integrated resistor 30 is formed directly in the ring region 5, without the presence of a dedicated well.

[0053] In this embodiment, the resistance value of integrated resistor 30 may be, for example, in the range of 0.001 to 0.1 ohms.

[0054] Referring initially to FIG. 5A, a process for fabricating power MOSFET device 100 will now be described with particular reference to the embodiment shown in FIGS. 2A and 2B (although it will be apparent that similar considerations can be replicated for the embodiment of FIGS. 3 and 4).

[0055] This manufacturing process deviates from a standard process flow (e.g., a flow for manufacturing a power MOSFET device 1 of the known type shown in FIGS. 1A and 1B) only with respect to forming the aforementioned integrated resistor 30 in the edge region 2 a, and therefore does not require any substantial modifications to the standard process flow.

[0056] In particular, as shown in FIG. 5A, a P-type body implant is first formed via a front mask 40 that is appropriately photolithographically patterned for formation in the functional layer 4 of body wells 6 in the active area 2b, including the outermost body well 6′ that is intended to be connected to the ring region 5 (which will be formed later).

[0057] According to one aspect of the invention, during this implantation step and through the same front mask 40, an isolation well 34 is also formed in the edge region 2a with P-type doping (similar to the body well 6 previously described).

[0058] 5B, a N SiO 2 layer is then formed through a front mask 40 with different appropriate patterning to provide source regions 8 in the active areas 2b within each body well 6. + Form a source implant in the mold.

[0059] According to one aspect of the invention, in this implementation step and through the same front mask 40, doped regions 32 of integrated resistors 30 are also formed in the end areas 2a, in this case in the insulating wells 34.

[0060] 5C, through a front mask 40 and with different appropriate patterning, P + Form an implant of the same type (with a higher doping than that of the body well 6).

[0061] Then, referring to FIG. 5D, through a front mask 40, with different appropriate patterning, a P-type implant is formed with a lower doping (lower than that of the body well 6) to provide a ring region 5, which, according to the present solution, surrounds the aforementioned isolation well 34 in the end area 2a, in which the doped region 32 of the integrated resistor 30 is formed.

[0062] The fabrication process proceeds with the removal of the front mask 40 and activation of the previously implanted dopants by heating, particularly at high temperatures (approximately 1800° C.).

[0063] 5E, gate structures 3' of basic units 3 of power MOSFET devices 1 are then formed in active areas 2b by forming and appropriate photolithographic patterning a first dielectric layer 12, a gate layer 14, and a second dielectric layer 15. Silicide contact regions 19 are also formed in each body well 6. According to one aspect of the invention, during the same process step, in end area 2a, thick oxide region 13 and then gate layer and second dielectric layer 15 are photolithographically defined to form openings 13' in which first and second contact regions 36a, 36b of silicide are formed in contact with the first and second ends, respectively, of doped region 32. The first and second contact regions 36a, 36b are separated and electrically isolated by isolation portion 38 of second dielectric layer 15 described above.

[0064] Next, referring to FIG. 5F, a single opening 15′ is defined via a photolithographic process across the second dielectric layer 15 to access the underlying gate layer 14 at the beginning of the edge region 2a, in front of the aforementioned second contact region 36b.

[0065] Referring now to FIG. 5G, the fabrication process proceeds with the deposition of a metal layer, for example of aluminum silicon copper alloy (AlSiCu), and photolithographic definition of that metal layer to form the aforementioned gate contact pad 18, gate source metallization 16, and gate metallization 20.

[0066] The result is the power MOSFET device 100 shown in Figure 5G and Figures 2A and 2B.

[0067] The advantages of the present invention are clear from the above description. In any event, the present invention makes it possible to improve the efficiency, performance and reliability of power devices, particularly MOSFET devices, constructed starting from a silicon carbide substrate.

[0068] In particular, the present invention makes it possible to obtain an integrated resistor in series with the gate contact, whose resistance is very precise and controllable, controlled by the properties of the implanted N-type silicon carbide, and whose temperature behavior is in particular controlled by its very stable physical properties.

[0069] This resistance value has very little variation across manufacturing batches and from die to die.

[0070] Advantageously, the resistance can be precisely controlled as a function of the geometry of the doped region 32; for example, the doped region 32 may not have a complete ring-like configuration, as shown in Figure 2A, but may be limited to only some portions of the same ring. Furthermore, as mentioned above, the resistance can be adjusted by varying the confined and isolated arrangement of the same doped region 32 within a region having a low or high dopant concentration (to have low and high resistances, respectively, as previously emphasized in connection with the variations of Figures 3 and 4).

[0071] Advantageously, the present invention does not require any additional steps in the manufacturing process, and only limited modifications to standard manufacturing process steps are required.

[0072] Additionally, it is advantageous to be able to bond the electrical gate line 17 to the gate contact pad 18 in some areas without the underlying polysilicon (thereby limiting the defectivity of the gate layer 14).

[0073] Thus, MOSFET transistor devices constructed in accordance with the present invention may find effective use in a variety of applications, such as power supplies and UPS with power factor correction (PFC), photovoltaic systems, energy distribution systems, industrial engines, and electric vehicles.

[0074] Finally, it is of course possible to make various modifications and variations without departing from the spirit and scope of the present invention. In particular, it is emphasized that the present invention may find advantageous application in different silicon carbide MOSFET transistor devices, for example, VDMOS signal or power devices, IGBTs (comprising MOSFET transistors), IP (intelligent power) MOSFET devices, for example, in both N-channel and P-channel MOSFET transistors for automotive applications.

Claims

1. In a silicon carbide power device (100), a functional layer (4) made of silicon carbide, comprising an end region (2a) and an active region (2b) surrounded by said end region (2a); a gate structure (3') formed on the upper surface (4a) of the functional layer (4) in the active area (2b); A gate contact pad (18) for biasing the gate structure (3'). and further comprising: In the end region (2a), a first conductivity type (N ＋ an integrated resistor (30) including a doped region (32) of It has The device is characterized in that the integrated resistor (30) is interposed between the gate contact pad (18) and the gate structure (3') to define an insulation resistance value within the functional layer (4).

2. 2. The device of claim 1, wherein the gate contact pad (18) further comprises a gate metallization (20) disposed in the end area (2a) and electrically contacting first ends of the doped regions (32) through respective first contact regions (36a), and configured to contact the gate structure (3') in the active area (2b) and electrically contact second ends of the doped regions (32) through respective second contact regions (36b).

3. 3. The device according to claim 2, further comprising an end termination region (5) in the end area (2a) constituted by a doped region having a second conductivity type (P) and a first doping level, the end termination region (5) being arranged adjacent to the upper surface (4a) of the functional layer (4).

4. 4. The device of claim 3, wherein the doped region (32) is confined within an isolation well (34) having a second conductivity type (P) and a second doping level higher than the first doping level, the isolation well (34) being disposed within the edge termination region (5).

5. 4. The device of claim 3, wherein the doped region (32) is confined within the edge termination region (5).

6. The device described in claim 3, further comprising a body well (6) having a second conductivity type within the active area (2b) and formed in the functional layer (4), wherein the end termination region (5) is connected to the body well (6') located closer to the end area (2a) and further outward with respect to the active area (2b) by a doped connection region (9) having the second conductivity type and having a third doping level higher than the first doping level, and wherein the doped region (32) is confined within the doped connection region (9).

7. A device described in any one of claims 2-6, having an outer dielectric region (13, 15) arranged on the upper surface (4a) of the functional layer (4) in the end region (2a), an opening (13') traversing the outer dielectric region (13, 15), and the first and second contact regions (36a, 36b) being electrically isolated from each other and arranged in the opening (13').

8. 8. The device of claim 7, wherein the gate contact pad (18) is disposed directly on the outer dielectric region (13, 15) over its entire horizontal extension.

9. A device as described in claim 7, having a conductive gate layer (14) connected to the gate structure (3') in the active area (2b) and extending to the end area (2a) and terminating before the opening (13').

10. 3. The device of claim 2, wherein the doped region (32) has a ring extension around the gate contact pad (18) in a horizontal plane (xy) parallel to the upper surface (4a) of the functional layer (4).

11. 2. The device according to claim 1, further comprising a plurality of MOSFET transistor basic units (3) arranged in the active area (2b), each of which has a respective one of the gate structures (3'), a respective body well (6) having the second conductivity type formed in the functional layer (4), and at least one respective source region (8) having the first conductivity type formed in the body well (6) below each of the gate structures (3').

12. A method of manufacturing a silicon carbide power device (100), comprising: forming a functional layer (4) made of silicon carbide, the functional layer (4) including an end region (2a) and an active region (2b) surrounded by the end region (2a); forming a gate structure (3') on the upper surface (4a) of said functional layer (4) in said active area (2b); forming a gate contact pad (18) for biasing the gate structure (3'); A first conductivity type (N) conductive layer (N) is disposed on the upper surface (4a) of the functional layer (4) in the end area (2a) and interposed between the gate contact pad (18) and the gate structure (3'). ＋ forming an integrated resistor (30) including a doped region (32) of the functional layer (4), the integrated resistor (30) defining an insulation resistance value in the functional layer (4).

13. Forming the integrated resistor (30) includes forming the first conductivity type (N ＋ 13. The method of claim 12, further comprising: implanting a dopant of 0.1% to 0.2% by volume; and thermally activating the dopant before forming the gate structure (3').

14. 14. A method according to claim 12 or 13, comprising forming a body well (6) having a second conductivity type (P) and a first doping level in the functional layer (4) in the active area (2b), and a source region (8) having the first conductivity type in the body well (6) below each of the gate structures (3'), the doped region (32) and the source region (8) being formed in the same dopant implantation step.

15. 15. The method of claim 14, wherein forming the doped region (32) includes forming the doped region such that the doped region is confined within an isolation well (34) having doping of the second conductivity type (P), the isolation well (34) and the body well (6) being formed in the same respective dopant implantation step.

16. 15. The method of claim 14, further comprising forming an end termination region (5) in the end area (2a) constituted by a doped region arranged adjacent to the front surface (4a) of the functional layer (4) and having a second doping level lower than the first doping level and of the second conductivity type (P).

17. 17. The method of claim 16, wherein forming the doped region (32) comprises forming the doped region (32) such that the doped region is confined within the edge termination region (5).

18. 17. The method of claim 16, further comprising forming a doped connection region (9) having a third doping level higher than the first doping level and of the second conductivity type to connect the end termination region (5) to a body well (6') located closer to the end area (2a) and further outward with respect to the active area (2b), wherein forming the doped region (32) comprises forming the doped region (32) such that the doped region is confined within the doped connection region (9).

19. 13. The method of claim 12, further comprising forming the gate contact pads (18) in the end areas (2 a), wherein forming the gate contact pads (18) comprises electrically connecting to first ends of the doped regions (32) through respective first contact regions (36 a), and further comprising forming a gate metallization (20) configured to contact the gate structure (3′) in the active area (2 b) and to contact second ends of the doped regions (32) through respective second contact regions (36 b).

20. A method as described in claim 19, comprising forming an outer dielectric region (13, 15) on the upper surface (4a) of the functional layer (4) in the end region (2a), and forming an opening (13') through the outer dielectric region (13, 15), wherein the first and second contact regions (36a, 36b) are electrically isolated from each other and positioned in the opening (13').

Images