Semiconductor device and method for manufacturing the same

Abstract

To provide a method for manufacturing a semiconductor device capable of improving a word line interference phenomenon between adjacent cells.SOLUTION: A semiconductor device according to an embodiment comprises: an element separation layer demarcating a plurality of active regions on a substrate and including a first region in which the active regions are separated at a first interval along a first direction and a second region in which the active regions are separated at a second interval wider than the first interval along the first direction; a gate trench extending in the first direction so as to cross the active regions and the element separation layer; and an embedded word line for gap-filling the gate trench. The first region of the element separation layer located in a lower part of the gate trench is composed of a first insulation layer, and the second region of the element separation layer located in the lower part of the gate trench may be composed of a lamination structure of the first insulation layer and a second insulation layer.SELECTED DRAWING: Figure 2A

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device having an embedded gate and a method for manufacturing the same.

Background Art

[0002] In order to improve the integration degree of semiconductor elements, semiconductor elements having a structure in which word lines are embedded in a substrate have been studied.

Summary of the Invention

Problems to be Solved by the Invention

[0003] Embodiments of the present invention provide a method for manufacturing a semiconductor device capable of improving the word line interference phenomenon between adjacent cells.

Means for Solving the Problems

[0004] The semiconductor device according to the present embodiment defines a plurality of active regions in a substrate, and an element isolation layer including a first region in which the active regions are separated at a first interval along a first direction, and a second region in which the active regions are separated at a second interval wider than the first interval along the first direction, a gate trench extending in the first direction so as to cross the active region and the element isolation layer, and an embedded word line filling the gap of the gate trench. The first region of the element isolation layer located below the gate trench is composed of a first insulating layer, and the second region of the element isolation layer located below the gate trench can be composed of a stacked structure of a first insulating layer and a second insulating layer.

[0005] A method for manufacturing a semiconductor device according to this embodiment includes the steps of defining a plurality of active regions on a substrate, forming an element isolation layer including a first region in which the active regions are spaced apart at a first interval along a first direction, and a second region in which the active regions are spaced apart at a second interval wider than the first interval along the first direction, forming a gate trench extending in the first direction so as to cross the active regions and the element isolation layer, and forming an embedded word line to gap-fill the gate trench, wherein the first region of the element isolation layer located below the gate trench is composed of a first insulating layer, and the second region of the element isolation layer located below the gate trench is composed of a laminated structure of the first insulating layer and the second insulating layer. [Effects of the Invention]

[0006] This technology has the effect of improving the reliability of semiconductor devices by improving word line interference between adjacent cells. [Brief explanation of the drawing]

[0007] [Figure 1] This is a plan view of the semiconductor device according to this embodiment. [Figure 2A] This is a cross-sectional view showing a semiconductor device according to this embodiment. [Figure 2B] This is a cross-sectional view showing a semiconductor device according to this embodiment. [Figure 3] This is a cross-sectional view showing a semiconductor device according to this embodiment. [Figure 4] This is a cross-sectional view showing a semiconductor device according to this embodiment. [Figure 5A] This is a cross-sectional view illustrating the manufacturing method of a semiconductor device according to this embodiment. [Figure 5B] This is a cross-sectional view illustrating the manufacturing method of a semiconductor device according to this embodiment. [Figure 5C] This is a cross-sectional view illustrating the manufacturing method of a semiconductor device according to this embodiment. [Figure 5D] This is a cross-sectional view illustrating the manufacturing method of a semiconductor device according to this embodiment. [Figure 5E] This is a cross-sectional view illustrating the manufacturing method of a semiconductor device according to this embodiment. [Figure 5F] This is a cross-sectional view illustrating the manufacturing method of a semiconductor device according to this embodiment. [Figure 5G] This is a cross-sectional view illustrating the manufacturing method of a semiconductor device according to this embodiment. [Figure 5H] This is a cross-sectional view illustrating the manufacturing method of a semiconductor device according to this embodiment. [Figure 6A] Figure 3 is a cross-sectional view illustrating the manufacturing method of the semiconductor device shown. [Figure 6B] Figure 3 is a cross-sectional view illustrating the manufacturing method of the semiconductor device shown. [Figure 6C] Figure 3 is a cross-sectional view illustrating the manufacturing method of the semiconductor device shown. [Figure 6D] Figure 3 is a cross-sectional view illustrating the manufacturing method of the semiconductor device shown. [Figure 7A] Figure 4 is a cross-sectional view illustrating the manufacturing method of the semiconductor device shown. [Figure 7B] Figure 4 is a cross-sectional view illustrating the manufacturing method of the semiconductor device shown. [Figure 7C] Figure 4 is a cross-sectional view illustrating the manufacturing method of the semiconductor device shown. [Figure 7D] Figure 4 is a cross-sectional view illustrating the manufacturing method of the semiconductor device shown. [Figure 7E] Figure 4 is a cross-sectional view illustrating the manufacturing method of the semiconductor device shown. [Modes for carrying out the invention]

[0008] The embodiments described herein will be described with reference to cross-sectional views, plan views, and block diagrams which are ideal schematic views of the present invention. Therefore, the form of the illustrated diagrams may be deformed due to manufacturing technology and / or tolerances, etc. Therefore, the embodiments of the present invention are not limited to the specific forms shown, and also include changes in the form generated by the manufacturing process. Therefore, the regions illustrated in the drawings have schematic attributes, and the shapes of the regions illustrated in the drawings are for exemplifying the specific forms of the regions of the elements, and are not for limiting the scope of the invention. The sizes and relative sizes of the components shown in the drawings may be exaggerated for clarity of explanation. Throughout the specification, the same reference numerals denote the same components, and "and / or" includes each of the recited items and all combinations of one or more.

[0009] When an element or layer is referred to as "on" or "above" another element or layer, it includes not only directly above the other element or layer, but also all cases where other layers or other elements are interposed therebetween. The terms used herein are for explaining the embodiments and the like, and are not intended to limit the present invention. In this specification, the singular form includes the plural form as well, unless otherwise specifically stated in the text.

[0010] FIG. 1 is a plan view of a semiconductor device according to this embodiment. FIGS. 2A and 2B are cross-sectional views showing the semiconductor device according to this embodiment. FIG. 2A is a cross-sectional view taken along the line A-A' of FIG. 1, and FIG. 2B is a cross-sectional view taken along the line B-B' of FIG. 1. FIGS. 3 and 4 are cross-sectional views showing the semiconductor device according to this embodiment. FIGS. 3 and 4 are cross-sectional views taken along the line A-A' of FIG. 1.

[0011] As shown in FIGS. 1, 2A, and 2B, the semiconductor device according to this embodiment can include a substrate 101 including an active region 103 and an element isolation layer 102, and a gate structure BG formed in the substrate 101. Further, it can include a bit line BL and a capacitor Cap formed on the substrate 101.

[0012] The substrate 101 can be a material suitable for semiconductor processing. The substrate 101 can include a semiconductor substrate. The substrate 101 can be made of a material containing silicon. The substrate 101 can include silicon, single-crystalline silicon, polysilicon, amorphous silicon, silicon germanium, single-crystalline silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, combinations thereof, or multilayers thereof. The substrate 101 can also include other semiconductor materials such as germanium. The substrate 101 can also include a III / V group semiconductor substrate, for example, a compound semiconductor substrate such as GaAs. The substrate 101 can also include an SOI (Silicon On Insulator) substrate.

[0013] The active region 103 defined by the element isolation layer 102 is formed to have a major axis and a minor axis and can be two-dimensionally arranged along the major axis direction and the minor axis direction. For example, the active region 103 can have a bar form with a length longer than the width and can be arranged in an island form.

[0014] The element isolation layer 102 can include element isolation trenches 102T that limit a plurality of active regions 103 in the substrate 101 and an insulating layer that fills the gaps in the element isolation trenches 102T. The element isolation layer 102 can have a difference between an insulating structure that fills the gaps in the element isolation trenches 102T overlapping with the field trench 105F and an insulating structure that fills the gaps in the element isolation trenches 102T in the region excluding the field trench 105F. The field trench 105F can refer to a gate trench 105 formed in the element isolation trench 102T.

[0015] An isolation insulating layer 102R can be gap-filled in the element isolation trench 102T in the region excluding the field trench 105F. The upper surface of the isolation insulating layer 102R can be at the same level as the upper surface of the substrate 101. The insulating structure gap-filled in the element isolation trench 102T overlapping with the field trench 105F can be an insulating structure formed in a first region R1 where the active regions 103 are spaced apart by a first interval along the first direction D1, or an insulating structure formed in a second region R2 where the active regions 103 are spaced apart by a second interval wider than the first interval along the first direction D1. In the first region R1 and the second region R2, a first insulating layer 102L can be gap-filled to a first height. In the second region R2, a second insulating layer 102U can be locally formed on the first insulating layer 102L. The isolation insulating layer 102R and the first insulating layer 102L can be continuous. The isolation insulating layer 102R and the first insulating layer 102L may contain the same material formed by the same process.

[0016] In other words, the element isolation layer 102 may include an isolation insulating layer 102R gap-filled in the element isolation trench 102T, a first insulating layer 102L gap-filled to a first height in the first region R1 and the second region R2 of the element isolation trench 102T that overlap with the field trench 105F, and a second insulating layer 102U locally formed on the first insulating layer 102L in the second region R2.

[0017] The upper surface of the first insulating layer 102L may be located at a lower level than the upper surface of the active region 103. The active region 103 protruding between the first insulating layers 102L may be referred to as a "fin 103F". The first insulating layer 102L may be gap-filled in the element isolation trench 102T and formed so that its sidewalls are in contact with the active region 103. The first insulating layer 102L may include, for example, silicon oxide.

[0018] The second insulating layer 102U can be locally formed on the first insulating layer 102L, which is gap-filled in the second region R2 of the element isolation trench. The second insulating layer 102U can be formed to have a width smaller than the width of the second region R2. That is, the width W2 of the second insulating layer 102U can be formed to be smaller than the width W1 of the first insulating layer 102L formed in the second region R2 (W1 > W2). The sidewalls of the second insulating layer 102U can be spaced apart from the sidewalls of adjacent active regions 103. In the second region R2, the first insulating layer 102L can be exposed between the second insulating layer 102U and the adjacent active region 103. Therefore, both the active regions 103 adjacent to the first region R1 and the second region R2 can have fins 103F of the same height formed by the first insulating layer 102L, which is located at a lower level than the upper surface of the active region 103. The second insulating layer 102U may include, for example, silicon oxide. The second insulating layer 102U may contain the same material as the first insulating layer, or it may contain other materials.

[0019] The upper surface of the second insulating layer 102U can be located at a higher level than the upper surface of the first insulating layer 102L. That is, the upper surface of the element isolation layer 102 formed in the first region R1 can be located at a lower level than the upper surface of the element isolation layer 102 formed in the second region R2. In this embodiment, the upper surface of the second insulating layer 102U can be located at a lower level than the upper surface of the active region 103.

[0020] In another embodiment, as shown in Figure 3, the upper surface of the second insulating layer 202U can be located at the same level as the upper surface of the active region 103.

[0021] In yet another embodiment, as shown in Figure 4, the upper surface of the second insulating layer 302U can be located at a higher level than the upper surface of the active region 103.

[0022] The word line WL may extend in a first direction D1 across the active region 103, and the bit line BL may extend in a second direction D2 intersecting the first direction D1. The first direction D1 and the second direction D2 may intersect perpendicularly.

[0023] The active region 103 is positioned at a predetermined angle with respect to the word lines 109 (WL1, WL2) and the bit line BL, so that one active region 103 can intersect with two word lines WL and one bit line BL. Therefore, one active region 103 has two unit cell structures, and one unit cell has a length of 2F in the first direction D1 and a length of 4F in the second direction, based on the minimum line width, so that the area of ​​the unit cell is 6F2. Here, F is the minimum line width size (minimum feature size).

[0024] In the 6F2 cell structure, the word line WL and the bit line BL intersect perpendicularly and are inclined diagonally with respect to the word line WL and the bit line BL in order to minimize the cell area. The semiconductor device according to this embodiment is not limited to the 6F2 cell structure and may include any cell structure that can improve the integration density of the semiconductor device.

[0025] The gate structure BG may include a gate trench 105 formed in the substrate 101, a gate insulating layer 108 uniformly formed on the inner wall of the gate trench 105, a word line 109 filling a portion of the gate trench 105, and a gate caffing layer 110 filling the rest of the gate trench 105 on the word line 109.

[0026] The word line 109 is formed by buried gate lines, thereby realizing a buried channel transistor. Compared to planar transistors, buried channel transistors can reduce the unit cell area and increase the effective channel length. Furthermore, because the word line 109 is embedded within the substrate 101, the capacitance between the word line 109 and the bit line BL, as well as the overall bit line capacitance, can be reduced, thereby decreasing parasitic capacitance.

[0027] The gate trench 105 may comprise an active trench 105A that crosses the active region 103 and a field trench 105F formed within the element isolation layer 102. The gate trench 105 may extend continuously from the active trench 105A to the field trench 105F.

[0028] The word line 109 may include an active gate electrode 109A in the active trench 105A and a field gate electrode 109P in the field trench 105F. The upper surfaces of the active gate electrode 109A and the field gate electrode 109P may be located at the same level within the active region 103 and the element isolation layer 102. The word line 109 may include a fin gate electrode 109F formed within a fin 103F along a first direction D1. The fin 103F may be formed on both sides of the active region 103 along the first direction. That is, the fin 103F may be formed in a second region R2 between the active region 103 and the field trench 105F, while being formed within a first region R1 of the element isolation layer 102.

[0029] The depth H3 of the fin gate electrode 109F can be greater than the depth of the field gate electrode 109P. The bottom surface of the fin gate electrode 109F can be located at a lower level than the bottom surface of the field gate electrode 109P. The bottom surface of the fin gate electrode 109F can be located at a lower level than the bottom surface of the active gate electrode 109A in the first region R1 of the element isolation layer 102 where word line interference between adjacent cells does not occur. Therefore, the fin gate electrode 109F can ensure sufficient channel length, increase the transistor drive current, and improve operating characteristics.

[0030] Within the active regions 103 on both sides of the active gate electrode 109A, a first impurity region 111 and a second impurity region 112 can be formed, which are supplied to the source and drain of the transistor. The first impurity region 111 can be electrically connected to the bit line BL, and the second impurity region 112 can be electrically connected to the capacitor Cap. The bit line BL and the first impurity region 111 can be electrically connected by a bit line contact plug BLC. The capacitor Cap and the second impurity region 112 can be electrically connected by a storage contact plug SNC.

[0031] The active trench 105A and the field trench 105F may have bottom surfaces at different levels. The depth H1 of the active trench 105A may be shallower than the depths H2 and H3 of the field trench 105F in the first and second regions R1 and R2. The bottom surface of the field trench 105F may be located at a lower level than the bottom surface of the active trench 105A. The field trench 105F may have bottom surfaces at different levels in the first region R1 and the second region R2.

[0032] In this embodiment, the depth H2 of the field trench 105F in the second region R2 can be shallower than the depth H3 of the field trench 105F in the first region R1 due to the second insulating layer 102U. In other words, the depth of the field gate electrode 109P, i.e., the passing gate, that crosses the element isolation layer 102 formed between the second impurity regions 112 of adjacent active regions 103 separated by a word line 109, can be made shallower by the thickness of the second insulating layer 102U. Therefore, the area of ​​the field gate electrode 109P of adjacent word lines facing the active gate electrode 109A of one word line is reduced, thereby preventing row hammering between adjacent cells. The effect of preventing row hammering can be increased as the area of ​​the field gate electrode 109P is reduced.

[0033] In other embodiments, as shown in Figure 3, the depth H2 of the field trench 105F in the second region R2 can be similar to the depth H1 of the active trench 105A. The depth H3 of the field trench 105F in the first region R1 can be deeper than the depth H2 of the field trench 105F in the second region R2.

[0034] In yet another embodiment, as shown in Figure 4, the depth H2 of the field trench 105F in the second region R2 can be shallower than the depth H1 of the active trench 105A and the depth H3 of the field trench 105F in the first region R1. The depth H3 of the field trench 105F in the first region R1 can be deeper than the depth H1 of the active trench 105A.

[0035] Figures 5A to 5H are cross-sectional views illustrating the manufacturing method of the semiconductor device according to this embodiment. Figures 5A to 5H are cross-sectional views taken along the line A-A' in Figure 1.

[0036] As shown in Figures 1 and 5A, element isolation trenches 102T that define multiple active regions 103 can be formed in the substrate 101.

[0037] The substrate 101 can be a material suitable for semiconductor processing. The substrate 101 can include semiconductor substrates. The substrate 101 can consist of a silicon-containing material. The substrate 101 can include silicon, single-crystal silicon, polysilicon, amorphous silicon, silicon germanium, single-crystal silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, combinations thereof, or multilayers thereof. The substrate 101 can also contain other semiconductor materials such as germanium. The substrate 101 can also include III / V semiconductor substrates, such as compound semiconductor substrates like GaAs. The substrate 101 can also include SOI (Silicon On Insulator) substrates.

[0038] The active regions 103 defined by the element isolation trench 102T are formed to have a long axis and a short axis, and can be arranged two-dimensionally along the long axis and the short axis. For example, the active regions 103 can have a bar shape with a length longer than its width, and can be arranged in an island shape.

[0039] The element isolation trench 102T may include a first region R1 in which the active region 103 is separated by a first interval along a first direction D1, and a second region R2 in which the active region 103 is separated by a second interval wider than the first interval along the first direction D1.

[0040] As shown in Figures 1 and 5B, an element isolation layer 102 can be formed to gap-fill the element isolation trench 102T. For example, the insulating material can include silicon oxide. The element isolation layer 102A can be formed by a series of steps in which an insulating material is gap-filled into the element isolation trench 102T and the insulating material is etched using the upper surface of the substrate 101 as a target. The element isolation layer 102A can be formed by the STI (Shallow Trench Isolation) process.

[0041] As shown in Figures 1 and 5C, a gate trench 105 can be formed extending along the short axis direction of the active region 103. The bottom surface of the gate trench 105 can be located at a higher level than the bottom surface of the element isolation trench 102T.

[0042] The gate trench 105 may comprise an active trench 105A that crosses the active region 103 and a field trench 105F formed within the element isolation layer 102B. The gate trench 105 may extend continuously from the active trench 105A to the field trench 105F. The element isolation layer 102B in the region excluding the field trench 105F may have the same upper surface as the upper surface of the substrate 101. The element isolation layer 102B in the region excluding the field trench 105F may be referred to as the "isolation insulating layer 102R" (see Figure 2B).

[0043] As shown in Figures 1 and 5D, the element isolation layer 102 embedded in the field trench 105F can be further recessed. Therefore, the bottom surface of the field trench 105F can be positioned at a lower level than the bottom surface of the active trench 105A.

[0044] The element isolation layer 102B, which is gap-filled in the element isolation trench 102T that overlaps with the field trench 105F, can be referred to as the "first insulating layer 102L".

[0045] The upper surface of the first insulating layer 102L can be located at a lower level than the upper surface of the active trench 105A. The protruding region of the active region 103 that is projected by the first insulating layer 102L can be referred to as a "fin 103F".

[0046] As shown in Figures 1 and 5E, sacrificial spacers 106 can be formed on both side walls of the fin 103F. The sacrificial spacers 106 may include an insulating material having an etching selectivity ratio with respect to the element isolation layer 102. For example, the sacrificial spacers 106 may include silicon nitride.

[0047] The sacrificial spacer 106 can be formed, for example, by a TS-ALD (topology selective atomic layer deposition) process. TS-ALD may include plasma ALD, and in particular, refers to a process of selectively depositing only on horizontal surfaces or vertical sidewalls according to plasma parameters.

[0048] The field trench 105F between adjacent active regions 103 along the first direction D1, i.e., the first region R1 of the element isolation trench 102T, can be completely gap-filled by the sacrificial spacer 106. The sacrificial spacer 106 can be formed thickly on the sidewall of the fin 103F to completely gap-fill the first region R1 of the element isolation trench 102T, while the sacrificial spacer 106 can be formed with a thinner thickness on the upper surface of the fin 103F. In other words, the upper surface and sidewall of the fin 103F can be completely covered by the sacrificial spacer 106 formed with different thicknesses. In the second region R2 of the element isolation trench 102T, the sacrificial spacer 106 is formed only on the sidewall of the adjacent active region 103, so all other regions are exposed.

[0049] As shown in Figures 1 and 5F, an insulating material layer 107 with a sacrificial spacer 106 can be formed.

[0050] The insulating material layer 107 may contain an insulating material having an etching selectivity ratio with respect to the sacrificial spacer 106. The insulating material layer 107 may contain the same oxide as the first insulating layer 102L. For example, the insulating material layer 107 may contain silicon oxide. In other embodiments, the insulating material layer 107 may also contain an oxide different from that of the first insulating layer 102L.

[0051] The insulating material layer 107 can be formed to have low step coverage characteristics. The insulating material layer 107 can be formed thickly in the horizontal plane parallel to the surface of the substrate 101 and thinly in the direction perpendicular to the surface of the substrate 101. In other words, the insulating material layer 107 can be formed thickly on the upper part of the first insulating layer 102L formed in the second region R2 of the element isolation trench 102T and on the sacrificial spacer 106 formed on the upper surface of the fin 103F, and thinly on the sacrificial spacer 106 formed on the sidewall of the fin 103F.

[0052] As shown in Figures 1 and 5G, the sacrificial spacer 106 (see Figure 5F) can be removed. The step of removing the sacrificial spacer 106 can be carried out under conditions that have an etching selectivity ratio for the first insulating layer 102L and the insulating material layer 107.

[0053] The sacrificial spacer 106 and the insulating material layer formed on the upper part of the fin 103F can be removed together when the sacrificial spacer 106 is removed. In other words, since the upper surface and side walls of the fin 103F are completely covered by the sacrificial spacer 106, the insulating material layer formed on the upper part of the fin 103F can be detached when the sacrificial spacer 106, which is formed between the upper surface of the fin 103F and the insulating material layer, is removed. As a result, the upper surface and both side walls of the fin 103F can be fully exposed.

[0054] The second region R2 of the element isolation trench 102T may retain the laminated structure of the first insulating layer 102L and the second insulating layer 102U, and the first region R1 of the element isolation trench 102T may retain the first insulating layer 102L.

[0055] As shown in Figures 1 and 5H, an embedded gate structure BG can be formed to gap-fill the gate trench 105.

[0056] The embedded gate structure BG may comprise a gate insulating layer 108 covering the surface of the gate trench 105 including the fins 103F, a gate electrode 109 gap-filling a portion of the gate trench 105 on the gate insulating layer 108, and a gate caffing layer 110 gap-filling the rest of the gate trench 105 on the gate electrode 109. For example, the gate insulating layer 108 may be formed by an oxidation process. In other embodiments, the gate insulating layer 108 may also be formed over the entire surface of the active trench 105A and field trench 105F of the gate trench 105 by a forming process.

[0057] The embedded gate structure BG can be referred to as the "word line WL". By forming the word line with embedded gate lines, an embedded channel transistor can be realized. Compared to planar transistors, embedded channel transistors can reduce the unit cell area and increase the effective channel length. Because the word line is embedded within the substrate, embedded channel transistors can reduce parasitic capacitance by lowering the capacitance between the word line and the bit line, as well as the overall capacitance of the bit line.

[0058] As described above, in this embodiment, by further forming a second insulating layer 102U on the second region R2 of the element isolation trench 102T that overlaps with the field trench 105F, the depth of the field gate electrode 109P, i.e., the passing gate, that crosses the element isolation layer 102 formed between the second impurity region 112 of the adjacent active region 103 separated by a word line 109, can be made shallower by the thickness of the second insulating layer 102U. Therefore, the area of ​​the field gate electrode 109P of adjacent word lines facing the active gate electrode 109A of one word line is reduced, and the word line interference phenomenon (row hammer) between adjacent cells can be prevented.

[0059] For example, when the first word line in Figure 1 is turned off and the second word line is turned on, if the area of ​​the field gate electrode of the second word line facing the active gate electrode of the first word line is reduced, the parasitic capacitance between the active gate electrode of the first word line and the field gate electrode of the second word line is reduced. This prevents word line interference, in which the voltage applied to the field gate electrode of the second word line raises the potential of the channel region below the active gate electrode of the first word line that has been turned off.

[0060] Figures 6A to 6D are cross-sectional views illustrating the manufacturing method of the semiconductor device shown in Figure 3. Figures 6A to 6D refer to the process from Figure 5E onward. Among the reference numerals shown in Figures 6A to 6D, those that are the same as those shown in Figures 5A to 5H refer to the same components.

[0061] As shown in Figures 1 and 6A, an insulating material layer 207 can be formed on the entire surface including the sacrificial spacer 106 formed by Figure 5E. The insulating material layer 207 can be formed with a thickness such that its upper surface is at a higher level than the upper surface of the fin 103F.

[0062] The insulating material layer 207 may contain an insulating material having an etching selectivity ratio with respect to the sacrificial spacer 106. The insulating material layer 207 may contain the same oxide as the first insulating layer 102L. For example, the insulating material layer 207 may contain silicon oxide. In other embodiments, the insulating material layer 207 may contain an oxide different from that of the first insulating layer 102L.

[0063] The insulating material layer 207 can be formed, for example, by a chemical vapor deposition process or an atomic layer deposition process.

[0064] As shown in Figures 1, 6B, and 6C, the insulating material layer 207 can be etched on a target in which the upper surface of the fin 103F is exposed. The insulating material layer 207 can be etched by a planarization process. The planarization process may include an etch-back process or a CMP (Chemical Mechanical Polishing) process, etc. In another embodiment, the insulating material layer 207 may also undergo the planarization process on a target in which a sacrificial spacer 106 formed on the upper surface of the fin 103F is exposed.

[0065] Next, the sacrificial spacers 106 can be removed. The step of removing the sacrificial spacers 106 can be carried out under conditions that have an etching selectivity ratio with respect to the first insulating layer 102L and the insulating material layer 207. The insulating material layer 207 remaining between the sacrificial spacers 106 in the first region R1 of the element isolation trench 102T can be removed together with the sacrificial spacers 106. In addition, the upper edge portion of the insulating material layer 207 formed between the sacrificial spacers 106 in the second region R2 of the element isolation trench 102T may be partially lost during the removal of the sacrificial spacers 106 or during the cleaning process.

[0066] Therefore, the second region R2 of the element isolation trench 102T can form a laminated structure of the first insulating layer 102L and the second insulating layer 202U having an upper surface at the same level as the upper surface of the fin 103F. The first insulating layer 102L can remain in the first region R1 of the element isolation trench 102T.

[0067] As shown in Figures 1 and 6D, an embedded gate structure BG can be formed to gap-fill the gate trench 105.

[0068] The embedded gate structure BG may comprise a gate insulating layer 108 covering the surface of the gate trench 105 including the fins 103F, a gate electrode 109 gap-filling a portion of the gate trench 105 on the gate insulating layer 108, and a gate caffing layer 110 gap-filling the rest of the gate trench 105 on the gate electrode 109. In other embodiments, the gate insulating layer 108 may also be formed over the entire surface of the active trench 105A and field trench 105F of the gate trench 105 by a forming process.

[0069] In the element isolation layer 202 at the bottom of the embedded gate structure BG, the second region R2 retains the laminated structure of the first insulating layer 102L and the second insulating layer 202U, while the first region R1 retains the first insulating layer 102L.

[0070] Figures 7A to 7E are cross-sectional views illustrating the manufacturing method of the semiconductor device shown in Figure 4. Figures 7A to 7E refer to the process from Figure 5E onward. Among the reference numerals shown in Figures 7A to 7E, those that are the same as those shown in Figures 5A to 5H refer to the same components.

[0071] As shown in Figures 1 and 7A, an insulating material layer 307 can be formed on the entire surface including the sacrificial spacer 106 formed by Figure 5E. The insulating material layer 307 can be formed with a thickness such that its upper surface is at a higher level than the upper surface of the fin 103F.

[0072] The insulating material layer 307 may contain an insulating material having an etching selectivity ratio with respect to the sacrificial spacer 106. The insulating material layer 307 may contain the same oxide as the first insulating layer 102L. For example, the insulating material layer 307 may contain silicon oxide. In other embodiments, the insulating material layer 307 may contain an oxide different from that of the first insulating layer 102L.

[0073] The insulating material layer 307 can be formed, for example, by a chemical vapor deposition process or an atomic layer deposition process.

[0074] As shown in Figures 1, 7B, and 7C, a mask pattern 310 can be formed on the insulating material layer 307 of the second region R2 of the element isolation trench 102T. The mask pattern 310 can be patterned to be smaller than the pass gate region. The mask pattern 310 can be formed in an island shape. The width of the mask pattern 310 in the first direction D1 can have a line width narrower than the line width of the second region R2. The width of the mask pattern 310 in the second direction D2 can be the same as the line width of the gate trench 105.

[0075] Next, the insulating material layer 307 can be etched using the mask pattern 310. The etching of the insulating material layer 207 can be carried out under conditions that have an etching selectivity ratio with respect to the substrate 101 and the sacrificial spacer 106. Thus, a second insulating layer 302U can be formed having an upper surface at a higher level than the upper surface of the fin 103F.

[0076] Next, the mask pattern 310 can be removed.

[0077] As shown in Figures 1 and 7D, the sacrificial spacer 106 (see Figure 7C) can be removed. The step of removing the sacrificial spacer 106 can be carried out under conditions that have an etching selectivity ratio for the first insulating layer 102L and the second insulating layer 302U.

[0078] Therefore, the second region R2 of the element isolation trench 102T may retain the laminated structure of the first insulating layer 102L and the second insulating layer 302U, and the first region R1 of the element isolation trench 102T may retain the first insulating layer 102L.

[0079] As shown in Figures 1 and 7E, an embedded gate structure BG can be formed to gap-fill the gate trench 105.

[0080] The embedded gate structure BG may comprise a gate insulating layer 108 covering the surface of the gate trench 105 including the fins 103F, a gate electrode 109 gap-filling a portion of the gate trench 105 on the gate insulating layer 108, and a gate caffing layer 110 gap-filling the rest of the gate trench 105 on the gate electrode 109. In other embodiments, the gate insulating layer 108 may also be formed over the entire surface of the active trench 105A and field trench 105F of the gate trench 105 by a forming process.

[0081] In the element isolation layer 302 at the bottom of the embedded gate structure BG, the second region R2 retains the laminated structure of the first insulating layer 102L and the second insulating layer 302U, while the first region R1 retains the first insulating layer 102L.

[0082] As described above, various embodiments for solving the problem to be addressed are described, but it is clear to any person with ordinary skill in the art to which the present invention belongs that various changes and modifications can be made within the scope of the technical concept of the present invention. [Explanation of Symbols]

[0083] 101 circuit board 103 Active region 102 Element Isolation Layer 103F Fin 105 Gate Trench 105A Active Trench 105F Field Trench

Claims

1. an isolation layer defining a plurality of active regions in the substrate, the active regions including a first region in which the active regions are spaced apart at a first interval along a first direction, and a second region in which the active regions are spaced apart at a second interval along the first direction that is wider than the first interval; a gate trench extending in the first direction across the active region and the isolation layer; a buried word line gap-filling the gate trench; Equipped with a first region of an element isolation layer located below the gate trench being composed of a first insulating layer, and a second region of the element isolation layer located below the gate trench being composed of a stacked structure of a first insulating layer and a second insulating layer.

2. 2. The semiconductor device according to claim 1, wherein an upper surface of the first insulating layer is located at a level lower than a bottom surface of a gate trench that crosses the active region.

3. 2. The semiconductor device according to claim 1, wherein an upper surface of the second insulating layer is located at a higher level than an upper surface of the first insulating layer.

4. 2. The semiconductor device according to claim 1, wherein an upper surface of the second insulating layer is located at a level lower than a bottom surface of a gate trench that crosses the active region.

5. 2. The semiconductor device according to claim 1, wherein an upper surface of the second insulating layer is located at the same level as a bottom surface of a gate trench that crosses the active region.

6. 2. The semiconductor device according to claim 1, wherein an upper surface of the second insulating layer is located at a level higher than a bottom surface of a gate trench that crosses the active region.

7. 2. The semiconductor device according to claim 1, wherein the width of the second insulating layer is smaller than the width of the second region of the element isolation layer.

8. 2. The semiconductor device of claim 1, wherein the buried word line includes an active gate electrode located in the active region and a pass gate electrode located in the isolation layer.

9. the buried word line further includes a fin gate electrode formed on the isolation layer; The semiconductor device of claim 8 , wherein the fin gate electrode is connected to the active gate electrode and the pass gate electrode.

10. The semiconductor device according to claim 9 , wherein a bottom surface of the fin gate electrode is located at a level lower than a bottom surface of the pass gate electrode.

11. The semiconductor device according to claim 9 , wherein a bottom surface of the fin gate electrode is located at a level lower than a bottom surface of the active gate electrode.

12. 2. The semiconductor device of claim 1, wherein the first and second insulating layers comprise a silicon oxide material.

13. forming an isolation layer in a substrate, the isolation layer including a first region in which the active regions are spaced apart at a first interval along a first direction, and a second region in which the active regions are spaced apart at a second interval along the first direction, the second interval being greater than the first interval; forming a gate trench extending in the first direction across the active region and the isolation layer; forming a buried word line gap-filling the gate trench; Including, A method for manufacturing a semiconductor device, wherein a first region of an element isolation layer located below the gate trench is composed of a first insulating layer, and a second region of the element isolation layer located below the gate trench is composed of a stacked structure of a first insulating layer and a second insulating layer.

14. After the step of forming the gate trench, forming the first insulating layer recessing the isolation layer to provide a fin; forming the second insulating layer on the isolation layer below the gate trench; The method for manufacturing a semiconductor device according to claim 13, further comprising:

15. The step of forming the second insulating layer includes: selectively forming sacrificial spacers on both sidewalls of the fin to expose the first insulating layer below the gate trench; forming an insulating material on the exposed first insulating layer; selectively removing the sacrificial spacers; The method for manufacturing a semiconductor device according to claim 14, comprising:

16. The method of claim 15 , wherein the sacrificial spacer comprises a material having an etching selectivity with respect to the first insulating layer and an insulating material.

17. 16. The method of claim 15, wherein the sacrificial spacers are selectively formed on the sidewalls of the fins by a Topology Selective ALD (TS-ALD) process.

18. The step of forming the second insulating layer includes: selectively forming sacrificial spacers on both sidewalls of the fin to expose the first insulating layer below the gate trench; forming an insulating material over the entire surface including the exposed first insulating layer; etching the insulating material with a target that exposes a top surface of the fin; removing the sacrificial spacer; The method for manufacturing a semiconductor device according to claim 14, comprising:

19. The method of claim 18 , wherein the sacrificial spacer comprises a material having an etching selectivity with respect to the first insulating layer and an insulating material.

20. 19. The method of claim 18, wherein the sacrificial spacers are selectively formed on the sidewalls of the fins by a Topology Selective ALD (TS-ALD) process.

21. The step of forming the second insulating layer includes: selectively forming sacrificial spacers on both sidewalls of the fin to expose the first insulating layer below the gate trench; forming an insulating material over the entire surface including the exposed first insulating layer; forming a mask pattern on the insulating material; patterning the insulating material using the mask pattern so that the insulating material remains on the exposed first insulating layer; removing the sacrificial spacer; The method for manufacturing a semiconductor device according to claim 14, comprising:

22. 22. The method of claim 21, wherein the sacrificial spacer comprises a material having an etching selectivity with respect to the first and second insulating layers.

23. 22. The method of claim 21, wherein the sacrificial spacers are selectively formed on the sidewalls of the fins by a Topology Selective ALD (TS-ALD) process.

24. The method for manufacturing a semiconductor device according to claim 13 , wherein the first and second insulating layers contain silicon oxide.

25. A semiconductor device comprising: a substrate; a plurality of active regions aligned along a first direction and separated by first and second regions of an isolation layer arranged alternately; a buried word line extending in the first direction and crossing the active regions and the first and second regions of the isolation layer; The semiconductor device has a first region of the element isolation layer formed of a first insulating layer, and a second region of the element isolation layer formed of a laminated structure of first and second insulating layers.

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