Display device

Abstract

To provide a display device capable of speeding up drive.SOLUTION: A display device includes: a first transistor connected between an image data signal line and a first node while switching is controlled by using a first control signal; a third transistor connected between the first node and a second node while switching is controlled by using a second control signal; a second transistor that has a gate electrode connected to the second node and is connected between a power line and a third node; a fourth transistor connected between a reference voltage power line and the second node while switching is controlled by using the second control signal; a fifth transistor connected between an initialization voltage power line and the third node while switching is controlled by using a third control signal; and a sixth transistor electrically connected between a precharge voltage power line and the first node while switching is controlled by using a fourth control signal.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a display device. [Background technology]

[0002] In recent years, self-luminous display devices have become widespread and are implemented in televisions, smartphones, digital signage (electronic billboards, electronic advertising boards, etc.). A self-luminous display device includes, for example, a plurality of pixels and a control circuit for driving the plurality of pixels. Each of the plurality of pixels includes, for example, a plurality of transistors, a capacitance element, and a light-emitting element. The light-emitting element is an element that emits light in a self-luminous manner, such as a light-emitting diode (LED), a micro-light-emitting diode (micro LED), or an organic electroluminescence (EL) element. In a self-luminous display device, a control circuit supplies a voltage to each of the plurality of pixels, causing a current corresponding to the supplied voltage value to flow through the light-emitting element included in each of the plurality of pixels. Each light-emitting element emits light at a brightness corresponding to the current flowing through the light-emitting element, and the pixel including the light-emitting element can display an image with a gradation corresponding to the brightness.

[0003] For example, Patent Document 1 discloses a display device that includes organic light-emitting elements and is capable of suppressing display defects such as display unevenness by using a precharge voltage generated by a source driver IC. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2005-37844 Summary of the Invention [Problem to be solved by the invention]

[0005] In recent years, display devices including organic light-emitting elements have been required to operate at higher speeds in order to accommodate higher resolutions, larger screens, or higher frequencies. Furthermore, when display devices including organic light-emitting elements are required to accommodate higher resolutions, larger screens, or higher frequencies, it is expected that the power consumption of the display devices will increase, and therefore there is a demand for reducing the power consumption of the display devices.

[0006] In view of the above, an object of one embodiment of the present invention is to provide a display device that can be driven at high speed and that can reduce power consumption. [Means for solving the problem]

[0007] A display device according to one embodiment of the present invention includes a first transistor whose switching is controlled using a first control signal and electrically connected between an image data signal line to which a data voltage is supplied and a first node; a third transistor whose switching is controlled using a second control signal different from the first control signal and electrically connected between the first node and a second node; a second transistor whose gate electrode is electrically connected to the second node and electrically connected between a power supply line to which a constant voltage is supplied and the third node; and a second transistor whose switching is controlled using the second control signal and electrically connected between a reference voltage power supply line to which a reference voltage is supplied and the second node. a fourth transistor electrically connected between the first node and the third node, a fifth transistor whose switching is controlled by a third control signal different from the first control signal and the second control signal, and electrically connected between an initialization voltage power supply line to which an initialization voltage is supplied and the third node, a sixth transistor whose switching is controlled by a fourth control signal different from the first control signal and the second control signal, and electrically connected between a pre-charge voltage power supply line to which a pre-charge voltage is supplied and the first node, a light-emitting element electrically connected to the third node, and a capacitive element electrically connected between the first node and the third node,

[0008] a third transistor whose switching is controlled by the first control signal and electrically connected between the first node and a second node; a second transistor whose gate electrode is electrically connected to the second node and electrically connected between a power supply line to which a constant voltage is supplied and the third node; a fourth transistor whose switching is controlled by a second control signal different from the first control signal and electrically connected between the second node and a third control signal line whose third control signal is supplied, the third control signal including a precharge voltage, a first initialization voltage different from the precharge voltage, and a second initialization voltage different from the precharge voltage and the first initialization voltage; a fifth transistor whose switching is controlled by a fourth control signal different from the first control signal, the second control signal, and the third control signal and electrically connected between the third control signal line and the third node; a light-emitting element electrically connected to the third node;

[0009] A display device according to one embodiment of the present invention includes a first transistor whose switching is controlled by a first control signal and electrically connected between a first node and an image data signal line to which a data voltage is supplied; a third transistor whose switching is controlled by a second control signal different from the first control signal and electrically connected between the first node and a third node; a second transistor having a gate electrode electrically connected to the second node and electrically connected between the third node and a fourth node; a fourth transistor whose switching is controlled by the second control signal and electrically connected between the third node and a third control signal line to which a third control signal including a first initialization voltage and a second initialization voltage different from the first initialization voltage is supplied; a fifth transistor whose switching is controlled by a control signal and electrically connected between the second node and the fourth node; a sixth transistor whose switching is controlled by the second control signal and electrically connected between the second node and the fourth node; a seventh transistor whose switching is controlled by the second control signal and electrically connected between a voltage line to which a constant voltage is supplied and the fourth node; an eighth transistor whose switching is controlled by a fifth control signal different from the first control signal, the second control signal, the third control signal, and the fourth control signal and electrically connected between the first node and a precharge voltage power supply line to which a precharge voltage is supplied; a light-emitting element electrically connected to the third node; and a capacitive element electrically connected between the first node and the second node. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a schematic diagram illustrating a configuration of a display device according to a first embodiment of the present invention. [Figure 2] FIG. 2 is a schematic diagram showing the configuration of a control circuit according to the first embodiment of the present invention. [Figure 3]1 is a circuit diagram showing a configuration of a control circuit according to a first embodiment of the present invention. [Figure 4] FIG. 2 is a schematic diagram showing input signals to a pixel circuit according to the first embodiment of the present invention. [Figure 5] 1 is a circuit diagram showing a configuration of a pixel circuit according to a first embodiment of the present invention. [Figure 6] 3 is a timing chart of the self-luminous display device according to the first embodiment of the present invention. [Figure 7] 3 is a timing chart of the self-luminous display device according to the first embodiment of the present invention. [Figure 8] 3 is a timing chart of the self-luminous display device according to the first embodiment of the present invention. [Figure 9] 3 is a timing chart of the self-luminous display device according to the first embodiment of the present invention. [Figure 10] 3 is a timing chart of the self-luminous display device according to the first embodiment of the present invention. [Figure 11] 3 is a timing chart of the self-luminous display device according to the first embodiment of the present invention. [Figure 12] FIG. 2 is a layout diagram of a pixel according to the first embodiment of the present invention. [Figure 13] 13 is a cross-sectional view showing a cross section taken along A1-A2 in the layout shown in FIG. 12. FIG. [Figure 14] 3 is a sequence diagram showing a method for manufacturing the self-luminous display device according to the first embodiment of the present invention. FIG. [Figure 15] FIG. 2 is a layout diagram of a pixel according to the first embodiment of the present invention. [Figure 16] FIG. 2 is a layout diagram of a pixel according to the first embodiment of the present invention. [Figure 17] FIG. 2 is a layout diagram of a pixel according to the first embodiment of the present invention. [Figure 18] FIG. 2 is a layout diagram of a pixel according to the first embodiment of the present invention. [Figure 19] 19 is a cross-sectional view showing a cross section taken along B1-B2 in the layout shown in FIG. 18. FIG. [Figure 20]3 is a sequence diagram showing a method for manufacturing the self-luminous display device according to the first embodiment of the present invention. FIG. [Figure 21] FIG. 2 is a layout diagram of a pixel according to the first embodiment of the present invention. [Figure 22] FIG. 2 is a layout diagram of a pixel according to the first embodiment of the present invention. [Figure 23] FIG. 2 is a layout diagram of a pixel according to the first embodiment of the present invention. [Figure 24] FIG. 2 is a layout diagram of a pixel according to the first embodiment of the present invention. [Figure 25] FIG. 10 is a schematic diagram showing input signals to a pixel circuit according to a second embodiment of the present invention. [Figure 26] FIG. 4 is a circuit diagram showing a configuration of a pixel circuit according to a second embodiment of the present invention. [Figure 27] 10 is a timing chart of a self-luminous display device according to a second embodiment of the present invention. [Figure 28] 10 is a timing chart of a self-luminous display device according to a second embodiment of the present invention. [Figure 29] 10 is a timing chart of a self-luminous display device according to a second embodiment of the present invention. [Figure 30] 10 is a timing chart of a self-luminous display device according to a second embodiment of the present invention. [Figure 31] FIG. 6 is a schematic diagram showing the configuration of a control circuit according to a second embodiment of the present invention. [Figure 32] FIG. 6 is a circuit diagram showing the configuration of a control circuit according to a second embodiment of the present invention. [Figure 33] 10 is a timing chart of a control circuit according to a second embodiment of the present invention. [Figure 34] FIG. 10 is a schematic diagram showing input signals to a pixel circuit according to a third embodiment of the present invention. [Figure 35] FIG. 10 is a circuit diagram showing a configuration of a pixel circuit according to a third embodiment of the present invention. [Figure 36] 10 is a timing chart of a self-luminous display device according to a third embodiment of the present invention. [Figure 37]10 is a timing chart of a self-luminous display device according to a third embodiment of the present invention. [Figure 38] 10 is a timing chart of a self-luminous display device according to a third embodiment of the present invention. [Figure 39] 10 is a timing chart of a self-luminous display device according to a third embodiment of the present invention. [Figure 40] FIG. 10 is a schematic diagram showing the configuration of a control circuit according to a third embodiment of the present invention. [Figure 41] FIG. 10 is a circuit diagram showing the configuration of a control circuit according to a third embodiment of the present invention. [Figure 42] 10 is a timing chart of a control circuit according to a third embodiment of the present invention. [Figure 43] 10 is a timing chart of a control circuit according to a third embodiment of the present invention. [Figure 44] FIG. 10 is a schematic diagram showing input signals to a pixel circuit according to a fourth embodiment of the present invention. [Figure 45] FIG. 10 is a circuit diagram showing a configuration of a pixel circuit according to a fourth embodiment of the present invention. [Figure 46] 10 is a timing chart of a self-luminous display device according to a fourth embodiment of the present invention. [Figure 47] 10 is a timing chart of a self-luminous display device according to a fourth embodiment of the present invention. [Figure 48] 10 is a timing chart of a self-luminous display device according to a fourth embodiment of the present invention. [Figure 49] 10 is a timing chart of a self-luminous display device according to a fourth embodiment of the present invention. [Figure 50] FIG. 10 is a diagram illustrating the setting of an input signal according to the fourth embodiment of the present invention. [Figure 51] FIG. 11 is a schematic diagram showing input signals to a pixel circuit according to a fifth embodiment of the present invention. [Figure 52] FIG. 10 is a circuit diagram showing a configuration of a pixel circuit according to a fifth embodiment of the present invention. [Figure 53] 10 is a timing chart of a self-luminous display device according to a fifth embodiment of the present invention. [Figure 54]10 is a timing chart of a self-luminous display device according to a fifth embodiment of the present invention. [Figure 55] 10 is a timing chart of a self-luminous display device according to a fifth embodiment of the present invention. [Figure 56] 10 is a timing chart of a self-luminous display device according to a fifth embodiment of the present invention. [Figure 57] FIG. 11 is a diagram illustrating the setting of an input signal according to the fifth embodiment of the present invention. [Figure 58] FIG. 13 is a schematic diagram showing input signals to a pixel circuit according to a sixth embodiment of the present invention. [Figure 59] FIG. 10 is a circuit diagram showing the configuration of a pixel circuit according to a sixth embodiment of the present invention. [Figure 60] 10 is a timing chart of a self-luminous display device according to a sixth embodiment of the present invention. [Figure 61] 10 is a timing chart of a self-luminous display device according to a sixth embodiment of the present invention. [Figure 62] 10 is a timing chart of a self-luminous display device according to a sixth embodiment of the present invention. [Figure 63] 10 is a timing chart of a self-luminous display device according to a sixth embodiment of the present invention. [Figure 64] FIG. 13 is a schematic diagram showing input signals to a pixel circuit according to a seventh embodiment of the present invention. [Figure 65] FIG. 12 is a circuit diagram showing a configuration of a pixel circuit according to a seventh embodiment of the present invention. [Figure 66] 13 is a timing chart of a self-luminous display device according to a seventh embodiment of the present invention. [Figure 67] 13 is a timing chart of a self-luminous display device according to a seventh embodiment of the present invention. [Figure 68] 13 is a timing chart of a self-luminous display device according to a seventh embodiment of the present invention. [Figure 69] 13 is a timing chart of a self-luminous display device according to a seventh embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention can be implemented in many different forms, and should not be construed as being limited to the description of the embodiments exemplified below. Furthermore, in order to clarify the explanation, the drawings may show the width, thickness, shape, configuration, etc. of each part schematically compared to the actual form, but these are merely examples and do not limit the interpretation of the present invention. Furthermore, the letters "first" and "second" attached to each element are convenient labels used to distinguish each element, and have no other meaning unless otherwise specified.

[0012] Furthermore, in this specification, unless otherwise specified, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude cases where α includes multiple combinations of A to C. Furthermore, these expressions do not exclude cases where α includes other elements.

[0013] For example, a display device according to one embodiment of the present invention is a display device that uses EL elements as self-luminous light-emitting elements. For example, a display device that uses EL elements may be called a self-luminous display device, an EL display device, or the like. For example, in the embodiment of the present invention, a display device that uses EL elements is called a self-luminous display device.

[0014] 1. First Embodiment <1-1. Overview of the self-luminous display device 10> An overview of a self-luminous display device 10 according to the first embodiment will be described with reference to Fig. 1. Fig. 1 is a schematic diagram showing the configuration of the self-luminous display device 10. The configuration of the self-luminous display device 10 shown in Fig. 1 is an example, and the configuration of the self-luminous display device 10 is not limited to the configuration shown in Fig. 1.

[0015] The self-emissive display device 10 includes an array substrate 100, a flexible printed circuit board 200 (FPC 200), and an IC chip 110. The self-emissive display device 10 also includes a display area 22 provided on the array substrate 100, a peripheral area 24 surrounding the display area 22, and a terminal area 26.

[0016] In the display region 22, a plurality of pixels 180 are arranged in a matrix along a first direction D1 (column direction) and a second direction D2 (row direction) intersecting the first direction D1. The pixel 180 is the smallest unit that constitutes part of an image displayed in the display region 22. For example, each of the plurality of pixels 180 may correspond to a sub-pixel R, a sub-pixel G, or a sub-pixel B. One pixel may also be formed by three sub-pixels. There are no limitations on the arrangement of the pixels 180, and the arrangement of the plurality of pixels 180 may be, for example, a stripe arrangement. The arrangement of the self-luminous display device 10 may be a delta arrangement, a pentile arrangement, or the like.

[0017] The sub-pixels R, G, and B are configured to display images of different colors. For example, each of the sub-pixels R, G, and B may include a light-emitting element including a light-emitting layer that emits the three primary colors of red, green, and blue. When a desired voltage or current is supplied to each of the three sub-pixels, the self-emissive display device 10 can display an image.

[0018] The peripheral region 24 is provided with an IC chip 110 and two control circuits 120. The two control circuits 120 are provided on the left and right sides of the display region 22. The IC chip 110 is connected to the terminal portion 150 using a connection wiring 341. Each of the two control circuits 120 is connected to the IC chip 110 using a connection wiring 342. The peripheral region 24 is sometimes referred to as a frame region. The connection wiring 341 may be referred to individually as the connection wiring 341, and a bundle of multiple connection wirings 341 may be referred to as the connection wiring 341. Like the connection wiring 341, the connection wiring 342 may be referred to individually as the connection wiring 342, and a bundle of multiple connection wirings 342 may be referred to as the connection wiring 342.

[0019] The terminal region 26 is provided with the terminal portion 150 and the FPC 200 electrically connected to the terminal portion 150. The terminal region 26 is on the opposite side of the peripheral region 24 in the first direction D1 from the region in which the display region 22 is provided.

[0020] The FPC 200 is connected to an external device (not shown) outside the self-emissive display device 10. Therefore, the self-emissive display device 10 is connected to the external device via the FPC 200 and the terminal section 150 connected to the FPC. Control signals and voltages are transmitted from the external device to the self-emissive display device 10 via the FPC 200 and the terminal section 150 connected to the FPC. The self-emissive display device 10 drives each pixel 180 provided in the self-emissive display device 10 using the control signals and voltages received from the external device. As a result, the self-emissive display device 10 can display an image in the display region 22.

[0021] The IC chip 110 supplies signals, voltages, and the like for driving each pixel 180 to the two control circuits 120 and each pixel 180 (pixel circuit 181) via the FPC 200, the terminal section 150, and the connection wiring 341.

[0022] In this specification and drawings, IC chip 110, each of the two control circuits 120, and each of IC chip 110 may be referred to individually as a control circuit, and a group of circuits including IC chip 110, each of the two control circuits 120, and part or all of IC chip 110 may be referred to as a control circuit.

[0023] <1-2. Configuration of IC chip 110> 1, an overview of the IC chip 110 will be described. The IC chip 110 is provided at a position adjacent to the display area 22 in the first direction D1. Image data signal lines 321, 322, and 323 extend from the IC chip 110 in the first direction D1 and are connected to a plurality of pixels 180 arranged in the first direction D1.

[0024] For example, the IC chip 110 includes a plurality of selection circuits (not shown). For example, each of the plurality of selection circuits is a switch controlled based on an on signal and an off signal supplied to a selection signal. The selection circuit is selected by an on signal supplied to the selection signal, and supplies an image data signal SL(m) to an image data signal line 321 and a pixel 180 electrically connected to the image data signal line 321. The selection signal and the image data signal SL(m) are transmitted from an external device to the IC chip 110 via an FPC 200 and a terminal unit 150 connected to the FPC. For example, the signal supplied to the image data signal SL(m) in each embodiment is a data signal VDATA, and the data signal VDATA includes a data voltage equal to or greater than a voltage VSIGL (see FIG. 8) and equal to or less than a voltage VSIGH (see FIG. 8). In reality, the image data signal SL(m) includes a data signal VDATA corresponding to each horizontal period HRP, but in the timing charts shown in each embodiment, only the data signal VDATA in the horizontal period HRP is illustrated as the image data signal SL(m), and the other data signals VDATA are omitted from the illustration.

[0025] For example, an on signal is a signal including a voltage that turns on a selection circuit (switch), and an off signal is a signal including a voltage that turns off the selection circuit (switch). In the present invention, the on signal may be a high-level voltage (potential) (high, High, HI) and the off signal may be a low-level voltage (potential) (low, Low, LO), or the on signal may be a low-level voltage (potential) (low, Low, LO) and the off signal may be a high-level voltage (potential) (high, High, HI). A high-level voltage is greater (higher) than a low-level voltage. In the self-luminous display device according to the embodiments in this specification, as an example, the on signal is a high-level voltage and the off signal is a low-level voltage.

[0026] <1-3. Configuration of Control Circuit 120> An overview of the control circuit 120 will be described with reference to Figures 1 to 3. Figure 2 is a schematic diagram showing the configuration of the control circuit 120, and Figure 3 is a circuit diagram showing the circuit configuration of the scan driver 160(n). The configurations of the control circuit 120 and scan driver 160(n) shown in Figures 2 and 3 are examples, and the configurations of the control circuit 120 and scan driver 160(n) are not limited to the configurations shown in Figures 2 and 3. Configurations that are the same as or similar to those in Figure 1 will be described as necessary.

[0027] 1, the two control circuits 120 are provided adjacent to each other on either side of the display area 22 in the second direction D2 of the display area 22. Scan signal lines 330, 331, 332, and 333 extend from the control circuits 120 in the second direction D2 and are connected to the plurality of pixels 180 arranged in the second direction D2.

[0028] 2, the control circuit 120 includes a shift register circuit 130 and a plurality of scan drivers 160(n). For example, the control circuit 120 is a gate driver. The number n is a positive integer. For example, the control circuit 120 receives control signals such as a clock signal CLK, a start pulse STV, an enable signal EN1, an enable signal EN1B, an enable signal EN2, and an enable signal EN2B, as well as voltages such as a drive voltage VDDEL and a reference voltage VSSEL. The control circuit 120 can sequentially select scan lines based on the input of the control signals and power supply.

[0029] The shift register circuit 130 is electrically connected to a plurality of scan drivers 160(n). The shift register circuit 130 includes a plurality of shift registers (e.g., shift registers 111, 112, 113, 114, and 115). A clock signal CLK, a start pulse STV, and the like are supplied to the shift register circuit 130 via a plurality of connection wirings 342, a drive voltage VDDEL is supplied via a drive power supply line PVDD, and a reference voltage VSSEL is supplied via a reference voltage line PVSS. Based on control signals such as the clock signal CLK and the start pulse STV, the shift register circuit 130 generates a plurality of output signals (output signal SR1(n), output signal SR2(n), output signal SR3(n), output signal SR4(n), output signal SR5(n), etc.) shifted at different timings, and sequentially outputs the signals to a plurality of scan drivers (e.g., scan driver 160(1), scan driver 160(2), scan driver 160(3), etc.).

[0030] For example, shift register 111 is electrically connected to shift register 112, shift register 112 is electrically connected to shift register 113, shift register 113 is electrically connected to shift register 114, and shift register 114 is electrically connected to shift register 115. Shift register 111 is electrically connected to scan driver 160(1) and supplies an output signal SR1(n) to input terminals IN1 and IN4 of scan driver 160(1). Shift register 112 is electrically connected to scan drivers 160(1) and 160(2) and supplies an output signal SR2(n) to input terminal IN5 of scan driver 160(1) and input terminals IN1 and IN4 of scan driver 160(2). Shift register 113 is electrically connected to scan drivers 160(1), 160(2), and 160(3) and supplies an output signal SR3(n) to input terminals IN2 and IN6 of scan driver 160(1), input terminal IN5 of scan driver 160(2), and input terminals IN1 and IN4 of scan driver 160(3). Shift register 114 is electrically connected to scan drivers 160(2) and 160(3) and supplies an output signal SR4(n) to input terminals IN2 and IN6 of scan driver 160(2) and input terminal IN5 of scan driver 160(3). Shift register 115 is electrically connected to scan driver 160(3) and supplies an output signal SR5(n) to input terminals IN2 and IN6 of scan driver 160(3).

[0031] The scan driver 160(n) has seven input terminals (input terminals IN1 to IN7) and four output terminals (output terminals OUT1 to OUT4). The multiple scan drivers 160(n) are supplied with enable signals EN1, EN1B, EN2, and EN2B from the IC chip 110 via multiple connection wirings 342, a drive voltage VDDEL via a drive power supply line PVDD, and a reference voltage VSSEL via a reference voltage line PVSS. Based on the multiple output signals, enable signals EN1, EN1B, EN2, and EN2B, the scan driver 160(n) sequentially supplies scan signals with different timings (e.g., a first scan signal SC1(n), a second scan signal SC2(n), a third scan signal SC3(n), and a fourth scan signal SC4(n)) to each scan signal line, and drives the pixels 180 (pixel circuits 181) electrically connected to each scan signal line. The first scan signal SC1(n) may be called the second control signal, the second scan signal SC(2) may be called the third or fourth control signal, the third scan signal SC3(n) may be called the fourth or fifth control signal, and the fourth scan signal SC4(n) may be called the first control signal. For example, the fourth scan signal SC4(n) and the scan signal line 333 to which the fourth scan signal SC4(n) is supplied are so-called scan signals and scan signal lines.

[0032] For example, as shown in FIG. 3, the scan driver 160(n) includes inverter circuits INV1-INV6, NOR circuits NR1-NR3, a transmission gate TMG, and a transistor TR1. The inverter circuit INV1 is electrically connected to the input terminal IN1 and the inverter circuit INV2. The NOR circuit NR1 is electrically connected to the input terminal IN2 and the inverter circuit INV2, and the inverter circuit INV3 is electrically connected to the NOR circuit NR1 and the output terminal OUT1. The NOR circuit NR2 is electrically connected to the input terminals IN4 and IN5 and the inverter circuit INV4. The NOR circuit NR3 is electrically connected to the input terminal IN3 and the inverter circuits INV4 and INV5. The inverter circuit INV5 is electrically connected to the output terminal OUT2, and the inverter circuit INV4 is electrically connected to the output terminal OUT3. The inverter circuit INV6 is electrically connected to the input terminal IN6, the transmission gate TMG, and the transistor TR1, and the transmission gate TMG is electrically connected to the input terminals IN6 and IN7 and the output terminal OUT4. The transistor TR1 is electrically connected to the reference voltage line PVSS, the transmission gate TMG, and the output terminal OUT4. For example, as shown in Fig. 2, control signals are input to seven input terminals (input terminals IN1 to IN7), and as shown in Figs. 1 to 3, a first scan signal SC1(n) is output to a scan signal line 330 electrically connected to the output terminal OUT1, a second scan signal SC2(n) is output to a scan signal line 331 electrically connected to the output terminal OUT2, a third scan signal SC3(n) is output to a scan signal line 332 electrically connected to the output terminal OUT3, and a fourth scan signal SC4(n) is output to a scan signal line 333 electrically connected to the output terminal OUT4.

[0033] <1-4. Configuration of pixel 180> An overview of the pixel 180 and pixel circuit 181 will be described with reference to FIGS. 1 to 5. FIG. 4 is a schematic diagram showing input signals to the pixel circuit 181 included in the pixel 180. FIG. 5 is a circuit diagram showing the configuration of the pixel circuit 181. FIGS. 4 and 5 show, as an example, the configuration of the pixel circuit 181 of the pixel 180 shown in FIG. 1. The configurations of the pixel 180 and pixel circuit 181 are not limited to the configurations shown in FIGS. 1, 4, and 5. Configurations that are the same as or similar to those in FIGS. 1 to 3 will be described as necessary.

[0034] The pixel circuit 181 is a circuit for driving the pixel 180. The pixel circuits of the sub-pixels R, G, and B included in the pixel 180 are similar to the pixel circuit 181, but the colors emitted by the light-emitting element OLED are different. In the following description, a light-emitting element OLED that emits red light will be described as an example.

[0035] 4, the pixel circuit 181 is supplied with an image data signal SL(m), a first scan signal SC1(n), a second scan signal SC2(n), a third scan signal SC3(n), a fourth scan signal SC4(n), a pre-charge voltage VPRC, a reference voltage VREF, and an initialization voltage VINI. Furthermore, the pixel circuit 181 is supplied with a driving voltage VDDEL and a reference voltage VSSEL as power supplies for driving the pixel 180. For example, the pre-charge voltage VPRC, the reference voltage VREF, the initialization voltage VINI, the driving voltage VDDEL, and the reference voltage VSSEL may be constant voltages or variable voltages that vary according to the timing of each signal.

[0036] The precharge voltage VPRC is supplied to the precharge voltage power line SVP, the reference voltage VREF is supplied to the reference voltage power line SVR, the initialization voltage VINI is supplied to the initialization voltage power line SVI, the drive voltage VDDEL is supplied to the drive power line PVDD, and the standard voltage VSSEL is supplied to the reference voltage line PVSS. For example, the precharge voltage VPRC, the reference voltage power line SVR, the initialization voltage power line SVI, the drive power line PVDD, and the standard voltage line PVSS are each electrically connected to a different connection wiring 342. Also, for example, the precharge voltage VPRC, the reference voltage power line SVR, the initialization voltage power line SVI, the drive power line PVDD, and the standard voltage line PVSS may each be a different connection wiring 342. For example, the precharge voltage VPRC is an intermediate voltage (potential) between the voltage VSIGL and the voltage VSIGH.

[0037] For example, the precharge voltage VPRC, the reference voltage VREF, the initialization voltage VINI, the drive voltage VDDEL, and the reference voltage VSSEL are supplied from an external device to the IC chip 110 via the FPC 200, the terminal unit 150, and the connection wiring 341. Also, for example, the precharge voltage VPRC, the reference voltage VREF, the initialization voltage VINI, the drive voltage VDDEL, and the reference voltage VSSEL are supplied from the IC chip 110 to the plurality of pixels 180 (pixel circuits 181) via the connection wiring 342, the precharge voltage power supply line SVP, the reference voltage power supply line SVR, the initialization voltage power supply line SVI, the drive power supply line PVDD, and the reference voltage line PVSS. Although not shown, the precharge voltage VPRC, the reference voltage VREF, the initialization voltage VINI, the drive voltage VDDEL, and the standard voltage VSSEL may be connected to the precharge voltage power line SVP, the reference voltage power line SVR, the initialization voltage power line SVI, the drive power line PVDD, and the standard voltage line PVSS from an external device via the FPC 200, the terminal unit 150, and the connection wiring 341, without passing through the IC chip 110 and the connection wiring 342, and may be supplied to a plurality of pixels 180 (pixel circuits 181). For example, the precharge voltage VPRC, the reference voltage VREF, the initialization voltage VINI, and the standard voltage VSSEL are smaller than the drive voltage VDDEL.

[0038] 5, the pixel circuit 181 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a capacitance element CS, and a light-emitting element OLED. Each of these transistors includes a gate electrode and a pair of electrodes (a source electrode and a drain electrode) consisting of a first electrode and a second electrode. Each of the capacitance element CS and the light-emitting element OLED includes a pair of electrodes consisting of a first electrode and a second electrode.

[0039] For example, the first transistor T1 is a selection transistor. The first transistor T1 has a function of supplying an image data signal SL(m) to the first node N1.

[0040] For example, the second transistor T2 is a driving transistor. The gate voltage (voltage between the gate electrode 622 and the first electrode (source) 624) applied to the gate electrode 622 of the second transistor T2 is a voltage in which variations in the threshold voltage VTH are corrected based on the reference voltage VREF and the initialization voltage VINI. Furthermore, the second transistor T2 controls the connection / disconnection between the driving power supply line PVDD and the light-emitting element OLED based on the gate voltage (voltage between the gate electrode 622 and the first electrode (source) 624) in which the threshold voltage VTH is corrected and the input image data signal SL(m). In other words, the second transistor T2 has the function of supplying a driving voltage VDDEL to the light-emitting element OLED and causing a current to flow therethrough, causing the light-emitting element OLED to emit light.

[0041] The third transistor T3 has a function of connecting the first node N1 and the second node N2 and supplying the image data signal SL(m) to the second node N2.

[0042] The fourth transistor T4 has a function of connecting the second node N2 and the reference voltage power supply line SVR to each other, supplying the reference voltage VREF to the second node N2, and initializing the second node N2.

[0043] The fifth transistor T5 has a function of connecting the third node N3 and the initialization voltage power supply line SVI to each other, supplying the initialization voltage VINI to the third node N3, and initializing the third node N3.

[0044] The sixth transistor T6 has a function of connecting the first node N1 and the precharge voltage power supply line SVP to each other, supplying the precharge voltage VPRC to the first node N1, and supplying an intermediate potential to the first node N1.

[0045] For example, the capacitive element CS has a function of holding a charge (e.g., a first charge) equivalent to the initialization voltage VINI supplied to the third node N3, and a function of holding a charge (e.g., a second charge) equivalent to the data voltage (a voltage equal to or greater than the voltage VSIGL (see FIG. 9) and equal to or less than the voltage VSIGH (see FIG. 9)) included in the image data signal SL(m) supplied to the first node N1.

[0046] The light-emitting element OLED has diode characteristics and emits light based on the current flowing through the light-emitting element OLED (that is, the drain current Ion of the second transistor T2).

[0047] The first transistor T1 includes a gate electrode 612, a first electrode 614, and a second electrode 616. The gate electrode 612 is electrically connected to the scan signal line 333. The first electrode 614 is electrically connected to the image data signal line 321. The second electrode 616 is electrically connected to the first node N1, the first electrode 634 of the third transistor T3, the second electrode 666 of the sixth transistor T6, and the second electrode 694 of the capacitor CS. As described above, a fourth scan signal SC4(n) is supplied to the scan signal line 333. The switching of the first transistor T1 is controlled using the fourth scan signal SC4(n). In other words, the conductive state (on state) and non-conductive state (off state) of the first transistor T1 are controlled by the fourth scan signal SC4(n). When the signal supplied to the fourth scan signal SC4(n) is LO, the first transistor T1 is in a non-conductive state. When the signal supplied to the fourth scan signal SC4(n) is HI, the first transistor T1 is in a conductive state.

[0048] The second transistor T2 includes a gate electrode 622, a first electrode 624, and a second electrode 626. The gate electrode 622 is electrically connected to the second node N2, the second electrode 636 of the third transistor T3, and the second electrode 646 of the fourth transistor T4. The first electrode 624 is electrically connected to the third node N3, the second electrode 656 of the fifth transistor T5, the first electrode 692 of the capacitor CS, and the second electrode 684 of the light-emitting element OLED. The second electrode 626 is electrically connected to the driving power supply line PVDD. The threshold voltage of the second transistor T2 is a threshold voltage VTH. The conductive state (ON state) and non-conductive state (OFF state) of the second transistor T2 are controlled according to the potential difference between the voltage supplied to the second node N2 and the voltage of the first electrode 624, the potential difference between the second electrode 626 and the first electrode 624, and the threshold voltage VTH. For example, when the potential difference between the voltage supplied to the second node N2 and the voltage of the first electrode 624 is smaller than the threshold voltage VTH and the potential difference between the second electrode 626 and the first electrode 624 is equal to or smaller than 0 V, the second transistor T2 is in a non-conductive state. For example, when the potential difference between the voltage supplied to the second node N2 and the voltage of the first electrode 624 is equal to or larger than the threshold voltage VTH and the potential difference between the second electrode 626 and the first electrode 624 is larger than 0 V, the second transistor T2 is in a conductive state.

[0049] The third transistor T3 includes a gate electrode 632, a first electrode 634, and a second electrode 636. The switching of the third transistor T3 is controlled using a first scan signal SC1(n). The conductive state (on state) and non-conductive state (off state) of the third transistor T3 are controlled by the first scan signal SC1(n). When the signal supplied to the first scan signal SC1(n) is LO, the third transistor T3 is in the conductive state. When the signal supplied to the first scan signal SC1(n) is HI, the third transistor T3 is in the non-conductive state.

[0050] The fourth transistor T4 includes a gate electrode 642, a first electrode 644, and a second electrode 646. The first electrode 644 is electrically connected to a reference voltage power line SVR. A reference voltage VREF is supplied to the reference voltage power line SVR. The switching of the fourth transistor T4 is controlled using a scan signal line 330. In other words, the conductive state (ON state) and non-conductive state (OFF state) of the fourth transistor T4 are controlled by the scan signal line 330. When the signal supplied to the scan signal line 330 is LO, the fourth transistor T4 is in a non-conductive state, and when the signal supplied to the scan signal line 330 is HI, the fourth transistor T4 is in a conductive state.

[0051] The fifth transistor T5 includes a gate electrode 652, a first electrode 654, and a second electrode 656. The gate electrode 652 is electrically connected to the scan signal line 331. The first electrode 654 is electrically connected to the initialization voltage power supply line SVI. A second scan signal SC2(n) is supplied to the scan signal line 331. The switching of the fifth transistor T5 is controlled using the second scan signal SC2(n). In other words, the fifth transistor T5 is controlled between a conductive state (ON state) and a non-conductive state (OFF state) by the second scan signal SC2(n). When the signal supplied to the second scan signal SC2(n) is LO, the fifth transistor T5 is in a non-conductive state, and when the signal supplied to the second scan signal SC2(n) is HI, the fifth transistor T5 is in a conductive state.

[0052] The sixth transistor T6 includes a gate electrode 662, a first electrode 664, and a second electrode 666. The gate electrode 662 is electrically connected to the scan signal line 332. The first electrode 664 is electrically connected to the precharge voltage power supply line SVP. A third scan signal SC3(n) is supplied to the scan signal line 332. The sixth transistor T6 has its switching controlled using the third scan signal SC3(n). In other words, the sixth transistor T6 has its conductive state (ON state) and non-conductive state (OFF state) controlled by the third scan signal SC3(n). When the signal supplied to the third scan signal SC3(n) is LO, the sixth transistor T6 is in a non-conductive state, and when the signal supplied to the third scan signal SC3(n) is HI, the sixth transistor T6 is in a conductive state.

[0053] The first electrode 682 of the light-emitting element OLED is electrically connected to the reference voltage line PVSS. As described above, the reference voltage VSSEL is supplied to the reference voltage line PVSS. The first electrode 682 of the light-emitting element OLED is, for example, a cathode electrode, and the second electrode 684 of the light-emitting element OLED is, for example, an anode electrode.

[0054] For example, the conductive state of a transistor in the self-emissive display device 10 means that the source electrode and drain electrode of the transistor are conductive and the transistor is in an ON state, and the non-conductive state of a transistor in the self-emissive display device 10 means that the source electrode and drain electrode of the transistor are non-conductive and the transistor is in an OFF state. Note that in each transistor, the source electrode and drain electrode may be interchanged depending on the voltage or potential supplied to each electrode. Furthermore, it is easily understood by those skilled in the art that even when a transistor is in an OFF state, a small amount of current, such as leakage current, still flows.

[0055] Each transistor shown in FIG. 5 may have a group 14 element such as silicon or germanium in its channel region, or an oxide exhibiting semiconducting properties. For example, a metal oxide exhibiting semiconducting properties may be used as the oxide exhibiting semiconducting properties. As an example, the metal oxide exhibiting semiconducting properties is an oxide semiconductor containing two or more metals including indium (In). Furthermore, the metal oxide exhibiting semiconducting properties may be gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconia (Zr), or a lanthanide in addition to indium. Furthermore, the metal oxide exhibiting semiconducting properties may be amorphous, crystalline, or a mixed phase of amorphous and crystalline. When the self-emissive display device 10 includes both a transistor having a group 14 element in its channel region and a transistor having an oxide exhibiting semiconducting properties in its channel region, the method for manufacturing the self-emissive display device 10 includes forming a semiconductor layer containing a group 14 element and forming a semiconductor layer (e.g., an oxide semiconductor layer) containing an oxide exhibiting semiconducting properties.

[0056] For example, the leakage current of a transistor having a metal oxide with semiconducting properties is extremely small. Therefore, when a transistor having a metal oxide with semiconducting properties is used, the charge corresponding to the voltage (potential) written to a capacitor element is unlikely to escape from the capacitor element. As a result, by using a transistor having a metal oxide with semiconducting properties, the charge written to the capacitor element can be retained for a long period of time. Furthermore, under the same conditions of gate-source voltage (potential difference between the gate electrode and the source electrode (Vgs)) and source-drain voltage (e.g., potential difference between the source electrode and the drain electrode (Vds)), the drain current of a transistor having a metal oxide with semiconducting properties may be larger than the drain current of a transistor having low-temperature polysilicon (LTPS). As a result, under the same conditions of drain current, the gate-source voltage and source-drain voltage of a transistor having a metal oxide with semiconducting properties can be smaller than those of a transistor having LTPS. Therefore, by using a transistor having a metal oxide with semiconducting properties, the power consumption of the self-emissive display device 10 can be reduced.

[0057] For example, the channel region of the first transistor T1 or the channel region of the fourth transistor T4 may be formed using a metal oxide having semiconducting properties. Also, the channel region of the second transistor T2 or the channel region of the fifth transistor T5 may be formed using a metal oxide having semiconducting properties. For example, when the channel region of the first transistor T1 is formed using a metal oxide, the charge (e.g., the second charge) corresponding to the voltage included in the data signal VDATA held in the first node N1 and the second electrode 694 of the capacitor CS is difficult to discharge, and the first node N1 and the second electrode 694 of the capacitor CS can hold the charge for a long time.

[0058] For example, the channel region of each transistor has crystalline silicon. For example, the crystalline silicon may be low-temperature polysilicon (LTPS) or single-crystal silicon. For example, each transistor in the self-emissive display device 10 is formed using a thin-film transistor (TFT). The channel region of each transistor may also be formed using single-crystal silicon such as a silicon wafer or SOI substrate. Each transistor may have either an n-channel field-effect transistor or a p-channel field-effect transistor. The transistor configuration, storage capacitor connection, power supply voltage, etc. of the self-emissive display device 10 may be appropriately adapted depending on the application and specifications.

[0059] In the first embodiment, the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are n-channel field effect transistors, and the third transistor T3 is a p-channel field effect transistor.

[0060] <1-5. Method for driving the self-luminous display device 10> A method for driving the self-luminous display device 10 will be described with reference to Figs. 6 to 11. Fig. 6 and Figs. 8 to 11 are schematic diagrams showing timing charts of the self-luminous display device 10. Fig. 7 is a schematic diagram showing a timing chart for explaining a method for driving the control circuit 120. The driving methods shown in Figs. 6 to 11 are examples, and the driving methods for the self-luminous display device 10 are not limited to the driving methods shown in Figs. 6 to 11. Configurations that are the same as or similar to those in Figs. 1 to 5 will be described as necessary. The horizontal axis of the timing chart represents time.

[0061] For example, the self-luminous display device 10 is driven at a frequency of 60 Hz, and one frame (1 FRAME) is driven at 60 Hz. For example, FIG. 6 shows the current frame (Kth FRAME), a portion of the frame immediately before the current frame (K-1st FRAME), and a portion of the frame immediately after the current frame (K+1st FRAME). Also, FIGS. 7 to 11 show the light-emitting period PEM of the frame immediately before the current frame (K-1st FRAME), and the periods PIP, PWR, and PVH of the current frame (Kth FRAME). Also, FIGS. 7 to 11 show one horizontal period (horizontal period HRP) for one pixel 180 (pixel circuit 181).

[0062] First, an overview of a method for driving the self-emissive display device 10 will be described with reference to Fig. 6. As shown in Fig. 6, the method for driving the self-emissive display device 10 includes, in one frame, at least an initialization and precharge period PIP (period PIP), a write period PWR (period PWR), and a threshold value acquisition and retention period PVH (period PVH). In a pixel 180 (pixel circuit 181) included in the self-emissive display device 10, the period PWR and period PVH are executed after the period PIP. Furthermore, the period PIP, period PWR, and period PVH of the current frame are executed after the light-emitting period PEM of the frame immediately before the current frame, and the period PIP, period PWR, and period PVH of the frame immediately after the current frame are executed after the light-emitting period PEM of the current frame.

[0063] The period PIP is a period during which a precharge voltage is supplied to the first node N1 and the second node N2 and the third node N3 are initialized. The period PWR is a period during which a data signal VDATA is written to the pixel 180 (pixel circuit 181). The period PVH is a period during which the threshold voltage of the second transistor T2 is acquired by performing an operation to make the potential difference Vgs of the second transistor T2 equal to the threshold voltage, and a charge corresponding to the threshold voltage is held at the third node N3 (the first electrode 692 of the capacitor CS). Furthermore, the light-emitting period PEM is a period during which the pixel 180 emits light based on the written (supplied) data signal VDATA and the acquired threshold voltage of the second transistor T2 (threshold voltage correction). In FIG. 6, for convenience of explanation, the period PWR overlaps with the period PVH. However, the actual period PVH starts after the period PWR starts and ends after the period PWR ends. That is, part of the period PWR overlaps with the period PVH.

[0064] Next, a method for driving the control circuit 120 will be described with reference to FIG. 7. As described in "1-3. Control circuit 120," the multiple output signals are generated based on control signals such as the clock signal CLK (see FIG. 2) and the start pulse STV (see FIG. 2). As shown in FIG. 7, the multiple output signals are signals shifted at different timings. Specifically, the output signal SR2(n) is a signal obtained by shifting the output signal SR1(n), and the output signal SR3(n) is a signal obtained by shifting the output signal SR2(n). The output signals SR4(n) and SR5(n) are signals obtained by shifting the output signals SR3(n) and SR4(n), respectively. The pulse widths of the output signals SR1(n) to SR(5) are equal to each other.

[0065] As explained in "1-3. Control circuit 120," the first scan signal SC1(n), the second scan signal SC2(n), the third scan signal SC3(n), and the fourth scan signal SC4(n) are generated based on the output signals SR1(n) to SR(5), the enable signals EN1, EN1B, EN2, and EN2B. For example, referring to FIGS. 2, 3 and 7, the first scan signal SC1(n) is generated based on the rising edge of the output signal SR1(n) and the falling edge of the output signal SR3(n), the second scan signal SC2(n) is generated based on the rising edge of the enable signal ENB2 and the falling edge of the output signal SR1(n), the third scan signal SC3(n) is generated based on the rising edge of the output signal SR1(n) and the falling edge of the output signal SR2(n), and the fourth scan signal SC4(n) is generated based on the rising edge of the output signal SR3(n) and the falling edge of the enable signal EN2. Since precision is required in controlling the timing for starting to write the data signal VDATA to the first node N1 and the timing for completing the initialization of the third node N3, the fourth scan signal SC4(n) is generated based on the enable signal EN2 supplied from the IC chip 110, and the second scan signal SC2(n) is generated based on the falling edge of the enable signal ENB2 supplied from the IC chip 110.

[0066] Next, one horizontal period (horizontal period HRP) of the method for driving the pixel 180 (pixel circuit 181) of the self-luminous display device 10 will be described with reference to FIGS.

[0067] In the method for driving the self-luminous display device 10, the horizontal period HRP includes a period PWR and a period PVH. During the horizontal period HRP, a first scan signal SC1(n), a second scan signal SC2(n), a third scan signal SC3(n), a fourth scan signal SC4(n), an image data signal SL(m), an initialization voltage VINI, and a reference voltage VREF are input to the pixel 180 (pixel circuit 181). For example, the pixel 180 (pixel circuit 181) is selected in accordance with the timing of the first scan signal SC1(n), the second scan signal SC2(n), the third scan signal SC3(n), and the fourth scan signal SC4(n). The image data signal SL(m), the initialization voltage VINI, and the reference voltage VREF are input to the selected pixel 180 (pixel circuit 181) in accordance with the timing of each signal. A similar operation is performed for all pixels 180 (pixel circuits 181), and based on the image data signals SL(m) input to all pixels 180 (pixel circuits 181), an image of the frame corresponding to one frame is displayed in the display area 22 of the self-luminous display device 10.

[0068] For example, Tables 1 and 2 show the voltages (potentials) supplied to the signals and nodes in each period of each frame in the timing charts shown in FIGS.

[0069] [Table 1]

[0070] [Table 2]

[0071] <1-5-1. First Example of Method for Driving Self-Emitting Display Device 10> A first example of a method for driving the self-luminous display device 10 will be described with reference to Fig. 8. The driving method shown in the first example involves the pixel 180 (pixel circuit 181) displaying a white image based on the voltage VSIGH in the frame (K-1stFRAME) immediately before the current frame (KthFRAME), and then the pixel 180 (pixel circuit 181) displaying a black image based on the voltage VSIGL in the KthFRAME. In other words, the driving method shown in the first example involves displaying images of different colors in successive frames.

[0072] A data signal VDATA is input to each pixel 180 (pixel circuit 181) in accordance with each horizontal period HRP. The data signal VDATA is analog data (video signal) including a voltage greater than or equal to VSIGL and less than or equal to VSIGH. For example, in each horizontal period HRP, a voltage greater than or equal to VSIGL and less than or equal to VSIGH is selected using a selection signal (not shown) and supplied to the image data signal SL(m). For example, during a period in which no data is selected using the selection signal, the image data signal SL(m) is maintained at a voltage greater than or equal to VSIGL and less than or equal to VSIGH. As shown in Table 2, for example, when the voltage VSIGL is −0.5 V, the pixel 180 supplied with the voltage VSIGL does not emit light and is black. For example, when the voltage VSIGH is 3.5 V, the pixel 180 supplied with the voltage VSIGH emits light and emits a color. Also, in Table 2 or FIG. 8, for example, the voltage VH (HI) is 10V, the voltage VL (LO) is −4V, the reference voltage VREF is 0V, the initialization voltage VINI is −2V, the voltage VM is 5V, and the voltage VN is −5V.

[0073] The light-emitting period PEM of the K-1st FRAME is a period during which the pixel 180 (pixel circuit 181) emits light in accordance with the potential difference Vgs (voltage V(N2)-voltage V(N3)=voltage Vna-voltage Vnb) of the second transistor T2. For example, the pixel 180 (pixel circuit 181) emits red light, and three pixels, a pixel 180 that emits red light, a pixel 180 that emits blue light, and a pixel 180 that emits green light, emit white light.

[0074] For example, during the light emission period PEM of the (K-1)th FRAME, no data is selected using a selection signal, and the pixel 180 (pixel circuit 181) is maintained at a voltage greater than or equal to voltage VSIGL and less than or equal to voltage VSIGH based on the data signal VDATA of the (n-1)th row immediately preceding the nth row, and LO is supplied to the first scan signal SC1(n), the second scan signal SC2(n), the third scan signal SC3(n), and the fourth scan signal SC4(n). The first transistor T1, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are in the off state, and the third transistor T3 is in the on state. Furthermore, the voltage Vna supplied to the first node N1 and the second node N2 is 7 V, the voltage Vnb supplied to the third node N3 is 2.5 V, and the potential difference Vgs is 4.5 V. Therefore, the second transistor T2 can pass a current Ion based on the potential difference Vgs and the potential difference Vds according to the voltage VSIGH input during the horizontal period HRP of the (K-1st) frame. Also, when the second transistor T2 is in the on state, the current Ion flows from the driving power supply line PVDD to the light-emitting element OLED and the reference voltage line PVSS, causing the light-emitting element OLED to emit light.

[0075] During the period between the light-emitting period PEM of the (K-1st) FRAME and the period PIP, which follows the light-emitting period PEM of the (K-1st) FRAME, the pixel 180 (pixel circuit 181) receives the image data signal SL(m), which includes the data signal VDATA including the voltage VSIGL corresponding to the non-light-emitting black color. The first scan signal SC1(n) changes from a state in which LO is supplied to a state in which HI is supplied. When the first scan signal SC1(n) changes to a state in which HI is supplied, the second scan signal SC2(n) changes from a state in which LO is supplied to a state in which HI is supplied. The third scan signal SC3(n) and the fourth scan signal SC4(n) are in a state in which LO is supplied. Therefore, the fourth transistor T4 and the fifth transistor T5 change from an off state to an on state, the third transistor T3 changes from an on state to an off state, and the first transistor T1 and the sixth transistor T6 maintain their off states. As a result, the voltage supplied to the first node N1 remains at voltage Vna, and the voltage supplied to the second node N2 gradually drops from voltage Vna toward the reference voltage VREF. Also, the voltage supplied to the third node N3 gradually drops from voltage Vnb toward voltage Vnc. Because the second transistor T2 and the fifth transistor T5 are on and a current flows from the driving power line PVDD to the initialization voltage power line SVI, the light-emitting element OLED does not emit light.

[0076] During the period PIP following the period between the light-emitting period PEM and the period PIP of the (K-1st) FRAME, for example, the pixel 180 (pixel circuit 181) maintains a state in which it receives the data signal VDATA based on the image data signal SL(m) of the n-1th row immediately preceding the nth row, the first scan signal SC1(n) and the second scan signal SC2(n) maintain a state in which they are supplied with HI, and the fourth scan signal SC4(n) maintains a state in which they are supplied with LO. The third scan signal SC3(n) changes from a state in which it is supplied with LO to a state in which it is supplied with HI. Therefore, the sixth transistor T6 changes from an OFF state to an ON state, the second transistor T2, the fifth transistor T5, and the fourth transistor T4 maintain an ON state, and the first transistor T1 and the third transistor T4 maintain an OFF state.

[0077] As a result, the voltage supplied to the first node N1 gradually drops from voltage Vna toward the precharge voltage VPRC (voltage Vnd, 1.5V) and becomes voltage Vnd. The voltage supplied to the second node N2 gradually drops from voltage Vna toward the reference voltage VREF (0V) and becomes reference voltage VREF (0V). The voltage supplied to the third node N3 gradually drops from voltage Vnb toward the initialization voltage VINI (voltage Vnc, -2V) and becomes voltage Vnc. The potential difference Vgs becomes 2V (0V - -2V), and the potential difference Vds becomes 10V (8V - -2V). Because the second transistor T2 and the fifth transistor T5 are on and a current flows from the drive power supply line PVDD to the initialization voltage power supply line SVI, the light-emitting element OLED does not emit light.

[0078] As described above, during the period PIP, a precharge voltage (intermediate potential) is supplied to the first node N1, the second node N2 is initialized by the reference voltage VREF (0V), and the third node N3 is initialized by the initialization voltage VINI (-2V).

[0079] During the initial period of the horizontal period HRP of the KthFRAME following the period PIP, the image data signal SL(m) is supplied with the data signal VDATA of the voltage VSIGL of the corresponding row (n), the first scan signal SC1(n) and the second scan signal SC2(n) are maintained at HI, and the fourth scan signal SC4(n) is maintained at LO. The third scan signal SC3(n) changes from HI to LO. Therefore, the sixth transistor T6 changes from ON to OFF, the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are maintained at ON, and the first transistor T1 and the third transistor T3 are maintained at OFF. As a result, the voltage supplied to the first node N1 is maintained at voltage Vnd, the voltage supplied to the second node N2 is maintained at the reference voltage VREF (0V), and the voltage supplied to the third node N3 is maintained at voltage Vnc. Similarly to the period PIP, the light-emitting element OLED does not emit much light.

[0080] During the period PWR following the beginning of the horizontal period HRP, the image data signal SL(m) maintains a state in which the data signal VDATA of voltage VSIGL is supplied, the first scan signal SC1(n) and the second scan signal SC1(n) maintain a state in which HI is supplied, and the third scan signal SC3(n) maintains a state in which LO is supplied. The fourth scan signal SC4(n) changes from a state in which LO is supplied to a state in which HI is supplied. Therefore, the first transistor T1 changes from an OFF state to an ON state, the second transistor T2, the fourth transistor T4, and the fifth transistor T5 maintain an ON state, and the third transistor T6 and the sixth transistor T6 maintain an OFF state. As a result, the voltage supplied to the first node N1 gradually drops from voltage Vnd toward voltage VSIGL (voltage Vnf, −0.5V), the voltage supplied to the second node N2 maintains the reference voltage VREF, and the voltage supplied to the third node N3 maintains voltage Vnc. Also, similar to the period PIP, the light-emitting element OLED does not emit much light.

[0081] During the period PVH parallel to (overlapping with) the period PWR, the image data signal SL(m) maintains the state in which the data signal VDATA of voltage VSIGL is supplied, the first scan signal SC1(n) and the fourth scan signal SC4(n) maintain the state in which HI is supplied, and the third scan signal SC3(n) maintains the state in which LO is supplied. The second scan signal SC2(n) changes from the state in which HI is supplied to the state in which LO is supplied. Therefore, the fifth transistor T5 changes from the ON state to the OFF state, the first transistor T1 and the fourth transistor T4 maintain the ON state, and the third transistor T6 and the sixth transistor T6 maintain the OFF state. As a result, the voltage supplied to the first node N1 gradually drops toward voltage Vnf, and the voltage supplied to the second node N2 maintains the reference voltage VREF.

[0082] Immediately after the start of the period PVH, the potential difference Vgs is 2 V, the potential difference Vds is 10 V, and both the potential difference Vgs and the potential difference Vds are greater than the threshold voltage VTH (1 V), so the second transistor T2 is in the ON state. Therefore, a drain current Ion flows from the second electrode 626 of the second transistor T2 to the first electrode 624. Although the fifth transistor T5 is in the OFF state, the second transistor T2 is in the ON state, so the drain current Ion flows from the drive power line PVDD (the second electrode 626 side) to the third node N3 (the first electrode 624 side), and the voltage supplied to the third node N3 gradually rises from the voltage Vnc.

[0083] When the potential difference Vgs reaches the threshold voltage VTH, the second transistor T2 changes from the on state to the off state, and the drain current Ion stops flowing. At this time, the voltage supplied to the third node N3 rises from the voltage Vnc (-2V) to the voltage Vne (-1V), and the potential difference Vgs is the same as the threshold voltage VTH (1V). Since the second transistor T2 is in the off state and no current flows from the driving power line PVDD to the reference voltage line PVSS, the light-emitting element OLED does not emit light.

[0084] During the final period of the period PVH, the image data signal SL(m) maintains the state in which the data signal VDATA of the voltage VSIGL is supplied, the first scan signal SC1(n) maintains the state in which HI is supplied, and the second scan signal SC2(n) and the third scan signal SC3(n) maintain the state in which LO is supplied. The fourth scan signal SC4(n) changes from the state in which HI is supplied to the state in which LO is supplied. Furthermore, when the fourth scan signal SC4(n) changes to the state in which LO is supplied, the first scan signal SC1(n) changes from the state in which HI is supplied to the state in which LO is supplied. Therefore, the third transistor changes from the off state to the on state, the first transistor T1 and the fourth transistor change from the on state to the off state, and the second transistor T2, the fifth transistor T5, and the sixth transistor T6 maintain their off states. As a result, the first node N1 becomes conductive with the second node N2, the voltage supplied to the second node N2 gradually drops toward voltage Vnf and reaches voltage Vnf, the voltage supplied to the first node N1 maintains voltage Vnf, and the voltage supplied to the third node N3 maintains voltage Vne. Note that the potential difference Vgs is 1 V, the potential difference Vds is 9 V, and the potential difference Vgs is the same as the threshold voltage VTH, so no current flows from the driving power line PVDD to the reference voltage line PVSS. Furthermore, the light-emitting element OLED does not emit light.

[0085] In this way, during the period PWR, the data signal VDATA is written to the pixel 180 (pixel circuit 181). During the period PVH, the threshold voltage VTH of the second transistor T2 is acquired by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is held at the third node N3 (the first electrode 692 of the capacitance element CS).

[0086] The light emission period PEM of the KthFRAME following the horizontal period HRP of the KthFRAME is a period during which the pixel 180 emits light based on the voltage VSIGL supplied to the first node N1 and the potential difference Vgs between the voltage supplied to the second node N2 and the voltage supplied to the third node N3.

[0087] For example, during the light emission period PEM of the Kth FRAME, no data is selected using a selection signal, and the pixel 180 (pixel circuit 181) is maintained at a voltage greater than or equal to the voltage VSIGL and less than or equal to the voltage VSIGH based on the data signal VDATA of the (n+1)th row after the nth row. Also, the first scan signal SC1(n), the second scan signal SC2(n), the third scan signal SC3(n), and the fourth scan signal SC4(n) maintain a state in which LO is supplied.

[0088] Therefore, the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 remain in the off state, and the third transistor T3 remains in the on state. Because the second transistor T2 is in the off state and no current flows from the driving power supply line PVDD to the reference voltage line PVSS, the light-emitting element OLED does not emit light. As a result, for example, the pixel 180 (pixel circuit 181) that emits red light turns black. Similarly to the pixel 180 that emits red light, the pixel 180 that emits blue light and the pixel 180 that emits green light also do not emit light, so the three pixels that use the pixel 180 that emits red light, the pixel 180 that emits blue light, and the pixel 180 that emits green light turn black.

[0089] The light-emitting display device 10 includes a sixth transistor T6 for supplying a precharge voltage (intermediate potential) to the first node N1, and a first transistor T1 for supplying a data signal VDATA that is equal to or greater than a voltage VSIGL and equal to or less than a voltage VSIGH to the first node N1. A method for driving the light-emitting display device 10 includes supplying the precharge voltage to the first node N1 by the sixth transistor T6, and, after supplying the precharge voltage to the first node N1, supplying a data signal VDATA that is equal to or greater than a voltage VSIGL and equal to or less than a voltage VSIGH to the first node N1 by the first transistor T1. That is, the light-emitting display device 10 can supply the intermediate potential to the first node N1, and then supply the data signal VDATA to the first node N1. For example, when a black image is displayed based on the voltage VSIGL in the K-1st FRAME and then a white image is displayed based on the voltage VSIGH in the Kth FRAME, the first node N1 is supplied with the voltage VSIGL (-0.5V), then with the intermediate potential (1.5V), and then with the voltage VSIGH (3.5V). That is, when writing a data voltage, the fluctuation in the potential of the first node N1 is 2V (3.5V-(1.5V)).

[0090] On the other hand, for example, in a display device including a configuration that supplies the data signal VDATA without supplying an intermediate potential to the first node N1, when a black image is displayed in the K-1st FRAME based on the voltage VSIGL and then a white image is displayed in the Kth FRAME based on the voltage VSIGH, the display device first supplies the pixel (pixel circuit) with the voltage VSIGL (-0.5V) and then with the voltage VSIGH (3.5V). As a result, in a display device including a configuration that supplies the data signal VDATA without supplying the intermediate potential to the first node N1, the fluctuation in the potential in the pixel (pixel circuit) is 4V (3.5V-(-0.5V)), which is larger than that of the self-luminous display device 10.

[0091] Therefore, when writing the data signal VDATA to a pixel (pixel circuit), the self-luminous display device 10 can supply the data signal VDATA after supplying an intermediate potential to the first node N1, so that fluctuations in the potential of the first node N1 in the self-luminous display device 10 can be made smaller than in a display device that supplies a data voltage without supplying an intermediate potential to the first node N1.

[0092] When the data signal VDATA is supplied to a pixel (pixel circuit), a reduction in fluctuations in the potential of the first node N1 is equivalent to a reduction in fluctuations in the potential of the image data signal line 321 to which the data signal VDATA is supplied. If the fluctuations in the potential of the image data signal line 321 are large, unwanted electromagnetic interference (EMI) caused by the fluctuations in the potential of the image data signal line 321 increases. The self-luminous display device 10 can reduce the fluctuations in the potential of the image data signal line 321, and therefore can reduce unwanted electromagnetic interference (EMI) caused by the fluctuations in the potential of the image data signal line 321.

[0093] Furthermore, since the self-luminous display device 10 can reduce fluctuations in the potential of the first node N1, the time required to write data to the first node N1 in the self-luminous display device 10 (writing speed) can be made shorter than that of a display device that supplies the data signal VDATA without supplying an intermediate potential to the first node N1. In other words, the self-luminous display device 10 can have a writing speed faster than that of a display device that supplies the data signal VDATA without supplying an intermediate potential to the first node N1.

[0094] Furthermore, the self-emissive display device 10 can increase the speed at which data is written to the first node N1, thereby shortening the time required for the horizontal period HRP. As a result, for example, the self-emissive display device 10 can increase the number of pixels that can be written in a shortened time. Therefore, the self-emissive display device 10 can provide a high-resolution display device and a large-screen display device.

[0095] Furthermore, since the self-luminous display device 10 can reduce fluctuations in the potential of the first node N1, the power consumption when writing data to the first node N1 in the self-luminous display device 10 can be reduced (suppressed) compared to a display device that supplies a data signal VDATA without supplying an intermediate potential to the first node N1.

[0096] Furthermore, the driving method of the self-luminous display device 10 includes a configuration in which the period PVH starts after the period PWR starts and ends after the period PWR ends. That is, a portion of the period PWR overlaps with the period PVH, and the period PVH is shifted from the period PWR. On the other hand, for example, in a driving method in which the shift between the periods PWR and PVH is small, when the second transistor T2 is turned on, the potential fluctuation of the third node N3 may become large depending on the magnitude of the data voltage (first node N1). As described above, the driving method of the self-luminous display device 10 includes a configuration in which the period PVH is shifted from the period PWR, and therefore the potential fluctuation of the third node N3 is small.

[0097] <1-5-2. Second Example of Method for Driving Self-Emitting Display Device 10> A second example of a method for driving the self-luminous display device 10 will be described with reference to FIG. 9. The driving method shown in the second example involves the pixel 180 (pixel circuit 181) displaying a white image based on the voltage VSIGH of the data signal VDATA in the frame (K-1stFRAME) immediately preceding the current frame (KthFRAME), and then the pixel 180 (pixel circuit 181) also displaying a white image based on the voltage VSIGH of the data signal VDATA in the KthFRAME. In other words, the driving method shown in the second example involves displaying images of the same color (white) in consecutive frames. Configurations that are the same as or similar to those in FIGS. 1 to 8 will be described as necessary.

[0098] The configurations of the first scan signal SC1(n), the second scan signal SC2(n), the third scan signal SC3(n), and the fourth scan signal SC4(n), the image data signal SL(m) in the light-emitting period PEM of the K-1st FRAME, and the image data signal SL(m) in the light-emitting period PEM of the Kth FRAME are the same as those described in "1-5-1. First Example of a Method for Driving a Self-Light-Emitting Display Device 10." Furthermore, the voltages (potentials) of the first node N1, the second node N2, and the third node N3 in periods other than the horizontal period HRP of the Kth FRAME and the light-emitting period PEM of the Kth FRAME are the same as those described in "1-5-1. First Example of a Method for Driving a Self-Light-Emitting Display Device 10." Furthermore, the operation of each transistor in each period is generally the same as the configuration described in "1-5-1. First Example of a Method for Driving a Self-Light-Emitting Display Device 10." Therefore, configurations similar to those explained in "1-5-1. First example of the method for driving the self-luminous display device 10" will be explained as necessary. Note that, as for the image data signal SL(m), the data signal VDATA of VSIGH corresponding to white is supplied during the period between the light emitting period PEM of the K-1st FRAME and the light emitting period PEM of the Kth FRAME.

[0099] In the initial period of the horizontal period HRP of the Kth FRAME following the period PIP, the pixel 180 (pixel circuit 181) receives the image data signal SL(m) including the data signal VDATA of the voltage VSIGH corresponding to white. The configuration except for the image data signal SL(m) in the initial period of the horizontal period HRP of the Kth FRAME is the same as that described in "1-5-1. First example of the method for driving the self-luminous display device 10".

[0100] During the period PIP in the second example, similar to what was explained in "1-5-1. First example of the method for driving the self-luminous display device 10", a precharge voltage (intermediate potential) is supplied to the first node N1, the second node N2 is initialized by the reference voltage VREF (0V), and the third node N3 is initialized by the initialization voltage VINI (-2V).

[0101] In the period PWR following the initial period of the horizontal period HRP in the second example, the operation of each transistor is the same as the configuration explained in "1-5-1. First Example of the Method for Driving the Self-Emitting Display Device 10." The voltage supplied to the first node N1 gradually rises from voltage Vnd toward voltage VSIGH (voltage Vng, 3.5V), the voltage supplied to the second node N2 maintains the reference voltage VREF, and the voltage supplied to the third node N3 maintains voltage Vnc. Also, as in the period PIP, the light-emitting element OLED does not emit light.

[0102] In the second example, during the period PVH that is parallel to (overlaps with) the period PWR, the operation of each transistor is the same as the configuration described in "1-5-1. First example of the method for driving the self-luminous display device 10," and the voltage supplied to the first node N1 gradually rises toward voltage Vng (3.5V) and becomes voltage Vng, while the voltage supplied to the second node N2 maintains the reference voltage VREF.

[0103] In the second example, immediately after the start of the period PVH, the potential difference Vgs is 2 V, the potential difference Vds is 10 V, and both the potential difference Vgs and the potential difference Vds are greater than the threshold voltage VTH (1 V), so the second transistor T2 is in the ON state. Therefore, a drain current Ion flows from the second electrode 626 of the second transistor T2 to the first electrode 624. Although the fifth transistor T5 is in the OFF state, the second transistor T2 is in the ON state, so the drain current Ion flows from the driving power line PVDD (the second electrode 626 side) to the third node N3 (the first electrode 624 side), and the voltage supplied to the third node N3 gradually rises from the voltage Vnc.

[0104] When the potential difference Vgs reaches the threshold voltage VTH, the second transistor T2 changes from the on state to the off state, and the drain current Ion stops flowing. At this time, the voltage supplied to the third node N3 rises from the voltage Vnc (-2V) to the voltage Vne (-1V), and the potential difference Vgs is the same as the threshold voltage VTH (1V). Since the second transistor T2 is in the off state and no current flows from the driving power line PVDD to the reference voltage line PVSS, the light-emitting element OLED does not emit light.

[0105] During the final period of the period PVH in the second example, the operation of each transistor is the same as that described in "1-5-1. First Example of the Method for Driving the Self-luminous Display Device 10," and the first node N1 is electrically connected to the second node N2, causing the voltage at the second node N2 to gradually rise. As a result, the second transistor T2 is electrically connected, causing a drain current Ion to flow from the drive power supply line PVDD to the reference voltage line PVSS. Therefore, the voltages at the first node N1 and the third node N3 rise in accordance with the rise in the voltage at the second node N2. Due to the rise in the voltage at the third node N3, the voltages at the first node N1 and the second node N2 further rise.

[0106] Furthermore, in the light emission period PEM of the Kth FRAME following the horizontal period HRP of the Kth FRAME in the second example, for example, the voltages of the first node N1 and the second node N2 rise to voltage Vna, and the voltage of the third node N3 rises to voltage Vnb. As a result, the potential difference Vgs becomes voltage Vna (7V) minus voltage Vnb (2.5V). That is, the potential difference Vgs becomes 4.5V, which is greater than the threshold voltage VTH (1V). Therefore, the second transistor T2 is in an on state, and a drain current Ion flows from the driving power supply line PVDD to the reference voltage line PVSS, causing the light emitting element OLED to emit light. For example, the pixel 180 (pixel circuit 181) emits red, and three pixels, including a pixel 180 emitting blue and a pixel 180 emitting green, emit white.

[0107] As described above, during the period PWR in the second example, the data signal VDATA is written to the pixel 180 (pixel circuit 181). During the period PVH in the second example, the threshold voltage VTH of the second transistor T2 is acquired by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is held at the third node N3 (the first electrode 692 of the capacitive element CS). During the light emission period PEM of the KthFRAME in the second example, three pixels emit white light.

[0108] The second example of the method for driving the self-luminous display device 10 has the same effects as those described in "1-5-1. First example of the method for driving the self-luminous display device 10."

[0109] <1-5-3. Third Example of Method for Driving Self-Emitting Display Device 10> A third example of a method for driving the self-luminous display device 10 will be described with reference to FIG. 10. The driving method shown in the third example involves the pixel 180 (pixel circuit 181) displaying a black image based on the voltage VSIGL of the data signal VDATA in the frame (K-1st FRAME) immediately preceding the current frame (Kth FRAME), and then the pixel 180 (pixel circuit 181) also displaying a black image based on the voltage VSIGL of the data signal VDATA in the Kth FRAME. In other words, the driving method shown in the third example involves displaying images of the same color (black) in consecutive frames. Configurations that are the same as or similar to those in FIGS. 1 to 9 will be described as necessary.

[0110] The configurations of the first scan signal SC1(n), the second scan signal SC2(n), the third scan signal SC3(n), and the fourth scan signal SC4(n), the image data signal SL(m) in the light emission period PEM of the K-1st FRAME, and the image data signal SL(m) in the light emission period PEM of the Kth FRAME are the same as those described in "1-5-1. First Example of a Method for Driving a Self-Light-Emitting Display Device 10." Furthermore, the voltages (potentials) of the first node N1, the second node N2, and the third node N3 in the horizontal period HRP and the light emission period PEM of the Kth FRAME, and the operation of each transistor are the same as those described in "1-5-1. First Example of a Method for Driving a Self-Light-Emitting Display Device 10." Configurations similar to those in "1-5-1. First Example of a Method for Driving a Self-Light-Emitting Display Device 10" and "1-5-2. Second Example of a Method for Driving a Self-Light-Emitting Display Device 10" will be explained as necessary. In addition, the image data signal SL(m) is supplied with a data signal VDATA of voltage VSIGL corresponding to black in the period between the light emitting period PEM of the (K-1)th FRAME and the light emitting period PEM of the Kth FRAME.

[0111] The light-emitting period PEM of the K-1st FRAME is a period during which the pixel 180 (pixel circuit 181) emits light in accordance with the potential difference Vgs (voltage V(N2) - voltage V(N3) = Vnf (-0.5 V) - voltage Vne (-1 V). For example, the potential difference Vgs is 0.5 V, which is smaller than the threshold voltage VTH of the second transistor T2. Therefore, the second transistor T2 is in the off state, and no current flows from the drive power supply line PVDD to the reference voltage line PVSS, so the light-emitting element OLED does not emit light. As a result, for example, the pixel 180 (pixel circuit 181) turns black.

[0112] During the period between the light-emitting period PEM of the (K-1st) FRAME and the period PIP following the light-emitting period PEM of the (K-1st) FRAME, the voltage supplied to the first node N1 remains at voltage Vnf, and the voltage supplied to the second node N2 gradually increases from voltage Vnf toward the reference voltage VREF. Furthermore, the voltage supplied to the third node N3 gradually decreases from voltage Vnb toward voltage Vnc. Since the second transistor T2 and the fifth transistor T5 are on and a current flows from the driving power supply line PVDD to the initialization voltage power supply line SVI, the light-emitting element OLED does not emit light.

[0113] During the period PIP following the period between the light-emitting period PEM and the period PIP of the (K-1st) frame, the voltage supplied to the first node N1 gradually increases from voltage Vnf toward the precharge voltage VPRC (voltage Vnd, 1.5V) and reaches voltage Vnd. The voltage supplied to the second node N2 gradually increases from voltage Vnf toward the reference voltage VREF (0V) and reaches reference voltage VREF (0V). The voltage supplied to the third node N3 gradually decreases from voltage Vne toward the initialization voltage VINI (voltage Vnc, -2V) and reaches voltage Vnc. The potential difference Vgs becomes 2V (0V - -2V), and the potential difference Vds becomes 10V (8V - -2V). Because the second transistor T2 and the fifth transistor T5 are on and a current flows from the drive power supply line PVDD to the initialization voltage power supply line SVI, the light-emitting element OLED does not emit light.

[0114] As described above, during the period PIP in the third example, a precharge voltage (intermediate potential) is supplied to the first node N1, the second node N2 is initialized by the reference voltage VREF (0V), and the third node N3 is initialized by the initialization voltage VINI (-2V).

[0115] As described above, the voltages (potentials) of the first node N1, the second node N2 and the third node N3, as well as the operation of each transistor, during the horizontal period HRP and the light-emitting period PEM of KthFRAME following the period PIP are the same as those in "1-5-1. First example of the method for driving the self-luminous display device 10."

[0116] Furthermore, during the period PWR in the third example, a data signal VDATA (voltage VSIGL in the third example) is written to the pixel 180 (pixel circuit 181) as in "1-5-1. First example of the method for driving the self-luminous display device 10." Furthermore, during the period PVH, the threshold voltage VTH of the second transistor T2 is acquired by an operation in which the potential difference Vgs of the second transistor T2 becomes equal to the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is held at the third node N3 (first electrode 692 of the capacitance element CS).

[0117] Furthermore, during the light emission period PEM of KthFRAME, as in "1-5-1. First example of the driving method of the self-luminous display device 10", the pixel 180 that emits red light, the pixel 180 that emits blue light, and the pixel 180 that emits green light do not emit light, so the three pixels using the pixel 180 that emits red light, the pixel 180 that emits blue light, and the pixel 180 that emits green light are black.

[0118] The third example of the method for driving the self-luminous display device 10 has the same effects as those described in "1-5-1. First example of the method for driving the self-luminous display device 10."

[0119] <1-5-4. Fourth Example of the Method for Driving the Self-Emitting Display Device 10> A fourth example of a method for driving the self-luminous display device 10 will be described with reference to FIG. 11. The driving method shown in the fourth example involves the pixel 180 (pixel circuit 181) displaying a black image based on the voltage VSIGL of the data signal VDATA in the frame (K-1st FRAME) immediately before the current frame (Kth FRAME), and then the pixel 180 (pixel circuit 181) displaying a white image based on the voltage VSIGH of the data signal VDATA in the Kth FRAME. In other words, the driving method shown in the fourth example involves displaying images of different colors in successive frames. Configurations that are the same as or similar to those in FIGS. 1 to 11 will be described as necessary.

[0120] The configurations of the first scan signal SC1(n), the second scan signal SC2(n), the third scan signal SC3(n), and the fourth scan signal SC4(n), the image data signal SL(m) in the light emitting period PEM of the K-1stFRAME, and the image data signal SL(m) in the light emitting period PEM of the KthFRAME are the same as those described in "1-5-1. First example of the method for driving the self-luminous display device 10." Furthermore, the voltages (potentials) of the first node N1, the second node N2, and the third node N3, and the operation of each transistor during the horizontal period HRP and the light emission period PEM of the KthFRAME are the same as those in "1-5-2. Second Example of the Method for Driving the Self-Light-Emitting Display Device 10," and the voltages (potentials) of the first node N1, the second node N2, and the third node N3, and the operation of each transistor during periods other than the horizontal period HRP and the light emission period PEM of the KthFRAME are the same as those in "1-5-3. Third Example of the Method for Driving the Self-Light-Emitting Display Device 10." Configurations similar to those in "1-5-1. First Example of the Method for Driving the Self-Light-Emitting Display Device 10," "1-5-2. Second Example of the Method for Driving the Self-Light-Emitting Display Device 10," and "1-5-3. Third Example of the Method for Driving the Self-Light-Emitting Display Device 10" will be explained as necessary. Note that, as for the image data signal SL(m), a data signal VDATA including a voltage VSIGH corresponding to white is supplied in the period between the light emission period PEM of the (K-1st) FRAME and the light emission period PEM of the Kth FRAME.

[0121] In the light emission period PEM of the (K-1st) frame in the fourth example, the pixel 180 (pixel circuit 181) turns black, as in "1-5-3. Third example of the method for driving the self-luminous display device 10."

[0122] During the period PIP in the fourth example, as in "1-5-3. Third example of the method for driving the self-luminous display device 10," a precharge voltage (intermediate potential) is supplied to the first node N1, the second node N2 is initialized by the reference voltage VREF (0V), and the third node N3 is initialized by the initialization voltage VINI (-2V).

[0123] During the period PWR in the fourth example, a data signal VDATA (voltage VSIGH in the fourth example) is written to the pixel 180 (pixel circuit 181) as in "1-5-2. Second example of the method of driving the self-luminous display device 10." Furthermore, during the period PVH, the threshold voltage VTH of the second transistor T2 is acquired by an operation in which the potential difference Vgs of the second transistor T2 becomes equal to the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is held at the third node N3 (first electrode 692 of the capacitance element CS).

[0124] Furthermore, during the light emission period PEM of KthFRAME, as in "1-5-2. Second example of the driving method of the self-luminous display device 10", the pixel 180 that emits red light, the pixel 180 that emits blue light, and the pixel 180 that emits green light emit light, and white light is emitted by the three pixels using the pixel 180 that emits red light, the pixel 180 that emits blue light, and the pixel 180 that emits green light.

[0125] The fourth example of the method for driving the self-luminous display device 10 has the same effects as those described in "1-5-1. First example of the method for driving the self-luminous display device 10."

[0126] <1-6. Cross-sectional structure of pixel 180 taken along line A1-A2> The cross-sectional structure of pixel 180 taken along line A1-A2 will be described with reference to FIGS. 5, 12, and 13. FIG. 12 is a layout diagram of pixel 180. FIG. 13 is a cross-sectional view showing a cross section taken along line A1-A2 in the planar layout of pixel 180 shown in FIG. 12. The layout of pixel 180 shown in FIG. 12 and the cross-section of pixel 180 shown in FIG. 13 are merely examples, and the planar layout and cross-section of pixel 180 are not limited to the examples shown in FIGS. 12 and 13. Configurations that are the same as or similar to those in FIGS. 1 to 11 will be described as necessary.

[0127] The cross section of pixel 180 shown in Figure 13 is an example of a cross section of pixel 180, and is a cross section along the drive power line PVDD, the contact hole opening 147 for the anode electrode, the first wiring 132B, the first electrode 692 and the second electrode 694 of the capacitance element CS, the gate electrode 622 of the second transistor T2, the channel region 123 of the semiconductor layer 122, the organic insulating film opening 138A for the capacitance element CS, the second contact hole opening 138B, the first wiring 132D, the first contact hole opening 135, the impurity region 124A, the scan signal line 331, the reference voltage power line SVR, the scan signal line 332, the precharge voltage power line SVP, and the initialization voltage power line SVI.

[0128] The substrate 101 includes a first surface 101A and a second surface 101B opposite to the first surface 101A. A semiconductor layer 122 is provided on the first surface 101A of the substrate 101 via an underlayer 121. The semiconductor layer 122 includes a semiconductor layer 122A, which includes a channel region 123 and an impurity region 124A. For example, the impurity region is called a source region or a drain region. Also, for example, the second transistor T2 and the fifth transistor T5 include the semiconductor layer 122A, and the first electrode 624 and the second electrode 656 include the impurity region 124A. In other words, the semiconductor layer 122A includes the channel region of the second transistor T2 and the channel region of the fifth transistor T5.

[0129] A gate insulating layer 125, a conductive layer 126, an insulating layer 128, and a conductive layer 132 are provided on the semiconductor layer 122 in this order. The conductive layer 126 includes a gate wiring 127A (gate electrode 622), a gate wiring 127B (scan signal line 331), a gate wiring 127C (reference voltage power supply line SVR), a gate wiring 127E (scan signal line 332), a gate wiring 127F (precharge voltage power supply line SVP), and a gate wiring 127D (initialization voltage power supply line SVI). The conductive layer 132 includes a first wiring 132A (drive power supply line PVDD), a first wiring 132B, a first wiring 132C (second electrode 694), and a first wiring 132D. The region where the conductive layer 126 and the semiconductor layer 122 overlap is a channel region. In other words, the region where the gate electrode and the semiconductor layer of each transistor overlap is a channel region.

[0130] Each of the transistors of the pixel 180 is formed using a semiconductor layer 122 (channel region 123 and impurity region 124A), a gate insulating layer 125, and a conductive layer 126 (for example, gate wiring 127A).

[0131] A first contact hole opening 135 reaching the semiconductor layer 122 is provided in the gate insulating layer 125 and the insulating layer 128. The first contact hole opening 135 exposes the semiconductor layer 122 (e.g., impurity region 124A). The conductive layer 132 is electrically connected to the semiconductor layer 122 (e.g., impurity region 124A) through the first contact hole opening 135. An opening (not shown) reaching the conductive layer 126 (e.g., gate wiring 127A) may also be provided in the insulating layer 128.

[0132] An insulating layer 131 is provided to cover the conductive layer 132. An insulating layer 136 is provided to cover the insulating layer 131.

[0133] A second contact hole opening 138B is provided in the insulating layer 131 and the insulating layer 136. An organic insulating film opening 138A for the capacitor element CS is provided in the insulating layer 136. A conductive layer 139 is provided on the insulating layer 136, in the organic insulating film opening 138A for the capacitor element CS and the second contact hole opening 138B. The conductive layer 139 includes a second wiring 140A (first electrode 692), a second wiring 140B, a second wiring 140D, and a second wiring 140C. The second contact hole opening 138B exposes the conductive layer 132 (e.g., the first wiring 132D). For example, the second contact hole opening 138B electrically connects the first electrode 692 and the first wiring 132D. The organic insulating film opening 138A for the capacitor element CS exposes the insulating layer 131. For example, the capacitance element CS is formed using the first wiring 132C (second electrode 694) and the second wiring 140A (first electrode 692) with the insulating layer 131 as a dielectric. For example, the second wiring 140A also serves as a pixel electrode. Although not shown, the second contact hole opening 138 exposes some of the multiple terminals (not shown) included in the terminal section 150. Some of the exposed terminals are electrically connected to the FPC 200 using a conductive film such as an anisotropic conductive film (not shown).

[0134] An insulating layer 141 is provided over the conductive layer 139 .

[0135] The base layer 121 , the semiconductor layer 122 , the gate insulating layer 125 , the conductive layer 126 , the insulating layer 128 , the conductive layer 132 , the insulating layer 131 , the insulating layer 136 , the conductive layer 139 , and the insulating layer 141 are collectively referred to as an array section 170 .

[0136] Next, a description will be given of layers above the insulating layer 141. An anode electrode contact hole opening 147 is provided in the insulating layer 141. The anode electrode contact hole opening 147 exposes the conductive layer 139 (for example, the second wiring 140A).

[0137] An anode electrode 143 is provided to cover the exposed conductive layer 139, the anode electrode contact hole opening 147, and the insulating layer 141. A functional layer 148 is provided on the anode electrode 143. A common electrode 149 is provided on the functional layer 148 to cover the functional layer 148. The common electrode 149 is a cathode electrode (first electrode 682 of the light-emitting element OLED). Here, the light-emitting element OLED is composed of the anode electrode 143, the functional layer 148, and the common electrode 149 (cathode electrode).

[0138] The configuration of the functional layer 148 can be selected as appropriate. For example, the functional layer 148 can be configured by combining a carrier injection layer, a carrier transport layer, an emission layer, a carrier blocking layer, an exciton blocking layer, etc. For example, the functional layer 148 shown in Fig. 13 includes a first layer 144, a second layer 145, and a third layer 146. For example, the first layer 144 is a carrier (hole) injection and transport layer, the second layer 145 is a emission layer, and the third layer 146 is a carrier (electron) injection and transport layer.

[0139] A sealing film 165 is provided on the common electrode 149. For example, the sealing film 165 includes a first inorganic insulating layer 152, an organic insulating layer 154, and a second inorganic insulating layer 156. The first inorganic insulating layer 152 and the second inorganic insulating layer 156 are formed so as to cover at least the display region 22. A cover film 158 is disposed on the second inorganic insulating layer 156.

[0140] For example, the first layer 144, the second layer 145 (light-emitting layer), and the third layer 146 included in the functional layer 148, as well as the common electrode 149, are not disposed on the IC chip 110 and the control circuit 120. A sealing film 165 and a cover film 158 are disposed on the IC chip 110 and the control circuit 120. The sealing film 165 and the cover film 158 prevent impurities (water, oxygen, etc.) from entering the light-emitting element OLED, each transistor, etc. from the outside of the self-luminous display device 10.

[0141] Common metal materials are used for the conductive layer 126, the conductive layer 132, the conductive layer 139, and the common electrode 149. For example, common metal materials include aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), and alloys or compounds thereof.

[0142] For example, the semiconductor layer 122 may include LTPS, and may include a metal oxide.

[0143] A general insulating material can be used as the material for forming the base layer 121, the gate insulating layer 125, the insulating layer 131, the first inorganic insulating layer 152, and the second inorganic insulating layer 156. For example, silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), silicon nitride (SiN x ), silicon oxynitride (SiN x O y Inorganic insulating layers such as the above are used.

[0144] For example, an organic compound material with excellent surface flatness can be used as the material for forming the insulating layer 128, the insulating layer 136, the insulating layer 141, and the organic insulating layer 154. The insulating layer 128, the insulating layer 136, and the insulating layer 141 may be referred to as organic insulating layers.

[0145] <1-7. Method for manufacturing the self-luminous display device 10> A method for manufacturing the self-luminous display device 10 (pixel 180) will be described with reference to Fig. 5 and Fig. 12 to Fig. 17. Fig. 14 is a sequence diagram showing the method for manufacturing the self-luminous display device 10. Figs. 15 to 17 are layout diagrams of the pixel 180. Configurations that are the same as or similar to those in Figs. 1 to 13 will be described as necessary.

[0146] As shown in FIG. 13, when the manufacture of the self-luminous display device 10 (pixel 180) starts, the base layer 121 is formed on the first surface 101A of the substrate 101.

[0147] As shown in FIG. 13 or 15, a semiconductor layer 122 is formed on the base layer 121 (step 10 (S10) of FIG. 14). The semiconductor layer 122 includes semiconductor layers 122A, 122B, 122C, and 122D. The semiconductor layer 122A serves as the semiconductor layer of both the second transistor T2 and the fifth transistor T5. The semiconductor layer 122B serves as the semiconductor layer of both the first transistor T1 and the third transistor T3. The semiconductor layer 122C is the semiconductor layer of the fourth transistor T4. The semiconductor layer 122D is the semiconductor layer of the sixth transistor T6. In other words, the semiconductor layer 122B includes the channel region of the first transistor T1 and the channel region of the third transistor T3, the semiconductor layer 122C includes the channel region of the fourth transistor T4, and the semiconductor layer 122D includes the channel region of the sixth transistor T6.

[0148] Impurities are implanted into the semiconductor layer 122 (step 11 (S11) of FIG. 14). S11 forms an impurity region 124A. For example, referring to FIG. 15, the first electrode 614, the second electrode 616, the first electrode 624, the second electrode 626, the first electrode 644, the second electrode 646, the first electrode 654 and the second electrode 656, and the first electrode 664 and the second electrode 666 include impurity regions implanted with impurities such as phosphorus (P). Also, referring to FIG. 15, for example, the first electrode 634 and the second electrode 636 include impurity regions implanted with impurities such as boron (B).

[0149] A gate insulating layer 125 (FIG. 13) is formed on the semiconductor layer 122 and on the underlying layer 121 where the semiconductor layer 122 is not formed (step 12 (S12) in FIG. 14).

[0150] A conductive layer 126 (FIG. 13) is formed on the gate insulating layer 125 (step 13 (S13) of FIG. 14). As shown in FIG. 13 or FIG. 15, the conductive layer 126 includes a gate wiring 127A (gate electrode 622), a gate wiring 127B (scan signal line 331), a gate wiring 127C (reference voltage power supply line SVR), a gate wiring 127E (scan signal line 332), a gate wiring 127F (precharge voltage power supply line SVP), a gate wiring 127D (initialization voltage power supply line SVI), a scan signal line 330, and a scan signal line 333. The gate wiring 127B (scan signal line 331) includes a gate electrode 652. The scan signal line 330 includes a gate electrode 632 and a gate electrode 642, and the scan signal line 333 includes a gate electrode 612.

[0151] The overlapping region between the gate electrode 622 and the semiconductor layer 122A of the second transistor T2 is the channel region 123, which corresponds to the channel length of the second transistor T2. Similarly, the overlapping region between the gate electrode 612 and the semiconductor layer 122B of the first transistor T1 is the channel region and the channel length of the first transistor T1. The overlapping region between the third transistor T3 and the semiconductor layer 122B is the channel region and the channel length of the third transistor T3. The overlapping region between the fourth transistor T4 and the semiconductor layer 122C is the channel region and the channel length of the fourth transistor T4. The overlapping region between the fifth transistor T5 and the semiconductor layer 122A is the channel region and the channel length of the fifth transistor T5. The overlapping region between the sixth transistor T6 and the semiconductor layer 122D is the channel region and the channel length of the sixth transistor T6.

[0152] 15 , in a plan view, the channel region 123 of the second transistor T2 is larger (longer) than the channel regions of the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6. That is, the channel length of the second transistor T2 is longer than the channel lengths of the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6. Because the second transistor T2 operates in the saturation region, the hot carrier resistance of the second transistor T2 must be higher than the hot carrier resistance of the other transistors in the pixel 180. As a result, the channel length of the second transistor T2 is longer than the channel lengths of the other transistors in the pixel 180.

[0153] An insulating layer 128 (FIG. 13) is formed on the conductive layer 126 and on the gate insulating layer 125 where the conductive layer 126 is not formed (step 14 (S14) in FIG. 14).

[0154] As shown in FIG. 13 or 15, first contact hole openings 135, 135A, 135B, 135C, 135D, 135E, 135F, 135G, 135H, 135J, 135K, 135L, 135M, and 135N are opened (step 15 (S15)). Each opening opens the gate insulating layer 125 and the insulating layer 128, exposing the corresponding wiring, semiconductor layer, or electrode. For example, first contact hole opening 135 exposes the semiconductor layer 122A (e.g., impurity region 124A), and first contact hole opening 135A exposes the gate wiring 127D. The other openings also expose the corresponding wiring, semiconductor layer, or electrode.

[0155] The conductive layer 132 (FIG. 13) is formed on the insulating layer 128 (step 16 (S16)). As shown in FIG. 13 or 16, the conductive layer 132 includes a first wiring 132A (driving power supply line PVDD), a first wiring 132B, a first wiring 132C (second electrode 694), a first wiring 132D, a first wiring 132E, a first wiring 132F, a first wiring 132G, a first wiring 132H, a first wiring 132J, and an image data signal line 321.

[0156] As shown in FIG. 16, in a plan view, the first wiring 132A is electrically connected to the second electrode 626 via the first contact hole opening 135D, the first wiring 132B is electrically connected to the first electrode 644 via the first contact hole opening 135J, the second electrode 694 is electrically connected to the second electrode 616 and the second electrode 636 via the first contact hole opening 135G and is electrically connected to the second electrode 666 via the first contact hole opening 135L, and the first wiring 132D is electrically connected to the second electrode 656 and the first electrode 624 via the first contact hole opening 135. 16, in plan view, first wiring 132E is electrically connected to initialization voltage power supply line SVI through first contact hole opening 135A and is electrically connected to first electrode 654 through first contact hole opening 135C, first wiring 132F is electrically connected to second electrode 646 through first contact hole opening 135K, first wiring 132G is electrically connected to second electrode 636 through first contact hole opening 135F and is electrically connected to first electrode 656 through first contact hole opening 135C, The first wiring 132H is electrically connected to the gate electrode 622 through the first contact hole opening 135E, the first wiring 132H is electrically connected to the reference voltage power supply line SVR through the first contact hole opening 135B, the first wiring 132J is electrically connected to the first electrode 664 through the first contact hole opening 135M and is also electrically connected to the precharge voltage power supply line SVP through the first contact hole opening 135N, and the image data signal line 321 is electrically connected to the reference voltage power supply line SVR through the first contact hole opening 135B.

[0157] 16, the second electrode 694, the gate electrode 622, and the semiconductor layer 122A (channel region 123) overlap with each other. That is, the second transistor T2 (its channel region and gate electrode 622) overlaps with the second electrode 694 of the capacitance element CS.

[0158] An insulating layer 131 (FIG. 13) is formed on the conductive layer 132 and on the insulating layer 128 where the conductive layer 132 is not formed (step 17 (S17) in FIG. 14).

[0159] As shown in FIG. 13 or 17, second contact hole openings 138B, 138C, 138D, 138E, 138F, 138G, and 138H are opened (step 18 (S18)). Each opening opens the insulating layer 131 and exposes the corresponding wiring, semiconductor layer, or electrode. For example, second contact hole opening 138B exposes the first wiring 132D, and second contact hole opening 138G exposes the first wiring 132G. The other openings also expose the corresponding wiring, semiconductor layer, or electrode.

[0160] An insulating layer 136 (organic insulating layer) (FIG. 13) is formed on the insulating layer 131 (step 19 (S19) in FIG. 14).

[0161] As shown in FIG. 13 or 17, an opening is made in the insulating layer 136 (organic insulating layer) (step 20 (S20)). In the opening of S20, an organic insulating film opening 138A for the capacitor element CS is opened. In addition, in the opening of S20, second contact hole openings 138B, 138C, 138D, 138E, 138F, 138G, and 138H are opened, similar to the opening of S18. That is, the second contact hole openings 138B, 138C, 138D, 138E, 138F, 138G, and 138H are opened twice. Each opening opens the insulating layer 136, exposing the corresponding insulating layer, wiring, or electrode. For example, organic insulating film opening 138A for capacitor element CS removes only insulating layer 136 on second electrode 694, exposing insulating layer 131. On the other hand, second contact hole opening 138G removes only insulating layer 136 on first wiring 132G, exposing first wiring 132G. Other openings also expose the corresponding insulating layer, wiring, or electrode.

[0162] A conductive layer 139 (FIG. 13) is formed on the insulating layer 136, on the insulating layer 131 exposed in the organic insulating film opening 138A for the capacitor element CS (step 21 (S21)). As shown in FIG. 12 or 13, the conductive layer 139 includes a second wiring 140A (first electrode 692), a second wiring 140B, a second wiring 140C, and a second wiring 140D.

[0163] 12 or 17, in a plan view, the first electrode 692 is electrically connected to the first wiring 132D and the second electrode 656 via the second contact hole opening 138B and the first contact hole opening 135. The second wiring 140B is electrically connected to the first wiring 132H and the reference voltage power supply line SVR via the second contact hole opening 138D and the first contact hole opening 135B. The second wiring 140C is electrically connected to the first wiring 132E and the initialization voltage power supply line SVI via the second contact hole opening 138C and the first contact hole opening 135A. The second wiring 140D is electrically connected to the first wiring 132J and the precharge voltage power supply line SVP via the second contact hole opening 138H and the first contact hole opening 135N, and is also electrically connected to the first electrode 664 via the second contact hole opening 138H, the first contact hole opening 135N, and the first wiring 132J.

[0164] 12 or 17, the second wiring 140B is connected to and overlaps with the gate wiring 127C (reference voltage power line SVR), and extends parallel to the gate wiring 127C in the second direction D2. Since the reference voltage power line SVR is formed using two layers of metal wiring, its wiring resistance is lower than that of a voltage line formed using a single layer of metal wiring. As a result, the reference voltage power line SVR has a high current supply capability and can supply a stable voltage to each transistor. The second wiring 140C is connected to and overlaps with the gate wiring 127D (initialization voltage power line SVI), and extends parallel to the gate wiring 127C in the second direction D2. Since the initializing voltage power line SVI is formed using two layers of metal wiring, similar to the reference voltage power line SVR, it provides the same effects as the reference voltage power line SVR. The second wiring 140D is connected to and overlaps with the gate wiring 127F (precharge voltage power line SVP), and extends parallel to the gate wiring 127C in the second direction D2. Therefore, the precharge voltage power supply line SVP is formed using two layers of metal wiring, similar to the reference voltage power supply line SVR, and therefore has the same effects as the reference voltage power supply line SVR.

[0165] 13, second wiring 140A (first electrode 692) included in the same conductive layer 139 contacts the insulating layer 131 and conductive layer 132 (first wiring 132D), and second wiring 140B included in the same conductive layer 139 contacts the insulating layer 136. In other words, different wirings included in the same conductive layer 139 contact different layers below the same conductive layer 139.

[0166] 12, the first electrode 692, the second electrode 694, the gate electrode 622, and the semiconductor layer 122A (channel region 123) overlap with each other. That is, the second transistor T2 overlaps with the capacitor CS.

[0167] Furthermore, the first wiring 132C (second electrode 694) is formed on an insulating layer 128 formed on a gate wiring 127A (gate electrode 622) having an area larger than the surface area of ​​the second electrode 694. Because the insulating layer 128 reduces unevenness in the underlying layer, the second electrode 694 is formed on the large-area gate electrode 622 and on the flat insulating layer 128. Furthermore, as shown in FIG. 16 , for example, in a plan view, the area of ​​the second electrode 694 is larger than the area of ​​the electrode of the same conductive layer 132. That is, the surface of the second electrode 694 is flat and the area of ​​the second electrode 694 is large. Furthermore, the film thickness of the insulating layer 131 formed on the second electrode 694 is thinner than the film thickness of the insulating layer 136. Therefore, the manufacturing method of the self-luminous display device 10 (pixel 180) includes forming the first electrode 692 on the large-area gate electrode 622 and on the second electrode 694 and thin insulating layer 131 with reduced unevenness.

[0168] Furthermore, the scan signal line 330 included in the conductive layer 126 is configured to intersect with a minimum number of signal lines. As shown in FIG. 12 or 15, the scan signal line 330 intersects with the semiconductor layer 122B, the drive power supply line PVDD, and the image data signal line 321. The scan signal line 330 does not intersect with other scan signal lines, the reference voltage power supply line SVR, the precharge voltage power supply line SVP, or the initialization voltage power supply line SVI. As a result, the self-emissive display device 10 can reduce the capacitance added to the scan signal line 330 by each wiring and signal line. Therefore, the self-emissive display device 10 can suppress a decrease in the speed at which the first scan signal SC1(n) supplied to the scan signal line 330 propagates through the scan signal line 330.

[0169] An insulating layer 141 (organic insulating layer) (FIG. 13) is formed on the conductive layer 139 and on the insulating layer 136 where the conductive layer 139 is not formed (step 22 (S22) in FIG. 14).

[0170] As shown in FIG. 12 or 13, an opening is made in the insulating layer 141 (organic insulating layer) (step 23 (S23)). In the opening of S23, a contact hole opening 147 for the anode electrode is made. The contact hole opening 147 for the anode electrode removes the insulating layer 141 above the second wiring 140A, exposing the second wiring 140A. The contact hole opening 147 for the anode electrode is sometimes called an organic insulating layer opening. Note that, as shown in FIG. 12, the contact hole opening 147 overlaps the second wiring 140A and the first wiring 132A in a plan view.

[0171] An anode electrode 143 is provided on the exposed second wiring 140A, on the anode electrode contact hole opening 147, and on the insulating layer 141. A functional layer 148 is provided on the anode electrode 143. A common electrode 149 is provided on the functional layer 148 (step 24 (S24)). Note that, for example, the anode electrode 143 and the functional layer 148 are provided for each pixel, and the common electrode 149 is provided so as to overlap the display region 22.

[0172] After S24, the sealing film 165 and the cover film 158 are provided on the common electrode 149 in this order.

[0173] As shown in FIG. 13, the manufacture of the self-luminous display device 10 (pixel 180) is completed in this manner.

[0174] <1-8. Method for manufacturing the self-luminous display device 10> 5 and 18 to 24, a method for manufacturing the self-luminous display device 10 (pixel 180) that differs from the method described in "1-7. Method for manufacturing the self-luminous display device 10" will be described. Specifically, the manufacturing method described in "1-8. Method for manufacturing the self-luminous display device 10" differs from the manufacturing method described in "1-7. Method for manufacturing the self-luminous display device 10" in that it includes a semiconductor layer formed using crystalline silicon and an oxide semiconductor layer formed using metal oxide. In the description of "1-8. Method for manufacturing the self-luminous display device 10", configurations that differ from those in "1-7. Method for manufacturing the self-luminous display device 10" will be described, and configurations that are similar to those in "1-7. Method for manufacturing the self-luminous display device 10" will be described as necessary.

[0175] 18 and 21 to 24 are layout diagrams of the pixel 180. FIG. 19 is a cross-sectional view showing a cross section cut along B1-B2 in the layout of the pixel 180 shown in FIG. 18. FIG. 20 is a sequence diagram showing a method for manufacturing the self-luminous display device 10. The method for manufacturing the self-luminous display device 10 (pixel 180) shown in FIGS. 18 to 24 is one example, and the method for manufacturing the self-luminous display device 10 (pixel 180) is not limited to the examples shown in FIGS. 18 to 24. Configurations that are the same as or similar to those in FIGS. 21, 23, and 1 to 17 will be described as necessary.

[0176] The cross section of pixel 180 shown in Figure 19 is an example of a cross section of pixel 180, and is a cross section along second wiring 140B, scan signal line 333, first wiring 132L, first contact hole opening 135G, semiconductor layer 122B, oxide semiconductor layer 192B, first wiring 132M, scan signal line 330, second wiring 140D, second contact hole opening 138F, first wiring 132G, first contact hole opening 135F, gate wiring 127A, third wiring 196, organic insulating film opening 194A for capacitance element CS, second wiring 140A, channel region 123 of semiconductor layer 122, contact hole opening 147 for the anode electrode, third contact hole opening 194B, and second wiring 140G. The organic insulating film opening 194A for the capacitor element CS includes a portion where the third contact hole opening 194B is opened at the same time, and may be called the third contact hole opening.

[0177] As shown in FIG. 19, when the manufacture of the self-luminous display device 10 (pixel 180) starts, the base layer 121 is formed on the first surface 101A of the substrate 101.

[0178] As shown in FIG. 19 or 21, a semiconductor layer 122 is formed on the base layer 121 (step 110 (S110) of FIG. 20). The semiconductor layer 122 is formed using a crystalline oxide. The semiconductor layer 122 includes semiconductor layers 122A, 122B, and 122D. The semiconductor layer 122A serves as the semiconductor layer of both the second transistor T2 and the fifth transistor T5. The semiconductor layer 122B is the semiconductor layer of the third transistor T3. The semiconductor layer 122D is the semiconductor layer of the sixth transistor T6. In other words, the semiconductor layer 122A includes the channel region of the second transistor T2 and the channel region of the fifth transistor T5, the semiconductor layer 122B includes the channel region of the third transistor T3, and the semiconductor layer 122D includes the channel region of the sixth transistor T6.

[0179] Impurities are implanted into the semiconductor layer 122 (step 111 (S111) of FIG. 20). S11 forms impurity region 124A. For example, referring to FIG. 21, first electrode 624, second electrode 626, first electrode 654 and second electrode 656, and first electrode 664 and second electrode 666 include impurity regions implanted with impurities such as phosphorus (P). Also, for example, referring to FIG. 21, first electrode 634 and second electrode 636 include impurity regions implanted with impurities such as boron (B).

[0180] A gate insulating layer 125 (FIG. 19) is formed on the semiconductor layer 122 and on the base layer 121 where the semiconductor layer 122 is not formed (step 112 (S112) in FIG. 20). The gate insulating layer 125 is a gate insulating layer of a transistor that uses the semiconductor layer 122 as a channel region, and may be called a first gate insulating layer.

[0181] A conductive layer 126 (FIG. 19) is formed on the gate insulating layer 125 (step 113 (S113) of FIG. 20). As shown in FIG. 19 or 21, the conductive layer 126 includes a gate wiring 127C (reference voltage power supply line SVR), a gate wiring 127G (scan signal line 330), a gate wiring 127H (scan signal line 333), a gate wiring 127A (gate electrode 622), a gate wiring 127B (scan signal line 331), a gate wiring 127E (scan signal line 332), a gate wiring 127D (initialization voltage power supply line SVI), and a gate wiring 127F (precharge voltage power supply line SVP). The gate wiring 127B (scan signal line 331) includes a gate electrode 652 (see FIG. 5), the gate wiring 127H (scan signal line 333) includes a gate electrode 612 (see FIG. 5), the gate wiring 127G (scan signal line 330) includes a gate electrode 632 (see FIG. 5) and a gate electrode 642, and the gate wiring 127E (scan signal line 332) includes a gate electrode 662 (see FIG. 5). The wiring included in the conductive layer 126 may be called a first gate wiring.

[0182] The region where the gate electrode 622 of the second transistor T2 and the semiconductor layer 122A overlap is the channel region 123, and the channel region 123 corresponds to the channel length of the second transistor T2. The region where the third transistor T3 and the semiconductor layer 122B overlap is the channel region and the channel length of the third transistor T3. The region where the fifth transistor T5 and the semiconductor layer 122A overlap is the channel region and the channel length of the fifth transistor T5. The region where the sixth transistor T6 and the semiconductor layer 122D overlap is the channel region and the channel length of the sixth transistor T6.

[0183] An insulating layer 128 (FIG. 19) is formed on the conductive layer 126 and on the gate insulating layer 125 where the conductive layer 126 is not formed (step 114 (S114) in FIG. 20).

[0184] An oxide semiconductor layer 191 (FIG. 19) is formed on the insulating layer 128 (step 115 (S115) of FIG. 20). As shown in FIG. 19 or FIG. 22, the oxide semiconductor layer 191 includes oxide semiconductor layers 192A and 192B. The oxide semiconductor layer 192A is a semiconductor layer of the first transistor T1. The oxide semiconductor layer 192B is a semiconductor layer of the fourth transistor T4. In other words, the oxide semiconductor layer 192A includes a channel region of the first transistor T1, and the oxide semiconductor layer 192B includes a channel region of the fourth transistor T4. The oxide semiconductor layer 192B overlaps the semiconductor layer 122B. The length of the oxide semiconductor layer 192B parallel to the first direction D1 is shorter than the length of the semiconductor layer 122B. The semiconductor layer 122D may be an oxide semiconductor layer, and the region where the sixth transistor T6 and the oxide semiconductor layer overlap may be the channel region of the sixth transistor T6 and may correspond to the channel length.

[0185] A gate insulating layer 190 (FIG. 19) is formed on the oxide semiconductor layer 192 and on the insulating layer 128 where the oxide semiconductor layer 192 is not formed (step 116 (S116) in FIG. 20). The gate insulating layer 190 is a gate insulating layer of a transistor in which the oxide semiconductor layer 192 serves as a channel region, and may be called a second gate insulating layer.

[0186] As shown in FIG. 19, FIG. 21, or FIG. 22, first contact hole openings 135, 135A, 135B, 135C, 135D, 135F, 135G, 135L, 135M, 135N, 135p, and 135q are opened (step 117 (S117)). Each opening opens gate insulating layer 190, insulating layer 128, and gate insulating layer 125, exposing the corresponding wiring, semiconductor layer, or electrode. For example, as shown in FIG. 19, first contact hole opening 135G exposes semiconductor layer 122B, and first contact hole opening 135F exposes gate wiring 127A, the side surface of gate insulating layer 125, and semiconductor layer 122B. The other openings also expose the corresponding wiring, semiconductor layer, or electrode.

[0187] A conductive layer 132 (FIG. 19) is formed on the insulating layer 131 (step 118 (S118)). As shown in FIG. 19 or FIG. 23, the conductive layer 132 includes a first wiring 132A (driving power supply line PVDD), a first wiring 132C, a first wiring 132D, a first wiring 132E, a first wiring 132G, a first wiring 132H, a first wiring 132J, a first wiring 132K, a first wiring 132L, a first wiring 132M, and an image data signal line 321. The wiring included in the conductive layer 132 may be called a second gate wiring.

[0188] 23, in plan view, first wiring 132A is electrically connected to second electrode 626 through first contact hole opening 135D, first wiring 132C is electrically connected to second electrode 666 through first contact hole opening 135L, first wiring 132D is electrically connected to first electrode 624 through first contact hole opening 135, first wiring 132E is electrically connected to first electrode 654 through first contact hole opening 135C and is also electrically connected to gate wiring 127D (initialization voltage power supply line SVI) through first contact hole opening 135A, and first wiring 132H is electrically connected to first electrode 654 through first contact hole opening 135C and is also electrically connected to gate wiring 127D (initialization voltage power supply line SVI) through first contact hole opening 135A. The first wiring 132K is electrically connected to the gate wiring 127C (reference voltage power supply line SVR) through the first contact hole opening 135B, the first wiring 132K is electrically connected to the gate wiring 127G (scan signal line 333) through the first contact hole opening 135p, the first wiring 132M is electrically connected to the gate wiring 127G (scan signal line 330) through the first contact hole opening 135q, and the first wiring 132J is electrically connected to the gate wiring 127F (precharge voltage power supply line SVP) through the first contact hole opening 135N and is electrically connected to the first electrode 664 through the first contact hole opening 135M.

[0189] 19 or 23, the first wiring 132L is electrically connected to the first electrode 634 through the first contact hole opening 135G. The first wiring 132G is electrically connected to the gate wiring 127A (gate electrode 622) and also to the second electrode 636 through the first contact hole opening 135F. By providing the first contact hole opening 135F at the end of the gate wiring 127A, the first wiring 132G can be connected to both the gate wiring 127A and the second electrode 636.

[0190] 19 or 23, the first wiring 132L is electrically connected to the first electrode 634 through the first contact hole opening 135G. The first wiring 132G is electrically connected to the gate wiring 127A (gate electrode 622) and also to the second electrode 636 through the first contact hole opening 135F. By providing the first contact hole opening 135F at the end of the gate wiring 127A, the first wiring 132G can be connected to both the gate wiring 127A and the second electrode 636.

[0191] The first wiring 132K includes a gate electrode 612 (see FIG. 5), the first wiring 132M includes a gate electrode 642 (see FIG. 5), and the gate wiring 127E (scan signal line 332) includes a gate electrode 612.

[0192] The first transistor T1 has a gate electrode 612 included in the gate wiring 127H and the first wiring 132K. The region where the gate electrode 612 of the first transistor T1 and the oxide semiconductor layer 192A overlap is a channel region and corresponds to the channel length. Specifically, the gate wiring 127H and the first wiring 132K are provided above and below the oxide semiconductor layer 192A included in the first transistor T1, and the oxide semiconductor layer 192A is sandwiched between the gate wiring 127H and the first wiring 132K. Therefore, because the first transistor T1 has channel regions above and below the oxide semiconductor layer 192A, the first transistor T1 can pass a larger current than a transistor having a channel region on either the upper or lower side. As a result, the switching speed of the first transistor T1 is faster than that of a transistor having a channel region on either the upper or lower side. That is, the speed at which the data voltage is written into the first transistor T1 and the speed at which the first transistor T1 switches from a conductive state to a non-conductive state are faster than those of a transistor having a channel region on either the upper or lower side. Also, as explained in "1-4. Configuration of the pixel 180," the leakage current of the first transistor T1 is extremely small, so that the charge corresponding to the voltage contained in the data signal VDATA held in the first node N1 and the second electrode 694 of the capacitive element CS is held for a long time.

[0193] The fourth transistor T4 has a gate electrode 642 included in the gate wiring 127G and the first wiring 132M. A region where the gate electrode 642 of the fourth transistor T4 overlaps with the oxide semiconductor layer 192B is a channel region and corresponds to the channel length. The fourth transistor T4 has a configuration similar to that of the first transistor T1 and can achieve the same effects as those of the first transistor T1.

[0194] An insulating layer 136 (organic insulating layer) (FIG. 19) is formed on the conductive layer 132 and on the insulating layer 131 where the conductive layer 132 is not formed (step 119 (S119) in FIG. 20).

[0195] As shown in FIG. 19 or FIG. 23, second contact hole openings 138B, 138C, 138D, 138E, 138F, 138G, 138H, 138J, 138K, 138L, and 138M are opened (step 120 (S120)). Each opening opens the insulating layer 136 or the insulating layer 131, exposing the corresponding wiring, oxide semiconductor layer, or electrode. For example, as shown in FIG. 19, second contact hole opening 138E exposes the oxide semiconductor layer 192B, and second contact hole opening 138F exposes the first wiring 132G, the side surface of the insulating layer 131, and the oxide semiconductor layer 192B. The other openings also expose the corresponding wiring, oxide semiconductor layer, or electrode. The second contact hole opening may open the insulating layer 136 to expose the first wiring included in the conductive layer 132.

[0196] A conductive layer 139 (FIG. 19) is formed on the insulating layer 136, on the insulating layer 136 exposed by the second contact hole opening, on the insulating layer 131, and on the oxide semiconductor layer 191 (step 121 (S121)). As shown in FIG. 19 or 24, the conductive layer 139 includes a second wiring 140A (first electrode 692), a second wiring 140B, a second wiring 140C, a second wiring 140D, a second wiring 140E, a second wiring 140F, and a second wiring 140G.

[0197] 19 or 24, the first electrode 692 is electrically connected to the first wiring 132C and the second electrode 666 via the second contact hole opening 138J and the first contact hole opening 135L, and is electrically connected to the second electrode 616 via the second contact hole openings 138M and 138L. The first electrode 692 is also electrically connected to the first wiring 132L, the second wiring 140B, the second electrode 636 (oxide semiconductor layer 192B), and the second electrode 646 (semiconductor layer 122B) via the second contact hole opening 138M, the first contact hole opening 135G, and the second contact hole opening 138E.

[0198] 19 or 24, the second wiring 140C is electrically connected to the first wiring 132E, the initialization voltage power supply line SVI, and the first electrode 654 via the second contact hole opening 138C and the first contact hole openings 135A and 135C. The second wiring 140D is electrically connected to the first wiring 132J and the precharge voltage power supply line SVP via the second contact hole opening 138H and the first contact hole opening 135N, and is also electrically connected to the first wiring 132J, the first electrode 664, and the gate wiring 127F (precharge voltage power supply line SVP) via the second contact hole opening 138H and the first contact hole openings 135N and 135M.

[0199] 19 or 24, the second wiring 140E is electrically connected to the first wiring 132G and the second electrode 646 (oxide semiconductor layer 192B) via the second contact hole opening 138F. By providing the second contact hole opening 138F at the end of the first wiring 132G, the second wiring 140E can be connected to both the first wiring 132G and the second electrode 646. Furthermore, since the first wiring 132G is connected to both the gate wiring 127A and the second electrode 636 (semiconductor layer 122B), the second wiring 140E can be connected to the first wiring 132G, the second electrode 646 (oxide semiconductor layer 192B), the gate wiring 127A, and the second electrode 636 (semiconductor layer 122B). That is, the second wiring 140E can electrically connect the oxide semiconductor layer 192B and the semiconductor layer 122B, which are provided in different layers, via two contact hole openings provided in different layers.

[0200] 19 or 24, the second wiring 140F is electrically connected to the second electrode 616 (oxide semiconductor layer 192A) through the second contact hole openings 138G and 138K. The second wiring 140F is also electrically connected to the image data signal line 321 through the second contact hole opening 138G.

[0201] Also, as shown in Figure 19 or Figure 24, the second wiring 140G is electrically connected to the first electrode 624 (semiconductor layer 122A) and the second electrode 656 (semiconductor layer 122A) via the second contact hole opening 138B and the first contact hole opening 135.

[0202] 18 or 24, the second wiring 140B, the second wiring 140C, and the second wiring 140D have the same configuration as that described in "1-7. Manufacturing method of the self-luminous display device 10." Therefore, the second wiring 140B, the second wiring 140C, and the second wiring 140D formed by "1-8. Manufacturing method of the self-luminous display device 10" have the same effects as the configuration described in "1-7. Manufacturing method of the self-luminous display device 10."

[0203] An insulating layer 193 (FIG. 19) is formed on the conductive layer 139 and on the insulating layer 136 where the conductive layer 139 is not provided (step 122 (S122) in FIG. 20).

[0204] 18, 19 or 24, an opening is made in the insulating layer 193 (step 123 (S123)). In the opening of S123, a third contact hole opening portion 194B is opened.

[0205] An insulating layer 141 (organic insulating layer) (FIG. 19) is formed on the insulating layer 193, on the side of the insulating layer 193 opened by the third contact hole opening 194B, and on the conductive layer 139 (e.g., the second wiring 140G) exposed by the third contact hole opening 194B (step 124 (S124) in FIG. 20).

[0206] As shown in FIG. 18, FIG. 19, or FIG. 24, an opening is made in the insulating layer 141 (organic insulating layer) (step 125 (S125)). In the opening in S125, an organic insulating film opening 194A for the capacitor element CS is opened. Similarly to the opening in S123, a third contact hole opening 194B is opened. That is, the third contact hole opening 194B is opened twice. Each opening opens the insulating layer 141 or the insulating layer 193, exposing the corresponding insulating layer, wiring, or electrode. For example, the organic insulating film opening 194A for the capacitor element CS removes only the insulating layer 141 on the second wiring 140A (second electrode 694), exposing the insulating layer 193. On the other hand, third contact hole opening 194B removes insulating layer 141 and insulating layer 193 on second wiring 140G to expose second wiring 140G. The other openings also expose the corresponding insulating layers, wiring, or electrodes.

[0207] A conductive layer 195 (FIG. 19) is formed on the insulating layer 141, on the side surfaces of the insulating layer 141 and the insulating layer 193 exposed by the third contact hole opening, and on the conductive layer 139 exposed by the third contact hole opening (step 126 (S126)). As shown in FIG. 18, 19 or 24, the conductive layer 195 includes a third wiring 196.

[0208] 18, 19, or 24, the third wiring 196 is electrically connected to the second wiring 140G through the third contact hole opening 194B. Also, as shown in Fig. 18, the first electrode 692, the gate electrode 622, and the semiconductor layer 122A (channel region 123) overlap with each other. That is, the second transistor T2 overlaps with the capacitance element CS.

[0209] An insulating layer 197 (organic insulating layer) (FIG. 19) is formed on the conductive layer 195 and on the insulating layer 141 where the conductive layer 195 is not formed (step 127 (S127) in FIG. 20).

[0210] As shown in FIG. 19, an opening is made in insulating layer 197 (organic insulating layer) (step 128 (S128)). In the opening in S128, a contact hole opening 147 for the anode electrode is made. The contact hole opening 147 for the anode electrode removes insulating layer 197 on conductive layer 195 (e.g., third wiring 196), exposing conductive layer 195. The contact hole opening 147 for the anode electrode is sometimes called an organic insulating layer opening.

[0211] An anode electrode 143 is provided on the exposed conductive layer 195, on the anode electrode contact hole opening 147, and on the insulating layer 197. A functional layer 148 is provided on the anode electrode 143. A common electrode 149 is provided on the functional layer 148 (step 129 (S129)). Note that, for example, the anode electrode 143 and the functional layer 148 are provided for each pixel, and the common electrode 149 is provided so as to overlap the display region 22.

[0212] After S129, the sealing film 165 and the cover film 158 are provided on the common electrode 149 in this order.

[0213] As shown in FIG. 19, the manufacture of the self-luminous display device 10 (pixel 180) is completed in this manner.

[0214] As described above, the self-emissive display device 10 includes a configuration that allows transistors in a pixel to be overlapped in a plan view. Therefore, the self-emissive display device 10 can reduce the length of the pixel in the first direction D1 or the second direction D2 corresponding to the overlapped transistors. As a result, for example, the self-emissive display device 10 can increase the number of pixels according to the total reduced length. Therefore, the self-emissive display device 10 can provide a high-resolution display device and a large-screen display device.

[0215] 2. Second Embodiment An overview of the self-luminous display device according to the second embodiment will be described with reference to Figures 1, 6, and 25 to 33. Figure 25 is a schematic diagram showing input signals to a pixel 180A (pixel circuit 181A) according to the second embodiment, Figure 26 is a circuit diagram showing the configuration of the pixel circuit 181A, and Figures 27 to 30 are timing charts of the self-luminous display device according to the second embodiment. Figure 31 is a schematic diagram showing the configuration of a control circuit 120A according to the second embodiment, Figure 32 is a circuit diagram showing the configuration of a scan driver 160A(n) according to the second embodiment, and Figure 33 is a timing chart of the control circuit 120A.

[0216] The self-luminous display device according to the second embodiment includes a pixel 180A, a pixel circuit 181A, and a control circuit 120A. The configurations of the pixel 180A and the pixel circuit 181A and the configuration of the control circuit 120A are different from the configurations of the pixel 180 and the pixel circuit 181 and the configuration of the control circuit 120 of the self-luminous display device 10 according to the first embodiment. Specifically, the self-luminous display device according to the second embodiment has a configuration and function in which the reference voltage power supply VREF and the initialization voltage VINI supplied to the pixel circuit 181 are replaced with a scan voltage power supply SIR(n). The scan voltage power supply SIR(n) is a power supply that changes initialization voltages VINI1 and VINI2 corresponding to the reference voltage power supply VREF and the initialization voltage VINI over time. Furthermore, the self-luminous display device according to the second embodiment has a configuration and function in which the control circuit 120 is replaced with a control circuit 120A. The other configurations and functions are the same as those of the self-luminous display device 10 according to the first embodiment. In describing the configuration and functions of the second embodiment, configurations and functions that are the same as those of the self-luminous display device 10 according to the first embodiment will be described as necessary. Also, configurations that are the same as or similar to those in Figures 1 to 24 will be described as necessary.

[0217] <2-1. Configuration of pixel 180A> The pixel 180A and pixel circuit 181A will be outlined with reference to FIGS.

[0218] The pixel circuit 181A is connected to a scan voltage power line SVIR. The scan voltage power line SVIR is a signal line that doubles as the reference voltage power line SVR and the initialization voltage power line SVI supplied to the pixel circuit 181. In other words, the scan voltage power line SVIR is a signal line that combines the reference voltage power line SVR and the initialization voltage power line SVI supplied to the pixel circuit 181. That is, the pixel circuit 181A has a configuration and function in which the reference voltage power line SVR and the initialization voltage power line SVI connected to the pixel circuit 181 are replaced with a scan voltage power line SVIR that combines the reference voltage power line SVR and the initialization voltage power line SVI. The scan voltage power line SVIR may be referred to as a fifth control signal line. The scan voltage power supply SIR(n) may be referred to as a fifth control signal. Note that although the scan voltage power line SVIR is a wiring that functions as a power supply, it is treated as a signal line because the voltage (potential) is changed during use.

[0219] A scan voltage power supply SIR(n) is supplied to the scan voltage power supply line SVIR. In the pixel circuit 181A, a first electrode 644 of the fourth transistor T4 and a first electrode 654 of the fifth transistor T5 are electrically connected to the scan voltage power supply line SVIR.

[0220] For example, the scan voltage power supply line SVIR is electrically connected to a connection wiring 342 (FIGS. 1 and 25) that is different from the drive power supply line PVDD and the reference voltage line PVSS. Also, for example, the scan voltage power supply line SVIR may be one of the connection wirings 342.

[0221] For example, the scan voltage power supply SIR(n) may be supplied from an external device to the IC chip 110 (FIG. 1), similar to the initialization voltage VINI, or may be supplied from the IC chip 110 to the plurality of pixels 180A (pixel circuits 181A) via the connection wiring 342 and the scan voltage power supply line SVIR. Although not shown, the scan voltage power supply SIR(n) may be connected to the scan voltage power supply line SVIR from the external device via the FPC 200, the terminal unit 150, and the connection wiring 341, similar to the initialization voltage VINI, without passing through the IC chip 110 and the connection wiring 342, and may be supplied to the plurality of pixels 180A (pixel circuits 181A).

[0222] The fourth transistor T4 has a function of connecting the second node N2 and the scan voltage power supply line SVIR and supplying the initialization voltage VINI1 or VINI2 to the second node N2 to initialize the second node N2. For example, the initialization voltages VINI1 and VINI2 are constant voltages.

[0223] The fifth transistor T5 has a function of connecting the third node N3 and the scan voltage power supply line SVIR to each other, supplying the initialization voltage VINI1 to the third node N3, and initializing the third node N3.

[0224] The configuration and functions of the pixel circuit 181A other than those described in "2-1. Configuration of the pixel 180A" are the same as those of the pixel circuit 181.

[0225] <2-2. Driving Method of Pixel Circuit 181A> A method for driving the self-luminous display device 10 according to the second embodiment will be described with reference to Figures 27 to 30. Configurations that are the same as or similar to those in Figures 1 to 26 will be described as necessary. As in the first embodiment, the horizontal axis of the timing chart represents time.

[0226] The method for driving the self-luminous display device according to the second embodiment has a configuration and functions in which the operations related to the reference voltage power supply line SVR and the initialization voltage power supply line SVI (reference voltage VREF and initialization voltage VINI) in the method for driving the self-luminous display device 10 according to the first embodiment are replaced with operations related to the scan voltage power supply SIR(n). The configuration and functions other than the operations related to the scan voltage power supply SIR(n) are the same as those of the method for driving the self-luminous display device 10 according to the first embodiment.

[0227] The method for driving the self-luminous display device according to the second embodiment includes the same period as the method for driving the self-luminous display device 10 according to the first embodiment shown in FIG.

[0228] In one horizontal period (horizontal period HRP) in the driving method of the self-luminous display device 10 according to the second embodiment, the pixel 180A (pixel circuit 181A) receives a first scan signal SC1(n), a second scan signal SC2(n), a third scan signal SC3(n), a fourth scan signal SC4(n), an image data signal SL(m) including a data signal VDATA, and a scan voltage power supply SIR(n). For example, the pixel 180A (pixel circuit 181A) is selected in accordance with the timing of the first scan signal SC1(n), the second scan signal SC2(n), the third scan signal SC3(n), and the fourth scan signal SC4(n). The image data signal SL(m) and the scan voltage power supply SIR(n) are input to the selected pixel 180A (pixel circuit 181A) in accordance with the timing of each signal. A similar operation is performed for all pixels 180A (pixel circuits 181A), and based on the image data signals SL(m) input to all pixels 180A (pixel circuits 181A), an image of the frame corresponding to one frame is displayed in the display area 22 of the self-luminous display device 10.

[0229] For example, the voltages (potentials) supplied to the signals and nodes in each frame in the timing charts shown in FIGS.

[0230] [Table 3]

[0231] [Table 4]

[0232] <2-2-1. First Example of Method for Driving Pixel Circuit 181A> A first example of a method for driving the pixel circuit 181A will be described with reference to Fig. 27. The first example of the method for driving the pixel circuit 181A includes displaying images of different colors in successive frames, similar to the first example of the method for driving the self-luminous display device 10 according to the first embodiment.

[0233] The scan voltage power supply SIR(n) supplies an initialization voltage VINI2 during the light emission period PEM of the K-1st FRAME, an initialization voltage VINI1 during the period PIP of the Kth FRAME, and an initialization voltage VINI2 during the period PVH of the Kth FRAME and the light emission period PEM.

[0234] For example, as shown in Table 4, the initialization voltage VINI2 is 0 V, and the initialization voltage VINI1 is −1.5 V. The initialization voltage VINI2 is the same as the reference voltage VREF, and the initialization voltage VINI1 is the same as the initialization voltage VINI. The setting values ​​of the other voltages are the setting values ​​shown in Table 2 described in “1-5. Method of driving the self-luminous display device 10.”

[0235] The configurations of the image data signal SL(m), the first scan signal SC1(n), the second scan signal SC2(n), the third scan signal SC3(n), and the fourth scan signal SC4(n) during the light emission period PEM of the K-1st FRAME and the light emission period PEM of the Kth FRAME are the same as those described in "1-5-1. First Example of the Method for Driving the Self-luminous Display Device 10." The voltages (potentials) of the first node N1, the second node N2, and the third node N3 during the light emission period PEM of the K-1st FRAME and the light emission period PEM of the Kth FRAME, as well as the operation of each transistor, are the same as those described in "1-5-1. First Example of the Method for Driving the Self-luminous Display Device 10." The scan voltage power supply SIR(n) during the light emission period PEM of the K-1st FRAME and the light emission period PEM of the Kth FRAME is supplied with an initialization voltage VINI2. Configurations similar to those explained in "1-5-1. First example of the method for driving the self-luminous display device 10" will be explained as necessary.

[0236] In the light emitting period PEM of the K-1st FRAME, the light emitting element OLED emits light in the same manner as in the configuration described in "1-5-1. First example of the method for driving the self-luminous display device 10."

[0237] During the period between the light-emitting period PEM of the (K-1st) FRAME and the period PIP, which follows the light-emitting period PEM of the (K-1st) FRAME, the pixel 180A (pixel circuit 181A) receives the image data signal SL(m) of the data signal VDATA of the voltage VSIGL corresponding to the non-light-emitting black color. The scan voltage power supply SIR(n) changes from a state in which the initialization voltage VINI2 (0 V) is supplied to a state in which the initialization voltage VINI1 (voltage Vnc, -2 V) is supplied. The first scan signal SC1(n) changes from a state in which LO is supplied to a state in which HI is supplied. When the first scan signal SC1(n) changes to a state in which HI is supplied, the third scan signal SC3(n) changes from a state in which LO is supplied to a state in which HI is supplied. The second scan signal SC2(n) and the fourth scan signal SC4(n) are in a state in which LO is supplied. Therefore, the fourth transistor T4 and the sixth transistor T6 change from an off state to an on state, the third transistor T3 changes from an on state to an off state, and the first transistor T1 and the fifth transistor T5 maintain their off states. As a result, the voltage supplied to the second node N2 gradually drops from the voltage Vna toward the voltage Vnc, the voltage supplied to the first node N1 gradually drops from the voltage Vna toward the precharge voltage VPRC (voltage Vnd, 1.5 V), and the voltage supplied to the third node N3 maintains the voltage Vnb.

[0238] During the period PIP following the period between the light-emitting period PEM and the period PIP of the (K-1st) FRAME, the pixel 180A (pixel circuit 181A) maintains a state in which it receives the data signal VDATA based on the image data signal SL(m) of the n-1th row immediately preceding the nth row, the first scan signal SC1(n) and the third scan signal SC3(n) maintain a state in which they are supplied with HI, and the fourth scan signal SC4(n) maintains a state in which they are supplied with LO. The second scan signal SC2(n) changes from a state in which it is supplied with LO to a state in which it is supplied with HI. Therefore, the fifth transistor T5 changes from an OFF state to an ON state, the second transistor T2 turns OFF, the sixth transistor T6 and the fourth transistor T4 maintain an ON state, and the first transistor T1 and the third transistor T3 maintain an OFF state.

[0239] As a result, the voltage supplied to the first node N1 gradually drops from voltage Vna toward the precharge voltage VPRC (voltage Vnd, 1.5V) and becomes voltage Vnd. The voltage supplied to the second node N2 gradually drops from voltage Vna toward the initialization voltage VINI1 (voltage Vnc, -2V) and becomes voltage Vnc. The voltage supplied to the third node N3 gradually drops from voltage Vnb toward the initialization voltage VINI1 and becomes voltage Vnc. The potential difference Vgs becomes 0V (-2V - -2V), and the potential difference Vds becomes 10V (8V - -2V). Because the potential difference Vgs is smaller than the threshold voltage VTH, the second transistor T2 is in an off state, and the drain current Ion does not flow from the drive power supply line PVDD to the initialization voltage power supply line SVI or the reference voltage line PVSS, so the light-emitting element OLED does not emit light.

[0240] As described above, during the period PIP, the precharge voltage (intermediate potential) is supplied to the first node N1, and the second node N2 and the third node N3 are initialized by the initialization voltage VINI1 (-2V).

[0241] During the initial period of the horizontal period HRP of the KthFRAME following the period PIP, the configurations of the image data signal SL(m), the first scan signal SC1(n), the second scan signal SC2(n), the third scan signal SC3(n), and the fourth scan signal SC4(n), and the operation of each transistor are the same as those described in "1-5-1. First Example of the Driving Method of the Self-Emitting Display Device 10." The scan voltage power supply SIR(n) maintains the state in which the initialization voltage VINI1 is supplied. As a result, the voltage supplied to the first node N1 maintains voltage Vnd, the voltage supplied to the second node N2 maintains initialization voltage VINI1, and the voltage supplied to the third node N3 maintains voltage Vnc (initialization voltage VINI1). Similarly to the period PIP, the light-emitting element OLED does not emit light.

[0242] During the period PWR following the initial period of the horizontal period HRP, the configurations of the image data signal SL(m), the first scan signal SC1(n), the second scan signal SC2(n), the third scan signal SC3(n), and the fourth scan signal SC4(n), and the operation of each transistor are the same as those described in "1-5-1. First Example of the Driving Method of the Self-Emitting Display Device 10." The scan voltage power supply SIR(n) maintains the state in which the initialization voltage VINI1 is supplied. As a result, the voltage supplied to the first node N1 gradually drops from voltage Vnd toward voltage VSIGL (voltage Vnf, −0.5V), the voltage supplied to the second node N2 maintains voltage Vnc, and the voltage supplied to the third node N3 maintains voltage Vnc. Similarly to the period PIP, the light-emitting element OLED does not emit light.

[0243] During the period PVH that is parallel to (overlaps with) the period PWR, the configurations of the image data signal SL(m), the first scan signal SC1(n), the second scan signal SC2(n), the third scan signal SC3(n), and the fourth scan signal SC4(n) and the operation of each transistor are the same as those described in "1-5-1. First Example of the Driving Method of the Self-luminous Display Device 10." The scan voltage power supply SIR(n) changes from a state in which the initialization voltage VINI1 is supplied to a state in which the initialization voltage VINI2(0V) is supplied. As a result, the voltage supplied to the second node N2 gradually increases from the voltage Vnc toward the initialization voltage VINI2(0V).

[0244] Immediately after the start of the period PVH, the potential difference Vgs is 0 V, the potential difference Vds is 10 V, and the second transistor T2 is in the OFF state. The fifth transistor T5 is also in the OFF state. Meanwhile, the fourth transistor T4 is in the ON state, and the voltage supplied to the second node N2 increases from the voltage Vnc toward the initialization voltage VINI2 (0 V). As the voltage supplied to the second node N2 approaches 0 V, the potential difference Vgs exceeds the threshold voltage VTH. As a result, the second transistor T2 is turned ON, charging of the third node N3 begins, and the voltage supplied to the third node N3 gradually increases.

[0245] When the potential difference Vgs between the voltage supplied to the second node N2 and the voltage supplied to the third node N3 becomes the threshold voltage VTH, the voltage supplied to the second node N2 and the voltage supplied to the third node N3 maintain their respective voltages at that time. For example, as shown in Figure 27, the voltage supplied to the second node N2 is the initialization voltage VINI2 (0V), and the voltage supplied to the third node N3 is the voltage Vne (-1V). Since the second transistor T2 is in the off state and no current flows from the driving power line PVDD to the reference voltage line PVSS, the light-emitting element OLED does not emit light.

[0246] During the final period of the period PVH, the configurations of the image data signal SL(m), the first scan signal SC1(n), the second scan signal SC2(n), the third scan signal SC3(n), and the fourth scan signal SC4(n), and the operation of each transistor are the same as those described in "1-5-1. First Example of the Driving Method of the Self-luminous Display Device 10." The scan voltage power supply SIR(n) maintains a state in which the initialization voltage VINI2 is supplied. As a result, the first node N1 is electrically connected to the second node N2, the voltage supplied to the first node N1 gradually drops toward voltage Vnf and reaches voltage Vnf, the voltage supplied to the second node N2 gradually drops toward voltage Vnf and reaches voltage Vnf, and the voltage supplied to the third node N3 maintains voltage Vne. Note that the potential difference Vgs is 1 V, the potential difference Vds is 9 V, and the potential difference Vgs is the same as the threshold voltage VTH, so no current flows from the driving power supply line PVDD to the reference voltage line PVSS. Also, the light emitting element OLED does not emit light.

[0247] In this way, during the period PWR, the data signal VDATA is written to the pixel 180 (pixel circuit 181). During the period PVH, the threshold voltage VTH of the second transistor T2 is acquired by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is held at the third node N3 (the first electrode 692 of the capacitance element CS).

[0248] During the light emission period PEM of the KthFRAME following the horizontal period HRP of the KthFRAME, the display becomes black with three pixels: a pixel 180A that emits red light, a pixel 180A that emits blue light, and a pixel 180A that emits green light, similar to the configuration described in "1-5-1. First example of the driving method for the self-luminous display device 10."

[0249] The first example of the method for driving the pixel circuit 181A including the configuration described above has the same effects as the method for driving the self-luminous display device 10 according to the first embodiment.

[0250] Furthermore, the pixel circuit 181A is connected to a scan voltage power supply line SVIR, which also serves as the reference voltage power supply line SVR and the initialization voltage power supply line SVI supplied to the pixel circuit 181. Therefore, the pixel circuit 181A has a configuration that allows the number of signal lines to be reduced, and therefore a self-luminous display device including the pixel circuit 181A can reduce the pixel size. As a result, a self-luminous display device including the pixel circuit 181A can increase the number of pixels, and can also achieve higher definition and a larger screen.

[0251] <2-2-2. Second Example of Method for Driving Pixel Circuit 181A> A second example of a method for driving the pixel circuit 181A will be described with reference to Fig. 28. The driving method shown in the second example of the pixel circuit 181A includes displaying images of the same color (white) in consecutive frames, similar to the second example of the method for driving the self-luminous display device 10 according to the first embodiment. Configurations that are the same as or similar to those in Figs. 1 to 27 will be described as necessary.

[0252] The configurations of the image data signal SL(m), the first scan signal SC1(n), the second scan signal SC2(n), the third scan signal SC3(n), the fourth scan signal SC4(n), and the scan voltage power supply SIR(n) during the light emission period PEM of the (K-1st) FRAME to the light emission period PEM of the Kth FRAME are the same as those described in "2-2-1. First Example of the Method for Driving the Pixel Circuit 181A." Furthermore, the voltages (potentials) of the first node N1, the second node N2, and the third node N3, and the operation of each transistor during the initial period of the horizontal period HRP during the light emission period PEM of the (K-1st) FRAME to the Kth FRAME are the same as those described in "2-2-1. First Example of the Method for Driving the Pixel Circuit 181A." Furthermore, the voltages (potentials) of the first node N1, the second node N2, and the third node N3, and the operation of each transistor from the end of the period PVH to the light emission period PEM of the Kth FRAME are the same as the configurations and operations described in "1-5-2. Second Example of the Method for Driving the Self-Light-Emitting Display Device 10." The contents described in "2-2-1. First Example of the Method for Driving the Pixel Circuit 181A" and the configurations similar to those described in "1-5-2. Second Example of the Method for Driving the Self-Light-Emitting Display Device 10" will be explained as necessary. Note that, as for the image data signal SL(m), the data signal VDATA of VSIGH corresponding to white is supplied during the period between the light emission period PEM of the K-1st FRAME and the light emission period PEM of the Kth FRAME.

[0253] In the light emitting period PEM of the K-1st FRAME, the light emitting element OLED emits light in the same manner as in the configuration described in "2-2-1. First example of the method for driving the pixel circuit 181A."

[0254] During the period between the light emission period PEM of the K-1st FRAME and the period PIP following the light emission period PEM of the K-1st FRAME, similar to the configuration described in "2-2-1. First example of the driving method of the pixel circuit 181A", the voltage supplied to the second node N2 gradually drops from voltage Vna towards voltage Vnc, the voltage supplied to the first node N1 gradually drops from voltage Vna towards the precharge voltage VPRC (voltage Vnd, 1.5V), and the voltage supplied to the third node N3 maintains voltage Vnb.

[0255] In the period PIP following the period between the light-emitting period PEM and the period PIP of the K-1st FRAME, similar to the configuration described in "2-2-1. First example of the method of driving the pixel circuit 181A", the voltage supplied to the first node N1 becomes the voltage Vnd, the voltage supplied to the second node N2 and the voltage supplied to the third node N3 become the voltage Vnc, the potential difference Vgs becomes 0 V, and the potential difference Vds becomes 10 V. In addition, the light-emitting element OLED does not emit light.

[0256] As described above, during the period PIP, the precharge voltage (intermediate potential) is supplied to the first node N1, and the second node N2 and the third node N3 are initialized by the initialization voltage VINI1 (-2V).

[0257] During the initial period of the horizontal period HRP of KthFRAME following the period PIP, similar to the configuration described in "2-2-1. First example of the method of driving the pixel circuit 181A", the voltage supplied to the first node N1 remains at the voltage Vnd, the voltage supplied to the second node N2 remains at the initialization voltage VINI1, and the voltage supplied to the third node N3 remains at the voltage Vnc, and the light-emitting element OLED does not emit light.

[0258] During the period PWR following the initial period of the horizontal period HRP, each transistor operates in the same manner as in the configuration described in "2-2-1. First example of the method of driving the pixel circuit 181A", the voltage supplied to the first node N1 gradually rises from voltage Vnd toward voltage VSIGH (voltage Vng, 3.5 V), the voltage supplied to the second node N2 maintains voltage Vnc, the voltage supplied to the third node N3 maintains voltage Vnc, and the light-emitting element OLED does not emit light.

[0259] In the middle of the period PWR, during the period PVH that is parallel to (overlaps with) the period PWR, each transistor operates in the same manner as the configuration described in "2-2-1. First example of the driving method for the pixel circuit 181A," and the voltage supplied to the first node N1 gradually rises from voltage Vnd toward voltage VSIGH (voltage Vng, 3.5V) and becomes voltage Vng, and the voltage supplied to the second node N2 gradually rises from voltage Vnc toward the initialization voltage VINI2 (0V) and becomes the initialization voltage VINI2 (0V).

[0260] Immediately after the start of the period PVH, the potential difference Vgs is 0 V, the potential difference Vds is 10 V, and the second transistor T2 is in the OFF state. The fifth transistor T5 is also in the OFF state. Meanwhile, the fourth transistor T4 is in the ON state, and the voltage supplied to the second node N2 increases from the voltage Vnc toward the initialization voltage VINI2 (0 V). As the voltage supplied to the second node N2 approaches 0 V, the potential difference Vgs exceeds the threshold voltage VTH. As a result, the second transistor T2 is turned ON, charging of the third node N3 begins, and the voltage supplied to the third node N3 gradually increases.

[0261] When the potential difference Vgs between the voltage supplied to the second node N2 and the voltage supplied to the third node N3 becomes the threshold voltage VTH, the voltage supplied to the second node N2 and the voltage supplied to the third node N3 maintain their respective voltages at that time. For example, as shown in Figure 28, the voltage supplied to the second node N2 is the initialization voltage VINI2 (0V), and the voltage supplied to the third node N3 is the voltage Vne (-1V). Since the second transistor T2 is in the off state and no current flows from the driving power supply line PVDD to the reference voltage line PVSS, the light-emitting element OLED does not emit light.

[0262] At the end of the period PVH, each transistor operates in the same manner as in the configuration described in "1-5-2. Second Example of the Method for Driving the Self-luminous Display Device 10." As a result, at the end of the period PVH, the first node N1 and the second node N2 are electrically connected, and the voltage at the second node N2 gradually rises, as in the configuration described in "1-5-2. Second Example of the Method for Driving the Self-luminous Display Device 10." As a result, the second transistor T2 is electrically connected, and a drain current Ion flows from the drive power supply line PVDD to the reference voltage line PVSS. Therefore, the voltages at the first node N1 and the third node N3 rise in accordance with the rise in the voltage at the second node N2. Due to the rise in the voltage at the third node N3, the voltages at the first node N1 and the second node N2 further rise.

[0263] Furthermore, during the light emitting period PEM of the Kth FRAME following the horizontal period HRP of the Kth FRAME, each light emitting element OLED emits light, similar to the configuration described in "1-5-2. Second Example of the Method for Driving the Self-Emitting Display Device 10." For example, three pixels, including a pixel 180A that emits red, a pixel 180A that emits blue, and a pixel 180A that emits green, emit white light.

[0264] As described above, during the period PWR, the data signal VDATA is written to the pixel 180A (pixel circuit 181A). During the period PVH, the threshold voltage VTH of the second transistor T2 is acquired by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is held at the third node N3 (the first electrode 692 of the capacitance element CS). During the light-emitting period PEM of the KthFRAME, the three pixels emit white light.

[0265] The second example of the method for driving the pixel circuit 181A including the configuration described above has the same effects as "2-2-1. First example of the method for driving the pixel circuit 181A."

[0266] <2-2-3. Third Example of Method for Driving Pixel Circuit 181A> A third example of a method for driving the pixel circuit 181A will be described with reference to Fig. 29. The driving method shown in the third example of the method for driving the pixel circuit 181A includes displaying images of the same color (black) in consecutive frames, similar to the third example of the method for driving the self-luminous display device 10 according to the first embodiment. Configurations that are the same as or similar to those in Figs. 1 to 28 will be described as necessary.

[0267] The configurations of the image data signal SL(m), the first scan signal SC1(n), the second scan signal SC2(n), the third scan signal SC3(n), the fourth scan signal SC4(n), and the scan voltage power supply SIR(n) during the light emission period PEM of the K-1st FRAME to the light emission period PEM of the Kth FRAME are the same as those described in "2-2-1. First Example of Method for Driving Pixel Circuit 181A." Furthermore, the voltages (potentials) of the first node N1, the second node N2, and the third node N3, and the operation of each transistor during the light emission period of the K-1st FRAME are the same as those described in "1-5-3. Third Example of Method for Driving Self-Light-Emitting Display Device 10." Furthermore, the voltages (potentials) of the first node N1, the second node N2, and the third node N3, and the operation of each transistor from the beginning of the horizontal period HRP of the Kth FRAME to the light emission period PEM of the Kth FRAME are the same as the configurations and operations described in "2-2-1. First Example of Method for Driving Pixel Circuit 181A." The same configurations as those described in "2-2-1. First Example of Method for Driving Pixel Circuit 181A" and "1-5-3. Third Example of Method for Driving Self-Light-Emitting Display Device 10" will be explained as necessary. Note that, for the image data signal SL(m), a data signal VDATA of voltage VSIGL corresponding to black is supplied during the period between the light emission period PEM of the K-1st FRAME and the light emission period PEM of the Kth FRAME.

[0268] During the light emitting period PEM of the K-1st FRAME, the light emitting element OLED does not emit light and the pixel 180A (pixel circuit 181A) is black, similar to the configuration described in "1-5-3. Third example of the method for driving the self-luminous display device 10."

[0269] During the period between the light-emitting period PEM of the (K-1st) FRAME and the period PIP, similar to the configuration described in "1-5-3. Third Example of the Method for Driving the Self-Emitting Display Device 10," the voltage supplied to the first node N1 is maintained at voltage Vnf, and the voltage supplied to the second node N2 gradually drops from voltage Vnf toward the initialization voltage VINI1 (Vnc, -2V). Furthermore, the voltage supplied to the third node N3 gradually drops from voltage Vne toward the initialization voltage VINI1 (Vnc, -2V). Furthermore, the light-emitting element OLED does not emit light.

[0270] During the period PIP following the period between the light-emitting period PEM and the period PIP of the (K-1st) FRAME, the voltage supplied to the first node N1 gradually increases from voltage Vnf toward the pre-charge voltage VPRC (voltage Vnd, 1.5V) and becomes voltage Vnd. The voltage supplied to the second node N2 gradually decreases from voltage Vnf toward voltage Vnc and becomes voltage Vnc. The voltage supplied to the third node N3 gradually decreases from voltage Vne toward voltage Vnc and becomes voltage Vnc. The potential difference Vgs becomes 0V, and the potential difference Vds becomes 10V. The light-emitting element OLED does not emit light.

[0271] As described above, during the period PIP, the precharge voltage (intermediate potential) is supplied to the first node N1, and the second node N2 and the third node N3 are initialized by the initialization voltage VINI1 (-2V).

[0272] As described above, the voltages (potentials) of the first node N1, the second node N2, and the third node N3, and the operation of each transistor, from the beginning of the horizontal period HRP of KthFRAME following the period PIP to the light emission period PEM of KthFRAME, are the same as the configuration and operation described in "2-2-1. First example of the method for driving the pixel circuit 181."

[0273] During the period PWR, a data signal VDATA (voltage VSIGL in the third example) is written to the pixel 180A (pixel circuit 181A) in the same manner as in the configuration described in "2-2-1. First Example of the Method for Driving the Pixel Circuit 181A." During the period PVH, the threshold voltage VTH of the second transistor T2 is acquired by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is held at the third node N3 (first electrode 692 of the capacitance element CS).

[0274] Furthermore, during the light emission period PEM of KthFRAME, similar to the configuration described in "2-2-1. First example of driving method for pixel circuit 181A", three pixels, using pixel 180A that emits red light, pixel 180A that emits blue light, and pixel 180A that emits green light, produce black.

[0275] The third example of the method for driving the pixel circuit 181A including the configuration described above has the same effects as those of 2-2-1. First example of the method for driving the pixel circuit 181A.

[0276] <2-2-4. Fourth Example of Method for Driving Pixel Circuit 181A> A fourth example of a method for driving the pixel circuit 181A will be described with reference to Fig. 30. The fourth example of a method for driving the pixel circuit 181A includes displaying images of different colors in successive frames, similar to the fourth example of the method for driving the self-luminous display device 10 according to the first embodiment. Configurations that are the same as or similar to those in Figs. 1 to 29 will be described as necessary.

[0277] The configurations of the image data signal SL(m), the first scan signal SC1(n), the second scan signal SC2(n), the third scan signal SC3(n), the fourth scan signal SC4(n), and the scan voltage power supply SIR(n) during the light emission period PEM of the K-1st FRAME to the light emission period PEM of the Kth FRAME are the same as those described in "2-2-1. First Example of the Method for Driving the Pixel Circuit 181A." Furthermore, the voltages (potentials) of the first node N1, the second node N2, and the third node N3, and the operation of each transistor during the light emission period PEM of the K-1st FRAME to the period PIP are the same as those described in "2-2-3. Third Example of the Method for Driving the Pixel Circuit 181A." Furthermore, the voltages (potentials) of the first node N1, the second node N2, and the third node N3, and the operation of each transistor from the beginning of the horizontal period HRP of the Kth FRAME to the light emission period PEM of the Kth FRAME are the same as the configurations and operations described in "2-2-2. Second Example of the Method for Driving the Pixel Circuit 181A." Configurations similar to those described in "2-2-1. First Example of the Method for Driving the Pixel Circuit 181A," "2-2-2. Second Example of the Method for Driving the Pixel Circuit 181A," and "2-2-3. Third Example of the Method for Driving the Pixel Circuit 181A" will be described as necessary. Note that, as the image data signal SL(m), a data signal VDATA including a voltage VSIGH corresponding to white is supplied during the period between the light emission period PEM of the K-1st FRAME and the light emission period PEM of the Kth FRAME.

[0278] In the light emission period PEM of the (K-1st) FRAME, the pixel 180 (pixel circuit 181) turns black, as in "2-2-3. Third example of the method for driving the pixel circuit 181A."

[0279] During the period PIP, as in "2-2-3. Third example of driving method for pixel circuit 181A," a precharge voltage (intermediate potential) is supplied to the first node N1, and the second node N2 and the third node N3 are initialized by the initialization voltage VINI2 (-2V).

[0280] During the period PWR, as in "2-2-2. Second Example of Method for Driving Pixel Circuit 181A," a data signal VDATA (voltage VSIGH in the fourth example) is written to the pixel 180A (pixel circuit 181A). Also, during the period PVH, the threshold voltage VTH of the second transistor T2 is acquired by an operation in which the potential difference Vgs of the second transistor T2 becomes equal to the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is held at the third node N3 (first electrode 692 of the capacitance element CS).

[0281] Furthermore, during the light emission period PEM of KthFRAME, as in "2-2-2. Second example of driving method for pixel circuit 181A", pixel 180 that emits red light, pixel 180 that emits blue light, and pixel 180 that emits green light emit light, and white light is emitted by three pixels using pixel 180 that emits red light, pixel 180 that emits blue light, and pixel 180 that emits green light.

[0282] The fourth example of the method for driving the pixel circuit 181A including the configuration described above has the same effects as "2-2-1. First example of the method for driving the pixel circuit 181A."

[0283] <2-3. Configuration of Control Circuit 120A> An overview of the control circuit 120A will be described with reference to FIG. 2 and FIGS. 31 to 33. FIG. 31 is a schematic diagram showing the configuration of the control circuit 120A, FIG. 32 is a circuit diagram showing the circuit configuration of the scan driver 160A(n), and FIG. 33 is a timing chart of the control circuit 120A. The configurations of the control circuit 120A and the scan driver 160A(n) and the timing charts shown in FIGS. 31 to 33 are merely examples, and the configurations of the control circuit 120A and the scan driver 160A(n) and the timing charts are not limited to the configurations shown in FIGS. 31 to 33. Configurations similar to those of the control circuit 120 will be explained as necessary. Configurations that are the same as or similar to those in FIGS. 1 to 30 will be explained as necessary.

[0284] The self-luminous display device according to the second embodiment includes two control circuits 120 A. The self-luminous display device according to the second embodiment includes a configuration in which the two control circuits 120 shown in FIG. 2 are replaced with two control circuits 120 A.

[0285] 31, the control circuit 120A includes a shift register circuit 130 and a plurality of scan drivers 160A(n). For example, the control circuit 120A receives inputs of control signals such as a clock signal CLK, a start pulse STV, an enable signal EN1, an enable signal EN1B, an enable signal EN2, and an enable signal EN2B, voltages VCM2 and VCZ, and voltages such as a drive voltage VDDEL and a reference voltage VSSEL. The control circuit 120A can sequentially select scan lines based on the inputs of the control signals and power supplies.

[0286] The shift register circuit 130 is electrically connected to a plurality of scan drivers 160A(n). The shift register circuit 130 has a configuration similar to that of the control circuit 120. The shift register circuit 130 has a role of generating a plurality of output signals (output signal SR1(n), output signal SR2(n), output signal SR3(n), output signal SR4(n), output signal SR5(n), etc.) shifted at different timings, and sequentially outputting them to a plurality of scan drivers (e.g., scan driver 160A(1), scan driver 160A(2), scan driver 160A(3), etc.).

[0287] Shift register 111 is electrically connected to scan driver 160A(1) and supplies an output signal SR1(n) to input terminals IN1 and IN4 of scan driver 160A(1). Shift register 112 is electrically connected to scan drivers 160A(1) and 160A(2) and supplies an output signal SR2(n) to input terminal IN5 of scan driver 160A(1) and input terminals IN1 and IN4 of scan driver 160A(2). Shift register 113 is electrically connected to scan drivers 160A(1), 160A(2), and 160A(3) and supplies an output signal SR3(n) to input terminals IN2 and IN6 of scan driver 160A(1), input terminal IN5 of scan driver 160A(2), and input terminals IN1 and IN4 of scan driver 160A(3). Shift register 114 is electrically connected to scan drivers 160A(2) and 160A(3) and supplies an output signal SR4(n) to input terminals IN2 and IN6 of scan driver 160A(2) and input terminal IN5 of scan driver 160A(3). Shift register 115 is electrically connected to scan driver 160A(3) and supplies an output signal SR5(n) to input terminals IN2 and IN6 of scan driver 160A(3).

[0288] The scan driver 160A(n) has nine input terminals (input terminals IN1 to IN9) and five output terminals (output terminals OUT1 to OUT5). The plurality of scan drivers 160A(n) are supplied with enable signals EN1, EN1B, EN2, and EN2B from the IC chip 110 via a plurality of connection wirings 342, with voltages VCM2 and VCZ also being supplied from the IC chip 110 via a plurality of connection wirings 342, with a drive voltage VDDEL being supplied via a drive power supply line PVDD, and with a reference voltage VSSEL being supplied via a reference voltage line PVSS. The scan driver 160A(n) sequentially supplies scan signals (for example, a first scan signal SC1(n), a second scan signal SC2(n), a third scan signal SC3(n), a fourth scan signal SC4(n), and a scan voltage power supply SIR(n)) with different timings to each scan signal line or connection wiring 342 based on the above-mentioned plurality of output signals, the enable signal EN1, the enable signal EN1B, the enable signal EN2, the enable signal EN2B, the voltage VCM2, and the voltage VCZ, and also sequentially supplies the scan signals (for example, a first scan signal SC1(n), a second scan signal SC2(n), a third scan signal SC3(n), a fourth scan signal SC4(n), and a scan voltage power supply SIR(n)) with different timings to each scan signal line or connection wiring 342. The connection wiring 342 to which the voltage VCM2 is supplied is electrically connected to the input terminals IN8 of the scan driver 160A(1), the scan driver 160A(2), and the scan driver 160A(3), and the connection wiring 342 to which the voltage VCZ is supplied is electrically connected to the input terminals IN9 of the scan driver 160A(1), the scan driver 160A(2), and the scan driver 160A(3). The voltage VCM2 is −2 V, the same as the initialization voltage VINI1, and the voltage VCZ is 0 V, the same as the initialization voltage VINI2.

[0289] For example, as shown in FIG. 32, the scan driver 160A(n) has a configuration in which input terminals IN8 and IN9, an output terminal OUT5, an inverter circuit INV7, and transistors TR2 and TR3 are added to the configuration of the scan driver 160(n). The transistor TR2 is electrically connected to the input terminal IN8, the output terminals OUT2 and OUT5, and the inverter circuit INV7. The transistor TR3 is electrically connected to the input terminal IN9, the inverter circuit INV7, and the output terminal OUT2. For example, as shown in FIG. 31, each control signal is input to nine input terminals (input terminals IN1 to IN9). Also, as shown in FIG. 31, the first scan signal SC1(n) is output to a scan signal line 330 electrically connected to the output terminal OUT1, the second scan signal SC2(n) is output to a scan signal line 331 electrically connected to the output terminal OUT2, the third scan signal SC3(n) is output to a scan signal line 332 electrically connected to the output terminal OUT3, the fourth scan signal SC4(n) is output to a scan signal line 333 electrically connected to the output terminal OUT4, and the scan voltage power supply SIR(n) is output to a scan voltage power supply line SVIR electrically connected to the output terminal OUT5.

[0290] Next, a driving method of the control circuit 120A will be described with reference to Fig. 33. The configuration of the control circuit 120A is different from the configuration of the control circuit 120 described in "1-3. Control Circuit 120" in the rising edges of the second scan signal SC2(n), the third scan signal SC3(n), and the scan voltage power supply SIR(n). Therefore, here, the rising edges of the second scan signal SC2(n), the third scan signal SC3(n), and the scan voltage power supply SIR(n) will be described.

[0291] 31 to 33, for example, the second scan signal SC2(n) is generated based on the rising edge of the enable signal ENB2 and the falling edge of the output signal SR1(n), and the third scan signal SC3(n) is generated based on the rising edge of the output signal SR1(n) and the falling edge of the output signal SR2(n). Furthermore, the scan voltage power supply SIR(n) is supplied with a voltage VCZ (0V) based on the timing at which the second scan signal SC2(n) is input as LO, and with a voltage VCM2 (-2V) based on the timing at which the second scan signal SC2(n) is input as HI. That is, as explained in "2-1. Configuration of pixel 180A," the scan voltage power supply SIR(n) is a signal line whose voltage (potential) is changed.

[0292] 3. Third Embodiment An overview of the self-luminous display device according to the third embodiment will be described with reference to Figures 1, 6, and 34 to 42. Figure 34 is a schematic diagram showing input signals to pixel 180B (pixel circuit 181B) according to the third embodiment, Figure 35 is a circuit diagram showing the configuration of pixel circuit 181B, and Figures 36 to 39 are timing charts of the self-luminous display device according to the third embodiment. Figure 40 is a schematic diagram showing the configuration of control circuit 120B according to the third embodiment, Figure 41 is a circuit diagram showing the configuration of scan driver 160B(n) according to the third embodiment, and Figure 42 is a timing chart of control circuit 120B.

[0293] The self-luminous display device according to the third embodiment includes a pixel 180B, a pixel circuit 181B, and a control circuit 120B. The configurations of the pixel 180B, the pixel circuit 181B, and the control circuit 120B are different from the configurations of the pixel 180A, the pixel circuit 181A, and the control circuit 120A of the self-luminous display device according to the second embodiment. Specifically, the self-luminous display device according to the third embodiment has a configuration and function in which the third scan signal SC3(n) supplied to the pixel circuit 181B also serves as the second scan signal SC2(n) and the third scan signal SC3(n) supplied to the pixel 180A. In other words, the self-luminous display device according to the third embodiment does not include the second scan signal SC2(n). Furthermore, the self-luminous display device according to the third embodiment has a configuration and function in which the control circuit 120A is replaced with the control circuit 120B. The other configurations and functions are the same as those of the self-luminous display device according to the second embodiment. In describing the configuration and functions of the third embodiment, configurations and functions similar to those of the self-luminous display device 10 according to the first embodiment or the self-luminous display device according to the second embodiment will be described as necessary. Also, configurations that are the same as or similar to those in Figures 1 to 33 will be described as necessary.

[0294] <3-1. Configuration of pixel 180B> The pixel 180B and pixel circuit 181B will be outlined with reference to FIGS.

[0295] The pixel circuit 181B is connected to a scan signal line 332. The scan signal line 332 connected to the pixel circuit 181B is a signal line that serves as both the scan signal line 331 and the scan signal line 332 that were connected to the pixel circuit 181A. In other words, the scan signal line 332 connected to the pixel circuit 181B is a common signal line that combines the scan signal line 331 and the scan signal line 332 that were connected to the pixel circuit 181A. Therefore, the pixel circuit 181B does not include the scan signal line 331. The scan signal line 332 according to the third embodiment may be referred to as a sixth control signal line. The third scan signal SC3(n) according to the third embodiment may be referred to as a sixth control signal.

[0296] A third scan signal SC3(n), which also serves as the second scan signal SC2(n) and the third scan signal SC3(n) supplied to the pixel circuit 181A, is supplied to the scan signal line 332 according to the third embodiment. In the pixel circuit 181B, a gate electrode 652 of the fifth transistor T5 and a gate electrode 662 of the sixth transistor T6 are electrically connected to the scan signal line 332.

[0297] The fifth transistor T5 has its switching controlled using the third scan signal SC3(n). In other words, the fifth transistor T5's conductive state (on state) and non-conductive state (off state) are controlled by the third scan signal SC5(n). When the signal supplied to the fifth scan signal SC5(n) is LO, the fifth transistor T5 is in a non-conductive state, and when the signal supplied to the third scan signal SC3(n) is HI, the fifth transistor T5 is in a conductive state. The other configurations and functions of the fifth transistor T5 are similar to those of the fifth transistor T5 according to the second embodiment.

[0298] The configuration and functions of the pixel circuit 181B other than those described in "3-1. Configuration of the pixel 180B" are the same as those of the pixel circuit 181A.

[0299] <3-2. Driving method of pixel circuit 181B> A method for driving the self-luminous display device 10 according to the third embodiment will be described with reference to Figures 36 to 39. Configurations that are the same as or similar to those in Figures 1 to 35 will be described as necessary. As in the first embodiment, the horizontal axis of the timing chart represents time.

[0300] The method for driving a self-luminous display device according to the third embodiment has a configuration and functions in which the operations associated with the second scan signal SC2(n) and the third scan signal SC3(n) in the method for driving a self-luminous display device according to the second embodiment are replaced with an operation in which the third scan signal SC3(n) also serves as the second scan signal SC2(n).The configuration and functions other than the operation in which the third scan signal SC3(n) also serves as the second scan signal SC2(n) are the same as those of the method for driving a self-luminous display device according to the second embodiment.

[0301] The method for driving the self-luminous display device according to the third embodiment includes the same period as the method for driving the self-luminous display device 10 according to the first embodiment shown in FIG.

[0302] In one horizontal period (horizontal period HRP) in the driving method of the self-luminous display device 10 according to the third embodiment, the pixel 180B (pixel circuit 181B) receives the first scan signal SC1(n), the third scan signal SC3(n), the fourth scan signal SC4(n), the image data signal SL(m) including the data signal VDATA, and the scan voltage power supply SIR(n). For example, the pixel 180B (pixel circuit 181B) is selected in accordance with the timing of the first scan signal SC1(n), the third scan signal SC3(n), and the fourth scan signal SC4(n). The image data signal SL(m) and the scan voltage power supply SIR(n) are input to the selected pixel 180B (pixel circuit 181B) in accordance with the timing of each signal. A similar operation is performed for all pixels 180B (pixel circuits 181B), and based on the image data signals SL(m) input to all pixels 180B (pixel circuits 181B), an image of the frame corresponding to one frame is displayed in the display area 22 of the self-luminous display device 10.

[0303] For example, the voltages (potentials) supplied to the signals and nodes in each frame in the timing charts shown in FIGS.

[0304] [Table 5]

[0305] [Table 6]

[0306] For example, as shown in Table 6, the initialization voltage VINI1 is −3.5 V, and the voltage VL(LO) is −5.5 V. The setting values ​​of the other voltages are the same as the setting values ​​shown in Table 4 described in “2-2. Driving method of pixel circuit 181A.”

[0307] In order to smoothly acquire the threshold voltage VTH, the threshold voltage VTHEL of the light-emitting element OLED is greater than (initialization voltage VINI2-threshold voltage VTH), and (initialization voltage VINI2-threshold voltage VTH) is set to (voltage VSIGH supplied to the first node N1-(voltage VSIGH supplied to the first node N1 (intermediate potential)-initialization voltage VINI1)).

[0308] <3-2-1. First Example of Method for Driving Pixel Circuit 181B> A first example of a method for driving the pixel circuit 181B will be described with reference to Fig. 36. The first example of the method for driving the pixel circuit 181B includes displaying images of different colors in successive frames, similar to the first example of the method for driving the self-luminous display device according to the second embodiment.

[0309] The configurations of the image data signal SL(m), the first scan signal SC1(n), the third scan signal SC3(n), the fourth scan signal SC4(n), and the scan voltage power supply SIR(n) during the light emission period PEM of the K-1st FRAME and the light emission period PEM of the Kth FRAME are the same as those described in "2-2-1. First example of driving method of pixel circuit 181A." Furthermore, the voltages (potentials) of the first node N1, the second node N2, and the third node N3, and the operation of each transistor during the light emission period PEM of the K-1st FRAME and the light emission period PEM of the Kth FRAME are the same as those described in "2-2-1. First example of driving method of pixel circuit 181A."

[0310] In the light emitting period PEM of the K-1st FRAME, the light emitting element OLED emits light in the same manner as in the configuration described in "2-2-1. First example of pixel circuit 181A."

[0311] During the period between the light-emitting period PEM of the (K-1st) FRAME and the period PIP following the light-emitting period PEM of the (K-1st) FRAME, the pixel 180B (pixel circuit 181B) holds the data signal VDATA of the voltage VSIGL corresponding to the non-light-emitting black color. The scan voltage power supply SIR(n) changes from a state in which the initialization voltage VINI2 (0 V) is supplied to a state in which the initialization voltage VINI1 (voltage Vnh, −3.5 V) is supplied. The first scan signal SC1(n) changes from a state in which LO is supplied to a state in which HI is supplied. When the first scan signal SC1(n) changes to a state in which HI is supplied, the third scan signal SC3(n) changes from a state in which LO is supplied to a state in which HI is supplied. The fourth scan signal SC4(n) is in a state in which LO is supplied. Therefore, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 change from an off state to an on state, the third transistor T3 changes from an on state to an off state, and the first transistor T1 maintains the off state. As a result, the voltage supplied to the second node N2 gradually drops from the voltage Vna toward the initialization voltage VINI1 (voltage Vnh, −3.5 V), the voltage supplied to the first node N1 gradually drops from the voltage Vna toward the precharge voltage VPRC (voltage Vnd, 1.5 V), and the voltage supplied to the third node N3 gradually drops from the voltage Vnb toward the initialization voltage VINI1 (voltage Vnh, −3.5 V).

[0312] During the period PIP following the period between the light emission period PEM and the period PIP of the (K-1st) FRAME, the image data signal SL(m) maintains a state in which the data signal VDATA of the voltage VSIGL is supplied, the first scan signal SC1(n) and the third scan signal SC3(n) maintain a state in which HI is supplied, and the fourth scan signal SC4(n) maintains a state in which LO is supplied. Therefore, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the fourth transistor T4 maintain an ON state, and the first transistor T1 and the third transistor T4 maintain an OFF state.

[0313] As a result, the voltage supplied to the first node N1 gradually drops from voltage Vna to voltage Vnd and reaches voltage Vnd. The voltage supplied to the second node N2 gradually drops from voltage Vna to voltage Vnh and reaches voltage Vnh. The voltage supplied to the third node N3 gradually drops from voltage Vnb to voltage Vnh and reaches voltage Vnh. The potential difference Vgs becomes 0 V, and the potential difference Vds becomes 11.5 V. Because the potential difference Vgs is smaller than the threshold voltage VTH, the second transistor T2 is in the off state, and the drain current Ion does not flow from the driving power line PVDD to the initialization voltage power line SVI or the reference voltage line PVSS, so the light-emitting element OLED does not emit light.

[0314] As described above, during the period PIP, the precharge voltage (intermediate potential) is supplied to the first node N1, and the second node N2 and the third node N3 are initialized by the initialization voltage VINI1 (-3.5V).

[0315] During the initial period of the horizontal period HRP of the KthFRAME following the period PIP, the configurations of the image data signal SL(m), the first scan signal SC1(n), the third scan signal SC3(n), the fourth scan signal SC4(n), and the scan voltage power supply SIR(n), as well as the operation of each transistor, are the same as those described in "2-2-1. First Example of the Driving Method of the Pixel Circuit 181A." As a result, the voltage supplied to the first node N1 remains at voltage Vnd, and the voltages supplied to the second node N2 and the third node N3 remain at voltage Vnh. Also, as in the period PIP, the light-emitting element OLED does not emit light.

[0316] During the period PWR following the initial period of the horizontal period HRP, the configurations of the image data signal SL(m), the first scan signal SC1(n), the third scan signal SC3(n), the fourth scan signal SC4(n), and the scan voltage power supply SIR(n), as well as the operation of each transistor, are the same as those described in "2-2-1. First Example of the Driving Method of the Pixel Circuit 181A." As a result, the voltage supplied to the first node N1 gradually drops from voltage Vnd toward voltage VSIGL (voltage Vnf, −0.5V), while the voltage supplied to the second node N2 and the voltage supplied to the third node N3 maintain voltage Vnh. Furthermore, as in the period PIP, the light-emitting element OLED does not emit light.

[0317] During the period PVH that is parallel to (overlaps with) the period PWR and is midway through the period PWR, the configurations of the image data signal SL(m), the first scan signal SC1(n), the third scan signal SC3(n), the fourth scan signal SC4(n), and the scan voltage power supply SIR(n), and the operation of each transistor are the same as those described in "2-2-1. First Example of the Driving Method of the Pixel Circuit 181A." As a result, the voltage supplied to the first node N1 gradually drops toward voltage Vnf and becomes voltage Vnf, and the voltage supplied to the second node N2 gradually rises from voltage Vnh toward the initialization voltage VINI2(0V) and becomes the initialization voltage VINI2(0V).

[0318] Immediately after the start of the period PVH, the potential difference Vgs is 0 V, the potential difference Vds is 11.5 V, and the second transistor T2 is in the off state. The fifth transistor T5 is also in the off state. Meanwhile, the fourth transistor T4 is in the on state, and the voltage supplied to the second node N2 increases from the voltage Vnh toward the initialization voltage VINI2 (0 V). As the voltage supplied to the second node N2 approaches 0 V, the potential difference Vgs exceeds the threshold voltage VTH. As a result, the second transistor T2 is turned on, charging of the third node N3 begins, and the voltage supplied to the third node N3 gradually increases.

[0319] When the potential difference Vgs reaches the threshold voltage VTH, the voltage supplied to the second node N2 and the voltage supplied to the third node N3 maintain their respective voltages at that time. For example, as shown in Fig. 36, the voltage supplied to the second node N2 is the initialization voltage VINI2 (0 V), and the voltage supplied to the third node N3 is the voltage Vne (-1 V). Since the second transistor T2 is in the off state and no current flows from the driving power supply line PVDD to the reference voltage line PVSS, the light-emitting element OLED does not emit light.

[0320] During the final period of the period PVH, the configurations of the image data signal SL(m), the first scan signal SC1(n), the third scan signal SC3(n), the fourth scan signal SC4(n), and the scan voltage power supply SIR(n), as well as the operation of each transistor, are the same as those described in "2-2-1. First Example of the Driving Method of the Pixel Circuit 181A." Therefore, the voltage supplied to the first node N1 and the voltage supplied to the second node N2 become Vnf, and the voltage supplied to the third node N3 maintains the voltage Vne. Because the potential difference Vgs is 1 V, the potential difference Vds is 9 V, and the potential difference Vgs is the same as the threshold voltage VTH, no current flows from the driving power supply line PVDD to the reference voltage line PVSS. Furthermore, the light-emitting element OLED does not emit light.

[0321] In this way, during the period PWR, the data signal VDATA is written to the pixel 180 (pixel circuit 181). During the period PVH, the threshold voltage VTH of the second transistor T2 is acquired by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is held at the third node N3 (the first electrode 692 of the capacitance element CS).

[0322] During the light emission period PEM of the KthFRAME following the horizontal period HRP of the KthFRAME, the display becomes black with three pixels, using pixel 180B that emits red light, pixel 180B that emits blue light, and pixel 180B that emits green light, similar to the configuration described in "2-2-1. First example of the driving method of pixel circuit 181A."

[0323] The first example of the method for driving the pixel circuit 181B including the configuration described above can supply an intermediate potential to the first node N1 and then supply the data signal VDATA, similar to "2-2-1. First example of the method for driving the pixel circuit 181A."

[0324] Furthermore, the first example of the method for driving the pixel circuit 181B includes performing the period PWR and the period PVH at the same timing. As a result, the first example of the method for driving the pixel circuit 181B, like "2-2-1. First Example of the Method for Driving the Pixel Circuit 181A," can increase the writing speed and increase the number of pixels that can be written in a time period in which the writing speed is shortened. Therefore, a self-luminous display device including the pixel circuit 181B can provide a high-resolution display device and a large-screen display device. Furthermore, a self-luminous display device including the pixel circuit 181B can reduce (suppress) power consumption.

[0325] Furthermore, the scan signal line 332 connected to the pixel circuit 181B is a signal line that serves both as the scan signal line 331 and the scan signal line 332 that were connected to the pixel circuit 181A. Therefore, the pixel circuit 181B has a configuration that allows the number of signal lines to be reduced, and therefore the size of the pixels in a self-luminous display device including the pixel circuit 181B can be reduced. As a result, the self-luminous display device including the pixel circuit 181B can increase the number of pixels, and can also achieve higher definition and a larger screen.

[0326] <3-2-2. Second Example of Method for Driving Pixel Circuit 181B> A second example of a method for driving the pixel circuit 181B will be described with reference to Fig. 37. The driving method shown in the second example of the pixel circuit 181B includes displaying images of the same color (white) in consecutive frames, similar to the second example of the method for driving the self-luminous display device 10 according to the first embodiment. Configurations that are the same as or similar to those in Figs. 1 to 36 will be described as necessary.

[0327] The configurations of the image data signal SL(m), the first scan signal SC1(n), the third scan signal SC3(n), the fourth scan signal SC4(n), and the scan voltage power supply SIR(n) during the light emission period PEM of the (K-1st) FRAME to the light emission period PEM of the Kth FRAME are the same as those described in "3-2-1. First Example of Driving Method of Pixel Circuit 181B." Furthermore, the voltages (potentials) of the first node N1, the second node N2, and the third node N3, and the operation of each transistor during the initial period of the horizontal period HRP during the light emission period PEM of the (K-1st) FRAME to the Kth FRAME are the same as those described in "3-2-1. First Example of Driving Method of Pixel Circuit 181B." Furthermore, the voltages (potentials) of the first node N1, the second node N2, and the third node N3, and the operation of each transistor from the end of the period PVH to the light emission period PEM of the Kth FRAME are the same as the configurations and operations described in "2-2-2. Second Example of the Method for Driving the Pixel Circuit 181A." The same configurations as those described in "3-2-1. First Example of the Method for Driving the Pixel Circuit 181B" and "2-2-2. Second Example of the Method for Driving the Pixel Circuit 181A" will be explained as necessary. Note that, as the image data signal SL(m), a data signal VDATA including VSIGH corresponding to white is supplied during the period between the light emission period PEM of the K-1st FRAME and the light emission period PEM of the Kth FRAME.

[0328] In the light emitting period PEM of the K-1st FRAME, the light emitting element OLED emits light in the same manner as in the configuration described in "3-2-1. First example of the method for driving the pixel circuit 181B".

[0329] During the period between the light-emitting period PEM of the K-1st FRAME and the period PIP following the light-emitting period PEM of the K-1st FRAME, similar to the configuration described in "3-2-1. First example of the driving method of the pixel circuit 181B", the voltage supplied to the second node N2 gradually drops from voltage Vna toward voltage Vnc, the voltage supplied to the first node N1 gradually drops from voltage Vna toward the precharge voltage VPRC (voltage Vnd, 1.5V), and the voltage supplied to the third node N3 gradually drops from voltage Vnb toward voltage Vnc.

[0330] During the period PIP following the period between the light-emitting period PEM and the period PIP of the K-1st FRAME, similar to the configuration described in "3-2-1. First example of the method for driving the pixel circuit 181B", the voltage supplied to the first node N1 becomes the voltage Vnd, the voltage supplied to the second node N2 and the voltage supplied to the third node N3 become the voltage Vnc (initialization voltage VINI1), the potential difference Vgs becomes 0 V, and the potential difference Vds becomes 11.5 V. In addition, the light-emitting element OLED does not emit light.

[0331] As described above, during the period PIP, the precharge voltage (intermediate potential) is supplied to the first node N1, and the second node N2 and the third node N3 are initialized by the initialization voltage VINI1 (-3.5V).

[0332] During the initial period of the horizontal period HRP of KthFRAME following the period PIP, similar to the configuration described in "3-2-1. First example of the method for driving the pixel circuit 181B", the voltage supplied to the first node N1 maintains the voltage Vnd, the voltage supplied to the second node N2 and the voltage supplied to the third node N3 maintain the voltage Vnc (initialization voltage VINI1), and the light-emitting element OLED does not emit light.

[0333] During the period PWR following the initial period of the horizontal period HRP, each transistor operates in the same manner as in the configuration described in "3-2-1. First example of the method of driving the pixel circuit 181B", the voltage supplied to the first node N1 gradually rises from the voltage Vnd toward the voltage VSIGH (voltage Vng, 3.5 V), the voltage supplied to the second node N2 and the voltage supplied to the third node N3 maintain the voltage Vnc, and the light-emitting element OLED does not emit light.

[0334] In the middle of the period PWR, during the period PVH that is parallel to (overlaps with) the period PWR, each transistor operates in the same manner as the configuration described in "3-2-1. First example of the driving method for the pixel circuit 181B", and the voltage supplied to the first node N1 gradually rises from voltage Vnd toward voltage VSIGH (voltage Vng, 3.5V) and becomes voltage Vng, and the voltage supplied to the second node N2 gradually rises from voltage Vnc toward the initialization voltage VINI2 (0V) and becomes the initialization voltage VINI2 (0V).

[0335] Immediately after the start of the period PVH, the potential difference Vgs is 0 V, the potential difference Vds is 11.5 V, and the second transistor T2 is in the OFF state. The fifth transistor T5 is also in the OFF state. Meanwhile, the fourth transistor T4 is in the ON state, and the voltage supplied to the second node N2 increases from the voltage Vnc toward the initialization voltage VINI2 (0 V). As the voltage supplied to the second node N2 approaches 0 V, the potential difference Vgs exceeds the threshold voltage VTH. As a result, the second transistor T2 is turned ON, charging of the third node N3 begins, and the voltage supplied to the third node N3 gradually increases.

[0336] When the potential difference Vgs between the voltage supplied to the second node N2 and the voltage supplied to the third node N3 reaches the threshold voltage VTH, the voltage supplied to the second node N2 and the voltage supplied to the third node N3 maintain their respective voltages at that time. For example, as shown in Figure 37, the voltage supplied to the second node N2 is the initialization voltage VINI2 (0 V), and the voltage supplied to the third node N3 is the voltage Vne (-1 V). Since the second transistor T2 is in the off state and no current flows from the driving power supply line PVDD to the reference voltage line PVSS, the light-emitting element OLED does not emit light.

[0337] At the end of the period PVH, each transistor operates in the same manner as in the configuration described in "2-2-2. Second Example of the Method for Driving the Pixel Circuit 181A." As a result, at the end of the period PVH, the second transistor T2 is in a conductive state, and a drain current Ion flows from the drive power supply line PVDD to the reference voltage line PVSS, in the same manner as in the configuration described in "2-2-2. Second Example of the Method for Driving the Pixel Circuit 181A." Therefore, the voltages of the first node N1 and the second node N2 rise to follow the rise in the voltage of the third node N3.

[0338] Furthermore, during the light emission period PEM of the Kth FRAME following the horizontal period HRP of the Kth FRAME, each light emitting element OLED emits light, similar to the configuration described in "2-2-2. Second Example of the Method of Driving the Pixel Circuit 181A." For example, three pixels, including a pixel 180B that emits red light, a pixel 180B that emits blue light, and a pixel 180B that emits green light, emit white light.

[0339] As described above, during the period PWR, the data signal VDATA is written to the pixel 180B (pixel circuit 181B). During the period PVH, the threshold voltage VTH of the second transistor T2 is acquired by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is held at the third node N3 (the first electrode 692 of the capacitance element CS). During the light-emitting period PEM of the KthFRAME, the three pixels emit white light.

[0340] The second example of the method for driving the pixel circuit 181B including the configuration described above has the same effects as "3-2-1. First example of the method for driving the pixel circuit 181B."

[0341] <3-2-3. Third Example of Method for Driving Pixel Circuit 181B> A third example of a method for driving the pixel circuit 181B will be described with reference to Fig. 38. The driving method shown in the third example of the method for driving the pixel circuit 181B includes displaying images of the same color (black) in consecutive frames, similar to the third example of the method for driving the self-luminous display device 10 according to the first embodiment. Configurations that are the same as or similar to those in Figs. 1 to 37 will be described as necessary.

[0342] The configurations of the image data signal SL(m), the first scan signal SC1(n), the third scan signal SC3(n), the fourth scan signal SC4(n), and the scan voltage power supply SIR(n) during the light emission period PEM of the K-1st FRAME to the light emission period PEM of the Kth FRAME are the same as those described in "3-2-1. First Example of the Method for Driving Pixel Circuit 181B." Furthermore, the voltages (potentials) of the first node N1, the second node N2, and the third node N3, and the operation of each transistor during the light emission period of the K-1st FRAME are the same as those described in "2-2-3. Third Example of the Method for Driving Pixel Circuit 181A." Furthermore, the voltages (potentials) of the first node N1, the second node N2, and the third node N3, and the operation of each transistor from the beginning of the horizontal period HRP of the Kth FRAME to the light emission period PEM of the Kth FRAME are the same as the configurations and operations described in "3-2-1. First Example of the Method for Driving the Pixel Circuit 181B." The same configurations as those described in "3-2-1. First Example of the Method for Driving the Pixel Circuit 181B" and "2-2-3. Third Example of the Method for Driving the Pixel Circuit 181A" will be explained as necessary. Note that, as for the image data signal SL(m), a data signal VDATA of a voltage VSIGL corresponding to black is supplied during the periods PWR and PVH.

[0343] During the light emitting period PEM of the K-1st FRAME, similar to the configuration described in "2-2-3. Third Example of the Method for Driving the Pixel Circuit 181A", the light emitting element OLED does not emit light and the pixel 180B (pixel circuit 181B) turns black.

[0344] During the period between the light-emitting period PEM of the (K-1st) FRAME and the period PIP, similar to the configuration described in "3-2-3. Third Example of the Method for Driving the Self-Emitting Display Device 10," the voltage supplied to the first node N1 is maintained at voltage Vnf, and the voltage supplied to the second node N2 gradually drops from voltage Vnf toward the initialization voltage VINI1 (Vnh, -3.5V). Also, the voltage supplied to the third node N3 gradually drops from voltage Vne toward the initialization voltage VINI1 (Vnh, -3.5V). Also, the light-emitting element OLED does not emit light.

[0345] During the period PIP following the period between the light-emitting period PEM and the period PIP of the (K-1st) FRAME, the voltage supplied to the first node N1 gradually increases from voltage Vnf toward the precharge voltage VPRC (voltage Vnd, 1.5V) and reaches voltage Vnd. The voltage supplied to the second node N2 gradually decreases from voltage Vnf toward voltage Vnh and reaches voltage Vnh. The voltage supplied to the third node N3 gradually decreases from voltage Vne toward voltage Vnh and reaches voltage Vnh. The potential difference Vgs becomes 0V, and the potential difference Vds becomes 11.5V. The light-emitting element OLED does not emit light.

[0346] As described above, during the period PIP, the precharge voltage (intermediate potential) is supplied to the first node N1, and the second node N2 and the third node N3 are initialized by the initialization voltage VINI1 (-3.5V).

[0347] As described above, the voltages (potentials) of the first node N1, the second node N2, and the third node N3, and the operation of each transistor, from the beginning of the horizontal period HRP of KthFRAME following the period PIP to the light emission period PEM of KthFRAME, are the same as the configuration and operation described in "3-2-1. First example of the method for driving the pixel circuit 181."

[0348] During the period PWR, a data signal VDATA (voltage VSIGL in the third example) is written to the pixel 180B (pixel circuit 181B) in the same manner as in the configuration described in "3-2-1. First Example of the Method for Driving the Pixel Circuit 181B." During the period PVH, the threshold voltage VTH of the second transistor T2 is acquired by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is held at the third node N3 (first electrode 692 of the capacitance element CS).

[0349] Furthermore, during the light emission period PEM of KthFRAME, similar to the configuration described in "3-2-1. First example of driving method for pixel circuit 181B", three pixels, using pixel 180B that emits red light, pixel 180B that emits blue light, and pixel 180B that emits green light, produce black.

[0350] The third example of the method for driving the pixel circuit 181B including the configuration described above has the same effects as "3-2-1. First example of the method for driving the pixel circuit 181B."

[0351] <3-2-4. Fourth Example of Method for Driving Pixel Circuit 181B> A fourth example of a method for driving the pixel circuit 181B will be described with reference to Fig. 39. The fourth example of a method for driving the pixel circuit 181B includes displaying images of different colors in successive frames, similar to the fourth example of the method for driving the self-luminous display device 10 according to the first embodiment. Configurations that are the same as or similar to those in Figs. 1 to 38 will be described as necessary.

[0352] The configurations of the image data signal SL(m), the first scan signal SC1(n), the third scan signal SC3(n), the fourth scan signal SC4(n), and the scan voltage power supply SIR(n) from the light emission period PEM of the K-1st FRAME to the light emission period PEM of the Kth FRAME are the same as those described in "3-2-1. First Example of Driving Method of Pixel Circuit 181B." Furthermore, the voltages (potentials) of the first node N1, the second node N2, and the third node N3, and the operation of each transistor from the light emission period of the K-1st FRAME to the period PIP are the same as those described in "3-2-3. Third Example of Driving Method of Pixel Circuit 181B." Furthermore, the voltages (potentials) of the first node N1, the second node N2, and the third node N3, and the operation of each transistor from the beginning of the horizontal period HRP of the Kth FRAME to the light emission period PEM of the Kth FRAME are the same as the configurations and operations described in "3-2-2. Second Example of the Method for Driving the Pixel Circuit 181B." Configurations similar to those described in "3-2-1. First Example of the Method for Driving the Pixel Circuit 181B," "3-2-2. Second Example of the Method for Driving the Pixel Circuit 181B," and "3-2-3. Third Example of the Method for Driving the Pixel Circuit 181B" will be described as necessary. Note that, as the image data signal SL(m), a data signal VDATA of a voltage VSIGH corresponding to white is supplied during the periods PWR and PVH.

[0353] In the light emission period PEM of the (K-1st) frame, the pixel 180 (pixel circuit 181) turns black, as in "3-2-3. Third example of the method for driving the pixel circuit 181B."

[0354] During the period PIP, as in "3-2-3. Third example of driving method for pixel circuit 181B," a precharge voltage (intermediate potential) is supplied to the first node N1, and the second node N2 and the third node N3 are initialized by the initialization voltage VINI1 (-3.5V).

[0355] During the period PWR, as in "3-2-2. Second Example of Method for Driving Pixel Circuit 181B," a data signal VDATA (voltage VSIGH in the fourth example) is written to the pixel 180B (pixel circuit 181B). Also, during the period PVH, the threshold voltage VTH of the second transistor T2 is acquired by an operation in which the potential difference Vgs of the second transistor T2 becomes equal to the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is held at the third node N3 (first electrode 692 of the capacitance element CS).

[0356] Furthermore, during the light emission period PEM of KthFRAME, as in "3-2-2. Second example of driving method for pixel circuit 181B", white light is emitted by three pixels using pixel 180B that emits red light, pixel 180B that emits blue light, and pixel 180B that emits green light.

[0357] The fourth example of the method for driving the pixel circuit 181B including the configuration described above has the same effects as "3-2-1. First example of the method for driving the pixel circuit 181B."

[0358] <3-3. Configuration of Control Circuit 120B> An overview of the control circuit 120B will be described with reference to FIG. 2 and FIGS. 40 to 42. FIG. 40 is a schematic diagram showing the configuration of the control circuit 120B, FIG. 41 is a circuit diagram showing the circuit configuration of the scan driver 160B(n), and FIG. 42 is a timing chart of the control circuit 120B. The configurations of the control circuit 120B and the scan driver 160B(n) and the timing charts shown in FIGS. 40 to 42 are merely examples, and the configurations of the control circuit 120B and the scan driver 160B(n) and the timing charts are not limited to those shown in FIGS. 40 to 42. Configurations similar to those of the control circuit 120 will be explained as necessary. Configurations that are the same as or similar to those in FIGS. 1 to 39 will be explained as necessary.

[0359] The self-luminous display device according to the third embodiment includes two control circuits 120B. The self-luminous display device according to the third embodiment includes a configuration in which the two control circuits 120 shown in FIG. 2 are replaced with two control circuits 120B.

[0360] 40, the control circuit 120B includes a shift register circuit 130 and a plurality of scan drivers 160B(n). For example, the control circuit 120B receives inputs of control signals such as a clock signal CLK, a start pulse STV, enable signals EN1 and EN2, voltages VCM2 and VCZ, and voltages such as a drive voltage VDDEL and a reference voltage VSSEL. The control circuit 120B can sequentially select scan lines based on the inputs of control signals and power supplies.

[0361] The shift register circuit 130 is electrically connected to a plurality of scan drivers 160B(n). The shift register circuit 130 has a configuration similar to that of the control circuit 120. The shift register circuit 130 has a role of generating a plurality of output signals (output signal SR1(n), output signal SR2(n), output signal SR3(n), output signal SR4(n), output signal SR5(n), etc.) shifted at different timings, and sequentially outputting them to a plurality of scan drivers (e.g., scan driver 160B(1), scan driver 160B(2), scan driver 160B(3), etc.).

[0362] Shift register 111 is electrically connected to scan driver 160B(1) and supplies an output signal SR1(n) to input terminals IN1 and IN3 of scan driver 160B(1). Shift register 112 is electrically connected to scan drivers 160B(1) and 160A(2) and supplies an output signal SR2(n) to input terminal IN4 of scan driver 160B(1) and input terminals IN1 and IN3 of scan driver 160B(2). Shift register 113 is electrically connected to scan drivers 160B(1), 160A(2), and 160A(3) and supplies an output signal SR3(n) to input terminals IN2 and IN5 of scan driver 160B(1), input terminal IN4 of scan driver 160B(2), and input terminals IN1 and IN3 of scan driver 160B(3). Shift register 114 is electrically connected to scan drivers 160B(2) and 160A(3) and supplies an output signal SR4(n) to input terminals IN2 and IN5 of scan driver 160B(2) and input terminal IN4 of scan driver 160B(3). Shift register 115 is electrically connected to scan driver 160B(3) and supplies an output signal SR5(n) to input terminals IN2 and IN5 of scan driver 160B(3).

[0363] The scan driver 160B(n) has eight input terminals (input terminals IN1 to IN8) and four output terminals (output terminals OUT1 to OUT4). The plurality of scan drivers 160B(n) are supplied with enable signals EN1 and EN2 from the IC chip 110 via a plurality of connection wirings 342, with voltages VCM2 and VCZ also supplied from the IC chip 110 via a plurality of connection wirings 342, with a drive voltage VDDEL supplied via a drive power supply line PVDD, and with a reference voltage VSSEL supplied via a reference voltage line PVSS. The scan driver 160B(n) sequentially supplies scan signals with different timings (for example, a first scan signal SC1(n), a third scan signal SC3(n), a fourth scan signal SC4(n), and a scan voltage power supply SIR(n)) to each scan signal line or connection wiring 342 based on the above-mentioned multiple output signals, enable signal EN1, enable signal EN2, voltage VCM2, and voltage VCZ, and also has a role of driving the pixels 180B (pixel circuits 181B) electrically connected to each scan signal line or connection wiring 342. The connection wiring 342 to which the voltage VCM2 is supplied is electrically connected to the input terminals IN7 of the scan drivers 160B(1), 160B(2), and 160B(3), and the connection wiring 342 to which the voltage VCZ is supplied is electrically connected to the input terminals IN8 of the scan drivers 160B(1), 160B(2), and 160B(3). The voltage VCM2 is −3.5 V, the same as the initialization voltage VINI1, and the voltage VCZ is 0 V, the same as the initialization voltage VINI2.

[0364] For example, as shown in FIG. 41, the scan driver 160B(n) has a configuration in which the NOR circuit NR2 and the inverter circuit INV4 are omitted from the configuration of the scan driver 160(n). The scan driver 160B(n) also has a configuration in which the connections of the input terminal IN5, the input terminal IN6, the input terminal IN7, the output terminal OUT3, and the output terminal OUT4 are changed from the configuration of the scan driver 160(n). Furthermore, the scan driver 160B(n) has a configuration in which the input terminal IN8 and transistors TR2, TR3, and TR4 are added to the configuration of the scan driver 160(n). The inverter circuit INV6 is electrically connected to the input terminal IN5, the transmission gate TMG, and the transistor TR1, and the transmission gate TMG is electrically connected to the input terminals IN5 and IN6 and the output terminal OUT3. The transistor TR1 is electrically connected to the reference voltage line PVSS, the transmission gate TMG, and the output terminal OUT3. The transistor TR2 is electrically connected to the input terminal IN7, the output terminal OUT4, and the inverter circuit INV5. The transistor TR3 is electrically connected to the input terminal IN8, the transistor TR4, the transmission gate TMG, the transistor TR1, and the output terminal OUT4. The transistor TR4 is electrically connected to the NOR circuit NR1 and the output terminal OUT4. For example, as shown in FIG. 40, each control signal is input to eight input terminals (input terminals IN1 to IN8). Also, as shown in FIG. 40, the first scan signal SC1(n) is output to a scan signal line 330 electrically connected to the output terminal OUT1, the third scan signal SC3(n) is output to a scan signal line 332 electrically connected to the output terminal OUT2, the fourth scan signal SC4(n) is output to a scan signal line 333 electrically connected to the output terminal OUT3, and the scan voltage power supply SIR(n) is output to a scan voltage power supply line SVIR electrically connected to the output terminal OUT4.

[0365] Next, a method for driving the control circuit 120B will be described with reference to Figures 41 to 43. As shown in Figure 42, the configuration of the control circuit 120B includes a configuration that does not use the second scan signal SC2(n) and the enable signal lines EN1B and EN2B from the configuration of the control circuit 120A described in "2-3. Control circuit 120A." The other configurations of the control circuit 120B are the same as the configuration of the control circuit 120A described in "2-3. Control circuit 120A."

[0366] Also, as shown in FIGS. 41 to 43, the first scan signal SC1(2), the third scan signal SC3(2), the fourth scan signal SC4(2), and the scan voltage signal SIR(2) are signals obtained by shifting the first scan signal SC1(1), the third scan signal SC3(1), the fourth scan signal SC4(1), and the scan voltage signal SIR(1), respectively, based on the output signals SR1(1) to SR4(1) and the enable signal lines EN1 and EN2.

[0367] 4. Fourth Embodiment An overview of the self-luminous display device according to the fourth embodiment will be described with reference to Fig. 1, Fig. 6, and Fig. 44 to Fig. 50. Fig. 44 is a schematic diagram showing input signals to pixel 180C (pixel circuit 181C) according to the fourth embodiment, Fig. 45 is a circuit diagram showing the configuration of pixel circuit 181C, Fig. 46 to Fig. 49 are timing charts for the self-luminous display device according to the fourth embodiment, and Fig. 50 is a diagram for explaining the setting of input signals according to the fourth embodiment of the present invention.

[0368] The self-luminous display device according to the fourth embodiment includes a pixel 180C and a pixel circuit 181C. The configurations of the pixel 180C and the pixel circuit 181C are different from the configurations of the pixel 180A and the pixel circuit 181A of the self-luminous display device according to the second embodiment. Specifically, the pixel 180C and the pixel circuit 181C have a configuration in which the third scan signal SC3(n) supplied to the pixel circuit 181A is replaced with a third scan signal SC4(n-1). Furthermore, the self-luminous display device according to the fourth embodiment has a configuration in which the third scan signal SC3(n) generated by the control circuit 120A is replaced with a third scan signal SC4(n-1). For example, the fourth scan signal SC4(n) of the self-luminous display device according to the fourth embodiment is a signal obtained by shifting the fourth scan signal SC4(n-1) based on the output signals SR1(n) to SR4(n), the enable signal lines EN1, EN1B, EN2, and EN2B, and the voltages VCM2 and VCZ. Furthermore, the timings of the third scan signal SC4(n-1) and the fourth scan signal SC4(n) of the self-luminous display device according to the fourth embodiment are different from the timings of the third scan signal SC3(n) and the fourth scan signal SC4(n) of the self-luminous display device according to the second embodiment. As a result, the self-luminous display device according to the fourth embodiment includes a period PVH after the period PWR. Other configurations and functions of the fourth embodiment are similar to those of the self-luminous display device according to the second embodiment. In describing the configuration and functions of the fourth embodiment, configurations and functions similar to those of the self-luminous display device 10 according to the first embodiment, the self-luminous display device according to the second embodiment, or the self-luminous display device according to the third embodiment will be described as necessary. Moreover, configurations that are the same as or similar to those in FIGS. 1 to 43 will be explained as necessary.

[0369] <4-1. Configuration of pixel 180C> The pixel 180C and pixel circuit 181C will be outlined with reference to FIGS.

[0370] As described above, the pixel 180C and pixel circuit 181C have a configuration in which the third scan signal SC3(n) supplied to the pixel circuit 181A is replaced with the third scan signal SC4(n-1). The configuration and functions of the pixel circuit 181C other than those described in "4-1. Configuration of the pixel 180C" are the same as those of the pixel circuit 181A.

[0371] <4-2. Driving method of pixel circuit 181C> A method for driving a self-luminous display device according to the fourth embodiment will be described with reference to Figures 46 to 49. Configurations that are the same as or similar to those in Figures 1 to 45 will be described as necessary. As in the first embodiment, the horizontal axis of the timing chart represents time.

[0372] As described above, the timings of the third scan signal SC4(n-1) and the fourth scan signal SC4(n) in the self-luminous display device according to the fourth embodiment are different from the timings of the third scan signal SC3(n) and the fourth scan signal SC4(n) in the self-luminous display device according to the second embodiment. The configuration and functions other than the timings of the third scan signal SC4(n-1) and the fourth scan signal SC4(n) in the fourth embodiment are the same as those in the method of driving the self-luminous display device according to the second embodiment.

[0373] The method for driving the self-luminous display device according to the fourth embodiment differs from the method for driving the self-luminous display device according to the first embodiment shown in FIG. 6 in that it includes executing the period PVH after the period PWR.

[0374] In one horizontal period (horizontal period HRP) in the driving method for the self-luminous display device according to the fourth embodiment, the pixel 180C (pixel circuit 181C) receives the first scan signal SC1(n), the third scan signal SC4(n-1), the fourth scan signal SC4(n), the image data signal SL(m) including the data signal VDATA, and the scan voltage power supply SIR(n). For example, the pixel 180C (pixel circuit 181C) is selected according to the timing of the first scan signal SC1(n), the third scan signal SC4(n-1), and the fourth scan signal SC4(n). The image data signal SL(m) and the scan voltage power supply SIR(n) are input to the selected pixel 180C (pixel circuit 181C) according to the timing of each signal. A similar operation is performed for all pixels 180C (pixel circuits 181C), and based on the image data signals SL(m) input to all pixels 180C (pixel circuits 181C), an image of the frame corresponding to one frame is displayed in the display area 22 of the self-luminous display device 10.

[0375] For example, the voltages (potentials) supplied to the signals and nodes in each frame in the timing charts shown in FIGS.

[0376] [Table 7]

[0377] [Table 8]

[0378] For example, as shown in Table 8, the initialization voltage VINI1 is −1.5 V, and the voltage VL(LO) is −3.5 V. The setting values ​​of the other voltages are the same as the setting values ​​shown in Table 4 described in “2-2. Driving method of pixel circuit 181A.”

[0379] <4-2-1. First Example of Driving Method of Pixel Circuit 181C> A first example of a method for driving the pixel circuit 181C will be described with reference to Fig. 46. The first example of the method for driving the pixel circuit 181C includes displaying images of different colors in successive frames, similar to the first example of the method for driving the self-luminous display device according to the second embodiment.

[0380] The configurations of the image data signal SL(m), the first scan signal SC1(n), the fourth scan signal SC4(n), and the scan voltage power supply SIR(n) during the light emission period PEM of the K-1st FRAME and the light emission period PEM of the Kth FRAME are the same as those described in "2-2-1. First Example of the Method for Driving the Pixel Circuit 181A." The voltages (potentials) of the first node N1, the second node N2, and the third node N3, and the operation of each transistor during the light emission period PEM of the K-1st FRAME and the light emission period PEM of the Kth FRAME are the same as those described in "2-2-1. First Example of the Method for Driving the Pixel Circuit 181A." As described above, the third scan signal SC4(n-1) is replaced with the third scan signal SC3(n), and the voltage VL(LO) is −3.5V.

[0381] In the light emitting period PEM of the K-1st FRAME, the light emitting element OLED emits light in the same manner as in the configuration described in "2-2-1. First example of the method for driving the pixel circuit 181A."

[0382] During the period PIP of the Kth FRAME following the light-emitting period PEM of the K-1st FRAME, the pixel 180C (pixel circuit 181C) maintains a state in which it receives the data signal VDATA based on the image data signal SL(m) of the n-1th row, which is immediately before the nth row. During the periods PWR and PVH, the pixel 180C (pixel circuit 181C) receives the image data signal SL(m) of the data signal VDATA with a voltage VSIGL corresponding to black, which is a non-emission color. The first scan signal SC1(n) changes from a LO state to a HI state. When the first scan signal SC1(n) changes to a HI state, the second scan signal SC2(n) changes from a LO state to a HI state. When the second scan signal SC2(n) changes from a LO state to a HI state, the third scan signal SC3(n-1) changes from a LO state to a HI state. The fourth scan signal SC4(n) is in a state in which LO is supplied. Therefore, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 change from an off state to an on state, the third transistor T3 changes from an on state to an off state, and the first transistor T1 maintains an off state. As a result, the voltage supplied to the first node N1 gradually drops from voltage Vna toward the precharge voltage VPRC (voltage Vnd, 1.5 V) and becomes voltage Vnd. The voltage supplied to the second node N2 gradually drops from voltage Vna toward the initialization voltage VINI1 (voltage Vnc, −1.5 V). The voltage supplied to the third node N3 gradually drops from voltage Vnb toward the initialization voltage VINI1 (voltage Vnc, −1.5 V) and becomes voltage Vnc. Although the voltage supplied to the second node N2 does not drop completely to voltage Vnc, the potential difference Vgs is approximately less than 1 V, and the potential difference Vds is less than 9.5 V. The second transistor T2 is in an off state, and the light-emitting element OLED does not emit light.

[0383] As described above, during the period PIP, a precharge voltage (intermediate potential) is supplied to the first node N1, the second node N2 is roughly initialized by the initialization voltage VINI1 (-1.5V), and the third node N3 is initialized by the initialization voltage VINI1 (-1.5V).

[0384] During the initial period of the horizontal period HRP of the KthFRAME following the period PIP, the image data signal SL(m) is supplied with the data signal VDATA of voltage VSIGL, the first scan signal SC1(n) and the second scan signal SC2(n) are maintained at HI, the fourth scan signal SC4(n) is maintained at LO, and the scan voltage power supply SIR(n) is maintained at the initialization voltage VINI1. The third scan signal SC3(n-1) is changed from HI to LO. Therefore, the sixth transistor T6 is changed from ON to OFF, the fourth transistor T4 and the fifth transistor T5 are maintained at ON, and the first transistor T1 and the third transistor T3 are maintained at OFF. As a result, the voltage supplied to the first node N1 is maintained at voltage Vnd, the voltage supplied to the second node N2 drops to near voltage Vnc, and the voltage supplied to the third node N3 is maintained at voltage Vnc. Also, similar to the period PIP, the light emitting element OLED does not emit light.

[0385] During the period PWR following the beginning of the horizontal period HRP, the image data signal SL(m) maintains a state in which the data signal VDATA of the voltage VSIGL is supplied, the first scan signal SC1(n) and the second scan signal SC2(n) maintain a state in which HI is supplied, the third scan signal SC4(n-1) maintains a state in which LO is supplied, and the scan voltage power supply SIR(n) maintains a state in which the initialization voltage VINI1 is supplied. The fourth scan signal SC4(n) changes from a state in which LO is supplied to a state in which HI is supplied. Therefore, the first transistor T1 changes from an OFF state to an ON state, the fourth transistor T4 and the fifth transistor T5 maintain an ON state, and the third transistor T3 and the sixth transistor T6 maintain an OFF state. As a result, the voltage supplied to the first node N1 gradually drops from voltage Vnd toward voltage VSIGL (voltage Vnf, −0.5V), the voltage supplied to the second node N2 becomes voltage Vnc, and the voltage supplied to the third node N3 maintains voltage Vnc. Also, similar to the period PIP, the light-emitting element OLED does not emit light.

[0386] As described above, during the period PWR, the data signal VDATA (here, the voltage VSIGL) is written to the pixel 180C (pixel circuit 181C). Also, the second node N2 and the third node N3 are initialized by the initialization voltage VINI1 (−1.5 V).

[0387] During the period PVH following the period PWR, the image data signal SL(m) maintains a state in which the data signal VDATA including the voltage VSIGL is supplied, the first scan signal SC1(n) and the fourth scan signal SC4(n) maintain a state in which HI is supplied, and the third scan signal SC4(n-1) maintains a state in which LO is supplied. The second scan signal SC2(n) changes from a state in which HI is supplied to a state in which LO is supplied, and the scan voltage power supply SIR(n) changes from a state in which the initialization voltage VINI1 is supplied to a state in which the initialization voltage VINI2 (0 V) is supplied. Therefore, the fifth transistor T5 changes from an ON state to an OFF state, the first transistor T1 and the fourth transistor T4 maintain an ON state, and the third transistor T6 and the sixth transistor T6 maintain an OFF state. As a result, the voltage supplied to the first node N1 maintains the voltage Vnf.

[0388] Immediately after the start of the period PVH, the potential difference Vgs is 0 V, the potential difference Vds is 9.5 V, and the second transistor T2 is in the OFF state. The fifth transistor T5 is also in the OFF state. Meanwhile, because the fourth transistor T4 is in the ON state, the voltage supplied to the second node N2 gradually increases from the voltage Vnc toward the initialization voltage VINI2 (0 V). As a result, the voltage supplied to the second node N2 approaches 0 V, causing the potential difference Vgs to exceed the threshold voltage VTH. As a result, the second transistor T2 is turned ON, charging of the third node N3 begins, and the voltage supplied to the third node N3 gradually increases from the voltage Vnc.

[0389] When the potential difference Vgs reaches the threshold voltage VTH, the voltage supplied to the second node N2 and the voltage supplied to the third node N3 maintain their respective voltages at that time. For example, as shown in Fig. 46, the voltage supplied to the second node N2 is the initialization voltage VINI2 (0 V), and the voltage supplied to the third node N3 is the voltage Vne (-1 V). Since the second transistor T2 is in the off state and no current flows from the driving power supply line PVDD to the reference voltage line PVSS, the light-emitting element OLED does not emit light.

[0390] When the potential difference Vgs reaches the threshold voltage VTH, the second transistor T2 changes from the on state to the off state, and the drain current Ion stops flowing. At this time, the voltage supplied to the third node N3 rises from the voltage Vnc (-1.5V) to the voltage Vne (-1V), and the potential difference Vgs is the same as the threshold voltage VTH (1V). Since the second transistor T2 is in the off state and no current flows from the driving power line PVDD to the reference voltage line PVSS, the light-emitting element OLED does not emit light.

[0391] In this way, during the period PVH, the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is held at the third node N3 (the first electrode 692 of the capacitive element CS).

[0392] During the light emission period PEM of the KthFRAME following the horizontal period HRP of the KthFRAME, the display becomes black with three pixels, using pixel 180C that emits red light, pixel 180C that emits blue light, and pixel 180C that emits green light, similar to the configuration described in "2-2-1. First example of driving method for pixel circuit 181A."

[0393] The first example of the method for driving the pixel circuit 181C including the configuration described above can supply an intermediate potential to the first node N1 and then supply the data signal VDATA, similar to "2-2-1. First example of the method for driving the pixel circuit 181A."

[0394] Furthermore, the first example of the method for driving pixel circuit 181C includes executing period PVH after period PWR. As a result, the first example of the method for driving pixel circuit 181C includes a configuration in which period PVH is shifted from period PWR, and therefore the potential fluctuation of first node N1 is small. Therefore, the method for driving pixel circuit 181C can reduce unnecessary electromagnetic interference (EMI) caused by fluctuations in the potential of image data signal line 321, similar to "2-2-1. First Example of Method for Driving Pixel Circuit 181A."

[0395] Furthermore, the driving method of pixel circuit 181C, like "2-2-1. First Example of Driving Method of Pixel Circuit 181A," can increase the writing speed and increase the number of pixels that can be written in a time period in which the writing speed is shortened. As a result, a self-luminous display device including pixel circuit 181C can provide a high-resolution display device and a large-screen display device. Furthermore, a self-luminous display device including pixel circuit 181C can reduce (suppress) power consumption.

[0396] Furthermore, the third scan signal SC4(n-1) in the self-luminous display device including the pixel circuit 181C is the signal before the fourth scan signal SC4(n) is shifted. That is, the third scan signal SC4(n-1) is a signal supplied to the pixel circuit 181C electrically connected to the row immediately preceding in the row direction. Therefore, the self-luminous display device including the pixel circuit 181C can share the control signal in the row direction with adjacent pixels. Therefore, for example, it is possible to simplify the configuration of the control circuit for generating the third scan signal SC4(n-1) and the fourth scan signal SC4(n).

[0397] <4-2-2. Second Example of Method for Driving Pixel Circuit 181C> A second example of a method for driving the pixel circuit 181C will be described with reference to Fig. 47. The driving method shown in the second example of the pixel circuit 181C includes displaying images of the same color (white) in consecutive frames, similar to the second example of the method for driving the self-luminous display device 10 according to the first embodiment. Configurations that are the same as or similar to those in Figs. 1 to 46 will be described as necessary.

[0398] The configurations of the image data signal SL(m), the first scan signal SC1(n), the third scan signal SC3(n), the fourth scan signal SC4(n), and the scan voltage power supply SIR(n) during the light emission period PEM of the K-1st FRAME to the light emission period PEM of the Kth FRAME are the same as those described in "4-2-1. First Example of the Method for Driving the Pixel Circuit 181C." Furthermore, the voltages (potentials) of the first node N1, the second node N2, and the third node N3, and the operation of each transistor during the light emission period PEM of the K-1st FRAME and the period PIP of the Kth FRAME are the same as those described in "4-2-1. First Example of the Method for Driving the Pixel Circuit 181C." Furthermore, the voltages (potentials) of the second node N2 and the third node N3 and the operation of each transistor during the period PWR and the period PVH of KthFRAME are the same as the configuration and operation described in "4-2-1. First Example of the Method for Driving the Pixel Circuit 181C." Configurations similar to those described in "4-2-1. First Example of the Method for Driving the Pixel Circuit 181C" and "2-2-2. Second Example of the Method for Driving the Pixel Circuit 181A" will be explained as necessary. Note that, as the image data signal SL(m), the data signal VDATA of VSIGH corresponding to white is supplied during the period PWR and the period PVH.

[0399] In the light emitting period PEM of the K-1st FRAME, the light emitting element OLED emits light in the same manner as in the configuration described in "4-2-1. First example of the method for driving the pixel circuit 181C".

[0400] During the KthFRAME period PIP following the light-emitting period PEM of the K-1stFRAME, similar to the configuration described in "4-2-1. First Example of the Method for Driving Pixel Circuit 181C," the voltage supplied to the first node N1 becomes voltage Vnd, the voltage supplied to the second node N2 gradually drops from voltage Vna toward the initialization voltage VINI1 (voltage Vnc, -1.5V), and the voltage supplied to the third node N3 becomes voltage Vnc. The potential difference Vgs becomes less than 1V, and the potential difference Vds becomes less than 9.5V. As a result, the light-emitting element OLED does not emit light.

[0401] As described above, during the period PIP, a precharge voltage (intermediate potential) is supplied to the first node N1, the second node N2 is roughly initialized by the initialization voltage VINI1 (-1.5V), and the third node N3 is initialized by the initialization voltage VINI1 (-1.5V).

[0402] During the initial period of the horizontal period HRP of KthFRAME following the period PIP, similar to the configuration described in "4-2-1. First example of the method for driving the pixel circuit 181C", the voltage supplied to the first node N1 maintains the voltage Vnd, the voltage supplied to the second node N2 drops to near the voltage Vnc, the voltage supplied to the third node N3 maintains the voltage Vnc (initialization voltage VINI1), and the light-emitting element OLED does not emit light.

[0403] During the period PWR following the initial period of the horizontal period HRP, similarly to the configuration described in "4-2-1. First example of the method of driving pixel circuit 181C", the signals are driven and the transistors operate, the voltage supplied to the first node N1 gradually rises from voltage Vnd towards voltage VSIGH (voltage Vng, 3.5V), the voltage supplied to the second node N2 drops to voltage Vnc and maintains voltage Vnc, and the voltage supplied to the third node N3 maintains voltage Vnc, and the light-emitting element OLED does not emit light.

[0404] In this way, during the period PWR, the data signal VDATA (here, the voltage VSIGH) is written to the pixel 180 (pixel circuit 181). The second node N2 and the third node N3 are initialized by the initialization voltage VINI1 (−1.5 V).

[0405] During the period PVH following the period PWR, the signals are driven and the transistors operate in the same manner as in the configuration described in "4-2-1. First Example of the Driving Method of the Pixel Circuit 181C." The voltage supplied to the first node N1 gradually increases from voltage Vnd toward voltage VSIGH (voltage Vng, 3.5 V) and becomes voltage Vng. The voltage supplied to the second node N2 gradually increases from voltage Vnc toward the initialization voltage VINI2 (0 V) and becomes the initialization voltage VINI2 (0 V). As the voltage supplied to the second node N2 approaches 0 V, the potential difference Vgs exceeds the threshold voltage VTH. As a result, the second transistor T2 is turned on, charging of the third node N3 begins, and the voltage supplied to the third node N3 gradually increases. The second transistor T2 is on, and current flows from the drive power line PVDD to the third node N3. However, the potential does not rise to the threshold voltage of the light-emitting element OLED, so the light-emitting element OLED does not emit light.

[0406] At the end of the period PVH, the signals are driven in the same manner as in the configuration described in "4-2-1. First Example of the Method for Driving the Pixel Circuit 181C," and the transistors operate in the same manner as in the configuration described in "2-2-2. Second Example of the Method for Driving the Pixel Circuit 181A." As a result, at the end of the period PVH, the second transistor T2 is turned on, and a drain current Ion flows from the drive power supply line PVDD to the reference voltage line PVSS. Therefore, the voltages of the first node N1 and the third node N3 rise to follow the rise in the voltage of the second node N2. Due to the rise in the voltage of the third node N3, the voltages of the first node N1 and the second node N2 further rise.

[0407] In this way, during the period PVH, the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is held at the third node N3 (the first electrode 692 of the capacitive element CS).

[0408] Furthermore, during the light emission period PEM of the Kth FRAME following the horizontal period HRP of the Kth FRAME, each light emitting element OLED emits light, similar to the configuration described in "2-2-2. Second Example of the Method for Driving the Pixel Circuit 181A." For example, three pixels, including a pixel 180C that emits red light, a pixel 180C that emits blue light, and a pixel 180C that emits green light, emit white light.

[0409] The second example of the method for driving the pixel circuit 181C including the configuration described above has the same effects as "4-2-1. First example of the method for driving the pixel circuit 181C."

[0410] <4-2-3. Third Example of Driving Method of Pixel Circuit 181C> A third example of a method for driving the pixel circuit 181C will be described with reference to Fig. 48. The driving method shown in the third example of the method for driving the pixel circuit 181C includes displaying images of the same color (black) in consecutive frames, similar to the third example of the method for driving the self-luminous display device 10 according to the first embodiment. Configurations that are the same as or similar to those in Figs. 1 to 47 will be described as necessary.

[0411] The configurations of the image data signal SL(m), the first scan signal SC1(n), the third scan signal SC4(n-1), the fourth scan signal SC4(n), and the scan voltage power supply SIR(n) during the light emission period PEM of the K-1st FRAME to the light emission period PEM of the Kth FRAME are the same as those described in "4-2-1. First Example of the Method for Driving the Pixel Circuit 181C." Furthermore, the voltages (potentials) of the first node N1, the second node N2, and the third node N3, and the operation of each transistor during the light emission period PEM of the K-1st FRAME are the same as those described in "2-2-3. Third Example of the Method for Driving the Pixel Circuit 181A." Furthermore, the voltages (potentials) of the first node N1, the second node N2, and the third node N3, and the operation of each transistor from the beginning of the horizontal period HRP of the KthFRAME to the light emission period PEM of the KthFRAME are the same as the configurations and operations described in "4-2-1. First Example of the Method for Driving the Pixel Circuit 181C." The same configurations as those described in "4-2-1. First Example of the Method for Driving the Pixel Circuit 181C" and "2-2-3. Third Example of the Method for Driving the Pixel Circuit 181A" will be explained as necessary. Note that, as for the image data signal SL(m), a data signal VDATA of a voltage VSIGL corresponding to black is supplied during the periods PWR and PVH.

[0412] During the light emission period PEM of the K-1st FRAME, similar to the configuration described in "2-2-3. Third Example of the Method for Driving the Pixel Circuit 181A", the light emitting element OLED does not emit light and the pixel 180C (pixel circuit 181C) turns black.

[0413] During the KthFRAME period PIP following the light-emitting period PEM of the K-1stFRAME, similar to the configuration and operation described in "2-2-3. Third Example of the Method for Driving the Pixel Circuit 181A," the voltage supplied to the first node N1 gradually increases from voltage Vnf toward the precharge voltage VPRC (voltage Vnd, 1.5V) and reaches voltage Vnd. The voltage supplied to the second node N2 gradually decreases from voltage Vnf toward the initialization voltage VINI1 (Vnc, -1.5V). The voltage supplied to the third node N3 gradually decreases from voltage Vne toward the initialization voltage VINI1 (Vnc, -1.5V). The light-emitting element OLED does not emit light.

[0414] As described above, during the period PIP, a precharge voltage (intermediate potential) is supplied to the first node N1, the second node N2 is roughly initialized by the initialization voltage VINI1 (-1.5V), and the third node N3 is initialized by the initialization voltage VINI1 (-1.5V).

[0415] During the period PWR following the period PIP, a data signal VDATA (voltage VSIGL in the third example) is written to the pixel 180C (pixel circuit 181C) in the same manner as in the configuration described in "4-2-1. First Example of the Method for Driving the Pixel Circuit 181C." Also, during the period PVH, the threshold voltage VTH of the second transistor T2 is acquired by an operation in which the potential difference Vgs of the second transistor T2 becomes equal to the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is held at the third node N3 (first electrode 692 of the capacitance element CS).

[0416] Furthermore, during the light emission period PEM of KthFRAME, similar to the configuration described in "4-2-1. First example of driving method for pixel circuit 181C", three pixels are used to produce black, using pixel 180C that emits red light, pixel 180C that emits blue light, and pixel 180C that emits green light.

[0417] The third example of the method for driving the pixel circuit 181C including the configuration described above has the same effects as "4-2-1. First example of the method for driving the pixel circuit 181C."

[0418] <4-2-4. Fourth Example of Driving Method of Pixel Circuit 181C> A fourth example of a method for driving the pixel circuit 181C will be described with reference to Fig. 49. The fourth example of a method for driving the pixel circuit 181C includes displaying images of different colors in successive frames, similar to the fourth example of the method for driving the self-luminous display device according to the first embodiment. Configurations that are the same as or similar to those in Figs. 1 to 48 will be described as necessary.

[0419] The configurations of the image data signal SL(m), the first scan signal SC1(n), the third scan signal SC4(n-1), the fourth scan signal SC4(n), and the scan voltage power supply SIR(n) during the light emission period PEM of the K-1st FRAME to the light emission period PEM of the Kth FRAME are the same as those described in "4-2-1. First Example of the Method for Driving the Pixel Circuit 181C." Furthermore, the voltages (potentials) of the first node N1, the second node N2, and the third node N3, and the operation of each transistor during the light emission period PEM of the K-1st FRAME to the period PIP are the same as those described in "4-2-3. Third Example of the Method for Driving the Pixel Circuit 181C." Furthermore, the voltages (potentials) of the first node N1, the second node N2, and the third node N3, and the operation of each transistor from the beginning of the horizontal period HRP of the Kth FRAME to the light emission period PEM of the Kth FRAME are the same as the configurations and operations described in "4-2-2. Second Example of the Method for Driving the Pixel Circuit 181C." Configurations similar to those described in "4-2-1. First Example of the Method for Driving the Pixel Circuit 181C," "4-2-2. Second Example of the Method for Driving the Pixel Circuit 181C," and "4-2-3. Third Example of the Method for Driving the Pixel Circuit 181C" will be described as necessary. Note that, as the image data signal SL(m), a data signal VDATA of a voltage VSIGH corresponding to white is supplied during the periods PWR and PVH.

[0420] In the light emission period PEM of the (K-1st) frame, the pixel 180 (pixel circuit 181) turns black, as in "4-2-3. Third example of the method for driving the pixel circuit 181C."

[0421] During the period PIP, a precharge voltage (intermediate potential) is supplied to the first node N1, the second node N2 is roughly initialized by the initialization voltage VINI1 (-1.5V), and the third node N3 is initialized by the initialization voltage VINI1 (-1.5V).

[0422] During the period PWR, as in "4-2-2. Second Example of the Method for Driving the Pixel Circuit 181C," a data signal VDATA (voltage VSIGH in the fourth example) is written to the pixel 180C (pixel circuit 181C). Also, during the period PVH, the threshold voltage VTH of the second transistor T2 is acquired by an operation in which the potential difference Vgs of the second transistor T2 becomes equal to the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is held at the third node N3 (first electrode 692 of the capacitance element CS).

[0423] Furthermore, during the light emission period PEM of KthFRAME, as in "4-2-2. Second example of driving method for pixel circuit 181C", white light is emitted by three pixels using pixel 180C that emits red light, pixel 180C that emits blue light, and pixel 180C that emits green light.

[0424] The fourth example of the method for driving the pixel circuit 181C including the configuration described above has the same effects as "4-2-1. First example of the method for driving the pixel circuit 181C."

[0425] <4-3. Setting values ​​of initialization voltages VINI1 and VINI2> The set values ​​of the initialization voltages VINI1 and VINI2 will be described with reference to Fig. 50. Fig. 50 is a diagram for explaining the set values ​​of the initialization voltages VINI1 and VINI2 of the scan voltage power supply line SVIR to which the scan voltage power supply SIR(n) is supplied. Configurations that are the same as or similar to those in Figs. 1 to 49 will be described as necessary.

[0426] For example, as shown in FIG. 50, between the period PWR and the period PVH, in accordance with the timing of the second scan signal SC2(n), the scan voltage power supply SIR(n) changes from a state in which the initialization voltage VINI1 is supplied to a state in which the initialization voltage VINI2 is supplied.

[0427] During the period PWR, in the pixel circuit 181C, the scan voltage power supply SIR(n) (initialization voltage VINI2) is supplied from the scan voltage power supply line SVIR to the second node N2 and the third node N3, and the second node N2 and the third node N3 are initialized. The pixel 180C including the pixel circuit 181C does not emit light during the period PWR. The condition for the light-emitting element OLED not to emit light is that the initialization voltage VINI1 supplied to the third node N3 is smaller than the threshold voltage VTHEL of the light-emitting element OLED. In other words, the initialization voltage VINI1<threshold voltage VTHEL.

[0428] Furthermore, during the period PVH, the pixel circuit 181C corrects the threshold voltage VTH and holds a charge equivalent to the threshold voltage VTH. The pixel 180C including the pixel circuit 181C does not emit light during the period PVH. The condition for the light-emitting element OLED not to emit light is that the voltage Vne supplied to the third node N3 is smaller than the threshold voltage VTHEL of the light-emitting element OLED. In other words, the voltage Vne<the threshold voltage VTHEL.

[0429] Furthermore, for example, when the pixel circuit 181C emits light based on the voltage VSIGH corresponding to white, the second node N2 is supplied with the initialization voltage VINI2, and the third node N3 is supplied with the voltage Vne. The potential difference Vgs is the difference between the voltage supplied to the second node N2 and the voltage supplied to the third node N3, and the potential difference Vgs = initialization voltage VINI2 - voltage Vne. Furthermore, since the potential difference Vgs is equal to the threshold voltage VTH, the initialization voltage VINI2 - voltage Vne = threshold voltage VTH.

[0430] The condition for the initialization voltage VINI2 calculated using the above formula is initialization voltage VINI2<threshold voltage VTHEL+threshold voltage VTH, as shown in Fig. 50. Also, the condition for the initialization voltage VINI1 is initialization voltage VINI1<threshold voltage VTHEL.

[0431] 5. Fifth Embodiment An overview of the self-luminous display device according to the fifth embodiment will be described with reference to Figs. 1, 6, and 51 to 57. Fig. 51 is a schematic diagram showing input signals to pixel 180D (pixel circuit 181D) according to the fifth embodiment of the present invention. Fig. 52 is a circuit diagram showing the configuration of pixel circuit 181D. Figs. 53 to 56 are timing charts for the self-luminous display device according to the fifth embodiment of the present invention, and Fig. 57 is a diagram for explaining the setting of input signals according to the fifth embodiment of the present invention.

[0432] The self-luminous display device according to the fifth embodiment includes pixel 180D, pixel 180D, and pixel circuit 181D, in addition to pixel 180C and pixel circuit 181C of the self-luminous display device according to the fourth embodiment. The configurations of pixel 180D and pixel circuit 181D are different from those of pixel 180C and pixel circuit 181C of the self-luminous display device according to the third embodiment. The configurations and functions of pixel 180D and pixel circuit 181D are such that the scan voltage power supply SIR(n) of pixel 180C and pixel circuit 181C is replaced with a scan voltage power supply SIRB(n) with inverted polarity. Furthermore, pixel circuit 181D has a configuration and function in which the scan voltage power supply SIR(n) of pixel circuit 181C, which is an n-channel field-effect transistor, is replaced with a p-channel field-effect transistor. In the pixel circuit 181D, the second electrode 684 of the light-emitting element OLED is electrically connected to the reference voltage line PVSS, and the first electrode 682 of the light-emitting element OLED is electrically connected to the first electrode 624 of the second transistor T2, the third node N3, the second electrode 656 of the fifth transistor T5, and the first electrode 692 of the capacitive element CS. Other configurations and functions are the same as those of the self-luminous display device according to the fourth embodiment. Therefore, in describing the configuration and functions of the fifth embodiment, configurations and functions similar to those of the self-luminous display devices 10 according to the first embodiment to the self-luminous display devices according to the fourth embodiment will be described as necessary. Furthermore, configurations that are the same as or similar to those in FIGS. 1 to 50 will be described as necessary.

[0433] <5-1.Configuration of pixel 180D> An overview of the pixel 180D and pixel circuit 181D will be described with reference to FIGS.

[0434] As described above, pixel circuit 181D has a configuration in which scan voltage power supply SIR(n) supplied to pixel circuit 181C is replaced with scan voltage power supply SIRB(n). Similarly to scan voltage power supply SIRB(n), the polarities of signals other than scan voltage power supply SIRB(n) supplied to pixel circuit 181D are also signals obtained by inverting the polarities of signals other than scan voltage power supply SIR(n) supplied to pixel circuit 181C.

[0435] 51, the pixel circuit 181D is connected to a scan signal line SVIRB to which a scan voltage power supply SIRB(n) is supplied. Also, as shown in FIG. 52, the pixel circuit 181D includes a second transistor T2, which is a p-channel field-effect transistor. Also, in the pixel circuit 181D, a second electrode 684 of the light-emitting element OLED is electrically connected to a reference voltage line PVSS, and a first electrode 682 of the light-emitting element OLED is electrically connected to a first electrode 624 of the second transistor T2, a third node N3, a first electrode 654 of the fifth transistor T5, and a first electrode 692 of the capacitor CS. The first electrode 682 of the light-emitting element OLED is, for example, a cathode electrode, and the second electrode 684 of the light-emitting element OLED is, for example, an anode electrode.

[0436] The fourth transistor T4 has the function of connecting the second node N2 and the scan voltage power supply line SVIRB to supply the scan voltage power supply SIRB(n) (initialization voltage VINI1 or VINI2) to the second node N2, thereby initializing the second node N2.

[0437] The fifth transistor T5 has the function of connecting the third node N3 and the scan voltage power supply line SVIRB to supply the scan voltage power supply SIRB(n) (initialization voltage VINI2) to the third node N3, thereby initializing the third node N3.

[0438] The configuration and functions of the pixel circuit 181D other than those described in "5-1. Configuration of the pixel 180D" are the same as those of the pixel circuit 181C.

[0439] <5-2. Driving method of pixel circuit 181D> A method for driving a self-luminous display device according to the fifth embodiment will be described with reference to Figures 53 to 56. Configurations that are the same as or similar to those in Figures 1 to 52 will be described as necessary. As in the first and second embodiments, the horizontal axis of the timing chart represents time.

[0440] For example, the method for driving a self-luminous display device according to the fifth embodiment has a configuration and functions in which the operation related to the scan voltage power supply SIR(n) in the method for driving a self-luminous display device according to the fourth embodiment is replaced with an operation related to a scan voltage power supply SIRB(n) in which the polarity of the scan voltage power supply SIR(n) is inverted. The configuration and functions other than the operation related to the scan voltage power supply SIRB(n) are the same as those of the method for driving a self-luminous display device according to the fourth embodiment.

[0441] Furthermore, for example, the driving method for the self-luminous display device according to the fifth embodiment is a driving method in which the polarity of each signal in the driving method for the self-luminous display device (pixel circuit 181C) according to the fourth embodiment is inverted, and the polarity of the voltage (potential) supplied to each node in the driving method for the self-luminous display device according to the fourth embodiment (pixel circuit 181C) is inverted.

[0442] The method for driving a self-luminous display device according to the fifth embodiment differs from the method for driving a self-luminous display device according to the first embodiment shown in FIG. 6 in that it includes executing a period PVH after a period PWR, and includes periods similar to the respective periods of the method for driving a self-luminous display device according to the fourth embodiment.

[0443] In one horizontal period (horizontal period HRP) in the driving method for the self-luminous display device according to the fifth embodiment, the pixel 180D (pixel circuit 181D) receives the first scan signal SC1(n), the third scan signal SC4(n-1), the fourth scan signal SC4(n), the image data signal SL(m) including the data signal VDATA, and the scan voltage power supply SIRB(n). For example, the pixel 180D (pixel circuit 181D) is selected according to the timing of the first scan signal SC1(n), the third scan signal SC4(n-1), and the fourth scan signal SC4(n). The image data signal SL(m) and the scan voltage power supply SIRB(n) are input to the selected pixel 180D (pixel circuit 181D) according to the timing of each signal. A similar operation is performed for all pixels 180D (pixel circuits 181D), and based on the image data signals SL(m) input to all pixels 180D (pixel circuits 181D), an image of the frame corresponding to one frame is displayed in the display area 22 of the self-luminous display device 10.

[0444] For example, the voltages (potentials) supplied to the signals and nodes in each frame in the timing charts shown in FIGS.

[0445] [Table 9]

[0446] [Table 10]

[0447] As described above, the polarity of the signal supplied to pixel circuit 181D is the inverse of the polarity of the signal supplied to pixel circuit 181C. For example, as shown in Table 9, Table 10, and FIGS. 53 to 56, the voltage VSIGL of the data signal VDATA is −3.5V, and the pixel 180 to which the voltage VSIGL is supplied emits light. For example, one pixel emits red, one pixel emits green, one pixel emits blue, and three pixels emit white. Also, for example, the voltage VSIGH of the data signal VDATA is 0.5V, and the pixel 180 to which the voltage VSIGH is supplied does not emit light and is black. Also, for example, the voltage VL(LO) is −10V, the voltage VNN is 5V, the voltage VMN is −5V, the initialization voltage VINI1 is 3.5V, the initialization voltage VINI2 is 0V, and the pre-charge voltage VPRC is −1.5V. For example, the voltage VH(HI), voltage VL(LO), voltage VNN, voltage VMN, initialization voltage VINI1, and initialization voltage VINI2 supplied to pixel circuit 181D correspond to voltages (potentials) with the polarity reversed from the voltage VL(LO), voltage VH(HI), voltage VN, voltage VM, initialization voltage VINI2, and initialization voltage VINI1 supplied to pixel circuit 181C.

[0448] <5-2-1. First Example of Method for Driving Pixel Circuit 181D> A first example of a method for driving the pixel circuit 181D will be described with reference to Figures 52 and 53, including the conductive and non-conductive states of each transistor during the light emission period PEM of the K-1st FRAME in "4-2-1. First Example of a Method for Driving the Pixel Circuit 181C." The first example of a method for driving the pixel circuit 181D involves the pixel 180D displaying a white image based on the voltage VSIGL (-3.5V) of the data signal VDATA in the frame (K-1st FRAME) immediately before the current frame (Kth FRAME), and then the pixel 180D displaying a black image based on the voltage VSIGH (0.5V) of the data signal VDATA in the Kth FRAME. In other words, the first example of a method for driving the self-emissive display device 10 according to the fifth embodiment involves displaying images of different colors in consecutive frames.

[0449] As described above, the configurations and functions of the signals from the light emitting period PEM to the light emitting period PEM of the K-1st FRAME are the same as those of the signals obtained by inverting the polarity of the voltage (potential) of each signal in the method for driving a self-luminous display device according to the fourth embodiment. Also, for example, the voltages (potentials) of the first node N1, the second node N2, and the third node N3 from the light emitting period PEM to the light emitting period PEM of the K-1st FRAME are voltages (potentials) obtained by inverting the polarity of the voltages (potentials) of each node in the method for driving a self-luminous display device according to the fourth embodiment.

[0450] For example, the voltages Vnan, Vnbn, Vncn, Vndn, Vnen, Vnfn, and Vngn are voltages (potentials) with the polarities of the voltages Vna, Vnb, Vnc, Vnd, Vne, and Vnf reversed. Referring to the voltages (potentials) in the driving method according to the fourth embodiment, the voltage Vnan is −7V, Vnbn is −2.5V, the voltage Vncn is 1.5V, the voltage Vndn is −1.5V, the voltage Vnen is 1V, the voltage Vnfn is −3.5V, and the voltage Vngn is 2.5V.

[0451] During the light emission period PEM of the K-1st FRAME, the pixel 180D emits light in accordance with the potential difference Vgs (voltage V(N2) - voltage V(N3) = voltage Vnan - voltage Vnbn) of the second transistor T2. The potential difference Vgs is -4.5 V, and the pixel 180B emits red light, and the three pixels, the pixel 180 that emits red light, the pixel 180 that emits blue light, and the pixel 180 that emits green light, emit white light.

[0452] For example, during the initial period of the horizontal period HRP of the Kth FRAME following the light emission period PEM of the K-1st FRAME, the voltage supplied to the first node N1 gradually increases from voltage Vnan toward the precharge voltage VPRC (voltage Vndn), and the voltage supplied to the second node N2 gradually increases from voltage Vnan toward the initialization voltage VINI1 (voltage Vncn).

[0453] For example, during the period PIP, the voltage supplied to the first node N1 gradually increases from voltage Vnan toward the precharge voltage VPRC and becomes voltage Vndn. The voltage supplied to the second node N2 gradually increases from voltage Vnan toward the initialization voltage VINI1 (voltage Vncn, 1.5V). Although the voltage supplied to the second node N2 has not yet increased to voltage Vncn, Vgs is a voltage near the threshold voltage VTHP (-1V), and the potential difference Vds is a voltage near -9.5V (-8V - (-1.5V)). The second transistor T2 is in an off state, and the light-emitting element OLED does not emit light.

[0454] In this way, during the period PIP, the first node N1 is supplied with a precharge voltage (intermediate potential), the second node N2 is roughly initialized by the initialization voltage VINI1 (1.5V), and the third node N3 is initialized by the initialization voltage VINI1 (1.5V).

[0455] In the initial period of the horizontal period HRP of the KthFRAME following the period PIP, the data signal VDATA of the voltage VSIGH is supplied as the image data signal SL(m). The voltage supplied to the first node N1 maintains the voltage Vndn, the voltage supplied to the second node N2 rises to near the voltage Vncn, and the voltage supplied to the third node N3 maintains the voltage Vncn. Also, as in the period PIP, the light-emitting element OLED does not emit light.

[0456] During the period PWR following the beginning of the horizontal period HRP, the image data signal SL(m) maintains a state in which the data signal VDATA of voltage VSIGH is supplied. The voltage supplied to the first node N1 gradually rises from voltage Vndn toward voltage VSIGH (voltage Vnfn, 0.5V) and becomes voltage VSIGH (voltage Vnfn, 0.5V), the voltage supplied to the second node N2 becomes voltage Vncn, and the voltage supplied to the third node N3 maintains voltage Vnc. Also, as in the period PIP, the light-emitting element OLED does not emit light.

[0457] As described above, during the period PWR, the data signal VDATA (here, the voltage VSIGH) is written to the pixel 180D (pixel circuit 181D). Also, the second node N2 and the third node N3 are initialized by the initialization voltage VINI1 (1.5 V).

[0458] During the period PVH following the period PWR, the image data signal SL(m) maintains the state in which the data signal VDATA of the voltage VSIGH is supplied, and the voltage supplied to the first node N1 maintains the voltage Vnfn.

[0459] Immediately after the start of the period PVH, the potential difference Vgs is 0 V, the potential difference Vds is −9.5 V, and the second transistor T2 is in the OFF state. The fifth transistor T5 is also in the OFF state. Meanwhile, because the fourth transistor T4 is in the ON state, the voltage supplied to the third node N3 gradually drops from the voltage Vncn toward the initialization voltage VINI2 (0 V). As the voltage supplied to the second node N2 approaches 0 V, the potential difference Vgs exceeds the threshold voltage VTHP. As a result, the second transistor T2 is turned ON, discharging of the third node N3 begins, and the voltage of the third node N3 gradually drops.

[0460] When the potential difference Vgs between the voltage supplied to the second node N2 and the voltage supplied to the third node N3 becomes the threshold voltage VTHP, the voltage supplied to the second node N2 and the voltage supplied to the third node N3 maintain their respective voltages at that time. For example, as shown in Figure 53, the voltage supplied to the second node N2 is the initialization voltage VINI2 (0V), and the voltage supplied to the third node N3 is the voltage Vnen (1V). Since the second transistor T2 is in the off state and no current flows from the driving power supply line PVDD to the reference voltage line PVSS, the light-emitting element OLED does not emit light.

[0461] When the potential difference Vgs reaches the threshold voltage VTHP, the second transistor T2 changes from the on state to the off state, and the drain current Ion stops flowing. At this time, the voltage supplied to the third node N3 drops to the voltage Vnen (1 V), and the potential difference Vgs is the same as the threshold voltage VTHP (-1 V). Since the second transistor T2 is in the off state and no current flows from the driving power line PVDD to the reference voltage line PVSS, the light-emitting element OLED does not emit light.

[0462] In this way, during the period PVH, the threshold voltage VTHP of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTHP, and a charge equivalent to the threshold voltage VTHP is held at the third node N3 (the first electrode 692 of the capacitance element CS).

[0463] During the light emission period PEM of the Kth FRAME following the horizontal period HRP of the Kth FRAME, no data is selected using the selection signal, and the data signal VDATA is switched to the data signal VDATA of the (n+1)th row after the nth row. For example, pixel 180D (pixel circuit 181D) that emits red, pixel 180D that emits blue, and pixel 180D that emits green do not emit light, so the three pixels using pixel 180D that emits red, pixel 180D that emits blue, and pixel 180D that emits green are black.

[0464] The first example of the method for driving the pixel circuit 181D including the configuration described above has the same effects as "4-2-1. First example of the method for driving the pixel circuit 181C."

[0465] <5-2-2. Second Example of Method for Driving Pixel Circuit 181D> A first example of a method for driving the pixel circuit 181D will be described with reference to FIGS. 52 and 54, including the conductive and non-conductive states of each transistor during the light emission period PEM of the K-1st FRAME in "4-2-2. Second Example of the Method for Driving the Pixel Circuit 181C." The driving method shown in the second example of the pixel circuit 181D involves the pixel 180D displaying a white image based on the voltage VSIGL (-3.5V) of the data signal VDATA in the frame (K-1st FRAME) immediately before the current frame (Kth FRAME), and then the pixel 180D also displaying a white image based on the voltage VSIGL (-3.5V) of the data signal VDATA in the Kth FRAME. In other words, the second example of the method for driving the self-luminous display device according to the fifth embodiment involves displaying images of the same color (white) in consecutive frames. Configurations that are the same as or similar to those in FIGS. 1 to 53 will be described as necessary.

[0466] The configuration and function of each signal from the light emitting period PEM to the light emitting period PEM of the K-1st FRAME are the same as those described in "5-2-1. First example of the method for driving the pixel circuit 181D".

[0467] During the light emission period PEM of K-1stFRAME, the configuration is the same as that described in "5-2-1. First example of driving method for pixel circuit 181D", and pixel 180B emits red light, and three pixels, using pixel 180 that emits red light, pixel 180 that emits blue light, and pixel 180 that emits green light, emit white light.

[0468] During the initial period of the horizontal period HRP of the KthFRAME following the light emission period PEM of the K-1stFRAME, similar to the configuration described in "5-2-1. First example of the driving method of the pixel circuit 181D", the voltage supplied to the first node N1 gradually increases from voltage Vnan toward the precharge voltage VPRC (voltage Vndn), and the voltage supplied to the second node N2 gradually increases from voltage Vnan toward the initialization voltage VINI1 (voltage Vncn).

[0469] During the period PIP, the volta...

Claims

1. a first transistor whose switching is controlled using a first control signal and electrically connected between an image data signal line to which a data voltage is supplied and a first node; a third transistor whose switching is controlled using a second control signal different from the first control signal, the third transistor being electrically connected between the first node and a second node; a second transistor having a gate electrode electrically connected to the second node, the second transistor being electrically connected between a power supply line to which a constant voltage is supplied and a third node; a fourth transistor whose switching is controlled using the second control signal and electrically connected between a reference voltage power supply line to which a reference voltage is supplied and the second node; a fifth transistor whose switching is controlled using a third control signal different from the first control signal and the second control signal, and which is electrically connected between an initialization voltage power supply line to which an initialization voltage is supplied and the third node; a sixth transistor whose switching is controlled using a fourth control signal different from the first control signal and the second control signal, and which is electrically connected between a precharge voltage power supply line to which a precharge voltage is supplied and the first node; a light-emitting element electrically connected to the third node; a capacitance element electrically connected between the first node and the third node; Including, Display device.

2. a fifth control signal line; the fifth control signal line serves as both the reference voltage power supply line and the initialization voltage power supply line; The display device according to claim 1 .

3. a sixth control signal line; the sixth control signal line serves as a third control signal line to which the third control signal is supplied and a fourth control signal line to which the fourth control signal is supplied; The display device according to claim 1 .

4. the third control signal is a shifted version of the fourth control signal; The display device according to claim 1 .

5. a control circuit that outputs the first control signal, the second control signal, the third control signal, and a fourth control signal; The control circuit a high-level voltage is supplied to the fourth control signal to turn on the sixth transistor, and after a period in which the sixth transistor supplies the precharge voltage to the first node, a high-level voltage is supplied to the first control signal to turn on the first transistor, and the first transistor is controlled to supply the data voltage to the first node; The display device according to claim 1 .

6. the first transistor, the second transistor, the fourth transistor, the fifth transistor, and the sixth transistor are n-channel field effect transistors, the third transistor is a p-channel field effect transistor; The display device according to claim 1 .

7. the first transistor, the fourth transistor, the fifth transistor, and the the sixth transistor is an n-channel field effect transistor, the second transistor and the third transistor are p-channel field effect transistors; The display device according to claim 1 .

8. a channel length of the second transistor is longer than a channel length of the first transistor, a channel length of the third transistor, a channel length of the fourth transistor, a channel length of the fifth transistor, and a channel length of the sixth transistor; The display device according to claim 1 .

9. a channel region of each of the second transistor, the third transistor, and the fifth transistor includes crystalline silicon; a channel region of each of the first transistor, the fourth transistor, and the sixth transistor includes an oxide semiconductor; the crystalline silicon of the third transistor overlaps with the oxide semiconductor of the fourth transistor in a plan view. The display device according to claim 1 .

10. a first conductive layer and a second conductive layer different from the first conductive layer; the reference voltage power supply line, the initialization voltage power supply line, and the precharge voltage power supply line each include the first conductive layer and the second conductive layer which are different from each other; In a plan view, the first conductive layer and the second conductive layer included in the reference voltage power supply line overlap each other, the first conductive layer and the second conductive layer included in the initialization voltage power supply line overlap each other, and the first conductive layer and the second conductive layer included in the precharge voltage power supply line overlap each other. The display device according to claim 1 .

11. In a plan view, the gate electrode overlaps with the capacitance element. The display device according to claim 1 .

12. a first transistor whose switching is controlled using a first control signal and electrically connected between an image data signal line to which a data voltage is supplied and a first node; a third transistor whose switching is controlled using the first control signal and electrically connected between the first node and a second node; a second transistor having a gate electrode electrically connected to the second node, the second transistor being electrically connected between a power supply line to which a constant voltage is supplied and a third node; a fourth transistor electrically connected between the second node and a third control signal line to which a third control signal is supplied, the fourth transistor being controlled to switch using a second control signal different from the first control signal and including a precharge voltage, a first initialization voltage different from the precharge voltage, and a second initialization voltage different from the precharge voltage and the first initialization voltage; a fifth transistor whose switching is controlled using a fourth control signal different from the first control signal, the second control signal, and the third control signal, and which is electrically connected between the third control signal line and the third node; a light-emitting element electrically connected to the third node; a capacitance element electrically connected between the first node and the third node; Including, Display device.

13. The first control signal, the second control signal, the third control signal, and the fourth control signal a control circuit for outputting the The control circuit a low-level voltage is supplied to the first control signal to turn off the first transistor, and the third transistor is turned on; a high-level voltage is supplied to the second control signal to turn on the fourth transistor; the fourth transistor supplies the precharge voltage to the second node; and after a period in which the third transistor supplies the precharge voltage to the first node, supplying a high-level voltage to the first control signal to turn on the first transistor and turn off the third transistor, thereby controlling the first transistor to supply the data voltage to the first node; The display device according to claim 12.

14. the first transistor, the second transistor, the fourth transistor, and the fifth transistor are n-channel field effect transistors, the third transistor is a p-channel field effect transistor; The display device according to claim 12.

15. a channel region of each of the second transistor, the third transistor, and the fifth transistor includes crystalline silicon; a channel region of each of the first transistor and the fourth transistor includes an oxide semiconductor; The display device according to claim 12.

16. a first transistor whose switching is controlled using a first control signal and electrically connected between an image data signal line to which a data voltage is supplied and a first node; a third transistor whose switching is controlled using a second control signal different from the first control signal, the third transistor being electrically connected between the first node and a third node; a second transistor having a gate electrode electrically connected to a second node and electrically connected between the third node and a fourth node; a fourth transistor whose switching is controlled by the second control signal and which is electrically connected between the third node and a third control signal line to which a third control signal including a first initialization voltage and a second initialization voltage different from the first initialization voltage is supplied; a fifth transistor whose switching is controlled using a fourth control signal different from the first control signal, the second control signal, and the third control signal, and which is electrically connected between the third control signal line and the fourth node; a sixth transistor whose switching is controlled using the second control signal and electrically connected between the second node and the fourth node; a seventh transistor whose switching is controlled using the second control signal and electrically connected between a voltage line to which a constant voltage is supplied and the fourth node; an eighth transistor whose switching is controlled using a fifth control signal different from the first control signal, the second control signal, the third control signal, and the fourth control signal, and which is electrically connected between a precharge voltage power supply line to which a precharge voltage is supplied and the first node; a light-emitting element electrically connected to the third node; a capacitance element electrically connected between the first node and the second node; Including, Display device.

17. a control circuit that outputs the first control signal, the second control signal, the third control signal, the fourth control signal, and the fifth control signal; The control circuit After a period in which a low-level voltage is supplied to the first control signal, the first transistor is turned off, a high-level voltage is supplied to the second control signal, the third transistor is turned off, a high-level voltage is supplied to the fifth control signal, the eighth transistor is turned on, and the precharge voltage is supplied to the first node, supplying a high-level voltage to the first control signal to turn on the first transistor, supplying a high-level voltage to the second control signal to keep the third transistor in an off state, supplying a low-level voltage to the fifth control signal to turn off the eighth transistor, and controlling the first transistor to supply the data voltage to the first node; The display device according to claim 16.

18. the first transistor, the second transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the eighth transistor are n-channel field effect transistors, the third transistor and the seventh transistor are p-channel field effect transistors; The display device according to claim 16.

19. a channel region of each of the second transistor, the third transistor, the fifth transistor, and the seventh transistor includes crystalline silicon; channel regions of the first transistor, the fourth transistor, the sixth transistor, and the eighth transistor contain an oxide semiconductor; The display device according to claim 16.

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