Semiconductor power device with short circuit protection and process for manufacturing semiconductor power device
Patent Information
- Application Number
- JP2022167881
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2021-10-29
- Filing Date
- 2022-10-19
- Publication Date
- 2025-10-10
AI Technical Summary
Conventional semiconductor power devices face challenges with short circuit strength due to high current densities, leading to irreversible damage and reduced performance, especially as device dimensions shrink, and existing solutions to mitigate this issue add significant cost and footprint.
A semiconductor power device design featuring a silicon carbide body with specific epitaxial layers and floating pockets that reduce electric field intensity and current density, enhancing short circuit withstand time without increasing device size or cost.
The design effectively increases short circuit withstand time and maintains breakdown voltage, reducing the risk of thermal runaway while maintaining device performance and efficiency.
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Abstract
Description
[Technical Field]
[0001] The present invention relates to a semiconductor power device equipped with short-circuit protection, and a process for manufacturing a semiconductor power device. [Background technology]
[0002] In semiconductor power devices, the tendency to reduce dimensions to achieve high performance is known to expose various hazardous conditions, primarily involving certain parameters. A significant problem for power devices based on special materials such as silicon carbide, as well as conventional silicon power devices, concerns short-circuit strength, often defined by short-circuit withstand time. Current density within the device can reach extremely high values, particularly around structures such as junctions between the body well and the drift region. Excessively high current density can cause intense localized heating and even irreversible damage. For example, heating can trigger uncontrolled electron-hole pair generation (thermal runaway), which can result in a short-circuit condition between the drain and source regions and may not be stopped even by switching off the device. Short-circuit withstand time represents how long the device can function under given current conditions before a thermal short circuit occurs. The longer the short-circuit withstand time, the longer the device can function without being damaged.
[0003] Since the problem is primarily related to current density and local power dissipation, it is clear that reducing the size of the device can have a negative impact unless performance requirements are reduced. While the reduction in size is possible because silicon carbide has a higher thermal conductivity than other semiconductor materials, allowing for more efficient heat dissipation, even such silicon carbide devices encounter limitations due to short-circuit triggers.
[0004] Various circuit solutions have been proposed to prevent or contain potentially dangerous conditions. However, regardless of their effectiveness, all of these solutions significantly increase costs and footprint.
[0005] Simply the on-state drain versus source resistor (usually R) DSON Structural solutions aimed at reducing (as shown) have limited benefits and, in any case, are not sufficient to increase the short-circuit withstand time in a sufficiently manner.
[0006] As a result, the general tendency to reduce the dimensions of power units to achieve higher levels of performance is hindered by problems arising from excessively high current densities. [Overview of the Initiative] [Problems that the invention aims to solve]
[0007] The object of the present invention is to provide a semiconductor power device capable of resolving or at least mitigating the above-mentioned problems, and a process, i.e., a method, for manufacturing such a semiconductor power device. [Means for solving the problem]
[0008] According to the present invention, a semiconductor power device and a method for manufacturing a semiconductor power device are provided, as defined in claims 1 and 14, respectively.
[0009] To better understand the present invention, several embodiments of the invention are described below as purely non-limiting examples with reference to the accompanying drawings. [Brief explanation of the drawing]
[0010] [Figure 1] Cross-sectional view of a semiconductor power device based on one embodiment of the present invention. [Figure 1A] Electrical equivalent circuit diagram of the power device shown in Figure 1. [Figure 2]Graph showing the electric field strength distribution in a known power device. [Figure 3] Graph showing the electric field strength distribution in the power device of FIG. 1. [Figure 4] Graph showing the short - circuit withstand time in a known power device and the power device of FIG. 1. [Figure 5] Graph showing the potential distribution in a known power device. [Figure 6] Graph showing the potential distribution in the power device of FIG. 1. [Figure 7] Cross - sectional view of a semiconductor power device based on another embodiment of the present invention. [Figure 8] Cross - sectional view of a semiconductor power device based on a further embodiment of the present invention. [Figure 9] Cross - sectional view of a semiconductor wafer at a certain step in the process of manufacturing a semiconductor power device based on one embodiment of the present invention. [Figure 10] Cross - sectional view of a semiconductor wafer at a certain step in the process of manufacturing a semiconductor power device based on one embodiment of the present invention. [Figure 11] Cross - sectional view of a semiconductor wafer at a certain step in the process of manufacturing a semiconductor power device based on one embodiment of the present invention. [Figure 12] Cross - sectional view of a semiconductor wafer at a certain step in the process of manufacturing a semiconductor power device based on one embodiment of the present invention. [Figure 13] Cross - sectional view of a semiconductor wafer at a certain step in the process of manufacturing a semiconductor power device based on one embodiment of the present invention.
Modes for Carrying Out the Invention
[0011] Referring to FIGS. 1 and 1A, a semiconductor power device according to one embodiment of the present invention is generally indicated by reference numeral 1, which has a drain terminal 1a, a source terminal 1b, a gate terminal 1c, and a semiconductor body 2 made of silicon carbide. The semiconductor body 2 has a substrate 3, a first epitaxial layer 4 formed on the substrate 3 and having a first thickness T1, and a second epitaxial layer 5 formed on the first epitaxial layer 4 and having a second thickness T2 that is even smaller than the first thickness T1. For example, the first thickness T1 is in the range of 10 - 30 μm, and the second thickness T2 is in the range of 0.8 - 2 μm. Both the first epitaxial layer 4 and the second epitaxial layer 5 have a first conductivity type, for example, N-type. The first epitaxial layer 4 has a first doping level N1, which is much lower than the second doping level N2 of the second epitaxial layer. For example, the first doping level N1 is about 10 16 atoms / cm 3 while the second doping level N2 is about 10 17 atoms / cm 3 . In one embodiment, the semiconductor body 2 further has an enrichment layer 6, which has a third thickness T3 (e.g., 0.1 μm) that is much smaller than the first thickness T1 and the second thickness T2, a first conductivity type (N), and a third doping level N3 that is much higher than the first doping level N1 and the second doping level N2. The enrichment layer 6 can be either a further epitaxial layer or obtained by implantation. The substrate 3 is of N+ type and has a doping level of about 10 18 atoms / cm 3 .
[0012] Here, a body well 7 having a second conductivity type, which is P-type, is formed in the second epitaxial layer 5 and houses respective source regions 8 having a first conductivity type, particularly N+ type. The second epitaxial layer 5 defines a current spread layer, which extends to a greater depth from the first surface 2a of the semiconductor body 2 compared to the body well 7, and the body well 7 is embedded within the current spread layer. In other words, the second thickness T2 of the second epitaxial layer 5 corresponding to the depth of the current spread layer is greater than the depth of the body well 7 from the first surface 2a.
[0013] The body wells 7 are separated from each other by a body distance LB of less than 1 μm, for example 0.6 μm. The body wells 7 and the portions of the second epitaxial layer 5 therebetween form parasitic JFET regions. A gate dielectric layer 10 extends over the first surface 2a of the semiconductor body 2 across the second epitaxial layer 5 (or, if present, the enrichment layer 6) between the source regions 8, and a gate region 12 is provided thereon. A source contact 13 extends across the source regions 8 and the gate region 12. An intermetallic dielectric layer 15 insulates the gate region 12 from the source contact 13. A drain contact 17 is formed on the second surface 2b of the semiconductor body 2 opposite to the first surface 2a.
[0014] At the interface with the epitaxial layer present on the upper side, i.e., the second epitaxial layer 5, the first epitaxial layer 4 has 10 18 atoms / cm 3It houses a floating protective pocket 20 having a doping level of a certain degree and a second conductivity type, for example, type P+. Furthermore, the shape and arrangement of the floating pocket 20 are defined relative to the structure within the semiconductor body 2 such that, for drain-to-source voltage VDS values at least higher than the threshold voltage, the maximum electric field strength around the floating pocket 20 is greater than the maximum electric field strength around the body well 7. The threshold voltage is less than the maximum nominal voltage, which is equal to, for example, 25%, 50%, or 65% of the maximum nominal voltage. The floating pocket 20 is located below the corresponding body well 7 and is separated from each other by a protective distance LP that is greater than the body distance LB, for example, the difference between the protective distance LP and the body distance LB is between 0.5 μm and 1.5 μm. The protective-to-body distance LPB between the floating pocket 20 and the corresponding body well 7 in a direction perpendicular to the surfaces 2a and 2b of the semiconductor body 2 is less than 0.5 μm. In fact, the depth of the body well 7 from the first surface 2a of the semiconductor body 2 is at most 0.5 μm smaller than the second thickness T2 of the second epitaxial layer 5.
[0015] Power unit 1 has a gate-to-source voltage of 18V and a maximum nominal voltage (maximum drain-to-source voltage VDS) exceeding 1kV, for example, 1.2kV or 3.3kV, and can be configured to operate with several hundred amperes or even higher currents. The floating pocket 20, as defined above, allows for a reduction in the strength of the electric field around the junction between the body well 7 and the second epitaxial layer 5, which is the most critical region, and is undesirable in combination with particularly high current densities at this junction, as well as due to the dimensions of the parasitic JEFT region. The state of the electric field is shown directly in Figures 2 and 3 and via potential lines in Figures 5 and 6 for the conventional power unit 40 (Figures 2 and 5) and the power unit 1 of Figure 1 (Figures 3 and 6), respectively. As can be seen, in the conventional power unit, the potential lines are particularly crowded around the body well and the electric field value is high. On the other hand, in power device 1, when the voltage is higher than the threshold voltage and in a conducting state, the potential lines are less crowded throughout the entire parasitic JFET region, and are more crowded around the floating pocket 20. In fact, the higher values of the electric field are deeper in the first epitaxial layer 4, but the current density is significantly reduced. This is because the region between the floating regions 20 is wider than the parasitic JFET region. In this way, the time required to trigger the phenomenon of uncontrolled short circuits due to excessive localized heating, i.e., the short-circuit withstand time, is effectively increased, as shown in the graph in Figure 4. In Figure 4, the dotted line represents a conventional power device, while the solid line represents power device 1 according to the present invention.
[0016] The effects of the reduction in the electric field in the critical region around the body well 7 and the corresponding increase in short-circuit withstand time are also benefited by the protection-to-body distance LPB between the floating pocket 20 and the body well 7. The protection-to-body distance LPB, in fact, when the value of the drain-to-source voltage VDS is significantly higher than the threshold voltage, does not cause the potential line to tend to surround the body well 7, but rather, it tends to extend into the floating pocket 20, either not penetrating or only slightly penetrating into the portion of the second epitaxial layer 5 that forms between the floating pocket 20 and the body well 7. Larger distances do not allow for the extension of the potential line and the corresponding reduction in the electric field in the critical region, particularly in the parasitic JFET region.
[0017] Further advantages include breakdown voltage or on-state drain-to-source resistance, R DSON , This is demonstrated by the fact that it is possible to improve the short-circuit withstand time without significantly altering any of the above. Furthermore, an increase in the thickness of the current spreading layer, defined by the second epitaxial layer 5 of about 10-20%, does not affect the breakdown voltage, and in conventional power devices, it actually decreases.
[0018] Referring to Figure 7, in one embodiment, the semiconductor power device 100 has a semiconductor body 102 made of silicon carbide that substantially includes a first epitaxial layer 104 and a second epitaxial layer 105 in which a body well 107 and a source region 108 are formed, as described above. An enrichment layer 106 can be provided on the surface of the semiconductor body 102. As in the embodiment of Figure 1, a gate dielectric layer 110, a gate region 112, a source contact 113, and an intermetallic dielectric layer 115 are formed on the first surface 102a of the semiconductor body 102. The drain contact 117 is on the first surface 112a It is formed on the second surface 102b of the semiconductor body 102 on the opposite side.
[0019] The semiconductor body 102 further has an intermediate epitaxial layer 140, which is located between the first epitaxial layer 104 and the second epitaxial layer 105 and has a thickness TINT (for example, in the range of 0.8-2 μm) that is substantially the same as the thickness T2 of the first epitaxial layer 105.
[0020] The doping level is the second epitaxial layer 105 (highest, for example 10 if no enriched layer exists). 17 Number of atoms / cm 3 ) to the intermediate epitaxial layer 140 (this is, It is intermediate not only in terms of its position but also in terms of doping, for example, 4 × 10 16 Number of atoms / cm 3 ) and the first epitaxial layer 104 (lowest, for example, 10 16 Number of atoms / cm 3 ) is decreasing. When enriched layer 106 is present, its doping level is the highest, for example, 3 × 10 17 Number of atoms / cm 3 That is the case.
[0021] At the interface with the upper epitaxial layer, in this case the intermediate epitaxial layer 140, the first epitaxial layer 104 contains a deep floating protective pocket 120, which is 10 18 Number of atoms / cm 3 It has a second conductivity type, for example, P+ type, at a certain level of doping.
[0022] At the interface with the second epitaxial layer 105, the intermediate epitaxial layer 140 contains an intermediate floating pocket 145 which is substantially the same as the deep floating pocket 120.
[0023] The deep floating pocket 120 and the intermediate floating pocket 145 are shaped and positioned relative to the structure within the semiconductor body 102 such that the maximum electric field strength around the deep floating pocket 120 is greater than the maximum electric field strength around the body well 107, at least for drain-to-source voltage VDS values that are greater than the threshold voltage, which is the maximum nominal voltage. In particular, the distances between the deep floating pocket 120 and the intermediate floating pocket 145, and between the intermediate floating pocket 145 and the body well 107, in directions perpendicular to the surfaces 102a and 102b of the semiconductor body 102, are less than 0.5 μm, for example, 0.3 μm. These distances are not necessarily the same as each other.
[0024] The presence of protective wells at multiple levels allows for amplification of the effect of high-value conversion of the electric field into the interior of the semiconductor body 102 at a greater distance from the first surface 102a.
[0025] The number of protective well levels is not limited to two. In other embodiments, for example, in the semiconductor power device 200 in Figure 8, in addition to the deep protective well shown here by reference no. 220, it is possible to provide two intermediate levels, for example, protective wells 245 and 246, or more, based on design priorities. Intermediate floating pockets are formed within the respective intermediate epitaxial layers 240 and 241 of each level.
[0026] The power device 1 in Figure 1 can be manufactured according to the following process, or method, as described with reference to Figures 9 and 13. First, a first epitaxial layer 4 is formed to the desired thickness. Then, a first mask layer 50 of TEOS (tetraethyl orthosilicate) is attached and planarized.
[0027] Next, a first mask layer 50 is patterned (Figure 10) to form a first injection mask 51, which is then used to form a floating pocket 20 by a first injection P to a desired depth. In one embodiment, the first injection P is a multi-injection consisting of multiple steps, which allows for precise control of the injection depth and the shape of the floating pocket 20. The dopant species to be injected can be aluminum, and the injection can be carried out in five steps, as shown in Table 1 below.
[0028] [Table 1]
[0029] After removing the first injection mask 1, the second epitaxial layer 5 is also grown to the desired thickness (Figure 11). If necessary, an enriched layer 6 is formed either through further epitaxial growth or by surface injection of dopant species.
[0030] A second mask layer 55 is attached and flattened, and then a pattern is formed to create a second injection mask 56 (Figure 12), which is used to form a body well 7 by a second injection P to a desired depth. This second injection can also be a multi-injection.
[0031] The second injection mask 56 is removed, and a third injection mask 58 is formed from the mask layer (not shown), thereby forming the source region 8.
[0032] The power device 1 is completed by removing the third injection mask 58, forming the gate dielectric layer 10, the gate region 12, the intermediate dielectric layer 15, and the source contact 13, and finally forming the drain terminal 1a, the source terminal 1b, and the gate terminal 1c (Figure 1A).
[0033] Although specific embodiments of the present invention have been described in detail above, the present invention should not be limited to these specific embodiments, and various modifications are possible without departing from the technical scope of the present invention.
Claims
1. In semiconductor power devices having a maximum nominal voltage, A first conductive terminal (1a) and a second conductive terminal (1b), a semiconductor body (2, 102) comprising silicon carbide and having a first conductivity type; body wells (7, 107) having a second conductivity type and housed within the semiconductor body and spaced apart by a body distance (LB); a source region contained within said body well (7); and a floating pocket (20, 120) having a second conductivity type and formed in the semiconductor body (2, 102) between the first surface (2a, 102a) and the second surface (2b, 102b) of the semiconductor body (2, 102) at a distance from the body well (7, 107); and the floating pocket (20, 120) is shaped and positioned relative to the body well (7, 107) such that the maximum intensity of the electric field around the floating pocket (20, 120) is greater than the maximum intensity of the electric field around the body well (7, 107) for values higher than a threshold voltage that is less than a maximum nominal voltage for values of a conduction voltage (VDS) between at least the first conductive terminal (1 a) and the second conductive terminal (1 b).
2. The semiconductor body (2, 102) comprises a first epitaxial layer (4, 104) having a first conductivity type and a first doping level (N1), and a second epitaxial layer (5, 105) having the first conductivity type and a second doping level (N2) higher than the first doping level (N1), the body well (7, 107) is contained within the second epitaxial layer (5, 105); The floating pocket (20, 120) is contained within the first epitaxial layer (4, 104).
10. The apparatus of claim 1.
3. 3. The device of claim 2, wherein the floating pocket (20, 120) is contained at an interface of the first epitaxial layer (4, 104) with an epitaxial layer above the first epitaxial layer (4, 104).
4. 4. The device of claim 3, wherein the epitaxial layer above the first epitaxial layer (4) is the second epitaxial layer (5).
5. 5. The device of claim 4, wherein a protection-to-body distance (LPB) between the floating pocket (20) and the corresponding body well (7) in a direction perpendicular to the first face (2a) and the second face (2b) of the semiconductor body (2) is less than 0.5 μm.
6. 4. The device of claim 3, wherein the semiconductor body (102) comprises an intermediate epitaxial layer (140) disposed between the first epitaxial layer (104) and the second epitaxial layer (105) and having an intermediate doping level between the first doping level (N1) and the second doping level (N2), and the epitaxial layer above the first epitaxial layer (104) is the intermediate epitaxial layer (140).
7. 7. The device of claim 6, further comprising an intermediate floating pocket (145) having the second conductivity type and formed in the intermediate epitaxial layer (140) at an interface with the second epitaxial layer (105).
8. 8. The device of claim 7, wherein the distance between the floating pocket (12) and the intermediate floating pocket (145) and between the intermediate floating pocket (145) and the body well (107) in a direction perpendicular to the first surface (102a) and the second surface (102b) of the semiconductor body (102) is less than 0.5 μm.
9. 9. The device according to claim 2, wherein the semiconductor body (2, 102) comprises an enriched layer (6, 106) having a third native doping level (N3) higher than the first doping level (N1) and the second doping level (N2), the first epitaxial layer (104) having a first thickness (T1), the second epitaxial layer (105) having a second thickness (T2), and the enriched layer (6, 106) having a third thickness (T3) smaller than the first thickness (T1) and the second thickness (T2).
10. 2. The device of claim 1, wherein the body wells (7, 107) are spaced apart from one another by a body distance (LB), and the floating pockets (20, 120) are disposed below the corresponding body wells (7, 107) and are spaced apart from one another by a protection distance (LP) greater than the body distance (LB), for example, an amount between 0.5 μm and 1.5 μm.
11. 11. The device of claim 10, wherein the body distance (LB) is less than 1 μm, for example 0.6 μm.
12. 3. The device of claim 2, wherein the second epitaxial layer (5, 105) defines a current spreading layer, the current spreading layer extending to a greater depth from the first surface (2a, 102a) of the semiconductor body (2, 102) than the body well (7, 107).
13. 2. The device of claim 1, wherein the floating pocket (20, 120) has a second conductivity type and a doping level on the order of 10@18 atoms / cm@3.
14. 1. A method of manufacturing a semiconductor power device, comprising: forming a semiconductor body (2, 102) including silicon carbide and having a first conductivity type (N); forming body wells (7, 107) having a second conductivity type (P) and contained within the semiconductor body and spaced apart by a body distance (LB); forming a source region (8) having a first conductivity type (N) and contained within the body well (7); forming a floating pocket (20, 120) having the second conductivity type (P) in the semiconductor body (2, 102) at a distance from the body well (7, 107) between the first surface (2a, 102a) and the second surface (2b, 102b) of the semiconductor body (2, 102); Forming a first conductive terminal (1a) and a second conductive terminal (1b); wherein the floating pocket (20, 120) is shaped and positioned relative to the body well (7, 107) such that the maximum intensity of the electric field around the floating pocket (20, 120) is greater than the maximum intensity of the electric field around the body well (7, 107) when the value of the conduction voltage (VDS) between at least the first conductive terminal (1 a) and the second conductive terminal (1 b) is greater than a threshold voltage that is less than the maximum nominal voltage.
15. 15. The method of claim 14, wherein forming the semiconductor body includes forming a first epitaxial layer (4, 104) having the first conductivity type and a first doping level (N1) and a second epitaxial layer (5, 105) having the first conductivity type and a second doping level (N2) higher than the first doping level (N1), and wherein the floating pocket (20, 120) is formed in the first epitaxial layer (4, 104) and the body well (7, 107) is formed in the second epitaxial layer (5, 105).
16. A method as described in claim 15, comprising, when forming the floating pocket (20), forming a first implantation mask (51) on the first epitaxial layer (4) and performing a first implantation, e.g., a first multi-implantation, of dopant species of the second conductivity type using the first implantation mask (51), and when forming the body well (7), forming a second implantation mask (56) and performing a second implantation, e.g., a second multi-implantation, of dopant species of the second conductivity type using the second implantation mask (56).