Method for detecting characteristic operating parameter of transistor of inverter

Abstract

To provide an inverter suitable for detecting a characteristic operating parameter of a transistor.SOLUTION: An inverter (1) includes: a first transistor (2) and a second transistor (3) which are a high-side transistor and a low-side transistor, respectively; and a control electronic circuit (4) which triggers a first switching operation where the first transistor (2) is switched on, the second transistor (3) is in a switched-off state, and a parasitic capacitance of the first transistor is discharged, which triggers a second switching operation where the first transistor (2) is switched off or switched on again, the second transistor (3) simultaneously remains in the switched-off state, and the parasitic capacitance of the first transistor is already discharged, and which determines a characteristic operating parameter of the first transistor (2) based on a time difference between a duration of the first switching operation and a duration of the second switching operation.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This invention relates to an inverter suitable for detecting characteristic operating parameters of an inverter's transistors. [Background technology]

[0002] Silicon carbide transistors, such as MOSFETs, are key components of inverters in the automotive environment. Throughout the lifespan of an inverter, its components undergo aging degradation, and this degradation also applies to the inverter's transistors. This aging degradation of the transistors leads to a decrease in their operating parameters, either due to aging or certain load conditions resulting from the use of the transistors. Another reason why the transistor's operating parameters may deviate from the target values ​​is tolerances in the manufacturing process.

[0003] Inverter transistors are often used in parallel configurations. In this configuration, if the operating parameters of individual transistors differ, the current distribution becomes asymmetrical, leading to losses and uneven thermal distribution of the transistors. This asymmetrical distribution increases the load on the corners of individual transistor chips that carry the maximum current. Consequently, the aging process is accelerated.

[0004] In an inverter where all transistors are evenly loaded, sensing the operating parameters of individual transistors is necessary to enable transistor control. It is known that the voltage characteristics of the drain-source voltage and gate-source voltage are considered to calculate the Miller charge induced by Miller capacitance, or the capacitance of Miller capacitance. To identify the corresponding value, the gate-source voltage is sampled and analyzed over time. However, this sampling operation can be inaccurate. Furthermore, monitoring the drain-source voltage is required, necessitating additional triggers. Also, monitoring the gate-source voltage throughout the transistor's switch-on operation cannot predict parasitic effects. In particular, capacitances not inherent in the transistor cannot be predicted. For example, effects resulting from the use of multiple transistor chips cannot be considered. [Overview of the project] [Means for solving the problem]

[0005] The inverter according to the present invention includes a first transistor and a second transistor, which are the high-side transistor and low-side transistor of the inverter; and a control electronic circuit configured to trigger a first switching operation in which the first transistor is switched on and the second transistor is switched off, and the parasitic capacitance of the first transistor is discharged during the first switching operation; to trigger a second switching operation in which the first transistor is switched off or switched on again, and at the same time the second transistor remains switched off, and the parasitic capacitance of the first transistor has already been discharged during the second switching operation; to detect a time difference representing the difference between the duration of the first switching operation and the duration of the second switching operation; and to identify the characteristic operating parameters of the first transistor based on the time difference.

[0006] A method for detecting specific operating parameters of transistors in an inverter, including a first transistor and a second transistor, which are the high-side transistor and the low-side transistor of the inverter according to the present invention, comprises: triggering a first switching operation in which the first transistor is switched on, the second transistor is in an off state, and the parasitic capacitance of the first transistor is discharged during the first switching operation; triggering a second switching operation in which the first transistor is switched off or switched on again, and at the same time the second transistor remains in the off state, and the parasitic capacitance of the first transistor has already been discharged during the second switching operation; detecting a time difference representing the difference between the duration of the first switching operation and the duration of the second switching operation; and specifying the characteristic operating parameters of the first transistor based on the time difference.

[0007] Therefore, the first transistor is either switched on twice or first switched on and then switched off. In particular, assuming that the gate charge during the on operation of the first transistor corresponds to or is of the same order as the gate charge during the off operation of the first transistor, the characteristic operating parameters are specified.

[0008] The high-side transistor is typically a transistor that connects the power supply voltage supplied to the inverter to the output side of the inverter. The low-side transistor is typically a transistor that connects the output side of the inverter to the ground potential. The switching operation is the period during which the transistor changes from the conductive state to the non-conductive state or from the non-conductive state to the conductive state. The switching operation is typically initiated by supplying a control signal to the transistor, particularly by changing the voltage between the gate and the source. The switching operation then ends when the transistor can conduct the minimum or maximum current through the drain-source contact, i.e., when the drain-source current is minimum or maximum, or when the voltage dropping through the drain-source contact is minimum, typically 0 volts, or maximum.

[0009] The first and / or second transistor is particularly a MOSFET transistor. The control electronic circuit is configured to detect a time difference. This time difference defines the difference between the duration of the first switching operation and the duration of the second switching operation. The time difference can be detected by first measuring the duration of the first switching operation, then measuring the duration of the second switching operation, and finally calculating the time difference from the measured values. The characteristic operating parameters of the first transistor are specified based on the time difference. That is, the characteristics of the first transistor can be specified from the turn-on characteristics of the first transistor when the second transistor is switched off.

[0010] During the first switching operation, the parasitic capacitance of the first transistor is discharged. In other words, the parasitic capacitance is charged before the first switching operation and can be discharged. Here, parasitic capacitance is the capacitance formed by the transistor and arises from the characteristics of the transistor itself. Therefore, parasitic capacitance is not an independent component connected to the transistor. During the second switching operation, the parasitic capacitance of the first transistor has already been discharged. For example, the parasitic capacitance of the first transistor has already been discharged during the first switching operation and remains in this state until the second switching operation is performed.

[0011] The cited claims illustrate preferred improved forms of the present invention. The parasitic capacitance is preferably a Miller capacitance, and the characteristic operating parameter is the charge or capacitance value of the Miller capacitance. Here, the Miller capacitance is the capacitance that occurs between the drain contact and the gate contact of the transistor. The Miller capacitance needs to be discharged by the gate current before the transistor is switched, and can therefore delay the switching operation of the transistor. Thus, it is advantageous to identify the charge stored in the Miller capacitance, or the capacitance value of the Miller capacitance, because the switching operation of the transistor can be time-adjusted based on these values.

[0012] Preferably, the control electronic circuit is further configured to set or detect the gate current of the first transistor and to determine the characteristic operating parameters of the first transistor based on the gate current and the time difference. In particular, the gate current flows into the parasitic capacitance of the transistor. Thus, the gate current can be used as the basis for calculating the operating parameters for calculating the parasitic capacitance of the transistor. Therefore, it is advantageous to set or detect the gate current of the first transistor so that it is known in order to perform the necessary calculations. The time difference defines the time over which the gate current flows into the parasitic capacitance.

[0013] Furthermore, the characteristic operating parameter is the Miller capacitance charge of the first transistor, and it is advantageous that this is determined by multiplying the gate current of the first transistor by its time difference. In particular, the Miller capacitance of the first transistor is an important parameter for synchronizing or coordinating the switching operation of multiple transistors. By calculating the Miller capacitance by multiplying the gate current of the first transistor by its time difference, it is possible to determine the Miller capacitance without measuring the voltage. In particular, particularly accurate results can be obtained for the Miller capacitance value to be determined.

[0014] Furthermore, it is advantageous for the first and second switching operations to be performed under no-load conditions of the inverter. This prevents current from flowing through the connected load to the output contacts between the first and second transistors. Therefore, the measurement results will not be inaccurate.

[0015] Furthermore, it is advantageous that the first switching operation is the first switching operation after the inverter has been switched to a no-load state. That is, after the inverter has been switched to a no-load state after load operation, the first transistor and / or the second transistor have not performed any other switching operations. In other words, as a result of operating under load conditions, the parasitic capacitances of the first and / or second transistors are still sufficiently charged. Therefore, it is also advantageous that the first switching operation be performed as soon as possible after the inverter has been switched to a no-load state. Thus, it is preferable that the first switching operation be performed immediately after the no-load state is detected. The fact that the parasitic capacitances of the first and second transistors are fully charged allows for particularly accurate identification of the impact on characteristic operating parameters.

[0016] The second switching operation is preferably the first switching operation immediately following the first switching operation. This is particularly advantageous if the first transistor is switched off during the second switching operation. This prevents other parameters, such as temperature changes, from causing incorrect results when determining characteristic operating parameters.

[0017] The duration of the first switching operation and / or the duration of the second switching operation is preferably defined by the time it takes for the gate-source voltage of the first transistor to rise or fall during the switching operation. In particular, the duration of the first switching operation is defined by the duration it takes for the gate-source voltage of the first transistor to rise. If the second switching operation is switching off the first transistor, the duration of the second switching operation is defined by the time it takes for the gate-source voltage of the first transistor to fall during the second switching operation. If the second switching operation is switching on the first transistor again during the second switching operation, the duration of the second switching operation is defined by the time it takes for the gate-source voltage of the first transistor to rise to its maximum value during the switching operation. Thus, the switching operation is defined by the rise or fall of the gate-source voltage.

[0018] Furthermore, it is advantageous if the first transistor is switched on again during the second switching operation, and the first transistor is switched off during the intermediate switching operation performed between the first and second switching operations, thereby enabling it to be switched on again during the subsequent second switching operation, while the second transistor remains switched off during the intermediate switching operation. In order to switch the first transistor on again, it is first necessary to switch the first transistor off. This is done by the intermediate switching operation. Simultaneously, this makes it possible to discharge the capacitance of the first and / or second transistors during the intermediate switch-on operation. Therefore, it is possible to compare the switching operation when the capacitance of the first transistor is charged with the switching operation when the capacitance of the first transistor is discharged.

[0019] The inverter according to the present invention has all the advantages of the method according to the present invention. [Brief explanation of the drawing]

[0020] Embodiments of the present invention will be described in detail below with reference to the attached drawings. [Figure 1] This is a diagram of an inverter according to the present invention. [Figure 2] This is the gate-source voltage characteristic of the first transistor during the first switching operation. [Figure 3] This figure shows the gate-source voltage characteristics of the first transistor during the second switching operation. [Figure 4] This figure shows the drain-source voltage of the first transistor during the first switching operation. [Figure 5] This figure shows the drain-source voltage characteristics of the first transistor during the second switching operation. [Figure 6] This is a circuit diagram of a circuit that detects the gate current of the first transistor. [Figure 7]This diagram shows the drain-source voltage and gate-source voltage of the first transistor during the first and second switching operations when the switching operation is performed continuously. [Modes for carrying out the invention]

[0021] Figure 1 shows an inverter 1 including a first transistor 2 and a second transistor 3. The first transistor 2 is the low-side transistor of inverter 1, and the second transistor 3 is the high-side transistor of inverter 1.

[0022] The drain contact of the second transistor 3 is connected to the potential of the power supply voltage of inverter 1, and the power supply voltage V is transmitted through it. DD A power supply voltage of 300 volts is supplied. DD A supply is provided. The source contact of the second transistor 3 is connected to the output contact 5 of the inverter 1 and the drain contact of the first transistor 2. The source contact of the first transistor 2 is connected to the circuit ground. Thus, the first transistor 2 and the second transistor 3 are connected in series via their switching contacts. The gate contact of the first transistor 2 and the gate contact of the second transistor 3 are coupled to the control electronic circuit 4 of the inverter 1. The control electronic circuit 4 is configured to carry out the method according to the present invention.

[0023] In the normal operation of inverter 1, the second transistor 3 and the first transistor 2 switch alternately, so the power supply voltage V DD The ground potential is then alternately applied to the output contact 5. In this way, for example, an AC phase is generated that operates the motor of a vehicle.

[0024] To adjust the switching operation of the first transistor 2 and the second transistor 3, it is advantageous that the characteristic operating parameters of the two transistors 2 and 3 are known to the control electronic circuit 4. For example, if the parasitic capacitance of the first transistor is known, it is advantageous because it affects the switching time of the first transistor. Depending on the characteristic operating parameters of the first transistor 2, for example, the Miller charge Q of the first transistor 2 can be determined. GD The characteristics are described. Further exemplary characteristic operating parameters are the switch-on capacitance and gate-source capacitance of the first transistor 2.

[0025] Below is the Miller charge Q of the first transistor 2. GD We will explain how to identify it. However, other characteristic operating parameters are also Miller charge Q GD Since this method is often dependent on other characteristics, it should be noted that other characteristic operating parameters can also be identified based on this method.

[0026] The control electronic circuit 4 first detects when the inverter 1 is in an unloaded state. This applies, for example, when an electric vehicle equipped with the inverter 1 is idle and no current is drawn from the inverter 1 by the vehicle's motor. In particular, in this state, the motor coil is disconnected from the inverter 1. In the unloaded state of the inverter 1, typically both the first transistor 2 and the second transistor 3 are initially switched off. That is, in this state, no current initially flows through the drain and source contacts of transistors 2 and 3.

[0027] The first switching operation is triggered by the control electronic circuit 4. In the first switching operation, the first transistor 2 is switched on, while the second transistor 3 remains switched off. The gate-source voltage of the first transistor 2 during the first switching operation is shown over time in Figure 2. Furthermore, the drain-source voltage of the first transistor 1 during the first switching operation is shown over time in Figure 4.

[0028] Fig. 2 shows the voltage characteristics 10 of the voltage between the gate and source of the first transistor 2 during the first switching operation over time. That is, it can be seen from Fig. 2 that the voltage between the gate and source of the first transistor 2 first rises during the first period t1. During the second period t2 following the first period t1, the voltage between the gate and source of the first transistor 2 remains on the plateau. This plateau is due to the parasitic capacitance between the drain and gate of the first transistor 2, that is, the Miller capacitance. During the second period t2, the Miller capacitance charged at the start of the first switching operation is discharged through the gate current flowing into the gate of the first transistor 2. As a result, during this period, the voltage between the gate and source of the first transistor 2 does not increase. When the second period t2 elapses, the voltage between the gate and source continues to rise until it reaches the maximum value during the third period t3. The voltage between the gate and source is supplied from the control electronic circuit 4. GS Fig. 4 shows the voltage characteristics 11 of the voltage between the drain and source of the first transistor 2 during the first switching operation over time. In the first period t1, the voltage between the drain and source remains at a high voltage level. The second transistor 3 is in the off state, but still, the charge in the system is held in the capacitances of transistors 2 and 3. As a result, the maximum voltage between the drain and source V

[0029] Fig. 4 shows the voltage characteristics 11 of the voltage between the drain and source of the first transistor 2 during the first switching operation over time. In the first period t1, the voltage between the drain and source remains at a high voltage level. The second transistor 3 is in the off state, but still, the charge in the system is held in the capacitances of transistors 2 and 3. As a result, the maximum voltage between the drain and source V DS shown in the first period t1 of Fig. 4 for the first transistor 2 is obtained. To maintain this state first, it is advantageous that the first switching operation is a switching operation in which no other switching operation is performed by the first or second transistor 3 before its switching operation after the inverter 1 transitions to the no-load state. Therefore, the first switching operation is the first switching operation after switching the inverter to the no-load state. DS shown in the first period t1 of Fig. 4 for the first transistor 2 is obtained. To maintain this state first, it is advantageous that the first switching operation is a switching operation in which no other switching operation is performed by the first or second transistor 3 before its switching operation after the inverter 1 transitions to the no-load state. Therefore, the first switching operation is the first switching operation after switching the inverter to the no-load state.

[0030] During the second period t2, current begins to flow between the drain and source of the first transistor 2, and the voltage applied to the drain and source of the first transistor drops. This continues until the end of the third period t3, at which point the drain-source voltage of the first transistor 2 reaches its minimum value of 0 volts. When the drain-source voltage through the first transistor 2 drops to 0 volts, this means that the output contact 5 of the inverter 1 is also at a potential of 0 volts. Therefore, the drain-source voltage of the second transistor 3 V DS It rises until it reaches the maximum level. Switch-on period t ON This includes a first period t1, a second period t2, and a third period t3. Switch-on period t ON The duration is detected by the control electronic circuit 4, for example, by monitoring the gate current of the first transistor 2.

[0031] Furthermore, Figure 4 shows the drain-source voltage V of the second transistor 3 during the first switching operation. DS The voltage characteristics 12 are shown over time. In the first switching operation, the parasitic capacitance of the first transistor is charged during load operation and then discharged.

[0032] After the first switching operation is completed, the control electronic circuit 4 triggers the second switching operation. At this time, the second transistor 3 remains switched off. In the second switching operation, the first transistor 2 is switched off. Figure 3 shows the gate-source voltage V of the first transistor 2. GS The voltage characteristics 10 are shown. Correspondingly, the drain-source voltage V of the first transistor 2 is shown. DS The relevant voltage characteristics 11 are shown in Figure 5. From Figure 3, it can be seen that the second switching operation starts after the fourth period t4 has elapsed. Therefore, the second switching operation starts after the switch-off period t offIt extends over a fifth period t5, also known as the fifth period t5. Since the second transistor 3 was switched off in both the first and second switching operations, charge cannot flow into the parasitic capacitance of the first transistor 2 and charge it. Therefore, during the fifth period t5, the gate-source voltage drops continuously. The drain-source voltage V of the first transistor 2 is shown in Figure 5. DS Looking at the voltage characteristics 11, which relate to the second switching operation, we see the drain-source voltage V related to the first transistor 2. DS We can see that it remains at 0 volts. This is because the drain-source voltage V related to the first transistor 2 is still switched off because the second transistor 3 is still switched off. DS This is because no current sufficient to establish a stable state flows through the second transistor 3. In other words, since the second transistor 3 is switched off, the first transistor 2 is disconnected from any voltage source. Since the voltage level at the output contact 5 of the inverter 1 is at a potential of 0 volts, the voltage drop across the first transistor 2 also remains at 0 volts regardless of its switching state.

[0033] Furthermore, Figure 5 shows the drain-source voltage V of the second transistor 3 during the second switching operation. DS The voltage characteristics 12 are shown over time. Furthermore, the second transistor 3 remains switched off throughout the entire possible time range between the first and second switching operations. Therefore, the parasitic capacitance of the first transistor is prevented from being recharged before the second switching operation. In the state described here, the parasitic capacitance of the first transistor is already completely discharged and remains discharged by the time of the second switching operation. The drain-source voltage V of the second transistor 3 is shown in Figure 5. DS The voltage characteristics are as follows: drain-source voltage V DS However, during the second switching operation, especially with the power supply voltage V DD This indicates that it remains at its maximum value, which corresponds to [the specified value].

[0034] The first switching operation and the second switching operation cause two switching operations of the first transistor 2. The Miller capacitance of the first transistor 2 is charged and discharged during one of the switching operations, in this case the first switching operation, and the Miller capacitance of the first transistor 2 has already been discharged during the second switching operation. In other words, the Miller charge Q accumulated in the Miller capacitance of the first transistor 2 GD This does not affect the switching time, i.e., the duration of the second switching operation, during the second switching operation. Therefore, the duration of the first switching operation, i.e., the switch-on period t, is not affected. ON Then, the duration of the second switching operation, i.e., the switch-off period t. off From the time difference, the mirror charge Q GD It is possible to infer this. Therefore, the control electronic circuit 4 detects a time difference that represents the difference between the duration of the first switching operation and the duration of the second switching operation. This is the switch-on period t ON And, the switch-off period t off This can be seen from the difference between them.

[0035] Furthermore, the control electronic circuit 4 controls the gate current I of the first transistor 2. G This is detected and applied to the gate contact of the first transistor 2 when the first switching operation is triggered, and is also used to charge the Miller capacitance of the first transistor 2. The gate current I of the first transistor 2 G By multiplying this by the time difference, the Miller capacitance Q of the first transistor 2 is obtained. GD The charge is identified.

[0036] The Miller capacitance can be derived from the following mathematical relationship.

[0037]

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[0038]

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[0039]

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[0040] Charge Q GS1 In the first period, the gate current I G This is the charge that flows through the capacitance of the first transistor 2. Charge Q GS2 In the third period t3, the gate current I G This is the charge that flows through the capacitance of the first transistor 2. Charge Q GS This is a Miller charge, and at the same time, in the second period t2, the gate current I G This is the charge that flows through the capacitance of the first transistor 2.

[0041]

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[0042]

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[0043] Charge Q required for the first switching operation GON The switch-on period t ON Over the course of the gate current I G This can be determined from the current flowing through the capacitance of the first transistor 2. The charge Q required for the second switching operation is... GOFF This is the switch-off period t off Over the course of the gate current I G This can be determined from the current flowing through the capacitance of the first transistor 2.

[0044]

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[0045]

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[0046]

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[0047] By appropriately rearranging equations (1) to (5), the gate current I G If the switch-on period t is known, ON and switch-off period t off The difference is the charge Q of the Miller capacitance. GD It can be identified. Optionally, the second switching operation is one in which the first transistor 2 is switched on again. This is shown in Figure 7. In order to be able to switch on the first transistor 2 again, it is necessary to turn it off beforehand. This is preferably done during the intermediate switching operation. Also, the second transistor 3 remains switched off during the intermediate switching operation. In this case as well, the parasitic capacitance of the first transistor is discharged during the first switching operation and remains discharged during the second switching operation.

[0048] For example, a PWM signal is applied to the gate of the first transistor 2 shown at the top of Figure 7 to turn the first transistor 2 on and off. The drain-source voltage V of the first transistor 2 shown in Figure 7. DS From the voltage characteristics, the drain-source voltage V of the first transistor 2 is DS It can be seen that the voltage rises only during the first switching operation and does not rise during the subsequent second switching operation. As a result, as shown in the lower part of Figure 7, the gate-source voltage V of the first transistor 2 during the first switching operation GS The rise in this value lags behind the second switching operation.

[0049] If the gate-source voltage rises above the first transistor 2, the second period t2 is omitted. The switch-on time for the second switching operation is the sum of the first period t1 and the third period t3.

[0050] Therefore, in the first switching operation, the switch-on period t ON This is generated by the sum t1+t2+t3 of the first to third periods. In the second switching operation, the switch-on period t ON This is generated by the sum of the first and third periods, t1+t3, because the second period t2 is omitted due to the Miller capacitance already being discharged.

[0051] In this case, the Miller charge is due to the gate current I G Here, it can be calculated by multiplying it by the time difference t2. This can also be done by multiplying these values ​​in addition to equations (6) to (8) mentioned earlier.

[0052]

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[0053] Here, the second period t2 is the switch-on period t ON And, the switch-off period t off This corresponds to the difference between the two. Current I supplied to the gate of the first transistor 2 G This is measured, for example, by the circuit shown in Figure 6. Therefore, the gate current I G The gate current I is supplied from the input current source 20 and flows to the gate contact of the first transistor 2. G The corresponding voltage is taken out via the voltage divider 21 and converted to a digital value by the analog-to-digital converter 22. Using this digital value, the characteristic operating parameter, which is Miller capacitance or Miller charge, can be calculated.

[0054] In the embodiment described above, the first transistor 2 is a low-side transistor. However, it should be noted that the characteristic operating parameters of the second transistor 3, i.e., the high-side transistor, can also be detected in the same way. This is possible because the control electronic circuit and the inverter 1 have a symmetrical configuration.

[0055] Values ​​described with mathematical background, such as switch-on capacitance or switch-off capacitance C. ON , C off Note that charge and capacitance characteristics related to inverter 1 can also be detected.

[0056] In addition to the above explanation, explicit reference is made to the disclosures in Figures 1 through 7.

Claims

1. a first transistor (2) and a second transistor (3) which are the high-side and low-side transistors of the inverter (1); a control electronic circuit (4), triggering a first switching operation in which the first transistor (2) is switched on and the second transistor (3) is switched off, the parasitic capacitance of the first transistor being discharged during the first switching operation; triggering a second switching operation in which the first transistor (2) is switched off or switched on again, while the second transistor (3) remains in the switched-off state, the parasitic capacitance of the first transistor being already discharged during the second switching operation; - detecting a time difference representative of the difference between the duration of said first switching operation and the duration of said second switching operation; and - determining a characteristic operating parameter of said first transistor (2) based on said time difference; a control electronic circuit (4) configured as follows: An inverter (1).

2. 2. The inverter (1) of claim 1, wherein the parasitic capacitance is a Miller capacitance and the characteristic operating parameter is a charge or capacitance value of the Miller capacitance.

3. 2. The inverter (1) of claim 1, wherein the control electronic circuit (4) is further configured to set or detect a gate current of the first transistor (2) and to determine the characteristic operating parameter of the first transistor (2) based on the gate current of the first transistor (2) and the time difference.

4. 4. The inverter (1) of claim 3, wherein the characteristic operating parameter is a charge on a Miller capacitance of the first transistor (2) and is determined by multiplying the gate current of the first transistor (2) by the time difference.

5. 2. The inverter (1) according to claim 1, wherein the first switching operation and the second switching operation are performed in a no-load state of the inverter (1).

6. 6. The inverter (1) according to claim 5, wherein the first switching operation is the first switching operation after switching the inverter (1) to a no-load condition.

7. 2. The inverter (1) according to claim 1, wherein the duration of the first switching operation and / or the duration of the second switching operation are defined by the time it takes for a gate-source voltage of the first transistor (2) to rise or fall during the switching operation.

8. 2. The inverter (1) according to claim 1, wherein the first transistor (2) is switched on again during the second switching operation, and the first transistor (2) is switched off during an intermediate switching operation performed between the first and second switching operations, thereby allowing the first transistor (2) to be switched on again during the subsequent second switching operation, and the second transistor (3) remains switched off during the intermediate switching operation.

9. 1. A method for detecting a specific operating parameter of a transistor of an inverter (1), comprising a first transistor (2) and a second transistor (3), which are high-side and low-side transistors of the inverter, the method comprising: - triggering said first switching operation, in which said first transistor (2) is switched on and said second transistor (3) is switched off, and the parasitic capacitance of said first transistor is discharged during said first switching operation; - triggering a second switching operation in which the first transistor (2) is switched off or switched on again, while the second transistor (3) remains switched off, the parasitic capacitance of the first transistor being already discharged during the second switching operation; - detecting a time difference representative of the difference between the duration of said first switching operation and the duration of said second switching operation; - determining characteristic operating parameters of said first transistor (2) based on said time difference; A method comprising:

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