Image forming apparatus

Abstract

To provide a technique that can reduce the number of signal lines connected to a control unit.SOLUTION: A voltage generating device includes a first circuit that outputs a first voltage, control means for controlling the value of the first voltage output by the first circuit by means of a control signal, and storage means for storing control information of the first circuit. The control means uses the control signal to communicate with the storage means.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a voltage generation device and an image forming apparatus.

Background Art

[0002] Generally, various devices include a voltage generation device that generates voltages of various values used in their operations. For example, an electrophotographic image forming apparatus includes a voltage generation device that generates a charging voltage used for charging a photoreceptor, a developing voltage for developing an electrostatic latent image formed on the photoreceptor, and the like. In order to operate the device stably, the voltage generation device is required to accurately control the value of each generated voltage.

[0003] For this reason, Patent Document 1 discloses a configuration in which control information is stored in a non-volatile memory of a voltage generation device. The voltage generation device controls a circuit for generating a voltage based on the control information stored in the non-volatile memory, thereby bringing the value of the generated voltage closer to the target value.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In the configuration of Patent Document 1, a control unit of a voltage generation device, a substrate (hereinafter referred to as a power supply substrate) provided with each circuit for generating a voltage and a non-volatile memory are connected by a plurality of signal lines. The plurality of signal lines include a signal line for controlling the voltage generated by each circuit and a signal line for reading the control information stored in the non-volatile memory. Here, the cost can be reduced by reducing the number of signal lines connected to the control unit.

[0006] This invention provides a technique that can reduce the number of signal lines connected to the control unit. [Means for solving the problem]

[0007] According to one aspect of the present invention, a voltage generating device comprises a first circuit that outputs a first voltage, control means that controls the value of the first voltage output by the first circuit using a control signal, and storage means that stores control information of the first circuit, wherein the control means uses the control signal for communication with the storage means. [Effects of the Invention]

[0008] According to the present invention, the number of signal lines connected to the control unit can be reduced. [Brief explanation of the drawing]

[0009] [Figure 1] A schematic cross-sectional view of an image forming apparatus according to one embodiment. [Figure 2] A diagram illustrating the configuration of a voltage generating device according to one embodiment. [Figure 3] A diagram illustrating the operation of each circuit according to one embodiment. [Figure 4] An explanatory diagram of a control method for a blade circuit according to one embodiment. [Figure 5] An explanatory diagram of a control method for a blade circuit according to one embodiment. [Modes for carrying out the invention]

[0010] The embodiments will be described in detail below with reference to the attached drawings. Note that the following embodiments do not limit the invention as defined in the claims. While the embodiments describe multiple features, not all of these features are essential to the invention, and the features may be combined in any way. Furthermore, in the attached drawings, identical or similar configurations are given the same reference numerals, and redundant descriptions are omitted.

[0011] <First Embodiment> Figure 1 is a schematic cross-sectional view of the image forming apparatus 101 according to this embodiment. The power supply board 107 is equipped with various circuits for generating different voltages and a non-volatile memory 171. Specifically, the charging circuit 132b provided on the power supply board 107 generates a charging voltage Vpri and outputs it to the charging roller 132a. The developing circuit 133b generates a developing voltage Vdev and outputs it to the developing roller 133a. The toner supply circuit 134b generates a toner supply voltage Vtsr and outputs it to the toner supply roller 134a. The blade circuit 135b generates a blade voltage Vbld and outputs it to the developing blade 135a. The transfer circuit 141b generates a transfer voltage Vtr and outputs it to the transfer roller 141a. The charging circuit 132b, developing circuit 133b, toner supply circuit 134b, blade circuit 135b, and transfer circuit 141b are circuits that generate various voltages used by the image forming apparatus 101 for image formation, and are collectively referred to simply as "circuits" below. The non-volatile memory 171 stores control information (correction information) for correcting the voltage values ​​generated by each circuit.

[0012] The photoreceptor 131 is driven to rotate in a clockwise direction in the figure during image formation. The charging roller 132a charges the surface of the photoreceptor 131 with a charging voltage Vpri. The scanning unit 137 scans and exposes the photoreceptor 131 based on image data to form an electrostatic latent image on the photoreceptor 131. The toner supply roller 134a moves the toner contained in the toner container 136 to the surface of the developing roller 133a with a toner supply voltage Vtsr. The developing roller 133a develops the electrostatic latent image on the photoreceptor 131 with toner using a developing voltage Vdev, thereby forming a toner image on the photoreceptor 131. The developing blade 135a is provided to regulate the thickness of the toner layer on the developing roller 133a and to make its height uniform.

[0013] To move the toner contained in the toner container 136 to the surface of the developing roller 133a, the absolute value of the toner supply voltage Vtsr is set to be greater than the absolute value of the developing voltage Vdev. Also, to prevent toner from sticking to the developing blade 135a, the absolute value of the blade voltage Vbld is set to be greater than the absolute value of the developing voltage Vdev. As an example, the developing voltage Vdev is set to -300V, and the toner supply voltage Vtsr and blade voltage Vbld are set to -400V.

[0014] The recording material P contained in the cassette 121 is fed into the transport path 111 by the feed roller 122 and transported to the position opposite the photoreceptor 131. The transfer roller 141a transfers the toner image of the photoreceptor 131 to the recording material P using the transfer voltage Vtr. The fixing unit 105 fixes the toner image to the recording material P by heating and pressurizing the recording material P. After the recording material P is fixed, it is discharged into the discharge tray 162.

[0015] The CPU 181 of the control unit 108 controls the image forming apparatus 101 by executing various programs stored in the ROM 182. In controlling the image forming apparatus 101, the CPU 181 uses the RAM 183 to store temporary information, etc. The control performed by the CPU 181 includes controlling the voltage output of each circuit of the power supply board 107. In doing so, the CPU 181 also uses control information stored in the non-volatile memory 171.

[0016] Figure 2 shows the configuration of the voltage generation device. The voltage generation device corresponds, for example, to the circuit and non-volatile memory 171 mounted on the power supply board 107. Alternatively, the voltage generation device corresponds to the circuit and non-volatile memory 171 mounted on the power supply board 107 and the functional part of the control unit 108 that controls each circuit on the power supply board 107 and communicates with the non-volatile memory 171. In the following description, it will be assumed that the power supply board 107 shown in Figure 2 and the functional part of the control unit 108 that controls the power supply board 107 constitute the voltage generation device.

[0017] First, let's explain the charging circuit 132b. The power supply voltage V1 is connected to one terminal of the primary winding T11-1 of the transformer T11, and the FET 11 is connected to the other terminal. For example, the power supply voltage V1 is 24V. The source terminal of FET 11 is connected to ground (GND). Also, the source terminal and gate terminal of FET 11 are connected via resistor R12. The gate terminal of FET 11 is connected to the CLK terminal of CPU 181 via resistor R17. CPU 181 outputs a square wave, i.e., a pulse signal, from the CLK terminal, which alternates between high and low levels. When the pulse signal from the CLK terminal becomes high, FET 11 turns on, and the drain voltage of FET 11 drops to approximately GND potential. As a result, a voltage is applied across the primary winding T11-1 of the transformer T11, and an excitation current flows through the primary winding T11-1. Next, when the pulse signal from the CLK terminal becomes low level, FET11 turns off, and a flyback voltage is generated between the terminals of the primary winding T11-1. Simultaneously, a flyback voltage corresponding to the turns ratio between the primary winding T11-1 and the secondary winding T11-2 is also generated in the secondary winding T11-2. The flyback voltage generated in the secondary winding T11-2 is rectified and smoothed by a rectifier circuit consisting of diode D12 and capacitor C12, generating a charged voltage Vpri. As an example, the value of the charged voltage Vpri is -1500V. Note that capacitor C11, resistor R11, and diode D11 connected between the terminals of the primary winding T11-1 act as snubbers to absorb surge voltages due to the leakage inductance of the primary winding T11-1.

[0018] The charging circuit 132b has a feedback control configuration for stably controlling the charging voltage Vpri to a desired voltage. Specifically, as shown in Figure 2, the charging voltage Vpri is connected to the power supply voltage V2 via resistors R14 and R13. For example, the power supply voltage V2 is 5V. The connection point between resistors R14 and R13 is connected to the positive input terminal of comparator IC 11. The negative input terminal of comparator IC 11 is connected to the power supply voltage V2 via resistors R16 and R15, and further connected to GND via capacitor C16. The connection point between resistors R15 and R16 is connected to the PRI_CONT terminal of CPU 181. The output terminal of comparator IC 11 is connected to the gate terminal of FET 11. CPU 181 outputs a pulse signal from the PRI_CONT terminal that alternately repeats between a high impedance (hereinafter referred to as Hi-Z) state and a low state. While the PRI_CONT terminal is in the Hi-Z state, current flows from the power supply voltage V2 through resistors R15 and R16 to charge capacitor C16. Conversely, while the PRI_CONT terminal is in the Low state, current flows through resistor R16 towards the PRI_CONT terminal to discharge capacitor C16. As the PRI_CONT terminal alternates between the Hi-Z and Low states, the balance of charging and discharging of capacitor C16 stabilizes at a predetermined voltage, and therefore, the voltage at the negative input terminal of comparator IC11 also stabilizes at this predetermined voltage. This predetermined voltage is determined by the duty cycle of the pulse signal from the PRI_CONT terminal. Specifically, the higher the proportion of the low state of the pulse signal from the PRI_CONT terminal, the lower the voltage at the negative input terminal of comparator IC11 becomes.

[0019] Here, when the voltage at the negative input terminal of the comparator IC11 is lower than the voltage at the positive input terminal, the output terminal of the comparator IC11 becomes the Hi-Z state. In that case, the pulse signal output from the CLK terminal of the CPU181 directly drives the FET11 to turn on and off. On the other hand, when the voltage at the negative input terminal of the comparator IC11 is greater than or equal to the voltage at the positive input terminal, the output terminal of the comparator IC11 becomes the low state. In this case, regardless of the level of the pulse signal from the CLK terminal, the FET11 is in the off state, so the absolute value of the charging voltage Vpri becomes lower. Therefore, as shown in Fig. 3(A), the greater the duty ratio of the low state of the pulse signal output from the PRI_CONT terminal, the greater the absolute value of the charging voltage Vpri.

[0020] Next, the developing circuit 133b will be described. The developing circuit 133b generates the developing voltage Vdev by dividing the charging voltage Vpri. The collector terminal of the transistor Tr31 in the developing circuit 133b is connected to the charging voltage Vpri via the resistor R50 and the Zener diode ZD51. The emitter terminal of the transistor Tr31 is connected to the power supply voltage V1. The base terminal and the emitter terminal of the transistor Tr31 are connected via the resistor R39. Also, the base terminal of the transistor Tr31 is connected to the output terminal of the operational amplifier IC31 via the resistor R38. Note that the voltage at the collector terminal of the transistor Tr31 becomes the developing voltage Vdev.

[0021] The developing circuit 133b also has a feedback control configuration for controlling the developing voltage Vdev to a stable and desired voltage. Specifically, the developing voltage Vdev is connected to the power supply voltage V2 via resistors R34 and R33. The connection point between resistor R34 and resistor R33 is connected to the positive input terminal of operational amplifier IC31. The negative input terminal of operational amplifier IC31 is connected to the power supply voltage V2 via resistors R36 and R35, and further connected to GND via capacitor C36. The connection point between resistor R35 and resistor R36 is connected to the DEV_CONT terminal of CPU181. The negative input terminal and the output terminal of operational amplifier IC31 are connected via resistor R37 and capacitor C37. This is for the phase compensation of operational amplifier IC31 and contributes to the stability of the feedback control.

[0022] A pulse signal that alternates between the Hi-Z state and the low state is output from the DEV_CONT terminal of CPU181. While the DEV_CONT terminal is in the Hi-Z state, a current flows to charge capacitor C36 from the power supply voltage V2 via resistors R35 and R36. On the other hand, while the DEV_CONT terminal is in the low state, a current to discharge capacitor C36 flows toward the DEV_CONT terminal via resistor R36. When the DEV_CONT terminal alternates between the Hi-Z state and the low state, the charge-discharge balance of capacitor C36 stabilizes at a predetermined voltage, and thus the voltage of the negative input terminal of operational amplifier IC31 also stabilizes at the predetermined voltage. This predetermined voltage is determined by the duty ratio of the pulse signal from the DEV_CONT terminal. Specifically, the larger the ratio of the low state of the pulse signal from the DEV_CONT terminal, the lower the voltage of the negative input terminal of comparator IC11.

[0023] Here, if the voltage at the negative input terminal of op-amp IC31 is lower than the voltage at the positive input terminal, the output terminal of op-amp IC31 becomes high level, and transistor Tr31 turns off. As a result, the absolute value of the developed voltage Vdev increases. On the other hand, if the voltage at the negative input terminal of op-amp IC31 is greater than or equal to the voltage at the positive input terminal, the output terminal of op-amp IC31 becomes low level, and transistor Tr31 turns on. As a result, the absolute value of the developed voltage Vdev decreases. Therefore, as shown in Figure 3(B), the larger the duty cycle of the low state of the pulse signal output from the DEV_CONT terminal, the larger the absolute value of the developed voltage Vdev. As an example, the value of the developed voltage Vdev is -300V.

[0024] Next, the blade circuit 135b will be explained. As shown in Figure 2, the development voltage Vdev is the voltage at the cathode terminal of the Zener diode ZD51, and the blade voltage Vbld is the voltage at the anode terminal of the Zener diode ZD51. Therefore, when the transistor Tr51, which is connected in parallel with the Zener diode ZD51, is in the off state, the blade voltage Vbld will have an absolute value greater than the development voltage Vdev by the amount of the Zener voltage of the Zener diode ZD51. When the transistor Tr51 is turned on, the two terminals of the Zener diode ZD51 are short-circuited, and the blade voltage Vbld becomes the same voltage as the development voltage Vdev. In this way, the blade circuit 135b is configured to select whether the blade voltage Vbld has a predetermined potential difference from the development voltage Vdev or is at the same potential. The reason for this will be explained below.

[0025] When the developing roller 133a is stopped rotating, if a potential difference occurs between the developing roller 133a and the developing blade 135a, the physical properties of the contact area may change. Subsequently, when the developing roller 133a is rotated to form an image, image defects such as streaks may occur. On the other hand, as described above, in order to prevent toner from adhering to the developing blade 135a, when the developing roller 133a is rotating, the absolute value of the blade voltage Vbld must be greater than the absolute value of the developing voltage Vdev. For this reason, the voltage generation device of this embodiment is configured to select whether to give the blade voltage Vbld a predetermined potential difference from the developing voltage Vdev or to make it the same potential as the developing voltage Vdev. Specifically, while the developing roller 133a is rotating, the control unit 108 turns off the transistor Tr51 and makes the absolute value of the blade voltage Vbld greater than the absolute value of the developing voltage Vdev by the amount of the Zener voltage of the Zener diode ZD51. Meanwhile, the control unit 108 turns on transistor Tr51 while the developing roller 133a is stopped, making the absolute value of the blade voltage Vbld equal to the absolute value of the developing voltage Vdev.

[0026] The base terminal of transistor Tr51 is connected to its emitter terminal via resistors R51 and R52. Capacitor C51 is connected in parallel to resistor R52. The connection point between resistors R51 and R52 is connected to the anode terminal of diode D51. The cathode terminal of diode D51 is connected to the anode terminal of diode D52, and the cathode terminal of diode D52 is connected to the emitter terminal of transistor Tr51. The cathode terminal of diode D51 is connected to the BLD_SW terminal of CPU181 via capacitor C50. The BLD_SW terminal outputs a pulse signal that alternates between high and low levels. While the pulse signal from the BLD_SW terminal is low level, current flows from the power supply voltage V1 through transistor Tr31, the emitter terminal and base terminal of transistor Tr51, resistor R51, diode D51, and capacitor C50 in that order, and finally flows into the BLD_SW terminal. While the BLD_SW terminal is at a high level, the current flowing from the BLD_SW terminal flows to the power supply voltage V1 via capacitor C50, diode D52, and transistor Tr31. Outputting a pulse signal from the BLD_SW terminal charges capacitor C51, allowing a stable base current to flow from the base terminal of transistor Tr51. When a stable base current flows from the base terminal of transistor Tr51, transistor Tr51 turns on, and the terminals of Zener diode ZD51 are short-circuited. On the other hand, when the BLD_SW terminal is fixed at a high or low level, transistor Tr51 is turned off, and the terminals of Zener diode ZD51 are not short-circuited.

[0027] Figure 3(C) shows the relationship between the duty cycle of the low state of the pulse signal output from the DEV_CONT terminal and the blade voltage Vbld. The solid line represents the state when transistor Tr51 is ON, and the dotted line represents the state when transistor Tr51 is OFF. The difference between the solid and dotted lines is the Zener voltage ΔVz of Zener diode ZD51. For example, if the Zener voltage ΔVz is 100V and the developing voltage Vdev is -300V, the blade voltage Vbld when transistor Tr51 is OFF is -400V.

[0028] Next, the toner supply circuit 134b will be described. The toner supply circuit 134b is a circuit that generates the toner supply voltage Vtsr by dividing the charging voltage Vpri, and has a configuration almost identical to that of the developer circuit 133b. The only difference is that there is no Zener diode in the voltage division line with the charging voltage Vpri. The collector terminal of transistor Tr41 is connected to the charging voltage Vpri via resistor R40, and the emitter terminal of transistor Tr4 is connected to the power supply voltage V1. The base terminal and emitter terminal of transistor Tr41 are connected via resistor R49. The base terminal of transistor Tr41 is also connected to the output terminal of op-amp IC41 via resistor R48. The voltage at the collector terminal of transistor Tr41 becomes the toner supply voltage Vtsr.

[0029] The toner supply circuit 134b also has a feedback control configuration for stably controlling the toner supply voltage Vtsr to a desired voltage. Specifically, the toner supply voltage Vtrs is connected to the power supply voltage V2 via resistors R44 and R43. The connection point between resistors R44 and R43 is connected to the positive input terminal of the operational amplifier IC41. The negative input terminal of the operational amplifier IC41 is connected to the power supply voltage V2 via resistors R46 and R45, and further connected to GND via capacitor C46. The connection point between resistors R45 and R46 is connected to the RS_CONT terminal of the CPU 181. A resistor R47 and a capacitor C47 are connected between the negative input terminal and the output terminal of the operational amplifier IC41. This is for phase compensation of the operational amplifier IC41 and contributes to the stability of the feedback control.

[0030] The RS_CONT terminal outputs a pulse signal that alternates between a Hi-Z state and a Low state. While the RS_CONT terminal is in the Hi-Z state, current flows from the power supply voltage V2 through resistors R45 and R46 to charge capacitor C46. On the other hand, while the RS_CONT terminal is in the Low state, current flows through resistor R46 towards the RS_CONT terminal to discharge capacitor C46. As the RS_CONT terminal alternates between the Hi-Z and Low states, the balance of charging and discharging of capacitor C46 stabilizes at a predetermined voltage, and therefore, the voltage at the negative input terminal of op-amp IC41 also stabilizes at this predetermined voltage. This predetermined voltage is determined by the duty cycle of the pulse signal from the RS_CONT terminal. Specifically, the larger the proportion of the Low state in the pulse signal from the RS_CONT terminal, the lower the voltage at the negative input terminal of op-amp IC41 becomes.

[0031] Here, when the voltage at the negative input terminal of op-amp IC41 is lower than the voltage at the positive input terminal, the output terminal of op-amp IC41 becomes high level, and transistor Tr41 turns off. As a result, the absolute value of the toner supply voltage Vtsr increases. On the other hand, when the voltage at the negative input terminal of op-amp IC41 is greater than or equal to the voltage at the positive input terminal, the output terminal of op-amp IC41 becomes low level, and transistor Tr41 turns on. As a result, the absolute value of the toner supply voltage Vtsr decreases. Therefore, as shown in Figure 3(D), the larger the duty cycle of the low state of the pulse signal output from the RS_CONT terminal, the larger the absolute value of the toner supply voltage Vtsr. As an example, the value of the toner supply voltage Vtsr is -400V.

[0032] The voltage values ​​of each voltage output by each circuit are controlled by the CPU 181 to target values. However, the actual voltage values ​​of each voltage generated may deviate from the target values ​​due to variations in the components that make up each circuit, especially resistors. For example, in the case of the charging circuit 132b, variations in the values ​​of resistors R13 and R14 will cause the charging voltage Vpri to deviate from the target value. Therefore, when the power supply board 107 or the image forming apparatus 101 is shipped, the output voltage is inspected and control information (correction information) is acquired to set the voltage values ​​of each voltage to target values. The non-volatile memory 171 stores the control information (correction information) to set the voltage values ​​of each voltage to target values. As an example, the control information shows the correction value of the target value. The CPU 181 controls each circuit 132b to 135b based on the corrected target value obtained by correcting the target value with the correction value. The correction value is set so that the output of each circuit becomes the target value when the CPU 181 controls each circuit 132b to 135b with the corrected target value.

[0033] As mentioned above, the non-volatile memory 171 is provided on the power supply board 107. While it is conceivable to store the control information in the CPU 181, the CPU 181 and high-voltage circuits such as the charging circuit 132b are often provided on separate boards. Furthermore, if component replacement becomes necessary in the future, these electrical components are replaced on a board-by-board basis. Therefore, if the control information were stored in the CPU 181, when the power supply board 107 is replaced with a new one, the CPU 181 would not be able to perform control operations that are compatible with the new power supply board 107. For this reason, in this embodiment, the non-volatile memory 171 is mounted on the power supply board 107 on which the charging circuit 132b and the like are mounted, and the control information is stored in the non-volatile memory 171.

[0034] The CPU 181 outputs a clock signal to the non-volatile memory 171 in order to read the information stored in the non-volatile memory 171. For this reason, the clock line (signal line) from the CPU 181 is connected to the ROM_CLK_R terminal of the non-volatile memory 171. In addition, the ROM_DATA_C terminal of the CPU 181 and the ROM_DATA_R terminal of the non-volatile memory 171 are connected by a data line (signal line). This data line is used, for example, to send and receive data between the CPU 181 and the non-volatile memory 171.

[0035] In this embodiment, the signal from the BLD_SW terminal used to control the blade circuit 135b is also used as a clock signal for the non-volatile memory 171. Therefore, as shown in Figure 2, the BLD_SW terminal of the CPU 181 is connected to both the capacitor C50 of the blade circuit 135b and the non-volatile memory 171. Specifically, the signal line connected to the BLD_SW terminal of the CPU 181 is split into two; one is connected to the capacitor C50, and the other is connected to the ROM_CLK_R terminal of the non-volatile memory 171. This eliminates the need for one signal line between the control unit 108 and the power supply board 107.

[0036] As described above, in this embodiment, while the developing roller 133a is stopped, a pulse signal is output from the BLD_SW terminal to short-circuit the Zener diode ZD51, thereby reducing the potential difference between the developing roller 133a and the developing blade 135a to approximately 0. At this time, since a pulse signal is output from the BLD_SW terminal, the CPU 181 can communicate with the non-volatile memory 171.

[0037] Meanwhile, while the developing roller 133a is rotating, the control unit 108 fixes the output from the BLD_SW terminal to a high or low level, thereby causing the blade voltage Vbld to differ from the developing voltage Vdev by the Zener voltage ΔVz. At this time, since no pulse signal is output from the BLD_SW terminal, the CPU 181 cannot communicate with the non-volatile memory 171.

[0038] Figure 4 shows the relationship between the rotation state of the developing roller 133a and the control state of the blade circuit 135b. In this embodiment, the CPU 181 cannot communicate with the non-volatile memory 171 while the developing roller 133a is rotating. However, the timing for reading the control information stored in the non-volatile memory 171 is before the image forming operation, that is, while the rotation of the developing roller 133a is stopped. Therefore, this is not a problem if there is no need to access the non-volatile memory 171 while the developing roller 133a is rotating.

[0039] As described above, by sharing the control signal for controlling the blade circuit 135b and the clock signal for the non-volatile memory 171, the number of signal lines connected to the control unit 108 can be reduced by one.

[0040] <Second Embodiment> Next, the second embodiment will be described, focusing on the differences from the first embodiment. In the first embodiment, while the developing roller 133a was rotating, the transistor Tr51 was kept off by outputting a signal fixed to a high or low level, i.e., a signal with a frequency of 0, from the BLD_SW terminal. However, depending on the values ​​of the resistors / capacitors etc. in each circuit of the configuration in Figure 2, the transistor Tr51 will be turned off if the frequency of the pulse signal output from the BLD_SW terminal is below the first threshold. In this case, a clock signal is supplied to the non-volatile memory 171 from the BLD_SW terminal regardless of the rotation state of the developing roller 133a, so the control unit 108 can access the non-volatile memory 171 regardless of the rotation state of the developing roller 133a.

[0041] In this case, to turn on transistor Tr51, the frequency of the pulse signal output from the BLD_SW terminal must be greater than the second threshold. The second threshold may be the same as the first threshold, but in order to stably turn on transistor Tr51, the second threshold must be greater than the first threshold. For example, the first threshold is 15kHz and the second threshold is 30kHz. Figure 5 shows the relationship between the rotation state of the developing roller 133a and the control state of the blade circuit 135b in this embodiment.

[0042] As described above, according to this embodiment, it is possible to share the control signal for controlling the blade circuit 135b and the clock signal for the non-volatile memory 171, while also enabling access to the non-volatile memory 171 during image formation.

[0043] <Other> Although each embodiment has been described using an image forming apparatus as an example of an apparatus having a voltage generating device, the present invention is applicable to any apparatus having a voltage generating device.

[0044] [Other embodiments] The present invention can also be realized by supplying a program that implements one or more of the functions of the above-described embodiments to a system or device via a network or storage medium, and by having one or more processors in the computer of that system or device read and execute the program. It can also be realized by a circuit (e.g., an ASIC) that implements one or more functions.

[0045] This embodiment includes the following configuration. (Configuration 1) A voltage generating device comprising: a first circuit that outputs a first voltage; control means that controls the value of the first voltage output by the first circuit using a control signal; and storage means that stores control information of the first circuit, wherein the control means uses the control signal for communication with the storage means. (Configuration 2) The voltage generating device according to Configuration 1, wherein the control means includes a terminal for outputting the control signal, and the signal line connected to the terminal is connected to both the first circuit and the storage means. (Configuration 3) The voltage generating device according to Configuration 1 or 2, wherein the first circuit and the storage means are provided on the same substrate. (Configuration 4) A voltage generating device according to any one of Configurations 1 to 3, wherein the control information includes information for bringing the value of the first voltage output by the first circuit closer to a target value. (Configuration 5) The voltage generating device according to any one of Configurations 1 to 4, wherein the control means uses the control signal as a clock signal for communicating with the storage means. (Configuration 6) A voltage generating device according to any one of Configurations 1 to 5, wherein the control signal is a pulse signal, and the control means controls the value of the first voltage output by the first circuit according to the frequency of the control signal. (Configuration 7) The voltage generating device according to Configuration 6, wherein the control means controls whether the value of the first voltage output by the first circuit is a first value or a second value different from the first value, based on the frequency of the control signal. (Configuration 8) The voltage generating device according to Configuration 7, wherein the control means sets the frequency of the control signal to a first threshold value when the first voltage is set to the first value. (Configuration 9) The voltage generating device according to Configuration 7, wherein the control means sets the frequency of the control signal to 0 when the first voltage is set to the first value. (Configuration 10) The voltage generating device according to Configuration 8, wherein the control means increases the frequency of the control signal to a second threshold value when the first voltage is set to the second value. (Configuration 11) The voltage generating device according to Configuration 10, wherein the second threshold is equal to or greater than the first threshold. (Composition 12) A voltage generating device described in any one of configurations 1 to 11, Image forming means for forming an image on a recording material using the first voltage, An image forming apparatus equipped with the following features. (Composition 13) The image forming means comprises a photoreceptor and a developing roller for developing the electrostatic latent image formed on the photoreceptor with toner. The image forming apparatus according to configuration 12, wherein the control means sets the value of the first voltage output by the first circuit to a first value while the developing roller is rotating, and sets the value of the first voltage generated by the first circuit to a second value while the developing roller is not rotating. (Composition 14) The circuit further comprises a second circuit that outputs a second voltage of the second value, The second voltage is applied to the first circuit, as described in configuration 13 of the image forming apparatus. (Composition 15) The second voltage is applied to the developing roller, The image forming apparatus according to configuration 14, wherein the first voltage is applied to a developing blade that regulates the thickness of the toner in the developing roller.

[0046] The invention is not limited to the embodiments described above, and various modifications and variations are possible without departing from the spirit and scope of the invention. Accordingly, claims are attached to disclose the scope of the invention. [Explanation of Symbols]

[0047] 135b: Blade circuit, 108: Control unit, 171: Non-volatile memory

Claims

1. a first circuit that outputs a first voltage; image forming means for forming an image on a recording material using the first voltage; control means for controlling the value of the first voltage output by the first circuit by a control signal; storage means for storing control information of the first circuit; comprising the control signal is a pulse signal; the control means controls whether to set the value of the first voltage output by the first circuit to a first value or a second value different from the first value by controlling the frequency of the control signal; an image forming apparatus, wherein the control means uses the control signal for communication with the storage means.

2. the control means includes a terminal for outputting the control signal; the signal line connected to the terminal is connected to both the first circuit and the storage means, and the image forming apparatus according to claim 1.

3. the first circuit and the storage means are provided on the same substrate, and the image forming apparatus according to claim 1.

4. the control information includes information for bringing the value of the first voltage output by the first circuit closer to a target value, and the image forming apparatus according to claim 1.

5. the control means uses the control signal as a clock signal for communicating with the storage means, and the image forming apparatus according to claim 1.

6. when the control means sets the first voltage to the first value, the control means sets the frequency of the control signal to be equal to or less than a first threshold value, and the image forming apparatus according to claim 1.

7. when the control means sets the first voltage to the first value, the control means sets the frequency of the control signal to 0, and the image forming apparatus according to claim 1.

8. when the control means sets the first voltage to the second value, the control means sets the frequency of the control signal to be greater than a second threshold value, and the image forming apparatus according to claim 6.

9. the second threshold value is equal to or greater than the first threshold value, and the image forming apparatus according to claim 8.

10. the image forming means includes a photoreceptor and a developing roller for developing an electrostatic latent image formed on the photoreceptor with toner; while the control means rotates the developing roller, the control means sets the value of the first voltage output by the first circuit to the first value, and while the developing roller is not rotating, the control means sets the value of the first voltage generated by the first circuit to the second value, and the image forming apparatus according to claim 1.

11. further comprising a second circuit that outputs a second voltage of the second value The image forming apparatus according to claim 10, wherein the second voltage is applied to the first circuit.

12. The second voltage is applied to the developing roller, The image forming apparatus according to claim 11, wherein the first voltage is applied to a developing blade that regulates the thickness of the toner on the developing roller.

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