Analog-to-Digital Converter

Abstract

The analog-to-digital converter (ADC) circuit includes a signal input terminal (101), a sample-and-hold circuit (110), and a successive approximation register (SAR) ADC (112). The sample-and-hold circuit (110) includes an input terminal (110A) coupled to the signal input terminal (101). The SAR ADC (112) includes a comparator, a first capacitive digital-to-analog converter (CDAC), and a second CDAC. The first CDAC includes a first input terminal coupled to the signal input terminal, a second input terminal coupled to the output terminal of the sample-and-hold circuit, and an output terminal coupled to the first input terminal of the comparator. The second CDAC includes a first input terminal coupled to the signal input terminal and an output terminal coupled to the second input terminal of the comparator.

Description

[Technical Field]

[0001] Various analog-to-digital data converters and conversion techniques are available to convert electrical signals from the analog domain to the digital domain. Generally, the analog-to-digital conversion process involves sampling the analog signal and comparing the sampled analog signal to a threshold. Depending on the result of the comparison, a binary result is recorded. The process of comparing a sample to a threshold can be repeated multiple times in each successive comparison using different thresholds and the remaining samples. The number of iterations is typically determined by the noise level in a particular iteration, as well as the resolution of the final digital signal.

[0002] A successive approximation register (SAR) converter is an example of an analog-to-digital converter (ADC). A SAR ADC performs a binary lookup of the digital value that best corresponds to the voltage of an analog signal. In a SAR ADC, the voltage input is compared to half of the voltage reference. If the voltage input is greater than half of the voltage reference, a logical "1" is stored in the register. Alternatively, if the voltage input is less than half of the voltage reference, a logical "0" is stored in the register. Next, if the previous comparison showed that the voltage input was greater than half of the voltage reference, the voltage input is compared to three-quarters of the voltage reference. Again, if the comparison shows that it is greater than the condition, a logical "1" is stored in the register. In contrast, if the comparison shows that it is less than the condition, a logical "0" is stored in the register. Alternatively, if the previous comparison showed that the voltage input was less than half of the voltage reference, the voltage input is compared to one-quarter of the voltage reference. Again, if the comparison shows that it is greater than the condition, a logical "1" is stored in the register. In contrast, if the comparison is less than the condition, a logical "0" is stored in the register. This process continues for lower multiples of the voltage reference. As can be seen, the process described above can provide high-resolution ADC results in a relatively short time. In particular, only one iteration may be used to generate each bit of resolution. For example, for 10-bit resolution, theoretically 10 iterations are required, and for 20-bit resolution, theoretically 20 iterations are required. [Overview of the Initiative]

[0003] Disclosed herein is a two-step successive approximation register (SAR) analog-to-digital converter (ADC) that improves coarse SAR ADC resolution through dynamic error correction. In one example, the analog-to-digital converter (ADC) circuit includes a signal input terminal, a sample-and-hold circuit, and a successive approximation register (SAR) ADC. The sample-and-hold circuit includes an input terminal coupled to the signal input terminal. The SAR ADC includes a comparator, a first capacitive digital-to-analog converter (CDAC), and a second CDAC. The first CDAC includes a first input terminal coupled to the signal input terminal, a second input terminal coupled to the output terminal of the sample-and-hold circuit, and an output terminal coupled to the first input terminal of the comparator. The second CDAC includes a first input terminal coupled to the signal input terminal and an output terminal coupled to the second input terminal of the comparator.

[0004] In another example, an analog-to-digital converter (ADC) circuit includes a sample-and-hold circuit and a SAR ADC. The sample-and-hold circuit is configured to sample the input signal to be digitized. The SAR ADC is coupled to the sample-and-hold circuit and configured to digitize the input signal. The SAR ADC includes a comparator, a first CDAC, and a second CDAC. The first CDAC is coupled to the first input of the comparator and configured to sample the input signal to be digitized and to sample the output of the sample-and-hold circuit. The second CDAC is coupled to the second input of the comparator and configured to sample the input signal to be digitized.

[0005] In a further example, the ADC circuit includes a first signal input terminal, a second signal input terminal, a first sample-and-hold circuit, a second sample-and-hold circuit, and a SAR ADC. The first sample-and-hold circuit includes an input terminal coupled to the first signal input terminal. The second sample-and-hold circuit includes an input terminal coupled to the second signal input terminal. The SAR ADC includes a comparator, a first CDAC, and a second CDAC. The first CDAC includes a first input terminal coupled to the first signal input terminal, a second input terminal coupled to the output terminal of the first sample-and-hold circuit, and an output terminal coupled to the first input terminal of the comparator. The second CDAC includes a first input terminal coupled to the second signal input terminal, a second input terminal coupled to the output terminal of the second sample-and-hold circuit, and an output terminal coupled to the second input terminal of the comparator.

[0006] For detailed explanations of various examples, please refer to the attached drawings. [Brief explanation of the drawing]

[0007] [Figure 1] A block diagram for a two-step successive approximation register (SAR) analog-to-digital converter (ADC) as described herein is shown.

[0008] [Figure 2] A schematic diagram of the sample-and-hold circuit and buffer according to this description is shown.

[0009] [Figure 3] A block diagram for the first stage of a two-step SAR ADC with dynamic error connectivity, as described herein, is shown.

[0010] [Figure 4] A schematic diagram for a crude SAR ADC, as described here, is shown.

[0011] [Figure 5]The timing diagram for digitization in a crude SAR ADC, as described here, is shown.

[0012] [Figure 6] A block diagram for a differential input 2-step SAR ADC, as described herein, is shown.

[0013] [Figure 7] A schematic diagram for a differential input coarse SAR ADC, as described here, is shown. [Modes for carrying out the invention]

[0014] In this specification, the term “to connect” means either an indirect or direct wired or wireless connection. Therefore, when a first device connects to a second device, the connection may be via a direct connection or via an indirect connection through other devices and connections. Also, in this specification, “based on” means “at least partially based on.” Thus, when X is based on Y, X may be a function of Y and any number of other factors.

[0015] In a two-step successive approximation register (SAR) analog-to-digital converter (ADC), the resolution of the coarse-stage SAR ADC is limited by sampling bandwidth mismatch, clock skew, and other factors. Some two-step SAR ADCs attempt to provide improved resolution by using a sample-and-hold amplifier or by merging the coarse ADC's capacitive analog-to-digital converter (CDAC) with the main CDA. However, the sample-and-hold amplifier consumes excessive power, and merging the coarse ADC CDAC with the main CDA limits the conversion speed.

[0016] The two-step SAR ADC disclosed herein increases coarse ADC resolution by reducing errors associated with sampling bandwidth mismatch without adding sample-hold amplifiers or merging coarse ADC CDACs with primary CDACs. The two-step SAR ADC disclosed herein compensates for signal-dependent residuals in different sampling paths by modifying the search target of the coarse SAR ADC during conversion. In the implementation, a downscaled replica of the primary CDAC is used to generate the sampled input voltage of the primary CDAC, and the sampled input voltage is applied to the coarse ADC CDAC to adjust the search target of the coarse SAR ADC. The adjusted search target compensates for errors in different sampling paths.

[0017] Figure 1 shows a block diagram for a two-step successive approximation register (SAR) analog-to-digital converter (ADC) 100 according to this description. The two-step SAR ADC 100 includes a first stage 102, a second stage 104, and an output circuit element 106. The two-step SAR ADC 100 generates an M-bit digital output representing an analog signal received at a signal input terminal 101. The first stage 102 generates a predetermined number of the most significant bits of the M bits, and the second stage 104 generates the remainder of the M bits. For example, in an implementation of the two-step SAR ADC 100 that generates a 16-bit output, the first stage 102 generates six most significant bits (with one or more additional redundant bits), and the second stage 104 generates ten least significant bits. The output circuit element 106 receives the digital values ​​generated by the first stage 102 and the second stage 104, and combines these digital values ​​(e.g., concatenated with overlap) to generate a digital output value. The two-step architecture allows for a reduction in the size of the capacitors used in the first stage 102 and the second stage 104.

[0018] The first stage 102 includes a sample-and-hold circuit 108, a sample-and-hold circuit 110, a SAR ADC 112, a digital-to-analog converter (DAC) 114 (main DAC), a subtraction circuit element 116, and a residue amplifier 118. The sample-and-hold circuit 108, the sample-and-hold circuit 110, and the SAR ADC 112 are coupled to a signal input terminal 101. The sample-and-hold circuit 108 includes an input terminal 108A coupled to the signal input terminal 101, the sample-and-hold circuit 110 includes an input terminal 110A coupled to the signal input terminal 101, and the SAR ADC 112 includes an input terminal 112A coupled to the signal input terminal 101. Each of the sample-and-hold circuit 108, the sample-and-hold circuit 110, and the SAR ADC 112 acquires a sample of an input signal 103 to be digitized as provided at the signal input terminal 101. An output terminal 112B of the SAR ADC 112 is coupled to an output circuit element 106 and an input terminal 114A of the DAC 114. The SAR ADC 112 digitizes the acquired sample and provides a digital value 120 to the output circuit element 106 and the DAC 114. The DAC 114 converts the digital value 120 into an analog voltage 122. The subtraction circuit element 116 is coupled to the sample-and-hold circuit 108, the DAC 114, and the residue amplifier 118. The subtraction circuit element 116 subtracts the analog voltage 122 from the sample 124 provided by the sample-and-hold circuit 108 to generate a residue signal 126 representing the total unadjusted error of the SAR ADC 112. The residue amplifier 118 is coupled to the subtraction circuit element 116 and amplifies the residue signal 126 to generate an amplified residue signal 128.

[0019] The second stage 104 includes a SAR ADC 130. The SAR ADC 130 is coupled to the residue amplifier 118 and digitizes the amplified residue signal 128 to generate a digital value 132. The SAR ADC 130 provides the digital value 132 to the output circuit element 106 for combination with the digital value 120.

[0020] The sample - hold circuit 110 is a down - scaled version of the sample - hold circuit 108. The sample - hold circuit 110 includes an input terminal 110A coupled to the signal input terminal 101 and an output terminal 110B coupled to the input terminal 112C of the SAR ADC 112. For any given sample 124 acquired by the sample - hold circuit 108, the sample - hold circuit 110 acquires a sample 134 having the same voltage as the sample 124. FIG. 2 shows a schematic diagram for the implementation of the sample - hold circuit 110 according to this description. The sample - hold circuit 108 and the SAR ADC 112 are also shown in FIG. 2 for reference. In FIG. 2, the sample - hold circuit 108 includes a higher capacitance and a lower resistance than the sample - hold circuit 110. The ratio of the capacitance and resistance of the sample - hold circuit 110 to the capacitance and resistance of the sample - hold circuit 108 varies in different implementations of the 2 - step SAR ADC 100.

[0021] The sample - hold circuit 110 includes a sampling capacitor 202, resistors 204 (representing switch resistance), resistors 206 (representing switch resistance), switches 208, 210, an amplifier 212, switches 214, 216, and switch 218. Switches 208 and 210 are closed when sampling the input signal 103 and open when sampling is complete and the sample - hold circuit 110 is in the hold state. The amplifier 212 buffers the voltage across the sampling capacitor 202 for providing to the SAR ADC 112. During sampling (e.g., at the sample interval), switches 214 and 216 are open and switch 218 is closed, disconnecting the sampling capacitor 202 from the amplifier 212. Similarly, when the sample - hold circuit 110 is in the hold state (e.g., the hold interval), switches 214 and 216 are closed and switch 218 is open, connecting the sampling capacitor 202 to the amplifier 212.

[0022] The amplifier 212 includes an input terminal 212A connected to the sampling capacitor 202 via a switch 214, and an output terminal 212B connected to the input terminal 112C of the SAR ADC 112. The switch 214 includes a terminal 214A connected to terminal 202B of the sampling capacitor 202, and a terminal 214B connected to the input terminal 212A of the amplifier 212. The switch 216 includes a terminal 216A connected to terminal 202A of the sampling capacitor 202, and a terminal 216B connected to the output terminal 212B of the amplifier 212. The switch 218 includes a terminal 218A connected to the output terminal 212B of the amplifier 212, and a terminal 218B connected to the input terminal 212A of the amplifier 212.

[0023] Figure 3 shows a block diagram of the coarse SAR ADC 300. The coarse SAR ADC 300 is an implementation of the SAR ADC 112. The coarse SAR ADC 300 includes a sampling network 302 for sampling the input signal 103. The sampled signal 308 (V n2 ) is provided to the output of sampling network 302. However, due to the difference in sampling bandwidth, the sampled signal 308 is provided by sample 134 (V) provided by sample-and-hold circuit 110. n1 This is different from the previous example. As explained earlier, sample 134 is the same sample 124 from which the residual signal 126 is derived. The coarse SAR ADC 300 compensates for the difference between sample 134 and the sampled signal 308 by taking the difference between sample 134 and the sampled signal 308 and subtracting that difference from the sampled signal 308, thereby generating a voltage 304 that is the same as the voltage of sample 134 for use as a reference in digitization.

[0024] Figure 4 shows a schematic diagram of the crude SAR ADC400 according to this description. The SAR ADC400 is an implementation of the SAR ADC112 and SAR ADC300. The SAR ADC400 includes CDAC402, CDAC404, comparator 406, SAR control circuit 408, switch 410, and switch 412. The CDAC402 includes a binary weighted capacitor 414 and switch 416. Switch 416 can connect the bottom plate of the binary weighted capacitor 414 to input terminal 112A or input terminal 112C, thereby controlling the binary weighted capacitor 414 to charge the input signal 103 or sample 134. The CDAC402 includes an output terminal 402A coupled to the input terminal 406A of the comparator 406, an input terminal 402b coupled to the input terminal 112C of the SAR ADC112, and an input terminal 402C coupled to the input terminal 112A of the SAR ADC112. The top plate of the binary weighted capacitor 414 is coupled to the output terminal 402A.

[0025] Similarly, the CDAC404 includes a binary weighted capacitor 418 and a switch 420. Switch 420 can be controlled to connect the bottom plate of the binary weighted capacitor 418 to input terminal 112A, a reference voltage source, or a common voltage source (e.g., ground). Switches 410 and 412 can be controlled to connect the top plates of the binary weighted capacitors 414 and 418 to ground, respectively. The CDAC404 includes an output terminal 404A coupled to input terminal 406B of comparator 406 and an input terminal 404C coupled to input terminal 112A of SAR ADC112. The top plate of the binary weighted capacitor 418 is coupled to output terminal 404A.

[0026] Comparator 406 compares the voltage on the top plate of binary weighted capacitor 418 with the voltage on the top plate of binary weighted capacitor 414 and provides the result of the comparison to SAR control circuit 408. SAR control circuit 408 is coupled to comparator 406, CDAC 402, and CDAC 404 and sets the bits of digital value 120 based on the result of the comparison. SAR control circuit 408 generates switch control signals 422 that control switches 410, 412, 416, and 420. Based on the output of comparator 406, SAR control circuit 408 determines how switch 420 should be set and activates the switch control signal 422 accordingly.

[0027] At the start of the digitization (acquisition phase) of each sample, the SAR control circuit 408 sets switches 416 and 420 to connect the bottom plates of binary weighted capacitors 414 and 418 to input terminal 112A of the SAR ADC 112, thereby charging binary weighted capacitors 414 and 418 to the input signal 103. After the SAR control circuit 408 selects one or more bits of the digital value 120 (the number of bits is based on the redundancy required to correct dynamic errors), the SAR control circuit 408 sets switch 416 of the CDAC 402 to connect the bottom plate of binary weighted capacitor 414 to input terminal 112C of the SAR ADC 112, thereby applying sample 134 to the bottom plate of binary weighted capacitor 414. As a result, the voltage on the top plate of the binary weighted capacitor 414 is set to the voltage of sample 134, which is lower than the voltage previously sampled from input terminal 112A (i.e., Vn1-Vn2). Therefore, the reference voltage applied to comparator 406 is set from zero to V n1 -V n2 The shift will continue, and the standards will be changed from scratch. n1 -V n2By shifting to, the voltage digitized by the SAR ADC400 is not the voltage sampled by the binary weighted capacitor 418 from the input terminal 112A, but is substantially the voltage of the sample 134.

[0028] FIG. 5 shows a timing diagram for digitization using the SAR ADC400 as a coarse SAR ADC in a two-step SAR ADC100. At interval 502, the sample-and-hold circuit 108, the sample-and-hold circuit 110, the CDAC402, and the CDAC404 sample the input signal 103. At the end of interval 502, the switches 214 and 216 are closed and the output of the amplifier 212 settles over interval 504. At the end of interval 502, the switch 416 is set to disconnect the signal input terminal 101 from the binary weighted capacitor 414. During interval 514, the bottom plate of the capacitor 416 is floating. At the end of interval 504, just before the DEC bit interval, the switch 416 is set to connect the output terminal 110B of the sample-and-hold circuit 110 to the binary weighted capacitor 414, so that the top plate of the binary weighted capacitor 414 is V n1 -V n2 becomes. At interval 504, the error of the selected bit is determined (the error associated with the use of zero as the reference on interval 504). In some embodiments, after digitization by the two-step SAR ADC100, the error is corrected digitally. At interval 508, the remaining bit determination is made in the SAR ADC400 using the reference voltage (not zero as in the prior art) V n1 -V n2 applied at 406A of the comparator 406.

[0029] Figure 6 shows a block diagram for the differential input two-step SAR ADC600 according to this description. The differential input two-step SAR ADC600 includes a first stage 602, a second stage 604, and an output circuit element 606. The first stage 602 includes a sample-and-hold circuit 608, a sample-and-hold circuit 609, a sample-and-hold circuit 610, a sample-and-hold circuit 611, a SAR ADC612, a digital-to-analog converter (DAC) 614 (main DAC), a subtraction circuit element 616, and a residual amplifier 618. Sample-and-hold circuits 608, 610, and SAR ADC612 are coupled to signal input terminal 601. Sample-and-hold circuits 609, 611, and SAR ADC612 are coupled to signal input terminal 603. The sample-and-hold circuit 608 includes an input terminal 608A coupled to the signal input terminal 601, the sample-and-hold circuit 610 includes an input terminal 610A coupled to the signal input terminal 601, and the SAR ADC 612 includes an input terminal 612A coupled to the signal input terminal 601. Each of the sample-and-hold circuits 608, 610, and 612 receives an input signal 605(V) to be digitized, as provided at the signal input terminal 601. IN+ Get a sample of ).

[0030] The sample-and-hold circuit 609 includes an input terminal 609A coupled to the signal input terminal 603, the sample-and-hold circuit 611 includes an input terminal 611A coupled to the signal input terminal 603, and the SAR ADC 612 includes an input terminal 612E coupled to the signal input terminal 603. Each of the sample-and-hold circuits 609, 611, and 612 receives an input signal 607(V) to be digitized, as provided at the signal input terminal 603. IN- Get a sample of ).

[0031] Sample-and-hold circuits 608 and 609 are implementations of sample-and-hold circuit 108. Sample-and-hold circuits 610 and 611 are implementations of sample-and-hold circuit 110. Sample-and-hold circuit 610 is a downscaled version of sample-and-hold circuit 608, and sample-and-hold circuit 611 is a downscaled version of sample-and-hold circuit 609. Sample-and-hold circuit 610 includes an input terminal 610A coupled to signal input terminal 601 and an output terminal 610B coupled to input terminal 612C of the SAR ADC 612. For any given sample 624 obtained by sample-and-hold circuit 608, sample-and-hold circuit 610 obtains a sample 634 having the same voltage as sample 624. The sample-and-hold circuit 611 includes an input terminal 611A coupled to the signal input terminal 603 and an output terminal 611B coupled to the input terminal 612D of the SAR ADC 612. For any given sample 644 acquired by the sample-and-hold circuit 609, the sample-and-hold circuit 611 acquires a sample 635 having the same voltage as sample 644.

[0032] Figure 7 shows a schematic diagram for the differential input coarse SAR ADC700 according to this description. The differential input coarse SAR ADC700 is an implementation of the SAR ADC612. The differential input coarse SAR ADC700 includes CDAC702, CDAC704, CDAC714, CDAC716, comparator 706, SAR control circuit 708, switches 710, 712, 718, and 720. The SAR control circuit 708 is coupled to comparator 706, CDAC702, CDAC704, CDAC714, and CDAC716. CDAC702, CDAC704, CDAC714, and CDAC716 include binary weighted capacitors and switches. In the CDAC702, a switch can control the capacitor by connecting its bottom plate to input terminal 612E or input terminal 612D, thereby charging the capacitor to the voltage of input signal 607 or sample 635. The CDAC702 includes an output terminal 702A coupled to input 706D of comparator 706, an input terminal 702B coupled to input terminal 612D, and an input terminal 702C coupled to input terminal 612E. The top plate of the capacitor in the CDAC702 is coupled to output terminal 702A. In the CDAC702, a switch can control the capacitor by connecting its bottom plate to input terminal 612E or input terminal 612D, thereby charging the capacitor to the voltage of input signal 607 or sample 635.

[0033] The CDAC716 includes an output terminal 716A coupled to the input 706C of the comparator 706, an input terminal 716B coupled to the input terminal 612C, and an input terminal 716C coupled to the input terminal 612A of the SAR ADC612. The top plate of the capacitor of the CDAC716 is coupled to the output terminal 716A. In the CDAC716, a switch can be used to control the bottom plate of the capacitor of the CDAC716 to be connected to either the input terminal 612A or the input terminal 612C, thereby charging the capacitor to the voltage of the input signal 605 or sample 634.

[0034] The CDAC704 includes an output terminal 704A coupled to input 706B of comparator 706, and an input terminal 704B coupled to input terminal 612E. The top plate of the capacitor in the CDAC704 is coupled to output terminal 704A. A switch in the CDAC704 can be controlled to connect the bottom plate of the capacitor to input terminal 612E, a reference voltage source, or a common voltage source (e.g., ground).

[0035] The CDAC714 includes an output terminal 714A coupled to the input 706A of comparator 706, and an input terminal 714B coupled to the input terminal 612A. The top plate of the capacitor in the CDAC714 is coupled to the output terminal 714A. A switch in the CDAC714 can control the bottom plate of the capacitor to connect to the input terminal 612A, a reference voltage source, or a common voltage source (e.g., ground).

[0036] At the start of digitization for each sample, the SAR control circuit 708 switches the CDAC702 and CDAC704 capacitors to connect the bottom plates of the CDAC702 and CDAC704 capacitors to the signal input terminal 603, and charges the CDAC702 and CDAC704 capacitors to the voltage of the input signal 607. After the SAR control circuit 708 selects the value of one or more bits of the digital value 620, the SAR control circuit 708 switches the CDAC702 capacitor via the switch control signal 722, disconnecting the bottom plate of the CDAC702 capacitor from the signal input terminal 603, and connecting the bottom plate of the CDAC702 capacitor to the output 611B of the sample-and-hold circuit 611, and charges the capacitor to the voltage of sample 635. As a result, the voltage on the top plate of the CDAC702 capacitor is set to the voltage of sample 635, which is lower than the previously sampled voltage of the input signal 607.

[0037] Similarly, at the start of digitization for each sample, the SAR control circuit 708 switches the CDAC714 and CDAC716 capacitors to connect the bottom plates of the CDAC714 and CDAC716 capacitors to the signal input terminal 601, and charges the CDAC714 and CDAC716 capacitors to the voltage of the input signal 605. After the SAR control circuit 708 selects a value for one or more bits of the digital value 620, the SAR control circuit 708 switches the CDAC716 capacitor to disconnect the bottom plate of the CDAC716 capacitor from the signal input terminal 601, and connects the bottom plate of the CDAC716 capacitor to the output 610B of the sample-and-hold circuit 610, and charges the capacitor to the voltage of sample 634. As a result, the voltage on the top plate of the CDAC716 capacitor is set to the voltage of sample 634, which is lower than the previously sampled voltage of the input signal 605.

[0038] Within the scope of the claims of the present invention, modifications may be made to the exemplary embodiments described, and other embodiments are possible.

Claims

1. 1. An analog-to-digital converter (ADC) circuit, comprising: A signal input terminal; a first sample and hold circuit having an input terminal coupled to the signal input terminal and an output terminal; a first successive approximation register (SAR) ADC, a comparator having a first input terminal and a second input terminal; a first capacitive digital-to-analog converter (CDAC), the first CDAC having a first input terminal coupled to the signal input terminal, a second input terminal coupled to an output terminal of the first sample and hold circuit, and an output terminal coupled to a first input terminal of the comparator; a second CDAC including a first input terminal coupled to the signal input terminal and an output terminal coupled to a second input terminal of the comparator; and the first SAR ADC, 1. An ADC circuit comprising:

2. 2. The ADC circuit of claim 1, the first sample and hold circuit a sampling capacitor having a first terminal and a second terminal; an amplifier having an input terminal coupled to the sampling capacitor and an output terminal coupled to a second input terminal of the first CDAC; 1. An ADC circuit comprising:

3. 3. The ADC circuit of claim 2, the first sample and hold circuit a first switch having a first terminal coupled to the first terminal of the sampling capacitor and a second terminal coupled to the input terminal of the amplifier; a second switch having a first terminal coupled to the second terminal of the sampling capacitor and a second terminal coupled to the output terminal of the amplifier; a third switch having a first terminal coupled to the output terminal of the amplifier and a second terminal coupled to the input terminal of the amplifier; The ADC circuit further comprises:

4. 2. The ADC circuit of claim 1, The ADC circuit further includes a second sample and hold circuit having an input terminal coupled to the signal input terminal.

5. 5. The ADC circuit of claim 4, a main digital-to-analog converter (DAC) having an input coupled to the output of the first SAR ADC; subtraction circuitry coupled to the main DAC and to the second sample and hold circuit; The ADC further comprises:

6. 6. The ADC circuit of claim 5, a residue amplifier coupled to the subtraction circuitry; a second SAR ADC coupled to the residue amplifier; The ADC further comprises:

7. 2. The ADC circuit of claim 1, the first CDAC includes a plurality of capacitors; the first SAR ADC is a SAR control circuit coupled to the comparator and the first CDAC, wherein in a given bit decision cycle: disconnecting the bottom plates of the plurality of capacitors of the first CDAC from the signal input terminal; connecting the bottom plate to the first sample and hold circuit; The ADC circuit further comprises the SAR control circuit configured to:

8. 1. An analog-to-digital converter (ADC) circuit, comprising: a first sample and hold circuit configured to sample the input signal to be digitized; a first successive approximation register (SAR) ADC coupled to the first sample and hold circuit and configured to digitize the input signal, a comparator having a first input terminal and a second input terminal; a first capacitive digital-to-analog converter (CDAC) coupled to a first input terminal of the comparator, sampling the input signal to be digitized; sampling the output of the first sample and hold circuit; the first CDAC configured as follows: a second CDAC coupled to a second input terminal of the comparator, the second CDAC configured to sample the input signal to be digitized; the first SAR ADC, 1. An ADC circuit comprising:

9. 9. The ADC circuit of claim 8, a SAR control circuit coupled to the comparator, the first CDAC, and the second CDAC, setting a switch of the first CDAC to charge a capacitor of the first CDAC to a voltage of the input signal to be digitized during selection of a first bit; setting a switch of the first CDAC to charge a capacitor of the first CDAC to a voltage of the output of the first sample and hold circuit during selection of a second bit; The ADC circuit further comprises the SAR control circuit configured to:

10. 10. The ADC circuit of claim 9, The ADC circuit, wherein the first CDAC is further configured to provide a voltage to the comparator equal to a difference between a voltage of the input signal to be digitized and a voltage of an output of the first sample and hold circuit.

11. 9. The ADC circuit of claim 8, a second sample and hold circuit configured to sample the input signal to be digitized; The ADC, wherein the first sample and hold circuit is a downscaled version of the second sample and hold circuit.

12. 9. The ADC circuit of claim 8, the first sample and hold circuit A sampling capacitor; An amplifier; a switch configured to disconnect the amplifier from the sampling capacitor during a sample interval and connect the amplifier to the sampling capacitor during a hold interval; 1. An ADC circuit comprising:

13. 9. The ADC circuit of claim 8, a main DAC coupled to the first SAR ADC, the main DAC configured to generate a voltage corresponding to a digital value generated by the SAR ADC; subtraction circuitry coupled to the main DAC, the subtraction circuitry configured to generate a difference between an output of the first sample and hold circuit and a voltage generated by the main DAC; The ADC further comprises:

14. 14. The ADC circuit of claim 13, a residue amplifier coupled to the subtraction circuitry, the residue amplifier configured to amplify an output of the subtraction circuitry; a second SAR ADC coupled to the residue amplifier, the second SAR ADC configured to digitize an output of the residue amplifier; and The ADC further comprises:

15. An ADC circuit, a first signal input terminal; a second signal input terminal; a first sample and hold circuit having an input terminal coupled to the first signal input terminal and an output terminal; a second sample and hold circuit having an input terminal coupled to the second signal input terminal and an output terminal; 1. A successive approximation register (SAR) ADC, comprising: a comparator having a first input terminal and a second input terminal; a first capacitive digital-to-analog converter (CDAC) having a first input terminal coupled to the first signal input terminal, a second input terminal coupled to an output terminal of the first sample and hold circuit, and an output terminal coupled to a first input terminal of the comparator; a second CDAC having a first input terminal coupled to the second signal input terminal, a second input terminal coupled to an output terminal of the second sample and hold circuit, and an output terminal coupled to the second input terminal of the comparator; a SAR ADC including:

1. An ADC circuit comprising:

16. 16. The ADC of claim 15, The SAR ADC is a third CDAC having a first input terminal coupled to the first signal input terminal and an output terminal coupled to a third input terminal of the comparator; a fourth CDAC having a first input terminal coupled to the second signal input terminal and an output terminal coupled to a fourth input terminal of the comparator; and The ADC further comprises:

17. 16. The ADC of claim 15, the first sample and hold circuit a first sampling capacitor having a first terminal and a second terminal; a first amplifier having an input terminal and an output terminal coupled to the second input terminal of the first CDAC; a first switch having a first terminal coupled to the first terminal of the first sampling capacitor and a second terminal coupled to the input terminal of the first amplifier; a second switch having a first terminal coupled to the second terminal of the first sampling capacitor and a second terminal coupled to the output terminal of the first amplifier; a third switch having a first terminal coupled to the output terminal of the first amplifier and a second terminal coupled to the input terminal of the first amplifier; 1. An ADC circuit comprising:

18. 18. The ADC of claim 17, the second sample and hold circuit a second sampling capacitor having a first terminal and a second terminal; a second amplifier having an input terminal and an output terminal coupled to the second input terminal of the second CDAC; a third switch having a first terminal coupled to the first terminal of the second sampling capacitor and a second terminal coupled to the input terminal of the second amplifier; a fourth switch having a first terminal coupled to the second terminal of the second sampling capacitor and a second terminal coupled to the output terminal of the second amplifier; a fifth switch having a first terminal coupled to the output terminal of the second amplifier and a second terminal coupled to the input terminal of the second amplifier; 1. An ADC circuit comprising:

19. 16. The ADC circuit of claim 15, a third sample and hold circuit coupled to the first input terminal, the first sample and hold circuit being a downscaled version of the third sample and hold circuit; a fourth sample and hold circuit coupled to the second input terminal, the second sample and hold circuit being a downscaled version of the fourth sample and hold circuit; The ADC circuit further comprises:

20. 16. The ADC of claim 15, a SAR control circuit coupled to the comparator, the first CDAC, and the second CDAC, wherein in a given bit decision cycle: disconnecting a bottom plate of a capacitor of the first CDAC from the first signal input terminal; connecting a bottom plate of the capacitor of the first CDAC to the first sample and hold circuit; disconnecting the bottom plate of the capacitor of the second CDAC from the second signal input terminal; connecting the bottom plate of the capacitor of the second CDAC to the second sample and hold circuit; The ADC circuit further comprises the SAR control circuit configured to:

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