Quantum Data Loader

Abstract

The present disclosure relates generally to the fields of quantum algorithms and quantum data loading, and more specifically to constructing quantum circuits for loading classical data into quantum states, which may reduce the computational resources of the circuit (e.g., the number of qubits, the depth of the quantum circuit, and the types of gates in the circuit).

Description

[Technical Field]

[0001] This disclosure relates in general to the fields of quantum algorithms and quantum data loading, and more specifically to constructing quantum circuits for loading classical data into quantum states, thereby reducing the computational resources of the circuit (e.g., the number of qubits, the depth of the quantum circuit, and the type of gates in the circuit). [Background technology]

[0002] Many quantum machine learning and optimization algorithms load classical data into quantum states, which is done to use quantum procedures for tasks such as classification, clustering, or solving linear systems. For this reason, these algorithms are unlikely to be available anytime soon, because these loaders, also known as quantum RAM (QRAM, Quantum Random Access Memory), are large and complex circuits in terms of both the number of qubits and the depth of the quantum circuit. For example, a conventional QRAM circuit has a depth of O(n), where n is the dimension of the vector representing the classical data points. [Brief explanation of the drawing]

[0003] Embodiments of this disclosure, when viewed in conjunction with the embodiments of the accompanying drawings, have other advantages and features that will become more readily apparent from the following detailed description and the accompanying claims.

[0004] [Figure 1A] This is a schematic diagram representing a quantum circuit used to load classical data into a quantum state using a single parameterized two-qubit gate (referred to as BS), according to an embodiment. [Figure 1B] This is a schematic diagram representing a quantum circuit used to load classical data into a quantum state using a single parameterized 2-qubit gate (referred to as BS) and its controlled version (referred to as c-BS), according to different embodiments. [Figure 2] This is a schematic diagram illustrating an example of applying a quantum data loader to estimate the distance (or equivalently, the inner product) between two data points, according to an embodiment. [Figure 3] This is a schematic diagram illustrating an example of applying a quantum data loader to estimate the distance (or equivalently, the inner product) between two data points, according to another embodiment. [Figure 4A] This is a schematic diagram illustrating an example of a hardware implementation of a quantum data loader using superconducting qubits, according to several embodiments. [Figure 4B] This is a schematic diagram illustrating an example of a hardware implementation of a quantum data loader using superconducting qubits, according to several embodiments. [Figure 5A] This is a schematic diagram showing several embodiments of hardware implementations of quantum data loaders using linear optical systems. [Figure 5B] This is a schematic diagram showing several embodiments of hardware implementations of quantum data loaders using linear optical systems. [Figure 6] Block diagram showing components of an exemplary computing system according to an embodiment, which can read instructions from a machine-readable medium and execute them on one or more processors (including a quantum processor).

[0005] The drawings illustrate various embodiments for illustrative purposes only. Those skilled in the art will readily recognize from the following discussion that alternative embodiments of the structures and methods shown herein can be employed without departing from the principles described herein, for example, by modifying the details of the BS gate. [Modes for carrying out the invention]

[0006] The figures and the following description relate to preferred embodiments for purposes of illustration only. It should be noted that from the following discussion, alternative embodiments of the structures and methods disclosed herein can be readily recognized as viable alternatives that can be employed without departing from the principles of the claims.

[0007] In this specification, a novel circuit configuration for loading classical data into a quantum computer, which can reduce both the number of qubits and the depth of the quantum circuit, will be described.

[0008] Part 1: Methods for Loading Classical Data into Quantum States In one aspect, a classical data point is represented by an n-dimensional vector (x1, x2, …, x n ), where x i is a real number and the Euclidean norm of the vector is 1. For purposes of clarity in presenting this aspect, it is assumed that n is a power of 2, although our method can be generalized.

[0009] What we will describe is a specific implementation example of a circuit that can efficiently create a quantum state encoding this classical data from the classical data point (x1, x2, …, x n ), specifically involving the creation of the following state:

Equation

[0010] The first step is to classically calculate a set of angles (θ1, θ2, …, θ n ) from the classical data point (x1, x2, …, x n-1 ). In one aspect, the angles are calculated as follows:

[0011]

Equation

[0012] The first n / 2 - 1 values (i.e., r1, r2,..., r n / 2-1 ) are also defined. Since the index j takes values within the interval [1, n / 2], the values are defined as follows:

Number

Number

[0013] The first n / 2 - 1 values (i.e., θ1, θ2,..., θ n / 2-1 ) are also defined. Since the index j takes values within the interval [1, n / 2], the values are defined as follows:

Number

[0014] There may also be similar methods for setting the values of angles, and they also belong to the same category as our method.

Number

number

[0015] In some cases, a controlled version of the BS(θ) gate is used, which is called c-BS(θ). Similar to other controlled gates, this gate is defined as follows:

number

[0016] In other words, this is a 3-qubit gate where, if the first qubit (control qubit) is in the |0> state, the identity matrix (Id) is applied to the second and third qubits (target qubits), and if the first qubit is in the |1> state, the (BS(θ)) gate is applied to the second and third qubits.

[0017] An exemplary method for constructing this circuit is described below, and it is referred to as the "parallel" loader. It begins by initializing all qubits to a state of 0. In the first step, an X gate is applied to the first qubit. Then, the circuit is constructed by adding BS gates hierarchically using the previously constructed angle θ. The first layer has one BS gate, the second layer has two BS gates, the third layer has four BS gates, and so on, up to the lognth layer which has n / 2 gates. The total number of BS gates is n-1, which is exactly the same as the number of angles θ calculated previously. The qubits to which gates are added follow a tree structure (e.g., a binary tree structure). For the first layer, there is one BS gate between qubits (0,n / 2) with angle θ1; for the second layer, there are two BS gates between (0,n / 4) with angle θ2 and (n / 2,3n / 4) with angle θ3; for the third layer, there are four BS gates between (0,n / 8) with angle θ4, (n / 4,3n / 8) with angle θ5, (n / 2,5n / 8) with angle θ6, and (3n / 4,7n / 8) with angle θ7; and so on for the other layers.

[0018] Figure 1A shows one specific implementation example of our method for loading 8-dimensional data points (x1, x2, ..., x8). In Figure 1A, T is the time step, q0-q7 are qubits, X is the X gate, and the vertical lines indicate which qubit the BS gate is applied to. A similar notation is used in Figures 1B-3. In Figure 1A, the X gate is applied to qubit q0 in the first layer, and subsequent layers apply BS gates according to a binary tree pattern, with q0 as the root node of the tree. The gate BS in Figure 1A is taken from left to right and from top to bottom, with angles (θ1, θ2, ..., θ7) as parameters, which can be calculated according to our explanation or a similar explanation. The number of qubits used in a quantum circuit, the depth of the circuit, and the number of gates for 2-qubit and 3-qubit circuits are generally as follows, although they will be discussed later for different dimensions:

[0019] In the case of 8 dimensions: Number of qubits = 8; depth = 4; number of 2-qubit gates = 7; number of 3-qubit gates = 0.

[0020] For 1024 dimensions: Number of qubits = 1024; Depth = 11; Number of 2-qubit gates = 1023; Number of 3-qubit gates = 0.

[0021] n-dimensional: Number of qubits = n; depth = log(n) + 1; number of 2-qubit gates = n-1; number of 3-qubit gates = 0.

[0022] Since the depth of a circuit can correspond to the execution time or time complexity of the circuit, a vector can be converted to a quantum state in ~ O(log(n)) time.

[0023] The following describes an exemplary quantum circuit for a parallel loader: A quantum circuit is created for use in encoding an n-dimensional vector representing classical data into an n-qubit quantum state. The quantum circuit includes a first layer with n qubits and an X gate applied to one of the qubits, and a plurality of subsequent layers. The plurality of subsequent layers apply BS gates to the qubits according to a binary tree pattern, where each BS gate is a single-parameterized 2-qubit gate, and the number of subsequent layers does not exceed an upper limit (log2(n)). In some embodiments, this quantum circuit is part of a larger quantum circuit that includes additional layers.

[0024] JPEG2023521804000010.jpg106166

[0025] JPEG2023521804000011.jpg56166

[0026] The structure described above can be adapted to work even when n is not a power of 4, or when the two sets of qubits are not of equal size, as previously mentioned (for example, when the sizes are t and n / t (note that their product is still equal to n)).

[0027] Figure 1B shows 16-dimensional data points (x1, x2, ..., x 16 Here is one exemplary implementation example of our method for loading ).

[0028] In Figure 1B, gates BS and c-BS are positioned from left to right and from top to bottom, with the parameters being angles (θ1, θ2, ..., θ 15 This involves ) which can be calculated according to our explanation or a similar explanation. Note that "@" indicates the control qubit for each c-BS gate.

[0029] The depth of the circuit in Figure 1B can be improved by noticing that many gates are applied to different qubits (e.g., gates at times 4 and 8, or 5 and 7, etc.), and therefore the total depth of the circuit is It can be rearranged to become JPEG2023521804000012.jpg2251.

[0030] The number of qubits used in quantum circuits, the circuit depth, and the number of gates for 2-qubit and 3-qubit circuits are generally as follows:

[0031] JPEG2023521804000013.jpg26166

[0032] JPEG2023521804000014.jpg24166

[0033] JPEG2023521804000015.jpg68166

[0034] Part 2: Application Examples of Methods for Loading Classical Data into Quantum States The following describes how the quantum data loader described in Part 1 can be used to perform several basic procedures that are useful, for example, in machine learning and optimization, although it has other applications. These applications include: distance estimation, inner product estimation, linear algebra, classification, clustering, neural networks, and numerous further applications. These are only some of the possible applications, and further applications can be determined based on the methods disclosed herein. For convenience, the following description uses a parallel loader. Other embodiments of the quantum data loader, such as a second loader, can also be used to perform these procedures.

[0035] JPEG2023521804000016.jpg32166

[0036] The distance between data points can be defined in different ways, and here, as one form, the distance between these two data points is defined as follows:

number

[0037] Figure 2 shows one specific implementation example of our method for estimating the distance between two 8-dimensional data points x=(x1,x2,...,x8) and y=(y1,y2,...,y8). In this implementation example, the first gate BS on the left (at T=1) has the parameter

number

[0038] The parameters of gate BS in the upper half of the circuit in Figure 2 are (related to q0-q7), and the vector (x1, x2, ..., x n This corresponds to the parameters of the quantum data loader for ). The gate BS in the lower half of the circuit in Figure 2 is (related to q8-q15), and the vector (y1, y2, ..., y nThis corresponds to the quantum data loader parameters for ). The last set of BS gates in the rightmost part of Figure 2 (at T=5) is accompanied by θ=π / 4. The last set of BS gates can be executed in parallel during a single time step.

[0039] The result of the circuit described in Figure 2 is the following quantum state:

number

[0040] The number of qubits used in quantum circuits, the circuit depth, and the number of gates for 2-qubit and 3-qubit circuits are generally as follows, although their dimensions will be discussed later:

[0041] In the case of 8 dimensions: Number of qubits = 16; depth = 6; number of 2-qubit gates = 23; number of 3-qubit gates = 0.

[0042] For 1024 dimensions: Number of qubits = 2048; Depth = 13; Number of 2-qubit gates = 3071; Number of 3-qubit gates = 0.

[0043] n-dimensional: Number of qubits = 2n; depth = log(n) + 3; number of 2-qubit gates = 3n-1; number of 3-qubit gates = 0.

[0044] Since the depth of a circuit can correspond to the execution time or time complexity of the circuit, the distance between two vectors can therefore be determined in ~ O(log(n)) time.

[0045] The following describes a quantum circuit according to the first embodiment: A quantum circuit is created to encode a first n-dimensional vector representing classical data into a first quantum state of n qubits, encode a second n-dimensional vector representing classical data into a second quantum state of n qubits, and to determine the distance between the first n-dimensional vector and the second n-dimensional vector. The quantum circuit includes a first layer with 2n qubits and an X gate applied to one of the qubits, a first group of successor layers, and an additional layer. The first group of successor layers applies BS gates to the qubits according to a binary tree pattern, where each BS gate is a single-parameterized 2-qubit gate. The additional layer follows the first group and applies BS gates in parallel to pairs of qubits, where the first qubit in a pair is associated with a first quantum state and the second qubit in a pair is associated with a second quantum state. The number of layers in the circuit is The image size does not exceed JPEG2023521804000020.jpg1964. In some embodiments, this quantum circuit is part of a larger quantum circuit that includes more layers.

[0046] JPEG2023521804000021.jpg43166

[0047] Figure 3 shows one specific implementation example of our method for estimating the distance between two 8-dimensional data points, x=(x1,x2,…,x8) and y=(y1,y2,…,y8). In this implementation example, the first part of the circuit corresponds to a parallel loader for the normalized vector x, similar to 1A, and the second part of the circuit corresponds to the complex conjugate of the loader for the vector y. In other words, the circuit is constructed by reversing the gate order for the loader of y and conjugating each gate.

[0048] JPEG2023521804000022.jpg59166

[0049] JPEG2023521804000023.jpg42166

[0050] The number of qubits used in quantum circuits, the circuit depth, and the number of gates for 2-qubit and 3-qubit circuits are generally as follows, although their dimensions will be discussed later:

[0051] In the case of 8 dimensions: Number of qubits = 8; Depth = 7; Number of 2-qubit gates = 14; Number of 3-qubit gates = 0.

[0052] For 1024 dimensions: Number of qubits = 1024; Depth = 21; Number of 2-qubit gates = 2046; Number of 3-qubit gates = 0.

[0053] n-dimensional: Number of qubits = n; depth = 2log(n) + 1; number of 2-qubit gates = 2n - 2; number of 3-qubit gates = 0.

[0054] Therefore, the time complexity of this circuit can be as low as ~O(2log(n)). Although the time complexity is doubled compared to the first embodiment, the number of qubits is halved.

[0055] The following describes a quantum circuit according to a second embodiment: A quantum circuit is created to encode a first n-dimensional vector representing classical data into a first quantum state of n qubits, encode a second n-dimensional vector representing classical data into a second quantum state of n qubits, and to determine the distance between the first n-dimensional vector and the second n-dimensional vector. The quantum circuit includes a first layer having n qubits and an X gate applied to one of the qubits, a first group of successor layers, and a second group of successor layers. The first group of successor layers applies BS gates to the qubits according to a binary tree pattern, where each BS gate is a single-parameterized 2-qubit gate. The second group of successor layers applies conjugate BS gates to the same qubits according to the inverse of the binary tree pattern, where each BS gate is a single-parameterized 2-qubit gate. The number of layers does not exceed the upper limit (2log2(n) + 1). In some embodiments, this quantum circuit is part of a larger quantum circuit that includes additional layers.

[0056] 2. Estimation of the inner product The distance between two data points and their dot product are related by the following mathematical formula:

number

[0057] 3. Matrix multiplication The aforementioned quantum method for inner product estimation can be used to provide applications in linear algebra (specifically, matrix multiplication), and here we consider the case where we need to calculate C=AB for two matrices A and B. In one embodiment, the method can be realized in a classical-quantum hybrid form, and for each row A of the matrix i and each column B of the matrix j Regarding this, we employ a quantum method for inner product estimation, C ij = A i Bj The elements of matrix C can be calculated as follows.

[0058] By performing matrix multiplication via the distance estimation method described above, the operation has a time complexity of ~O(n 2 This can be done as log(n). The time complexity is ~O(n 3 This represents a significant improvement compared to conventional matrix multiplication algorithms, which result in ).

[0059] 4. Classification The distance estimation method described above can be readily used to provide classification applications. One example among many possible embodiments relating to this application is described below.

[0060] In one embodiment, a known nearest centroid algorithm can be used, in which case the classification of data points is performed by calculating the distance of the data point to all centroids and selecting the centroid with the minimum distance. The distance estimation method described above can be used to obtain a classical-quantum hybrid classification algorithm, in which case the data points are classified using the quantum method described in relation to Figure 2 or Figure 3.

[0061] 5. Clustering The distance estimation method described above can be readily used to provide clustering applications. One example among many possible embodiments is described below.

[0062] In one embodiment, a classical-quantum hybrid algorithm based on the well-known k-means algorithm can be used. In this case, the quantum distance estimation method described above in relation to Figure 2 or Figure 3 can be used for both assigning data points to centroids (similar to the classification case) and updating the centroids, in relation to the case where matrix multiplication is used.

[0063] 6. Training and evaluation of neural networks The inner product estimation method described above can be used to provide applications related to neural networks. One example among many possible embodiments of this application is described below.

[0064] In one embodiment, a classical-quantum hybrid algorithm based on well-known feedforward and backpropagation algorithms can be used. In this case, the quantum distance estimation method described above, in relation to Figures 2 and 3, can be used both for evaluation and for multiplying the matrix and weights of the data points in the backpropagation algorithm (which may also be a gradient descent algorithm), in relation to cases where matrix multiplication is used.

[0065] It should be noted that alternative embodiments of our methods disclosed herein are readily recognizable as viable alternatives that can be adopted without departing from the principles of disclosure.

[0066] Part 3: Hardware Implementation Examples of Quantum Data Loaders This document describes how quantum data loaders can be implemented using different types of current quantum hardware, including superconducting qubits or photonics. These are only a few examples of possible hardware implementations, and many more can be built more easily based on the same methods described herein, or with different qubit technologies such as trapped ions or atoms.

[0067] 1. Implementation with superconducting qubits A gate within the family called BS(θ) can be used to couple two superconducting qubits in such a manner that the next gate can be directly applied to any parameter θ:

number

[0068] Therefore, although the quantum data loader described in Part 1 can be implemented using these gates, new connectivity may be required in relation to the current connectivity of superconducting qubit machines connected as a 2-D grid.

[0069] Our proposal for a quantum data loader may require superconducting qubits that are connected in a tree structure (rather than a grid) and have the ability to apply the aforementioned BS(θ) family gates.

[0070] There are many alternatives to arranging qubits in a 2-D plane to enable tree-structure connectivity, and Figure 4A discloses an exemplary architecture for a quantum data loader for a 32-dimensional vector using 35 qubits in a grid of dimensions 9x5 (32 corresponds to the number of qubits required for the loader, with an additional 3 qubits to accommodate the loader within the grid with some qubit iterations). Figure 4B illustrates how the 32 dimensions are mapped to the qubits in the grid. Many alternative embodiments are possible, all of which follow our method with embedded tree-structure connectivity.

[0071] In Figures 4A and 4B, "O" corresponds to a superconducting qubit, and horizontal (--) or vertical (|) connections correspond to the ability to perform a BS(θ) gate between pairs of qubits.

[0072] 2. Implementation example with a linear optical system The gates within the family known as BS(θ) can also be implemented using a linear optical system scheme, which can be achieved by implementing a reconfigurable beam splitter, also known as a tunable beam splitter or tunable Mach-Zender interferometer.

[0073] In Figure 5A, according to the embodiment, the reconfigurable beam splitter is implemented as a partial mirror.

[0074] In Figure 5B, such a reconfigurable beam splitter is represented as a gate with two inputs and two outputs that performs operations on the BS(θ) family. The reconfigurable beam splitter has a parameter θ (not shown), which corresponds to the ratio of reflectance to transmittance (for example, this decomposes coupled light, with cos(θ) being reflected and sin(θ) being transmitted). Thus, the quantum data loader described in Part 1 can be implemented using a single-photon source, a reconfigurable beam splitter, and a photon detector.

[0075] In some embodiments, the quantum data loader may be implemented within an integrated photonic chip.

[0076] While numerous alternative architectures exist to achieve tree-structured connectivity, Figures 5A and 5B disclose exemplary architectures for photonic linear optical system schemes that can be used as quantum data loaders. Many alternative embodiments following our method with tree-structured connectivity are possible.

[0077] Figure 6 is a block diagram showing the components of an exemplary computing system, according to some embodiments, which can read instructions from a machine-readable medium and execute them on one or more processors (or controllers), including a quantum processor. Specifically, Figure 6 shows a schematic representation of computer system 600. Computer system 600 may be used to execute instructions 624 (e.g., software) that cause the computing system to perform any one or more of the methodologies (or processes) described herein, such as method 100. In some embodiments, the computing system can operate as a standalone device or as a device connected to other machines (e.g., networked). In a networked deployment, the computing system can operate as a server machine or a client machine in a server-client network environment, or as a peer machine in a P2P (or distributed) network environment. Note that Figure 6 and its description describe an exemplary device. Other computing systems with quantum processors may behave differently and may have more, fewer, or different components.

[0078] The exemplary computer system 600 includes one or more processing units (e.g., processors 601, 602). For example, the conventional processor 602 may be a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), a controller, a state machine, one or more application-specific integrated circuits (ASICs), or any combination thereof.

[0079] The quantum processor 601 can be one or more physical devices that perform operations based on quantum effects, one or more devices exhibiting such behavior, or any other device that can be reasonably interpreted as exhibiting quantum processing behavior. The quantum processor 601 utilizes the laws of quantum mechanics to perform operations. The quantum processor 601 generally uses qubits (quantum bits) instead of bits used in classical computers. Classical bits are always either 0 or 1. Roughly speaking, qubits have non-zero probabilities that are in a superposition state or linear combination of 0 and 1. Because the quantum processor 601 can perform operations on qubits, the ability of qubits to exist in a superposition state of 0 and 1 can result in significantly enhanced performance for certain computational tasks. For example, Shor's algorithm describes how to use a quantum processor to efficiently factorize large integers, which has considerable applications and implications in cryptography. Grover's search algorithm describes how to use a quantum processor to efficiently search large sets of information, such as lists or databases.

[0080] The quantum processor 601 may configure and execute one or more quantum circuits 626. A quantum circuit is a model of quantum computation, which is a series of quantum gates, which are reversible transformations for one or more qubits.

[0081] The computer system 600 also includes a main memory 604. The computer system may include a storage unit 616. The processors 601, 602, the memory 604, and the storage unit 616 communicate via some communication medium 608. For example, a conventional processor 602, the main memory 604, and the storage unit 616 can communicate via a bus, while processors 602 and 601 can communicate with each other via separate dedicated communication paths.

[0082] In addition, the computer system 600 may include static memory 606 and a display driver 610 (for driving a plasma display panel (PDP), liquid crystal display (LCD), or projector that can display the UI 105 to the user). The computer system 600 may also include an alphanumeric input device 612 (e.g., a keyboard), a cursor control device 614 (e.g., a mouse, trackball, joystick, motion sensor, or other pointing device), a signal generator 618 (e.g., a speaker), and a network interface device 620, which are also configured to communicate via a communication medium 608.

[0083] The storage device 616 includes a machine-readable medium 622 in which instructions 624 (e.g., software) embodying one or more of the methodologies or functions described herein are stored. Instructions 624 may also reside, fully or at least partially, in the main memory 604 or the processor 601 (e.g., in the processor's cache memory) during execution by the computer system 600, and the main memory 604 and the processor 601 may be accompanied by a machine-readable medium. Instructions 624 may be partially executed by the quantum circuit 626 using the methods described above. Instructions 624 may be transmitted or received over the network 626 via the network interface device 620.

[0084] Although the machine-readable medium 622 is shown to be a single medium in exemplary embodiments, the term “machine-readable medium” should be understood to include a single or multiple mediums (e.g., a centralized or distributed database, or associated caches and servers) capable of storing instructions 624. The term “machine-readable medium” should also be understood to include any medium capable of storing instructions 624 for machine execution, allowing a machine to execute any one or more of the methodologies disclosed herein. The term “machine-readable medium” includes, but is not limited to, data repositories in the form of solid-state memory, optical media, and magnetic media.

[0085] While the detailed description includes many specific details, these should not be interpreted as limiting the scope of the invention, but merely as illustrating different embodiments. It should be noted that the scope of this disclosure also includes other embodiments not detailed above. Various other modifications, changes, and variations that would be apparent to those skilled in the art may be introduced in the arrangement, operation, and details of the methods and apparatus disclosed herein without departing from the spirit and scope defined in the appended claims. Therefore, the scope of the invention should be determined by the appended claims and their legal equivalents.

Claims

1. 1. A quantum circuit for use in encoding an n-dimensional vector representing classical data into a quantum state of n qubits, the quantum circuit comprising: n qubits, a first layer comprising an X-gate applied to one of the qubits; A number of subsequent layers of applying BS gates to the qubits according to a binary tree pattern, where each BS gate is a single parameterized two-qubit gate, and the number of subsequent layers is a ceiling function (log 2 (n)) of the number of subsequent layers, A quantum circuit comprising:

2. 2. The quantum circuit of claim 1, wherein n is a power of two.

3. 2. The quantum circuit of claim 1, wherein a root node of the binary tree pattern is a qubit to which an X gate is applied.

4. 10. The quantum circuit of claim 1, wherein a total number of qubits in the quantum circuit does not exceed n.

5. 2. The quantum circuit of claim 1, wherein the total number of BS gates in the quantum circuit does not exceed n-1.

6. 3. The quantum circuit of claim 2, wherein the number of the plurality of subsequent layers is the base 2 logarithm of n.

7. 2. The quantum circuit of claim 1, wherein each BS gate is of the form: [0010] 。

8. 8. The quantum circuit of claim 7, wherein n is a power of 2, and the n-dimensional vector is (x 1 , x 2 , …, x n ) and as j goes from 1 to n / 2-1, [0025] [0030]

9. 10. The quantum circuit of claim 1, wherein the qubit is a superconducting qubit.

10. 10. The quantum circuit of claim 1, wherein the BS gate is implemented as a reconfigurable beam splitter.

11. 1. A quantum circuit for use in encoding an n-dimensional vector representing classical data into a quantum state, the quantum circuit comprising: [0045] The first group of qubits and [0050] A second group of qubits; and a first layer comprising first X-gates applied to qubits in the first group and second X-gates applied to qubits in the second group; a first plurality of subsequent layers applying BS gates to said first group of qubits according to a binary tree pattern, each BS gate being a single parameterized two-qubit gate; a second plurality of subsequent layers applying control BS gates (c-BS gates) to qubits in the first and second groups, each c-BS gate applying a BS gate to a qubit in the second group and controlled by a qubit in the first group; The number of layers is Ceiling Function 【number】 A quantum circuit that does not exceed the value of

12. 12. The quantum circuit of claim 11, wherein the second plurality of subsequent layers includes a group of c-BS gates. [006] wherein each group of c-BS gates applies BS gates to the second group of qubits according to a binary tree pattern.

13. 13. The quantum circuit of claim 12, wherein c-BS gates in the same group are controlled by the same qubit in the first group.

14. 13. The quantum circuit of claim 12, wherein the root node of each binary tree pattern in each group of c-BS gates is a qubit in the second group of qubits to which an X gate is applied.

15. 12. The quantum circuit of claim 11, wherein a root node of the binary tree pattern is a qubit in the first group of qubits to which an X gate is applied.

16. 12. The quantum circuit of claim 11, wherein n is a power of four.

17. 12. The quantum circuit according to claim 11, wherein the number of the BS gates is [0070] Quantum circuits that do not exceed.

18. In the quantum circuit according to claim 11, the number of the c-BS gates is [0080] Quantum circuits that do not exceed.

19. 12. The quantum circuit of claim 11, wherein the qubit is a superconducting qubit.

20. 12. The quantum circuit of claim 11, wherein the BS gate is implemented as a reconfigurable beam splitter.

21. 1. A quantum circuit for use in encoding a first n-dimensional vector representing classical data into a first quantum state of n qubits, encoding a second n-dimensional vector representing classical data into a second quantum state of n qubits, and determining a distance between the first n-dimensional vector and the second n-dimensional vector, the quantum circuit comprising: 2n qubits, a first layer comprising an X-gate applied to one of the qubits; a first subsequent layer group for applying BS gates to the qubits according to a binary tree pattern, each BS gate being a single parameterized two-qubit gate; an additional layer after the first group that applies BS gates to pairs of qubits in parallel, where a first qubit in the pair is associated with a first quantum state and a second qubit in the pair is associated with a second quantum state; A quantum circuit in which the number of layers does not exceed the value of the ceiling function (log2(n) + 3).

22. 22. The quantum circuit of claim 21, wherein n is a power of two.

23. 22. The quantum circuit of claim 21, wherein a root node of the binary tree pattern is a qubit to which an X gate is applied.

24. 22. The quantum circuit of claim 21 , wherein a total number of qubits in the quantum circuit does not exceed 2n.

25. 22. The quantum circuit of claim 21, wherein the total number of BS gates in the quantum circuit does not exceed 3n-1.

26. 23. The quantum circuit of claim 22, wherein the number of the first subsequent layers is the logarithm to the base 2 of n.

27. 22. The quantum circuit of claim 21, wherein each BS gate is of the form: [0097] 。

28. 28. The quantum circuit of claim 27, wherein for a first BS gate of the binary tree: [0089] That is, quantum circuits.

29. 28. The quantum circuit of claim 27, wherein θ=π / 4 for BS gates in the additional layer.

30. 22. The quantum circuit of claim 21 , wherein the probability of observing all zeros on the first n qubits is equal to the distance between the first n-dimensional vector and the second n-dimensional vector divided by four.

31. 1. A quantum circuit for use in encoding a first n-dimensional vector representing classical data into a first quantum state of n qubits, encoding a second n-dimensional vector representing classical data into a second quantum state of n qubits, and determining a distance between the first n-dimensional vector and the second n-dimensional vector, the quantum circuit comprising: n qubits, a first layer comprising an X-gate applied to one of the qubits; a first subsequent layer group for applying BS gates to the qubits according to a binary tree pattern, each BS gate being a single parameterized two-qubit gate; a second subsequent group of layers applying BS gates to the same qubits according to the inverse of the binary tree pattern; A quantum circuit in which the number of layers does not exceed the value of the ceiling function (2log2(n) + 1).

32. 32. The quantum circuit of claim 31 , wherein n is a power of two.

33. 32. The quantum circuit of claim 31 , wherein a root node of the binary tree pattern in the first subsequent layer group is a qubit to which an X gate is applied.

34. 32. The quantum circuit of claim 31 , wherein a root node of the binary tree pattern in the second subsequent layer group is a qubit to which an X gate is applied.

35. 32. The quantum circuit of claim 31 , wherein a total number of qubits in the quantum circuit does not exceed n.

36. 32. The quantum circuit of claim 31 , wherein the total number of BS gates in the quantum circuit does not exceed 2n−2.

37. 32. The quantum circuit of claim 31 , wherein a BS gate in the second subsequent group of layers is a conjugate gate of a BS gate in the first subsequent group of layers.

38. 32. The quantum circuit of claim 31 , wherein each BS gate in the first subsequent group is of the form: ##EQU00011## 。

39. 39. The quantum circuit of claim 38, wherein each BS gate in the second subsequent group of layers is of the form: ##EQU00012## 。

40. 32. The quantum circuit of claim 31 , wherein the number of BS gates in the second subsequent group of layers is equal to the number of BS gates in the first subsequent group of layers.

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