High-bandwidth IJTAG via high-speed parallel bus

Abstract

The system in the circuit includes a first network configurable to transmit data in parallel within the circuit, the first network comprising a circuit block interface device, each of the circuit block interface devices coupled to a port of one of the circuit blocks in the circuit, a plurality of second networks, each of the plurality of second networks configurable to transmit data serially with one of the circuit blocks, a third network configurable to transmit data serially within the circuit when coupled to the plurality of second networks, and a plurality of network switching interface devices.

Description

Technical Field

[0001] Related Invention This application was filed on August 19, 2020, claims the benefit of U.S. Provisional Patent Application No. 63 / 067,534, with inventors Jean-Francois Cote et al., and is hereby incorporated by reference in its entirety.

[0002] The technology disclosed herein relates to the fields of integrated circuit design, verification, manufacturing, and testing. Various implementations of the disclosed technology are particularly useful for increasing the bandwidth of serial networks within a circuit.

Background Art

[0003] The number of functional units in semiconductor devices has been continuously increasing significantly as the integration of functions into a single semiconductor device continues. The functional units can be an entire temperature or voltage sensor, a clock control circuit such as a phase-locked loop (PLL), a scan configuration controller, or a built-in self-test (BIST) engine for memory or logic testing. Accessing, controlling, observing, or more generally, "operating" these numerous functional units poses a challenge to designers.

Summary of the Invention

Problems to be Solved by the Invention

[0004] Traditionally, functional units were daisy-chained in a single serial access network. This involved numerous scan operations to shift data bits in and out of these functional blocks. To reduce access time, a reconfigurable scan network can be employed as an alternative to the traditional serial access network. Based on the specific programmed operation of special elements of the access network, parts of the reconfigurable scan network can enter and exit the scan network. A typical reconfigurable scan network compliant with IEEE 1687-2014 and IEEE 1149.1-2013 is called an IJTAG network.

[0005] An actively reconfigurable IJTAG network can minimize the number of shift operations required to operate the desired functional unit, such as setting all aspects of the circuit's test mode. As device complexity increases and the amount of diagnostic data that needs to be extracted increases, the slow speed and serial nature of IJTAG scan networks become a bottleneck, leading to longer test times.

[0006] Attempts have been made to increase the shift speed by introducing a clock gap around the control (clock stretch) transition or by matching stages on the scancampus and adding a pipelined stage to the control signal. Unfortunately, these two techniques are mutually exclusive. While these solutions help achieve shift speeds in the low 100MHz range, the increased bandwidth is still orders of magnitude lower than required due to the serial nature of the solutions and the two edge timings used when crossing clock domains.

[0007] While it supports the IEEE 1687-2014 standard using a multi-chain scan interface, routing many scan chains across physical block boundaries is costly, extremely cumbersome, and incompatible with modern core-based design flows. [Means for solving the problem]

[0008] Various aspects of the disclosed technology relate to increasing the bandwidth of a serial network. In one aspect, a system in a circuit comprises: a first network configured to transmit data serially within the circuit, the first network comprising circuit block interface devices, each of which is coupled to a port of one of the circuit blocks within the circuit; a plurality of second networks, each of which is configured to transmit data serially to one of the circuit blocks within the circuit; a third network configured to transmit data serially within the circuit when the circuit is connected to the plurality of second networks; and a plurality of network switching interface devices, each of which is configured to couple either the first network or the third network to one of the plurality of second networks based on control signals stored in each of the plurality of interface devices.

[0009] Control signals stored in each of the multiple interface devices can be updated using the third network when the third network is connected to one of the multiple second networks, or using the first network when the first network is connected to one of the multiple second networks.

[0010] Multiple second networks may be configured to connect to the first network in daisy-chain mode, parallel mode, broadcast mode, or any combination thereof.

[0011] The first network may operate at a clock frequency that is a multiple (greater than 1) of the clock frequency on which the multiple second networks operate, and the multiple second networks may be coupled to the first network in time-slot multiplexing mode.

[0012] One of the multiple second networks may have a section configurable to transmit data in parallel, and this section is configurable to be coupled in parallel to the first network.

[0013] One or more of the second networks may use the clock stretching technique to increase the shift speed.

[0014] The third network and multiple second networks may comply with the IEEE 1687 standard (IJTAG, Internal Joint Test Action Group).

[0015] The first network may further include a multiplexer, a pipeline, or both, and the multiplexer may be configured to modify the data streaming path of the first network based on other control data that can be transmitted to the multiplexer via a plurality of second networks coupled to either the first network or the third network.

[0016] Each of the multiple second networks includes a configuration interface device, the configuration interface device is coupled to one of the circuit block interface devices, and configuration data for the configuration interface device is transmittable through each of the multiple networks coupled to either the first network or the third network, and the configuration data includes data that determines whether the circuit block interface device of a circuit block is operational, and data that determines which parts of the data transmitted to the first network are captured, replaced, or captured and replaced by each of the operational circuit block interface devices.

[0017] The circuit block interface device may include registers and clock signal generation logic, and the first network includes data channels and is configurable to transmit a plurality of data packets sequentially, each of which has a plurality of bits, each of which is assigned to one of the circuit blocks from which the circuit block interface device is invoked, and the number of bits is equal to or greater than the number of data channels used to transmit the plurality of data packets. Each of the plurality of data packets may include one or more bits of a test pattern or a compressed test pattern for testing one or more of the circuit blocks, and the clock signal generation logic in the circuit block interface device coupled to a port of one of the circuit blocks may be configurable to generate a clock signal for scan-based testing, and the port of one of the circuit blocks may include inputs and outputs of a scan chain, inputs and outputs of one or more test controllers, or a combination thereof, each of which has a decompressor and a compactor.

[0018] In another embodiment, there is one or more non-temporary computer-readable media that store computer-executable instructions for causing a computer to perform a method, and the method includes generating the above system in a circuit design.

[0019] In yet another aspect, a method for testing a circuit, comprising the step of transmitting network configuration data via a third network coupled to a plurality of second networks, wherein the third network is configured to transmit data serially within the circuit, the plurality of second networks are configured to transmit data to one of the circuit blocks of the circuit, the network configuration data includes first network switching interface control data for a plurality of network switching interface devices, the first network switching interface control data activates each of the plurality of second networks to disconnect one of the plurality of second networks from the third network, and to connect one of the plurality of second networks to the first network A step of connecting a first network to a network and configuring the first network to transmit data in parallel to a circuit; and a step of transmitting setup data through the first network connected to a plurality of second networks, wherein the setup data includes test setup data for a circuit block, network setup data for communication between the first network and the circuit block, and second network switching interface control data for a plurality of network switching interface devices, the second network switching interface control data causing the plurality of network switching interface devices to decouple one of the plurality of second networks from the first network and to connect the one of the plurality of second networks to a third network. The process includes the steps of sending test data to a circuit block via a first network.

[0020] The method may further include transmitting interface enabling data via a third network coupled to a plurality of second networks to enable an interface device between the first network and a circuit block before transmitting test data.

[0021] The network configuration data may further include network reconfiguration data for a plurality of multiplexing devices, and the network reconfiguration data causes the first network to bypass zero, one, or a plurality of circuit blocks.

[0022] Certain inventive aspects are set forth in the accompanying independent claims and dependent claims. Features from the dependent claims may be combined with the features of the independent claims and the features of other dependent claims as appropriate and are not merely limited to what is explicitly recited in the claims.

[0023] Certain objectives and advantages of various aspects of the invention have been described above in this specification. It should of course be understood that not necessarily all such objectives or advantages will be achieved in accordance with any particular embodiment of the disclosed technology. Thus, for example, those skilled in the art will recognize that the disclosed technology may be embodied or practiced in a manner that achieves or optimizes one advantage or a group of advantages as taught herein without necessarily achieving other objectives or advantages as taught herein.

Brief Description of the Drawings

[0024] [Figure 1] FIG. 1 shows an example of an IJTAG network. [Figure 2] FIG. 2 shows an example of a data streaming system within a circuit, and the serial network is used to configure a core interface for communication with a parallel data streaming network. [Figure 3]FIG. 3 shows an example of bit allocation of a data channel of the parallel data streaming network in FIG. 2. [Figure 4] FIG. 4 shows an example of a circuit block interface device such as the first interface device in FIG. 2 implemented according to various embodiments of the disclosed technology. [Figure 5] FIG. 5 shows an example of a pipeline device implemented according to various embodiments of the disclosed technology. [Figure 6] FIG. 6 shows an example of a multiplexing device implemented according to various embodiments of the disclosed technology. [Figure 7] FIG. 7 shows an example of a system that utilizes a data streaming network to increase the serial network bandwidth according to various embodiments of the disclosed technology. [Figure 8] FIG. 8 shows an example of a network switching interface device according to various embodiments of the disclosed technology. [Figure 9] FIG. 9 shows an example of a detailed block diagram of a network switching interface device according to various embodiments of the disclosed technology. [Figure 10] FIG. 10 shows an example of a data streaming network coupled to three local serial networks in daisy chain mode according to various embodiments of the disclosed technology. [Figure 11] FIG. 11 shows an example of a TAP state machine compliant with the IEEE1149.1-2013 standard. [Figure 12] FIG. 12 shows a table explaining an example of some bits of the scan / memory elements in FIG. 10 in 19 consecutive clock cycles. [Figure 13] FIG. 13 shows an example of a data streaming network coupled to three local serial networks in broadcast mode according to various embodiments of the disclosed technology. [Figure 14]Figure 14 shows examples of data streaming networks coupled in parallel mode to two local serial networks, according to various embodiments of the disclosed technology. [Figure 15] Figure 15 shows examples of data streaming networks coupled to two local serial networks in a time slot multiplexing mode according to various embodiments of the disclosed technology. [Figure 16] Figure 16 shows examples of a local network memory BIST (Built-in Self-Test) section configurable to be coupled in parallel to a data streaming network (the first network) according to various embodiments of the disclosed technology. [Figure 17] Figure 17 shows a flowchart illustrating the process of setting up circuit tests via a high-bandwidth serial network enabled by a data streaming network, as implemented according to various examples of the disclosed technology. [Figure 18] Figure 18 shows examples of several clock and control signal waveforms illustrating a clock extension technique for increasing the shift speed of an IJTAG network, as implemented according to various embodiments of the disclosed technique. [Figure 19] Figure 19 shows a programmable computer system employing various embodiments of the disclosed technology. [Modes for carrying out the invention]

[0025] Various aspects of the disclosed technology relate to increasing the bandwidth of serial networks within circuits. The following description includes numerous details for illustrative purposes. However, those skilled in the art will understand that the disclosed technology can be implemented without using these specific details. In other examples, well-known features are not described in detail to avoid obscuring the disclosed technology.

[0026] Detailed descriptions of methods or apparatus sometimes use terms such as “transmit” and “enable” to describe the function / structure of the disclosed method or apparatus. Such terms are high-level abstractions. The actual operations or functions / structures corresponding to these terms will vary depending on the specific implementation and will be readily identifiable to those skilled in the art. Also, those skilled in the art should understand that the term “combined” means “connected directly or indirectly.”

[0027] The operations of the disclosed methods are described in a specific order for the sake of convenient presentation, but it should be understood that this method of description involves rearrangement unless a specific order is required by the specific language described below. For example, actions described sequentially may, in some cases, be rearranged or performed simultaneously. Furthermore, for simplicity, the disclosed flowcharts and block diagrams do not typically illustrate the various ways in which a particular method is used in conjunction with other methods.

[0028] Reconfigurable scan network A reconfigurable scan network compliant with IEEE 1687-2014 (IJTAG) provides, among other things, access to embedded tests and test setups for manufacturing testing. Figure 1 shows an example of an IJTAG network 100. In the IJTAG network 100, a SIB (Segment Insertion Bit) 123 switches between two access paths between a TDI (Test Data Input) port 115 and a TDO (Test Data Output) port 117 belonging to a TAP (Test Access Port) 110. The short access path connects SIB 123 directly to SIB 121, while the long access path connects SIB 123 to SIB 121 via two TDRs (Test Data Registers) 135 and 136. A ScanMux (multiplexer) 140 selects one of two scan segments of the access network 100 (one via TDR 133 and the other via TDR 134) based on the received control data. To access these two scan segments, SIB121 and 122 must be programmed accordingly. The scan path can also bypass TDR132, 133, and 134, reaching SIB122 directly from TDR131.

[0029] As shown in Figure 1, programmable configuration elements of the reconfigurable scan network, such as SIB121, 122, and 123 and ScanMux140 within the scan network 100, enable dynamic configuration of the access network, bringing specific functional blocks within the scope of the access network. These programmable components can be programmed by shifting configuration data to a shift flip-flop in a control register and latching the shifted bits into a parallel latch within it. The functional blocks of the circuit are controlled by TDR131-136. This dynamic access network configuration minimizes the number of shift operations required to operate the desired functional block.

[0030] An additional advantage of such a reconfigurable scan network lies in its ability to configure the access network according to power domains and clock domains. For example, placing an SIB in front of a power domain ensures that the portion of the access network outside of that power domain remains operational even when the power domain is switched off. In a similar manner, hierarchical design entities can be brought in and out of the scope of the access network, enabling bypass of all functional objects within each design hierarchy entity.

[0031] Data Streaming Network As integrated circuits grow to contain billions of transistors, designing them flatly without splitting them down becomes virtually impossible. Electronic Design Automation (EDA) tools cannot handle this efficiently. Furthermore, there is significant reuse of intellectual property (IP) from one design to another. Larger designs, known as Systems-On-A-Chip (SOC), contain numerous "cores" used as building blocks (also called circuit blocks). Each core is typically designed and validated individually first, and then integrated with other cores to form the entire SOC. This is called hierarchical design. Ideally, much of the design and validation work is done at the core level, making it smaller and more manageable, while integration and validation at the chip level are done at the top level. All work done at the core level can also be done earlier if it is done at the core level. As the SOC comes together and approaches its tape-out deadline, it goes off the critical path.

[0032] As designs have grown, the number of core hierarchy levels has also increased. Hierarchical designs began with two hierarchy levels: the core level and the chip / top level. Cores are first integrated into larger cores or subsystems, and then integrated into the chip. This represents a three-level core hierarchy. Some larger designs have even more levels of core hierarchy.

[0033] Just as design employs hierarchical design to manage complexity, so does scan testing. In hierarchical testing methodology logic, scan chains and compression logic are injected into every core. Test patterns are generated and validated at the core level to test the majority of the logic within the core. Subsequently, patterns from multiple cores are retargeted or mapped to the top level. They are also merged with retargeted patterns for other cores being tested simultaneously. In addition to delaying the generation of patterns to test the majority of the content of each core, test pattern generation is performed at the next level down to the peripheral testing logic between cores, as well as the logic at that level involved in integrating the cores. If this higher level is not the chip level, those patterns also need to be retargeted to the chip level.

[0034] The same test pattern generation and retargeting method logic is applied recursively regardless of the hierarchy level, but the design planning and design for testing (DFT) becomes more complex with each additional level of hierarchy when using traditional scan-access methods.

[0035] Planning and implementing hierarchical scan testing in a SOC presents several challenges, most of which relate to providing access to scan channels within the core. Scan channels are channels connected to the inputs / outputs of the scan chain, the inputs / outputs of the test controller for test compression, or a combination thereof. When retargeting and merging core-level patterns to the top level, a subset of cores is typically tested at arbitrary points for two reasons: Firstly, power dissipation may prevent testing all cores simultaneously; and secondly, a limited number of chip-level inputs / outputs (I / O, or ports) may prevent simultaneous access to all core-level channels.

[0036] When testing groups of cores simultaneously, using a traditional point-to-point scan access method (sometimes called a star or switch topology), the channel I / O needs to be connected to different chip-level I / O. Typically, there are more core-level channels available for scanning at chip-level I / O, so pin availability limits the number of cores that can be tested simultaneously, increasing the number of groups (test sessions). Each top-level I / O can be connected to a different core-level pin in each group. As the number of cores increases and the number of chip-level I / O available for scan testing decreases, fewer cores can be directly accessed from the chip-level I / O, allowing them to be tested simultaneously.

[0037] A relatively recent trend in SOC design, known as tile-based layout, adds further complexity and constraints to DFT architectures. In tile-based designs, virtually all logic and routing takes place within the cores, not at the top level. Cores abut each other as they are integrated into the chip by connections flowing from one core to the next. Connections between cores must pass through the cores between them. Logically, logic at the top level must be pushed into the cores and designed as part of the core.

[0038] To overcome the challenges of test access, we propose a general packet-based core access architecture. In this architecture, each parallel word contains the address of the core (or group of cores) to which the information is destined, an opcode indicating what to do with the data, and the actual payload. This architecture works with both heterogeneous and homogeneous cores. For homogeneous cores, it supports efficient broadcasting of stimuli and expected values ​​(good machine responses), on-chip comparison, and accumulation of pass / fail data, enabling testing of multiple homogeneous cores in nearly constant time. However, this architecture is inefficient due to its significant overhead in all parallel words. Information that is not payload, namely the address and opcode, occupies a certain number of bits. Very narrow buses would not be able to support this architecture.

[0039] Another packet-based core access architecture reserves all streamed packets for the actual payload and employs a separate serial network to set up a core interface for communication with a parallel data streaming network. Figure 2 shows an example of such a data streaming system 200 in circuit. The data streaming system 200 comprises a first network 220 and a second network 230. The first network 220 comprises a first data channel 227 (first data bus) and a first interface device 225 (also called a circuit block interface device). The second network 230 comprises one or more second data channels 237 (second data bus) and a second interface device 235. The first interface device 225 comprises registers and clock signal generation logic. Each of the first interface devices 225 is coupled to one port of a circuit block 210 in circuit 200. Also, each of the first interface devices 225 is coupled to one of the second interface devices 235. The inputs and outputs of the first data channel 227 can be connected to some chip-level I / O (GPIO pads). The inputs and outputs of one or more second data channels 237 can also be connected to several other chip-level I / O (GPIO pads). Although only one first network 220 and one second network 230 are shown in Figure 2, the circuit may have multiple first networks 220 and one or more second networks 230.

[0040] A first data channel within the first network 220 can be formed by a chain of flip-flops and act as a pipeline stage. Some of these flip-flops are located within the first interface device 225. The first network 220 can be configured to transmit multiple data packets sequentially. Each of the multiple data packets has m bits, each of which is assigned to one of the circuit blocks 210 pre-configured in active mode. The second network 230 can be configured to transmit configuration data to the first interface device. The configuration data includes data for determining whether the first interface device within the first interface device 230 is activated, and data for determining which bits of each of the multiple data packets are to be captured, replaced, or captured, replaced, and replaced by each of the activated first interface devices. The second network 230 can comply with the IEEE 1687 standard (IJTAG, Internal Joint Test Action Group).

[0041] The active mode of a circuit block may be a test mode or a data load / unload mode, where m is greater than or equal to the number of first data channels 225 used to carry multiple data packets. The total number of first data channels for a manufactured circuit is typically fixed, but the number of first data channels used to carry multiple data packets may be less than the total. For example, a setup for wafer testing may not require all of the first data channels 225, while a setup for testing the same circuit in a system may utilize all of the first data channels 225.

[0042] Assume that the number of initial data channels used for transport data packets is n. The first network 220 transports data packets at a rate of one n-bit word per clock cycle, and if m is greater than n, then, according to various embodiments of the disclosed technology, bit assignments to circuit blocks 210 in active mode for a particular n-bit word (bus word) are repeated every LCM(m,n) / n clock cycles, where LCM(m,n) is the least common multiple of m and n. In some bit assignments, each bit of multiple data packets is divided into bit blocks, each bit in a bit block is adjacent to one another except for the bits at the two ends of the block, and each bit block is assigned to one of the circuit blocks pre-configured in active mode. Each of the first activated interface devices can be configured to track the position of its data bits within each bus word.

[0043] Figure 3 shows an example of bit allocation for the first data channel 225 used to transfer data packets. In this example, two circuit blocks (core A and core B) are driven through the first network – exchanging data in the first network. One of them loads / unloads 4 bits per shift cycle of the circuit block, and the other loads / unloads 5 bits. Thus, the size of each data packet is 9 bits. In the figure, "AI" means the data bits of core A, and "BI" means the data bits of core B. To shift the two circuit blocks once, 9 bits (m=9) must be sent out. The number of first data channels used for data streaming is 8. That is, the width of the bus that transmits data is 8 bits (n=8). Thus, the position of the 9-bit packet within each 8-bit bus word rotates with each packet to use each bit in each bus word without using unnecessary padding. As a result, packets start from the same bus bit position every 9 clock cycles. That is, the same bit allocation is repeated every 9 clock cycles. Furthermore, each data packet is divided into two bit blocks. For example, the data packet 310 in Figure 3 is divided into a bit block consisting of AI64-AI60 and a bit block consisting of BI60-BI63.

[0044] Data packets can widen as needed and occupy the required number of bus words. Internal channel requirements (9 bits in the example shown in Figure 3) are decoupled from scan pins available at the chip level (8 x 2 I / O in this case). If a packet is wider than the bus and occupies multiple bus words, circuit blocks can shift less frequently than once per bus shift cycle, but still drive all necessary circuit blocks. The scan canvas can typically shift data at a higher rate than the circuit blocks can shift internally, allowing circuit blocks to continue shifting at the maximum rate without shifting each bus clock cycle. The bus (the first data channel) can be reprogrammed to reduce its active width so that the number of bits in a packet does not exceed the number of bits in the packet when the packet size (m) is less than the physical bus width (n).

[0045] Using a system for streaming data within a circuit, implemented according to various embodiments of the disclosed technology, different types of data within a circuit, such as data to be stored in memory circuits and data for circuit testing, can be transmitted. As mentioned above, hierarchical design is currently widely used. Packet-based streaming based on the disclosed technology can greatly improve the test efficiency and flexibility of SOC design. To test one or more circuit blocks, each data packet contains one or more bits of a test pattern or a compressed test pattern. As shown in Figure 3, each data packet may contain bits of multiple test patterns for testing different circuit blocks.

[0046] Figure 4 shows an example of a first interface device (circuit block interface device) 400. The first interface device 400 has several static registers 410 labeled as IJTAG static registers. The several static registers 410 are programmed (set) before the start of streaming. Programming data can be sent using IJTAG or other access mechanisms. When the interface device 400 is started, bits in the bus word received from bus-in 420 are selected and sent to scan_in port 430, while bits received from scan_out port 440 are added to the bus word before being forwarded via bus_out 450 of the interface device 400. Since data bits in a word belonging to a given core can be rotated when the packet width is not a multiple of the bus width, the interface device 400 can use a shifter to access the key bits. Furthermore, since bits in a packet heading to the core can be distributed across multiple bus words, it may be necessary to collect data over multiple bus clock cycles before one shift cycle occurs in the core. The same thing happens with unloaded data. Data unloaded from one cycle of the core is inserted into a packet. This data can occupy bits that are part of a busword, the entire busword, or span multiple buswords. Interface device 400 has a clock generation circuit 470 for generating edt_clock 475 and shift_cap_clock 480. A finite state machine 490 (FSM) is used to generate the scan_en 492 and edt_update 495 signals. If interface device 400 is not started, the original busword bypasses the internal logic and is selected by the multiplexer 460 for output. In this way, interface device 400 acts as a pipeline stage in the first network.

[0047] Referring to Figure 2, the first network 220 may further include a multiplexer, a pipeline, or both. Figure 5 shows an example of a pipeline 500 that can be implemented according to various embodiments of the disclosed technology. The pipeline 500 can be used to meet timing requirements. If there is a long route between two cores, or between a core and chip-level I / O, the propagation delay through that route may hinder the bus's ability to operate at high frequencies. One or more pipelines can be inserted to shorten the length of the route through which data propagates within one cycle. Once data begins propagating through the first network 220 and the nodes in the network are filled with data, there is no loss of throughput due to the presence of additional nodes such as those pipeline stages. Their presence may slightly increase latency at the start of a test application.

[0048] Figure 6 shows an example of a multiplexer 600 that can be implemented according to various embodiments of the disclosed technology. The multiplexer 600 can select which of two preceding nodes to connect to its output. It can serve the same purpose as a segment insertion bit (SIB) node in the IJTAG standard. Such a node allows parts of the network to be included in the network or bypassed when inactive. This enables, among other things, 1) improved efficiency by bypassing parts of the network when not in use; 2) improved operational flexibility by enabling power to be supplied to a core containing an inactive section of the network without disrupting the operation of the active section of the network; 3) bypassing parts of the network when there is a manufacturing defect in that section of the network without disabling the entire network; and 4) making the entire wider width available by linking sections of different widths of the network when a smaller width section is bypassed.

[0049] Architecture for using data streaming networks to increase serial network bandwidth Figure 7 shows an example of a system 700 that utilizes a data streaming network to increase serial network bandwidth, as implemented according to various embodiments of the disclosed technology. System 700 includes a first network 710 (data streaming network) that can be configured to transmit data within the circuit in parallel. The first network 710 includes circuit block interface devices (not shown). Each of the circuit block interface devices is coupled to one port of a circuit block in the circuit. An example of a circuit block interface device is shown in Figure 4. The first network 710 can be configured to transmit test data into a circuit block via a circuit block interface device and to transmit test response data from the circuit block. Figure 7 shows that the circuit includes three circuit blocks: circuit block 750, circuit block 755, and circuit block 757.

[0050] The first network 710 may be implemented using the two packet-based core access systems described earlier, such as the data streaming system 200 shown in Figure 2. Similar to the data streaming system 200, the first network 710 may be reconfigurable, allowing one or more circuit blocks to be bypassed for data streaming. To achieve configurability, devices such as the multiplexer 600 shown in Figure 6 can be employed.

[0051] System 700 also includes a plurality of second networks, including second networks 720, 725, and 727, and a third network 730. Each of the plurality of second networks is configurable to transmit data serially within one of the circuit blocks in the circuit. As shown in Figure 7, the second networks 720, 725, and 727 are located within circuit blocks 750, 755, and 757, respectively. The third network 730 is configurable to transmit data serially within the circuit while being coupled to the plurality of second networks. The plurality of second networks and the third network 730 may be reconfigurable. Conventionally, the second networks 720, 725, and 727 are permanently coupled to the third network 730 to form a single network used, for example, for test setup. An example of such a network is an IJTAG network.

[0052] System 700 further comprises several network switching interface devices, such as network switching interface devices 740, 745, and 747 shown in Figure 7. Each of the network switching interface devices can be configured to connect either the first network 710 or the third network 730 to one of the multiple second networks, based on control signals stored in each of the multiple interface devices. For example, network switching interface device 740 can enable the second network 720 to be connected to either the first network 710 or the third network 730. The first network 710 is inherently parallel and can operate at a much higher frequency than the serial network formed by the combination of the third network 730 and the multiple second networks. Therefore, the ability to connect the first network 710 to the second networks 720, 725, and 727 can significantly increase the bandwidth for transmitting data in and out of circuit blocks 750, 755, and 757 for devices served by the second networks 720, 725, and 727.

[0053] Figure 8 shows an example of a network switching interface device 800 according to various embodiments of the disclosed technology. The network switching interface device 800 is configured to connect a local network 820 (second network) to either a serial network 830 (third network) or a parallel network 810 (first network) based on control signals stored in register 840. The control signals stored in register 840 can be updated using the serial network 830 when the serial network 830 is connected to the local network 820, or using the parallel network 810 when the parallel network 810 is connected to the local network 820. Thus, access to the local network 820 via either the parallel network 810 or the serial network 830 is actively changeable.

[0054] Figure 9 shows an example of a detailed block diagram of a network switching interface device 900 according to various embodiments of the disclosed technology. The network switching interface device 900 is configured to connect a local IJTAG network 920 (second network) to either a serial network 930 (third network) or a parallel network 910 (first network), depending on control bits stored in the SIH enable register 950. The control bits stored in the SIH enable register 950 can be updated via either the first network 910 or the third network 930, depending on the bits stored before the update operation. The first network 910 has eight data channels SiN-SoN (N=0-7), where data channels Si0-So0 are used to transmit a TMS signal (tms) when the local IJTAG network 920 is connected to the first network 910. The TMS (Test Mode Select) signal is a control signal supplied from a JTAG (Joint Test Action Group, IEEE1149.1) compliant TAP controller. The network switching interface device 900 can use the TMS signal to drive a finite state machine (FSM) 949 that controls the shift, capture, and update operations of data registers. The other seven data channel SiN-SoNs (N=1-7) can be used to transmit data into and out of the local IJTAG network 920 when the local IJTAG network 920 is coupled to the first network 910.

[0055] The network switching interface device 900 is configured from two registers 940 and 945 for the first network 910. Each of registers 940 and 945 can contain eight flip-flops, one for each data channel of the first network 910. The two flip-flops in registers 940 and 945 for each channel are connected serially to function as two pipeline stages of the first network 910.

[0056] The network switching interface device 900 also includes a multiplexer device 947, a host SIB 960, a configuration SIB 970, a broadcast control unit 980, and a configuration unit 990. The multiplexer device 947 is configured to select one of seven data channel SiN-SoNs (N=1-7) to be coupled to the local IJTAG network 920. The host SIB 960 and configuration SIB 970 are typical IJTAG segment insertion bit devices as shown in Figure 1. The host SIB 960 determines whether or not to bypass the local IJTAG network 920. The configuration SIB 970 determines whether or not the configuration unit 990 should be bypassed. The configuration unit 990 is configured to store control bits that determine which clock cycle (stored in register 991) and when the local IJTAG network 920 receives data from the data channel of the first network 910 (stored in register 992), and which represent the ratio between the global clock frequency and the local clock frequency (stored in register 993). The broadcast control unit 980 is configured to store control bits for output from the local IJTAG network 920 in the broadcast mode described later.

[0057] When a data streaming network (e.g., the first network 710 in Figure 7) is coupled to local serial networks (e.g., the second networks 720, 725, and 727 in Figure 7), at least three coupling modes can be used. Figure 10 shows an example of a data streaming network 1010 coupled to three local serial networks 1020, 1030, and 1040 in daisy-chain mode, according to various embodiments of the disclosed technology. The data streaming network 1010 has eight data channels. The rightmost data channel 1060 is configured to transmit a TMS signal, and the second rightmost data channel 1050 is configured to transmit data to and from the three local serial networks 1020, 1030, and 1040. Each of the three local serial networks 1020, 1030, and 1040 has two-bit shift elements (1025, 1035, and 1045). Each of the three 2-bit shift elements 1025, 1035, and 1045 is coupled in parallel to the memory elements (latch elements) (1027, 1037, and 1047). In daisy-chain mode, data bits shifted in data channel 1050 are shifted into the local serial network when the local serial network is selected based on the TSM bits shifted in data channel 1060. Daisy-chain mode can also be configured so that data bits captured by the local serial network are shifted back into data channel 1050 based on the TSM bits shifted in data channel 1060.

[0058] Figure 11 shows an example of a TAP state machine 1100 compliant with the IEEE 1149.1-2013 standard. The TAP state machine 1100 progresses along the test clock (TCK) edge with the value of the test mode selection (TMS) pin controlling its operation. Assuming the TAP state machine 1100 starts with a test logic reset, the test clock moves, and when TMS=0, the TAP state machine 1100 enters the run-test / idle state, and then, when TMS=1, the TAP state machine 1100 enters the select IR state, which can enter either the data register path 1110 or the instruction register path 1120. The data register path 1110 contains three important states: Capture-DR, Shift-DR, and Update-DR. In the Capture-DR state, the shift elements of the data registers load the data bits present in their parallel inputs. In the Shift-DR state, the shift elements of the data registers shift the data bits from TDI to TDO along the scan. In Update-DR state, the data bits of the shift element of the data register are latched to the storage element of the data register.

[0059] Figure 12 shows Table 1200 illustrating an example of some bits of the scan / memory element in Figure 10 over 19 consecutive clock cycles (0-18). The TMS row shows the state change sequence of the TAP state machine on local serial network 1020 as follows: Run-Test / Idol(1)→Select-DR-Scan(0)→Capture-DR(0)→Shift-DR(0)→Shift-DR(0)→Shift-DR(0)→Shift-DR(0)→Shift-DR(1)→Exit1-DR(1)→Update-DR(1)→Select-DR-Scan(0)→Capture-DR(0)→Shift-DR(0)→Shift-DR(0)→Shift-DR(0)→Shift-DR(0)→Shift-DR(0)→Shift-DR(0). Here, the numbers in parentheses are the TMS values. The 2-bit shift element 1025 captures C5 and C4 in clock cycle 4 and subsequently shifts these values ​​out. Similarly, the 2-bit shift element 1035 captures and shifts out C3 and C2, and the 2-bit shift element 1045 captures and shifts out C1 and C0. The sequence "C0 C1 C2 C3 C4 C5" is ultimately shifted out via the data streaming network 1010. Meanwhile, S5 and S4 are shifted into the 2-bit shift element 1025 and then latched into the memory element 1027 in clock cycle 12, S3 and S2 are shifted into the 2-bit shift element 1035 and then latched into the memory element 1037 in clock cycle 16, and S1 and S0 are shifted into the 2-bit shift element 1045 and then latched into the memory element 1047 in clock cycle 18.

[0060] Figure 13 shows an example of a data streaming network 1310 coupled to three local serial networks 1320, 1330, and 1340 in broadcast mode, according to various embodiments of the disclosed technology. Similar to the setup shown in Figure 10, the rightmost data channel 1360 of the data streaming network 1310 is configured to transmit the TMS signal, and the second rightmost data channel 1350 is configured to transmit data to the three local serial networks 1320, 1330, and 1340. However, unlike in daisy-chain mode, the local serial networks in broadcast mode typically receive and latch the same data bits (S1 and S0 of local serial networks 1320, 1330, and 1340 respectively versus S1 and S0 of local serial network 1040, S3 and S2 of local serial network 1030, and S5 and S4 of local serial network 1020). Furthermore, only the last local serial network 1340 captures data bits via the data streaming network 1310 and shifts them out. The state change sequence of the TAP state machine is Run-Test / Idle(0) → Run-Test / Idle(1) → Select-DR-Scan(0) → Capture-DR(0) → Shift-DR(0) → Shift-DR(1) → Exit1-DR(1) → Update-DR(0) → Run-Test / Idle.

[0061] Figure 14 shows an example of a data streaming network 1410 coupled to two local serial networks 1420 and 1430 in parallel mode, according to various embodiments of the disclosed technology. In this setup, data channel 1440 is configured to transmit data to and from local serial network 1420, and another data channel 1450 is configured to transmit data to and from local serial network 1430. The three modes described above (daisy-chain mode, broadcast mode, and parallel mode) can be used individually or in any combination, according to various embodiments of the disclosed technology. For example, some local networks may be coupled to the data streaming network in broadcast mode, and the remaining local networks may be coupled to the data streaming network in daisy-chain mode via different data channels of the data streaming network.

[0062] Figure 15 shows an example of a data streaming network 1510 coupled to two local serial networks 1520 and 1530 in time-slot multiplexing mode according to various embodiments of the disclosed technology. While the data streaming network can typically operate in the high 100 MHz range, the IJTAG network often operates at 20 MHz due to various limitations. Using several techniques, such as clock stretching around several special clock cycles, the IJTAG network can operate in the low 100 MHz range. To match the local IJTAG network, the data streaming network can operate at a reduced clock speed. If more bandwidth is required, time-slot multiplexing mode can be used. In the example shown in Figure 15, it is assumed that the data streaming network 1510 operates at 400 MHz, while the local serial networks 1520 and 1530 operate at 100 MHz. The local serial networks 1520 and 1530 can be pre-configured to scan one bit for every four bits scanned by the data streaming network 1510. The specific position (called phase) of each 4-bit sequence being scanned in can also be programmed. In the setup shown in Figure 15, the two local serial networks 1520 and 1530 have the same phase. The two local serial networks 1520 and 1530 can operate in daisy-chain mode or broadcast mode. To use multiple phases for multiple local networks, as shown in Figure 13, the local networks can be coupled to the data streaming network 1510 in parallel mode, i.e., coupled to multiple data channels of the data streaming network 1510.

[0063] A local network primarily transmits data serially. Depending on the circumstances, the local network may include a section configurable to transmit data in parallel. This section can be coupled in parallel to a data streaming network. Figure 16 shows an example of a memory BIST (built-in self-test) section 1610 of a local network 1620 configurable to be coupled in parallel to a data streaming network 1630 (first network), according to various embodiments of the disclosed technology. The network switching interface device 1640 has two devices 1645 and 1647. When device 1645 couples the local network 1620 to a third network 1650, the memory BIST section 1610 can be accessed via the coupled serial network. When device 1647 couples the local network 1620 to a data streaming network 1630, device 1647 can couple the memory BIST section 1610 in parallel to the data streaming network 1630, i.e., to multiple data channels of the data streaming network 1630. This allows simultaneous access to multiple memory BIST controllers, further increasing bandwidth.

[0064] Figure 17 shows a flowchart 1700 illustrating the process of setting up a circuit test via a high-bandwidth serial network enabled by a data streaming network, as implemented according to various examples of the disclosed technology. For ease of understanding, a method for setting up a circuit test via a high-bandwidth serial network enabled by a data streaming network, as employed according to various embodiments of the disclosed technology, will be described with reference to system 700 in Figure 7 and flowchart 1700 shown in Figure 17. However, it should be understood that alternative implementations of the system that utilize a data streaming network to increase the bandwidth of the serial network may be used to perform the method for setting up a circuit test via a high-bandwidth serial network enabled by a data streaming network, as shown by flowchart 1700, according to various embodiments of the disclosed technology. Similarly, system 700 may be employed to implement other methods for setting up a circuit test via a high-bandwidth serial network enabled by a data streaming network, according to various embodiments of the disclosed technology.

[0065] In operation 1710 of flowchart 1700, network configuration data is transmitted over a third network 730 which is coupled to a plurality of second networks, including second networks 720, 725, and 727. The network configuration data includes first network switching interface control data for a plurality of network switching interface devices, including network switching interface devices 740, 745, and 747. The first network switching interface control data enables each of the plurality of network switching interface devices to decouple one of the plurality of second networks from the third network 730 and to couple one of the plurality of second networks to the first network 710. The network configuration data may further include network reconfiguration data for a plurality of multiplexers. The network reconfiguration data allows the first network 710 to bypass zeros, which are one or more of the circuit blocks. The plurality of second networks are reconfigurable and are initially configured to enable the plurality of network switching interface devices and possibly to bypass most of the devices other than the multiplexers. As a result, even though the third network 730 is being used, the data transmission speed does not slow down significantly.

[0066] In operation 1720, setup data is transmitted via the first network 710, which is coupled to several second networks, including the second networks 720, 725, and 727. The setup data includes test setup data for circuit blocks, network setup data for communication between the first network and the circuit blocks, and second network switching interface control data for several network switching interface devices. The test setup data may include data for setting up various test controllers, on-chip clock controllers, phase-locked loop (PLL) clock generators, or any combination thereof. The network setup data may be used to set up devices such as circuit block interface devices (e.g., the first interface device 225 shown in Figure 2). The data transmission speed is significantly increased via the first network 710 compared to via the third network 730, especially considering the amount of data being transmitted. The second network switching interface control data enables each of the multiple network switching interface devices, after setup, to disconnect one of the multiple second networks from the first network 710 and to connect one of the multiple second networks to the third network 730.

[0067] Optionally, in operation 1730, interface enable data is transmitted via a third network 730 coupled to multiple second networks, enabling the circuit block interface device in the first network 710, and then sending test data. To ensure proper operation of some types of the first network 710, the first network 710 should be idle before the circuit block interface device is turned on.

[0068] In operation 1740, test data is sent to the circuit block via the first network 710. The circuit block can then be tested.

[0069] The disclosed technology allows a local network within a circuit block to not only benefit from the parallelism and high-speed capabilities of the data streaming network within the circuit, but also to increase its own operating speed by using clock stretching techniques while pipelining. Figure 18 shows examples of several clock and control signal waveforms illustrating the clock stretching technique. To meet the timing requirements of some clock and control signals, the clock in the IJTAG network typically operates at speeds lower than 100 MHz. However, this limitation can be greatly mitigated by increasing the clock frequency when the control signals are not transitioning. As shown in Figure 18, the ToCaptureEn signal 1810 and the ToShiftEn signal 1820 transition between the Capture DR state 1850 and the ShiftDR state 1860 immediately following the Capture DR state 1850, and the ToShiftEn signal 1820 and the ToUpdateEn signal 1830 transition between the Exit DR state 1870 and the Update DR state 1880. Therefore, the tck_stretched clock signal 1840 only needs to be stretched for four states. In the diagram, the clock is stretched to run at a slower speed for 3 hours. Note that Figure 18 is just one example, and the clock can be stretched to operate at a faster or slower speed than shown in the diagram.

[0070] Stretching the global clock 1070 in Figure 10 is not feasible because the local serial networks 1020, 1030, and 1040 are pipelined and do not change to the same state simultaneously. On the other hand, the locally generated clocks for these local serial networks 1020, 1030, and 1040 can be stretched for the Capture DR state, the Shift DR state immediately following the Capture DR state, the Exit1 DR state, and the running Update DR state of the global clock 1070. As a result, each local serial network can operate at a shift rate of 200 MHz or more, depending on the various implementations of the disclosed technology, which is much faster than a typical IJTAG network in a large circuit. A register 995 in the configuration unit 990 in Figure 9 can be used to store a control signal that determines the number of clock cycles to be stretched for those four states.

[0071] Exemplary computing environment Some embodiments of the disclosed techniques relating to generating systems of streaming data in circuit design can be implemented through the execution of software instructions by a computing device such as a programmable computer. Figure 19 shows an exemplary example of such a programmable computer (computer 1901). As seen in this figure, computer 1901 includes a computing unit 1903 with a processing unit 1905 and a system memory 1907. The processing unit 1905 is any type of programmable electronic device for executing software instructions, but conventionally it is a microprocessor. The system memory 1907 may include both read-only memory 1909 and random-access memory 1911. As will be understood by those skilled in the art, both the read-only memory 1909 and the random-access memory 1911 can store software instructions for execution by the processing unit 1905.

[0072] The processing unit 1905 and the system memory 1907 are connected directly or indirectly to one or more peripheral devices through the bus 1913 or an alternative communication structure. For example, the processing unit 1905 or the system memory 1907 are connected directly or indirectly to one or more additional memory storage devices, such as a “hard” magnetic disk drive 1915, a removable magnetic disk drive 1917, an optical disk drive 1919, or a flash memory card 1921. The processing unit 1905 and the system memory 1907 are also connected directly or indirectly to one or more input devices 1923 and one or more output devices 1925. The input devices 1923 may include, for example, a keyboard, a pointing device (such as a mouse, touchpad, stylus, trackball, or joystick), a scanner, a camera, and a microphone. The output devices 1925 may include, for example, a monitor display, a printer, and a speaker. In various examples of computer 1901, one or more of the peripheral devices 1915-1925 may be housed inside the computing unit 1903. Alternatively, one or more of the peripheral devices 1915-1925 may be located outside the housing for the computing unit 1903 and connected to bus 1913, for example, via a Universal Serial Bus (USB) connection.

[0073] In some implementations, the computing unit 1903 may be directly or indirectly connected to one or more network interfaces 1927 to communicate with other devices that constitute the network. The network interface 1927 converts data and control signals from the computing unit 1903 into network messages according to one or more communication protocols, such as the Transmission Control Protocol and the Internet Protocol. The interface 1927 may also employ any suitable connection agent (or combination of agents) for connecting to the network, including, for example, a wireless transceiver, a modem, or an Ethernet connection. Such network interfaces and protocols are well known in the art and will therefore not be discussed in further detail here.

[0074] Naturally, computer 1901 is illustrated merely as an example and is not limiting. Various embodiments of the disclosed technology can be implemented using one or more computing devices that include the configuration elements of computer 1901 shown in Figure 19, including only a subset of the configuration elements shown in Figure 19, or alternative combinations of configuration elements that include configuration elements not shown in Figure 19. For example, various embodiments of the disclosed technology may be implemented using a multiprocessor computer, a network of single and / or multiprocessor computers, or any combination of both.

[0075] conclusion While the disclosed technology has been described with respect to specific examples, including currently preferred modes for implementing the disclosed technology, those skilled in the art will understand that numerous variations and substitutions of the above-mentioned systems and technologies exist that fall within the spirit and scope of the disclosed technology as described in the appended claims. For example, while the data streaming network shown in Figure 2 is employed to illustrate the disclosed technology, it should be understood that other parallel networks can be used to increase the bandwidth of a serial network.

Claims

1. A system in a circuit comprising: a first network configured to transmit data in parallel within the circuit, the first network comprising circuit block interface devices, each of the circuit block interface devices coupled to a port of one of the circuit blocks within the circuit; a plurality of second networks, each of the plurality of second networks configured to transmit data serially to one of the circuit blocks in the circuit; a third network configured to serially transmit data within said circuit when said circuit is connected to said plurality of second networks; a plurality of network switching interface devices, each of the plurality of network switching interface devices configured to couple either the first network or the third network to one of the plurality of second networks based on control signals stored in each of the plurality of interface devices; A system equipped with

2. The control signal stored in each of the plurality of interface devices is using the third network when the third network is coupled to the one of the plurality of second networks; or using the first network when the first network is coupled to the one of the plurality of second networks; It is updatable, The system of claim 1 .

3. 2. The system of claim 1, wherein the plurality of second networks are configured to be coupled to the first network in a daisy-chain mode, a parallel mode, a broadcasting mode, or a combination thereof.

4. the first network operates at a clock frequency that is a multiple (greater than one) of a clock frequency at which the plurality of second networks operate; the plurality of second networks are coupled to the first network in a time slot multiplexing mode; The system of claim 1 .

5. 2. The system of claim 1, wherein a second network of the plurality of second networks includes a section configured to transmit data in parallel that is configured to be coupled to the first network in parallel.

6. 2. The system of claim 1, wherein one or more of the plurality of second networks employs a clock stretching technique to increase the shift speed.

7. 2. The system of claim 1, wherein the third network and the plurality of second networks are compliant with the IEEE 1687 standard (IJTAG, Internal Joint Test Action Group).

8. the first network further includes a multiplexing device, a pipeline device, or both; the multiplexing device is configured to change a data streaming path of the first network based on further control data transmittable to the multiplexing device via the first network or the plurality of second networks coupled to the third network; The system of claim 1 .

9. each of the plurality of second networks includes a configuration interface device; the configuration interface unit is coupled to one of the circuit block interface units; configuration data for the configuration interface device is transmittable over the respective one of the plurality of second networks coupled to either the first network or the third network; the configuration data includes data determining whether a circuit block interface device of the circuit block is operational and data determining which portions of data transmitted to the first network are to be captured, replaced, or both captured and replaced by each of the circuit block interface devices that is operational; The system of claim 1 .

10. the circuit block interface device includes a register and a clock signal generation logic; the first network includes a data channel and is configured to transmit a plurality of data packets in succession; each of the plurality of data packets having a plurality of bits; each of the plurality of bits being assigned to one of the circuit blocks in which the circuit block interface device is operating; the number of bits is equal to or greater than the number of data channels used to transmit the data packets; The system of claim 1 .

11. each of the plurality of data packets includes one or more bits of a test pattern or a compressed test pattern for testing one or more of the circuit blocks; the clock signal generation logic of a circuit block interface device coupled to a port of one of the circuit blocks is configured to generate a clock signal for scan-based testing; the ports of one of the circuit blocks include inputs and outputs of a scan chain, inputs and outputs of one or more test controllers, or a combination thereof; each of the one or more test controllers includes an expander and a compactor; The system of claim 10.

12. One or more computer-readable media storing computer-executable instructions for causing a computer to perform a method, the method comprising the step of generating, in a circuit design, a system according to any one of claims 1 to 11.

13. 1. A method for testing a circuit, comprising: transmitting network configuration data over a third network coupled to the plurality of second networks, the third network is configured to transmit data serially within the circuit; each of the plurality of second networks is configured to transmit data to one of the circuit blocks of the circuit; the network configuration data includes first network switching interface control data for a plurality of network switching interface devices; the first network switching interface control data operates each of the plurality of second networks to decouple one of the plurality of second networks from the third network and to couple the one of the plurality of second networks to a first network; the first network is configured to transmit data in parallel within the circuit; Steps and transmitting setup data over the first network coupled to the plurality of second networks; the setup data includes test setup data for the circuit block, network setup data for communication between the first network and the circuit block, and second network switching interface control data for the plurality of network switching interface devices; the second network switching interface control data operates the plurality of network switching interface devices to isolate one of the plurality of second networks from the first network and to couple the one of the plurality of second networks to the third network. Steps and transmitting test data to the circuit block via the first network; The method includes:

14. 14. The method of claim 13, wherein the network configuration data further comprises network reconfiguration data for a plurality of multiplexing devices, the network reconfiguration data causing the first network to bypass zero, one, or more of the circuit blocks.

15. 14. The method of claim 13, further comprising the step of transmitting interface enabling data over the third network coupled to the plurality of second networks, activating an interface device between the first network and the circuit block prior to the step of transmitting the test data.