Semiconductor device

Abstract

To suppress hot carrier deterioration without reducing an operation speed, in a semiconductor device that generates an output voltage having a voltage amplitude higher than a withstanding voltage of a transistor.SOLUTION: A P-type transistor MP0 and a P-type transistor MP2 are connected in series between a power supply terminal 11 and an output terminal 13. An N-type transistor MN0 and an N-type transistor MN2 are connected between a ground terminal 12 and a power supply terminal 13. The N-type transistor MN2 and the P-type transistor MP2 are on / off-controlled in a complementary manner in response to an input signal VIN. A gate voltage control circuit 110 changes at least one of gate voltages of the P-type transistor MP0 and the N-type transistor MN0 whose drains are electrically connected with the output terminal 13 so as to follow an output voltage VOUT at the output terminal 13 while maintaining an ON state of the P-type transistor MP0 or the N-type transistor MN0.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device, and more particularly to a semiconductor device for outputting a signal having a voltage amplitude higher than the breakdown voltage of a transistor. [Background technology]

[0002] In a semiconductor device having a level shift circuit, a circuit that receives a low-amplitude logic signal and outputs a high-amplitude logic signal is known to be configured using transistors with a withstand voltage corresponding to the low amplitude. For example, a semiconductor device that generates an output signal set to 0[V] (GND) or 3.3[V] in response to an input signal set to 0[V] (GND) or 1.8[V] is known to be configured using transistors with a withstand voltage of 1.8[V].

[0003] Japanese Patent Application Laid-Open No. 2017-175288 (Patent Document 1) shows a circuit configuration in which a withstand voltage is ensured by connecting two low-voltage transistors in series between a high-voltage power supply terminal and an output terminal where an output signal is generated, and between the output terminal and a ground terminal, respectively, in an output stage. Furthermore, in Patent Document 1, a voltage is supplied to the gate of the low-voltage transistor constituting the output stage when it is turned on via a potential conversion circuit. This keeps the gate-source voltage applied when the low-voltage transistor is turned on low. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2017-175288 A Summary of the Invention [Problem to be solved by the invention]

[0005] In the semiconductor device of Patent Document 1, hot carrier degradation can be suppressed by suppressing the transient drain-source voltage when a low-voltage transistor is turned on.

[0006] However, in the technology of Patent Document 1, the gate-source voltage is kept low, which reduces the operating speed when the transistor is turned on. In other words, it is understood that there is a trade-off between suppressing hot carrier degradation and improving operating speed.

[0007] For this reason, when the technology of Patent Document 1 is applied to a semiconductor device manufactured using an advanced process in which hot carrier degradation is significant, adjusting the gate voltage to suppress hot carrier degradation will result in a significant decrease in the operating speed of the transistor, raising concerns that this may cause problems in application to circuits that require high-speed response.

[0008] The present disclosure is intended to solve the above-mentioned problems, and provides a semiconductor memory device that is capable of suppressing hot carrier degradation without reducing operating speed when generating an output voltage with a voltage amplitude higher than the breakdown voltage of a transistor.

[0009] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0010] A semiconductor device according to an embodiment generates an output signal having a voltage amplitude larger than that of an input signal, and includes a first P-type transistor, a second P-type transistor, a first N-type transistor, a second N-type transistor, and a gate voltage control circuit. The first P-type transistor and the second P-type transistor are connected in series between a power supply line that supplies a first power supply potential and an output terminal at which an output signal is generated. The first N-type transistor and the second N-type transistor are connected in series between a reference potential line that supplies a reference potential and the output terminal. The first N-type transistor and the first P-type transistor have drains electrically connected to the output terminal. Signals for complementarily turning on and off the second N-type transistor and the second P-type transistor according to the input signal are input to the gates of the second N-type transistor and the second P-type transistor, respectively. The gate voltage control circuit changes the gate voltages of the first P-type transistor and the first N-type transistor according to the voltage of the output terminal. The gate voltage control circuit is configured to change at least one of the gate voltage of the first N-type transistor and the gate voltage of the first P-type transistor in accordance with a change in the voltage of the output terminal while keeping the first P-type transistor or the first N-type transistor on when the voltage of the output signal changes in response to a change in the logic level of the input signal. Effect of the Invention

[0011] According to the above embodiment, in a semiconductor device that generates an output voltage with a voltage amplitude higher than the breakdown voltage of a transistor, hot carrier degradation can be suppressed without reducing the operating speed. [Brief description of the drawings]

[0012] [Figure 1] FIG. 2 is a circuit diagram illustrating a configuration of a semiconductor device according to a first comparative example. [Diagram 2] 2 is a diagram showing transient operation waveforms of the semiconductor device shown in FIG. 1. [Diagram 3] 1. FIG. 4 is a transient operation waveform diagram of a modified example of the semiconductor device shown in FIG. [Figure 4]FIG. 11 is a circuit diagram illustrating a configuration of a semiconductor device according to a second comparative example. [Diagram 5] FIG. 1 is a circuit diagram illustrating a configuration of a semiconductor device according to a first embodiment. [Figure 6] 1 is a circuit diagram illustrating a configuration example of an intermediate potential generating circuit. [Figure 7] 4 is a diagram showing transient operation waveforms of the semiconductor device according to the first embodiment. [Figure 8] FIG. 11 is a circuit diagram illustrating a configuration of a semiconductor device according to a second embodiment. [Figure 9] FIG. 11 is a circuit diagram illustrating a configuration of a semiconductor device according to a third embodiment. [Figure 10] FIG. 11 is a circuit diagram illustrating a configuration of a modified example of the semiconductor device according to the present embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, each embodiment will be described in detail with reference to the drawings. In addition, the same or corresponding parts are designated by the same reference characters and description thereof will not be repeated.

[0014] <Explanation of Comparative Example> FIG. 1 is a circuit diagram illustrating the configuration of a semiconductor device 100A according to a first comparative example.

[0015] 1, a semiconductor device 100A according to a first comparative example outputs an output signal having a logic level corresponding to an input signal VIN at an input node Ni to an output terminal 13. The input signal VIN is a binary signal that is set to the ground potential GND, which is the reference potential, at a logic low level (hereinafter, "L level") and is set to a low power supply potential VCCQ at a logic high level (hereinafter, "H level").

[0016] On the other hand, the output signal is set to the ground potential GND at the L level, and is set to the high power supply potential VCCQH higher than the low power supply potential VCCQ at the H level. That is, the amplitude of the output signal is larger than the amplitude of the input signal VIN. As an example, the low power supply potential VCCQ is 1.8 [V], and the high power supply potential VCCQH is 3.3 [V].

[0017] In the following, the voltage value of the output terminal 13 is referred to as the output voltage VOUT. Therefore, when the output signal is at H level, VOUT=VCCQH (3.3 [V]), and when the output signal is at L level, VOUT=GND (0 [V]). When the output signal changes from H level to L level or from L level to H level, the output voltage VOUT changes transiently between the ground potential GND (0 [V]) and the high power supply potential VCCQH (3.3 [V]).

[0018] The semiconductor device 100A is configured similarly to Patent Document 1, and includes an inverter 15, a level shift circuit 20, potential conversion circuits 21 and 22, and P-type transistors MP1 and MP2 and N-type transistors MN1 and MN2 that constitute an output stage. The transistors MP1, MP2, MN1, and MN2 have a breakdown voltage equivalent to the low power supply potential VCCQ (here, 1.8 [V]). In other words, the breakdown voltage of the transistors MP1, MP2, MN1, and MN2 is lower than the potential difference between the high power supply potential VCCQH and the ground potential GND.

[0019] The inverter 15 operates by receiving a low power supply potential VCCQ, and outputs an inverter output signal VINV obtained by inverting an input signal VIN. When the input signal VIN is at a logical low level (hereinafter, "L level"), VINV=VCCQ, and when the input signal VIN is at a logical high level (hereinafter, "H level"), VINV=GND.

[0020] The level shift circuit 20 outputs a level shift signal VLFP that is an inversion of the input signal VIN. The level shift circuit 20 sets VLFP=VCCQH when the input signal VIN is at an L level, and sets VLFP=(1 / 2)·VCCQH when the input signal VIN is at an H level.

[0021] The potential conversion circuit 21 converts the potential of the inverter output signal VINV from the inverter 15 to generate a gate voltage signal VNG2, which is output to the gate of the transistor MN2. The potential conversion circuit 21 has an N-type transistor MN5 that receives a low power supply potential VCCQ at its gate and functions as an NMOS transfer gate. While the amplitude of the inverter output signal VINV is between GND and VCCQ, the amplitude of the gate voltage signal VNG2 output from the potential conversion circuit 21 is between GVD and VCCQ-Vtn, where Vtn is the threshold voltage of the transistor MN5.

[0022] Similarly, the potential conversion circuit 22 converts the potential of the level shift signal VLFP from the level shift circuit 20 to generate a gate voltage signal VPG2, which is output to the gate of the transistor MP2. The potential conversion circuit 22 has a P-type transistor MP5 that receives a low power supply potential VCCQ at its gate and functions as a PMOS transfer gate. While the amplitude of the level shift signal VLFP in a transient state is (1 / 2)·VCCQH to VCCQH, the amplitude of the gate voltage signal VPG2 output from the potential conversion circuit 22 is (1 / 2)·VCCQH+Vtp to VCCQH. Here, Vtp is the threshold voltage of the transistor MP5.

[0023] In the output stage, P-type transistors MP1 and MP2 are connected in series via node NP1 between an output node No connected to the output terminal 13 and a power supply line PL connected to the power supply terminal 11. That is, the source of transistor MP2 is connected to the power supply line PL, and the drain is connected to node NP1. The source of transistor MP1 is connected to node NP1, and the drain is connected to the output node No.

[0024] Similarly, N-type transistors MN1 and MN2 are connected in series via node NN1 between the output node No and a ground line GL connected to the ground terminal 12. That is, the source of transistor MN2 is connected to the ground line GL, and the drain is connected to node NN1. The source of transistor MN1 is connected to node NN1, and the drain is connected to the output node No.

[0025] A bias voltage VREFP is input to the gate of the transistor MP1, and a bias voltage VREFN is input to the gate of the transistor MN1. The bias voltages VREFP and VREFN are set to an intermediate potential between the ground potential GND and the high power supply potential VCCQH, which can turn on the transistors MP1 and MN1. For example, they are set to VREFN=VCCQ and VREFP=(1 / 2)·VCCQH.

[0026] A gate voltage signal VPG2 from the potential converter circuit 21 is input to the gate of the transistor MP2. A gate voltage signal VNG2 from the potential converter circuit 22 is input to the gate of the transistor MN2.

[0027] When the input signal VIN is at the L level (GND), the inverter 15 outputs the H level (VINV=VCCVQ), and the level shift circuit 20 outputs the H level (VLFP=VCCQH). Therefore, VPG2=VCCQH is input to the gate of the transistor MP2, and VNG2=VCCQ-Vtn is input to the gate of the transistor MN2. As a result, the transistor MP2 is turned off, while the transistor MN2 is turned on, so that the ground potential GND is transmitted to the output node No, and the output signal becomes the L level (VOUT=GND).

[0028] Conversely, when the input signal VIN is at the H level (VCCQ), the inverter 15 outputs the L level (VINV=GND), and the level shift circuit 20 outputs the L level (VLFP=(1 / 2)·VCCQH). For this reason, VPG2=(1 / 2)·VCCQH+Vtp is input to the gate of the transistor MP2, and VNG2=GND is input to the gate of the transistor MN2. As a result, the transistor MN2 is turned off while the transistor MP2 is turned on, so that the high power supply potential VCCQH is transmitted to the output node No and the output signal becomes the H level (VOUT=VCCQH).

[0029] In this way, the semiconductor device 100A can receive a low-amplitude (GND to VCCQ) logic signal (input signal VIN) as input and output a high-amplitude (GND to VCCQH) logic signal (output voltage VOUT).

[0030] FIG. 2 shows a transient operation waveform diagram of the semiconductor device 100A shown in FIG. 1, specifically, a transient operation waveform diagram when the input signal VIN changes from H level to L level.

[0031] 2, when the input signal VIN changes from H level (VCCQ=1.8[V]) to L level (GND=0[V]), as described above, the gate voltage signal VPG2 changes from L level ((1 / 2)·VCCQH+Vtp≈2.0[V]) to H level (VCCQH=3.3[V]). Also, the gate voltage signal VNG2 rises from L level (GND=0[V]) to H level (VCCQ-Vtn≈1.0[V]).

[0032] In response to the changes in the gate voltage signals VNG2 and VPG2, in the output stage, the transistor MP2 is turned off, while the transistor MN2 is turned on. In response to this, the output voltage VOUT of the output terminal 13 changes from the H level (VCCQH=3.3 [V]) to the L level (GND=0 [V]).

[0033] When the output voltage VOUT drops, there is a concern that the drain-source voltages Vds1n and Vds2n of the turned-on transistors MN1 and MN2 will become transiently large. The potential VNN1 of the node NN1 corresponding to the connection node of the transistors MN1 and MN2 is equivalent to the bias voltage VREFN input to the gate of the transistor MN1 during the period when the output signal is at the H level (VOUT=VCCQH). If VREFN=VCCQ=1.8[V], then in the transistor MN1, Vds1n=VCCQH-VCCQ=about 1.5[V], and in the transistor MN1, Vds1n=VREFN=about 1.8[V]. At this time, both Vds1n and Vds2n are below the breakdown voltage level (1.8[V]) of the transistors MN1 and MN2.

[0034] 2, in the process in which the gate voltage signal VNG2 rises, the potential VNN1 of the node NN1 falls before the output voltage VOUT, so that Vds1n of the transistor MN1 becomes transiently large. In the semiconductor device 100A, the gate voltage signal VNG2 of the transistor MN2 is generated by the potential conversion circuit 21, thereby suppressing the amount of transient rise in Vds1n of the transistor MN1.

[0035] FIG. 3 shows an operation waveform diagram similar to that of FIG. 2 in the case where the potential conversion circuits 21 and 22 are omitted from the semiconductor device 100A.

[0036] 3, when the potential conversion circuits 21 and 22 are not provided, the gate voltage signal VPG2 rises from 1.8 [V] (L level: (1 / 2)·VCCQH) to 3.3 [V] (H level: VCCQH), more quickly than in FIG. 2. Similarly, the gate voltage signal VNG2 rises from 0 [V] (L level: GND) to 1.8 [V] (H level: VCCQ), more quickly than in FIG. 2.

[0037] Accordingly, in Fig. 3, the turn-on operation of transistor MN2 becomes faster, so the amount of drop in potential VNN1 of node NN1 becomes larger compared to Fig. 2. As a result, in Fig. 3, Vds1n of transistor MN1 becomes excessively large transiently compared to Fig. 2, exceeding the breakdown voltage level (1.8 [V]) and rising to about 2.5 [V]. As a result, hot carrier degradation in transistor MN1 is a concern.

[0038] In other words, in the semiconductor device 100A according to the first comparative example, by providing the potential conversion circuits 21 and 22, the gate-source voltage (Vga2n in FIG. 1) of the transistor MN1 at the time of turn-on can be lowered, and the change in the potential VNN1 of the node NN1 can be made gentler. This reduces the transient Vds1n of the transistor MN1 compared to FIG. 3, and as a result, it becomes possible to suppress hot carrier degradation.

[0039] On the other hand, as can be seen from a comparison of Figure 3 and Figure 2, suppressing the gate-source voltage results in a decrease in the turn-on speed of the transistor, and so the time required for the level transition of the output voltage VOUT (from H level to L level in Figures 2 and 3) increases in Figure 2. In other words, it can be seen that the operating speed of the semiconductor device 100A decreases in exchange for suppressing hot carrier degradation.

[0040] A circuit diagram for explaining the configuration of a semiconductor device according to a second comparative example is shown in Fig. 4. In Fig. 2, in order to avoid a decrease in the operating speed, the potential conversion circuits 21 and 22 in Fig. 2 are not arranged, and the number of transistors connected in series in the output stage is increased to decrease the drain-source voltage per transistor.

[0041] 4, a semiconductor device 100B according to a second comparative example includes P-type transistors MP0 to MP2 and N-type transistors MN0 to MN2 that constitute an output stage. In Fig. 4, the low power supply potential VCCQ and the high power supply potential VCCQH are at the same levels as in Fig. 2. As described above, the breakdown voltage of each of the transistors MN0 to MN2 and MP0 to MP2 that constitute the output stage is equivalent to the low power supply potential VCCQ (1.8 [V]), which is lower than the potential difference between the high power supply potential VCCQH and the ground potential GND.

[0042] P-type transistors MP0 to MP2 are connected in series between the output node No and the power supply line PL via nodes NP1 and NP2. Specifically, the drain of transistor MP0 is connected to the output node No (output terminal 13), and the source is connected to node NP1. The source of transistor MP1 is connected to node NP2, and the drain is connected to node NP1. Moreover, the source of transistor MP2 is connected to the power supply line PL, and the drain is connected to node NP2.

[0043] N-type transistors MN0 to MN2 are connected in series between the output node No and the ground line GL via nodes NN1 and NN2. Specifically, the drain of transistor MN0 is connected to the output node No, and the source is connected to node NN1. The drain of transistor MN1 is connected to node NN1, and the source is connected to node NN2. Moreover, the source of transistor MP2 is connected to the ground line GL, and the drain is connected to node NN2.

[0044] A fixed bias voltage VREFP0 is input to the gate of transistor MP0, and a fixed bias voltage VREFP1 is input to the gate of transistor MP1. For example, VREFP0=VREFP1=0.5·VCCQH is set. An output signal (VLFP) of the level shift circuit 20 of FIG. 1 is input to the gate of transistor MP2 without passing through the potential conversion circuit 22 (FIG. 1). That is, the gate voltage signal VPG2 of transistor MP2 has an amplitude of (1 / 2)·VCCQH to VCCQH, that is, (1 / 2)·3.3 [V] to 3.3 [V].

[0045] A fixed bias voltage VREFN0 is input to the gate of transistor MN0, and a fixed bias voltage VREFN1 is input to the gate of transistor MN1. For example, VREFN0=VREFN1=VCCQ is set. An output signal (VINV) of the inverter 15 in FIG. 1 is input to the gate of transistor MN2 without passing through the potential conversion circuit 21 (FIG. 1). That is, the gate voltage signal VNG2 of transistor MN2 has an amplitude of GND to VCCQ, that is, 0 [V] to 1.8 [V].

[0046] In the semiconductor device 100B, consider the operation of transistors MN0 to MN2 when the gate voltage signal VNG2 changes from 0 [V] to 1.8 [V] (low power supply potential VCCQ) in response to a change in the logic level of the input signal VIN, and the output voltage VOUT drops from 3.3 [V] to 0 [V] (VCCQH).

[0047] First, consider the first case where VREFN0=VREFN1, for example, both are 1.8 [V]. In the first case, when the output voltage VOUT changes from H level to L level in response to an increase in the output voltage (VNG2) of the inverter 15, the transistors MN2 and MN1 are turned on in that order. Therefore, due to a drop in the potential of the node NN1, the drain-source voltage Vds0n of the transistor MN0 on the output terminal 13 side increases, and the hot carrier degradation of the transistor MN0 increases.

[0048] Next, consider the second case where VREFN0>VREFN1, for example, VREFN0=2.2[V] and VREFN1=1.8[V]. In the second case, the potential of the node NN1 becomes higher than in the first case described above by increasing the gate-source voltage Vgs0n of the transistor MN0, whose gate receives VREFN0. This suppresses the drain-source voltage Vds0n of the transistor MN0, i.e., hot carrier degradation, more than in the first case. However, in the second case, when the output voltage VOUT of the output terminal 13 drops to 0[V], there is a concern that an overvoltage of 2.2[V] will be applied between the drain and gate of the transistor MN0, which has a breakdown voltage of 1.8[V]. In other words, in the first case, the gate voltage (VREFN0) of the transistor MN0 is set so that an overvoltage is not applied between the drain and gate of the transistor MN0 even if the output voltage VOUT drops to 0[V].

[0049] As described above, the inventors have discovered that in the semiconductor device 100B of the second comparative example, a new challenge is to set the gate voltage for transistors MN0 and NP0, whose drains are connected to the output terminal 13, so as not to exceed the breakdown voltage and to suppress hot carrier degradation.

[0050] <First embodiment> FIG. 5 is a circuit diagram illustrating the configuration of the semiconductor device 101A according to the first embodiment.

[0051] As shown in FIG. 5, the semiconductor device 101A includes a level shift circuit 20, a gate voltage control circuit 110, N-type transistors MN0 to MN2, and P-type transistors MP0 to MP0.

[0052] The transistors MN0-MN2 and MP0-MP0 configure an output stage similar to that of the semiconductor device 100B according to the second comparative example. That is, of the N-type transistors MN0-MN2 connected in series between the output terminal 13 and the ground line GL, the transistor MN0 is disposed closest to the output terminal 13 and has a drain electrically connected to the output terminal 13. The withstand voltages of the transistors MN0-MN2 and MP0-MP2 are also similar to those described in FIG.

[0053] Similarly, of the P-type transistors MP0 to MP2 connected in series between the output terminal 13 and the power supply line PL, the transistor MP0 is arranged closest to the output terminal 13 and has a drain electrically connected to the output terminal 13.

[0054] 1 is input as a gate voltage signal VPG2 to the gate of transistor MP2. Therefore, when the input signal VIN is at the L level (GND=0[V]), VCCQH (3.3[V]) is input to the gate of transistor MP2, and when the input signal VIN is at the H level (VCCQ=1.8[V]), (1 / 2)·VCCQH (1.65[V]) is input to the gate of transistor MP2.

[0055] 1 is input as a gate voltage signal VGN0 to the gate of transistor MN2. That is, when the input signal VIN is at an L level, the low power supply potential VCCQ is input to the gate of transistor MN2, and when the input signal VIN is at an H level, the ground potential GND is input to the gate of transistor MN2. In this way, signals for complementarily turning on and off transistors MN2 and MP2 in accordance with the input signal VIN are input to the gates of transistors MN2 and MP2, respectively.

[0056] 5, transistor MP0 corresponds to an embodiment of a "first P-type transistor", transistor MP2 corresponds to a "second P-type transistor", and transistor MP1 corresponds to an embodiment of a "third P-type transistor". Similarly, transistor MN0 corresponds to an embodiment of a "first N-type transistor", transistor MN2 corresponds to an embodiment of a "second N-type transistor", and transistor MN1 corresponds to an embodiment of a "third N-type transistor". In addition, the ground potential GND corresponds to an embodiment of a "reference potential", the high power supply potential VCCQH corresponds to an embodiment of a "first power supply potential", the low power supply potential VCCQ corresponds to an embodiment of a "second power supply potential", and the ground line GL corresponds to an embodiment of a "reference potential line".

[0057] In the semiconductor device 101A, when the input signal VIN is at H level (VCCQ=1.8 [V]), the output terminal 13 is electrically connected to the power supply terminal 11 by turning on the transistors MP0 to MP2, and the output voltage VOUT is set to VCCQH (3.3 [V]). On the other hand, when the input signal VIN is at L level (GND=0 [V]), the output terminal 13 is electrically connected to the ground terminal 12 by turning on the transistors MN0 to MN2, and the output voltage VOUT is set to GND (0 [V]).

[0058] A bias voltage VREFP for turning on the transistor MP1 is input to the gate of the transistor MP1, and a bias voltage VREFN for turning on the transistor MN1 is input to the gate of the transistor MN1. For example, the bias voltages VREFP, VREFN are set corresponding to an intermediate potential between the high power supply potential VCCQH and the ground potential GND. For example, the bias voltages VREFP, VREFN can be generated by an intermediate potential generating circuit 120 shown in Fig. 6. The bias voltage VREFP corresponds to an embodiment of a "first bias voltage", and the bias voltage VREFN corresponds to an embodiment of a "second bias voltage".

[0059] Referring to FIG. 6, the intermediate potential generation circuit 120 has resistor elements R2 and R3 connected in series between the power supply line PL and the ground line GL via intermediate potential nodes NRFP and NRFN. As a result, an intermediate potential obtained by dividing the high power supply potential VCCQH by the resistor elements R2 and R3 is generated at the intermediate potential nodes NRFP and NRFN.

[0060] The potential of the intermediate potential node NRFP is input as a bias voltage VREFP to the gate of the transistor MP1 and to the gate voltage control circuit 110. Similarly, the potential of the intermediate potential node NRFN is input as a bias voltage VREFN to the gate of the transistor MN1 and to the gate voltage control circuit 110. Accordingly, 0 < VREFN, VREFP < VCCQH (3.3 [V]), and VREFN and VREFP are determined by the voltage division ratio of the resistor elements R2 and R3.

[0061] Note that the bias voltages VREFN and VREFP may be set to the same potential by a common intermediate potential generation circuit 120, or may be set to different potentials by individual intermediate potential generation circuits 120 having different voltage division ratios.

[0062] Referring to FIG. 5 again, the gate voltage control circuit 110 includes N-type transistors MN11 and MN12 and P-type transistors MP11 and MP12. The gate voltage control circuit 110 controls the gate voltage signal VPG0 of the transistor MP0 and the gate voltage signal VNG0 of the transistor MN0 according to the output voltage VOUT of the output terminal 13.

[0063] The sources of the transistors MN11 and MN12 are electrically connected to a node NPG0 that transmits the gate voltage signal VPG0 to the transistor MP0. The drain of the transistor MN11 is electrically connected to the output terminal 13 via the resistor element R1, and the drain of the transistor MN12 is electrically connected to the intermediate potential node NRFP of the intermediate potential generation circuit 120.

[0064] A bias voltage VREFP from the intermediate potential generation circuit 120 is input to the gate of the transistor MN11, and the gate of the transistor MN12 is electrically connected to the output terminal 13 via the resistor element R1. The transistor MN11 corresponds to an embodiment of the "fourth N-type transistor", and the transistor MN12 corresponds to an embodiment of the "fifth N-type transistor", respectively.

[0065] The sources of the transistors MP11 and MP12 are electrically connected to a node NNG0 that transmits the gate voltage signal VNG0 to the transistor MN0. The drain of the transistor MP11 is electrically connected to the output terminal 13 via the resistor element R1, and the drain of the transistor MP12 is electrically connected to the intermediate potential node NRFN of the intermediate potential generation circuit 120.

[0066] A bias voltage VREFN from the intermediate potential generation circuit 120 is input to the gate of the transistor MP11, and the gate of the transistor MP12 is electrically connected to the output terminal 13 via the resistor element R1. That is, the transistor MP11 corresponds to an embodiment of the "fourth P-type transistor", and the transistor MP12 corresponds to an embodiment of the "fifth P-type transistor", respectively.

[0067] Thereby, the gate voltage signal VNG0 of the transistor MN0 is controlled according to the high and low relationship between the output voltage VOUT of the output terminal 13 and the bias voltage VREFN according to the on / off states of the transistors MP11 and MP12. Specifically, when VOUT < VREFN, the gate voltage signal VNG0 is set to the bias voltage VREFN by turning on the transistor MP12. On the other hand, when VOUT > VREFN, the gate voltage signal VNG0 is set to change following the output voltage VOUT by turning on the transistor MP11.

[0068] Similarly, the gate voltage signal VPG0 of transistor MP0 is controlled according to the high or low relationship between the output voltage VOUT of output terminal 13 and the bias voltage VREFP in response to the on / off states of transistors MN11 and MN12. Specifically, when VOUT > VREFP, the gate voltage signal VPG0 is fixed to the bias voltage VREFP due to the turning on of transistor MN12. On the other hand, when VOUT < VREFP, the gate voltage signal VPG0 is set to change following the output voltage VOUT due to the turning on of transistor MN11.

[0069] In this way, the gate voltage control circuit 110 operates such that at least one of the gate voltage signals VNG0 and VPG0 changes following the output voltage VOUT in the transient state where the output voltage VOUT changes between GND and VCCQH while maintaining transistor MP0 or MN0 in the on state.

[0070] Next, in semiconductor device 101A, a transient operation in which the output voltage VOUT changes from the state of VOUT = VCCQH (H level) to VOUT = GND (L level) due to the turning on of transistors MN0 to MN2 will be described.

[0071] In this transient operation, the gate voltage signal VNG0 of transistor MN0 decreases following the output voltage VOUT, starting from a voltage higher than the bias voltage VREFN (VOUT = VCCGH). Thus, similar to the second case described for semiconductor device 100B according to the second comparative example, the drain-source voltage Vds0n of transistor MN0 generated in response to the turning on of transistors MN2 and MN1 can be suppressed.

[0072] In the process where the output voltage VOUT further decreases in response to the turn-on of transistors MN0 to MN2, when VOUT < VREFN, the gate voltage signal VNG0 is set equal to the bias voltage VREFN. Therefore, by setting the bias voltage VREFN below the breakdown voltage of transistor MN0, transistor MN0 can be prevented from having an overvoltage applied between its drain and gate in the same manner as in the first case described for the semiconductor device 100B according to the second comparative example while maintaining the on state.

[0073] Next, in the semiconductor device 101A, a transient operation in which the output voltage VOUT changes from the state of VOUT = GND (L level) to VOUT = VCCQH (H level) due to the turn-on of transistors MP0 to MP2 will be described.

[0074] In this transient operation, the gate voltage signal VPG0 of transistor MP0 rises after starting from a voltage lower than the bias voltage VREFP (VOUT = GND) following the output voltage VOUT. Thereby, the drain-source voltage Vds0p of transistor MP0 generated in response to the turn-on of transistors MP2 and MP1 can be suppressed.

[0075] In the process where the output voltage VOUT further increases in response to the turn-on of transistors MP0 to MP2, when VOUT > VREFP, the gate voltage signal VNG0 is fixed to the bias voltage VREFP. Therefore, by setting the bias voltage VREFP below the breakdown voltage of transistor MP0, transistor MN0 will not have an overvoltage applied between its drain and gate while maintaining the on state.

[0076] In this way, due to the arrangement of the gate voltage control circuit 110, for transistors MN0 and NP0 whose drains are electrically connected to the output terminal 13, the gate voltage can be controlled so as to suppress hot carrier degradation without exceeding the breakdown voltage in a manner that enjoys both the advantages of the first and second cases in the semiconductor device 100B according to the second comparative example.

[0077] In the semiconductor device 101A according to the first embodiment, the gate voltage signals VPG2, VNG2 of the transistors MN2, MP2 are generated without disposing the potential conversion circuits 21, 22 in the semiconductor device 100A according to the first comparative example. That is, by suppressing the gate-source voltages of the transistors MN2, MP2 when they are turned on, it is possible to both suppress hot carrier degradation without reducing the operating speed.

[0078] Fig. 7 shows a transient operation waveform diagram of the semiconductor device 101A shown in Fig. 5, specifically, a transient operation waveform diagram when the input signal VIN changes from H level to L level. Note that Fig. 7(a) shows the transient operation waveform diagram of the semiconductor device 101A, while Fig. 7(b) shows the transient operation waveform diagram of the semiconductor device 100A (first comparative example). Fig. 7(b) shows the waveform diagram of Fig. 2 again on the same time axis as Fig. 7(a).

[0079] As shown in FIG. 7(a), the gate voltage signal VPG2 rises from 1.8 [V] (L level: (1 / 2)·VCCQH) to 3.3 [V] (H level: VCCQH) more quickly in FIG. 7(b) than in FIG. 2, as in FIG. 3. Similarly, the gate voltage signal VNG2 rises from 0 [V] (L level: GND) to 1.8 [V] (H level: VCCQ) more quickly than in FIG. 7(b). Therefore, it can be seen that the turn-on operation of transistor MN2 is faster in FIG. 7(a) than in FIG. 7(b), and the rate of change of the output voltage VOUT is also higher.

[0080] 7(a), when the gate voltage signal VNG2 rises, the gate voltage signal VNG0 is set higher than VREFN (1.8 [V]) by the gate voltage control circuit 110 in accordance with the output voltage VOUT. As a result, by reducing the on-resistance of the transistor MN0, the amount of decrease in the potential (VNN1) of the node NN1 can be suppressed, and the transient drain-source voltage Vds0n of the transistor MN0 can be reduced to the same level as or lower than Vds1n in FIG. 7(b). This makes it possible to suppress hot carrier degradation in the same way as in the first comparative example.

[0081] In this way, according to the semiconductor device 101A of the first embodiment, when generating an output voltage with a voltage amplitude (here, 3.3 [V]) higher than the breakdown voltage of the transistor (here, 1.8 [V]), hot carrier degradation can be suppressed in the same manner as in the first comparative example (semiconductor device 100A) without reducing the operating speed as in the first comparative example (semiconductor device 100A).

[0082] <Second embodiment> FIG. 8 is a circuit diagram illustrating the configuration of a semiconductor device 101B according to the second embodiment.

[0083] 8 and 5, semiconductor device 101B is different from semiconductor device 100A (FIG. 5) according to the first embodiment in that the gates of transistors MN12 and MP12 in gate voltage control circuit 110 are connected to different destinations. Specifically, the gate of transistor MN12 is electrically connected to node NP1 corresponding to the source of transistor MP0, rather than output terminal 13. Similarly, the gate of transistor MP12 is electrically connected to node NN1 corresponding to the source of transistor MN0, rather than output terminal 13. Since other configurations of semiconductor device 101B are similar to those of semiconductor device 101A, detailed description will not be repeated.

[0084] In the semiconductor device 101B, in a transient operation in which the output voltage VOUT changes from an H level to an L level in response to the turning on of the transistors MN0 to MN2, the potential of the node NN1 closer to the ground terminal 12 drops earlier than the potential of the output terminal 13. This allows the gate voltage control circuit 110 to turn on the transistor MP12 before the transistor MP11 turns off.

[0085] Similarly, in a transient operation in which the output voltage VOUT changes from an L level to an H level in response to the turning on of the transistors MN0 to MN2, the potential of the node NP1 closer to the power supply terminal 11 rises earlier than the potential of the output terminal 13. This allows the gate voltage control circuit 110 to turn on the transistor MN12 before the transistor MN11 turns off.

[0086] 5, the gates of the transistors MN12, MP12 are electrically connected to the output terminal 13. Therefore, during a period in which the output voltage VOUT is transiently equal to the bias voltages VREFN, VREFP, both of the transistors MP11, MP12, or both of the transistors MN11, MN12 may be turned off. Specifically, during a period in which the voltage difference between the bias voltage VREFN or VREFP and the output voltage VOUT is smaller than the threshold voltage of the transistors MN11, MN12 or the threshold voltage of the transistors MP111, MP12, both of the transistors MP11, MP12, or both of the transistors MN11, MN12 are turned off.

[0087] In this way, when both the transistors MP11 and MP12 or both the transistors MN11 and MN12 are turned off, the node NNG0 or NPG0 becomes floating, which may cause the gate voltage signals VNG0 and VPG0 to become transiently unstable. For example, during the period when the node NNG0 or NPG0 is floating, the gate voltage signals VNG0 and VPG0 change due to the influence of the voltage change at the output terminal 13 through capacitive coupling, which may cause the on-current of the transistors MN0 and MP0 to decrease. In particular, during high-speed operation, the decrease in operating speed due to the decrease in on-current may destabilize the operation of the semiconductor device 101A.

[0088] In the semiconductor device 101B according to the second embodiment, the gate voltage signals VNG0 and VPG0 can be stabilized by changing the gate connection destination of the transistors MN12 and MP12 in the gate voltage control circuit 110 from that in the first embodiment. This allows the semiconductor device 101B to operate stably even under high-speed operation.

[0089] <Third embodiment> In the third embodiment, a configuration is described that enables a semiconductor device of the first or second embodiment to be switched between a low-voltage operation mode in which the amplitude of an output signal corresponds to a low power supply potential VCCQ, and a high-voltage operation mode in which the amplitude corresponds to a high power supply potential VCCQH.

[0090] 9 is a circuit diagram for explaining the configuration of a semiconductor device 101C according to a third embodiment. The semiconductor device 101C is configured to be operable by selecting, in accordance with a power supply mode signal POC*, a high voltage operation mode in which VCCQH=3.3 [V] supplied to the power supply terminal 11 and the power supply line PL, and a low voltage operation mode in which VCCQH=1.8 [V]. Here, the power supply mode signal POC* is set to an L level in the high voltage operation mode, and is set to an H level in the low voltage operation mode. The high voltage operation mode corresponds to an example of a "first operation mode", and the low voltage operation mode corresponds to an example of a "second operation mode".

[0091] 9 and 5, semiconductor device 101C differs from semiconductor device 100A (FIG. 5) according to the first embodiment in that it includes a gate voltage control circuit 111 instead of gate voltage control circuit 110. Gate voltage control circuit 111 further includes connection selection circuits 115 and 116 in addition to the configuration of gate voltage control circuit 110 shown in FIG. 8. Since other configurations of semiconductor device 101C are similar to those of semiconductor device 101A, detailed description will not be repeated.

[0092] The connection selection circuit 115 has N-type transistors MN13 and NM14. The transistors MN13 and MN14 are connected in series between the node NPG0 (the gate of the transistor MP0) and the ground line GL. A bias voltage VREFN is input to the gate of the transistor MN13, and a power supply mode signal POC* is input to the gate of the transistor MN14. The connection selection circuit 115 corresponds to a "first connection selection circuit" provided for the gate of the transistor MP0.

[0093] The connection selection circuit 116 has N-type transistors MN15 and MN16 and P-type transistors MP13 and MP14. The transistor MP14 is connected between a node NNG0 (the gate of the transistor MN0) and an intermediate potential node NRFN. The gate of the transistor MP14 is connected to a node Nx. The transistor MP13 is connected between the power supply line PL and the node Nx. A bias voltage VREFN is input to the gate of the transistor MP13.

[0094] The transistors MN15 and MN16 are connected in series between the node Nx and the ground line GL. A bias voltage VREFN is input to the gate of the transistor MN15. A power supply mode signal POC* is input to the gate of the transistor MN16. The connection selection circuit 116 corresponds to a "second connection selection circuit" provided for the gate of the transistor MN0.

[0095] In the low voltage operation mode, the power supply mode signal POC* is set to the H level, VCCQH=1.8 [V], and the bias voltages VREFN, VREFP are set to about 0.8 [V] to 1.0 [V].

[0096] When transistor MN14 is turned on in response to POC*=H, the source of transistor MN13, which receives bias voltage VREFN at its gate, becomes ground potential GND, so that transistor MN13 is also turned on. When transistors MN13 and MN14 are turned on, connection selection circuit 115 electrically connects node NPG0, which transmits gate voltage signal VPG0, to the ground line GL.

[0097] Similarly, in the low-voltage operation mode, in conjunction with the turning on of transistor MN16, which receives the power supply mode signal POC* at its gate, transistor MN15, which receives the bias voltage VREFN at its gate, also turns on. In response to the turning on of transistors MN15 and MN16, node Nx becomes the ground potential GND, turning off transistor MP13, which receives the bias voltage VREFN at its gate, while transistor MP14, whose gate is connected to node Nx, turns on. As a result, the connection selection circuit 116 electrically connects node NNG0, which transmits the gate voltage signal VNG0, to the intermediate potential node NRFN, which supplies the bias voltage VREFN.

[0098] As a result, in the low voltage operation mode (POC*=H level), the gate voltage control circuit 111 fixes the gate voltage signal VPG0 to the ground potential GND and fixes the gate voltage signal VNG0 to the bias voltage VREFN, regardless of the operation of the gate voltage control circuit 110, i.e., regardless of the output voltage VOUT.

[0099] Therefore, in the low-voltage operation mode, in the semiconductor device 101C, the transistors MN0 and MP0 are maintained in the on state regardless of the output voltage VOUT. Also, in the low-voltage operation mode, the voltage conversion function by the level shift circuit 20 is stopped, and a signal equivalent to the inverter output signal VINV (0 to 1.8 [V]) from the inverter 15 is input to the gate of the transistor MP2. As a result, the semiconductor device 101C operates to output the output voltage VOUT according to the input signal VIN (0 to 1.8 [V]) with an amplitude of 0 [V] (GND) to 1.8 [V] (VCCQH).

[0100] In contrast, in the high-voltage operation mode in which the power supply mode signal POC* is set to the L level, the additional transistors MN13 to MN16 are turned off in the gate voltage control circuit 111. Furthermore, with VCCQH=3.3 [V] and VREFN=1.8 [V], the transistor MP13 is turned on, and the high power supply potential VCCQH (3.3.3 [V]) is transmitted to the node Nx. As a result, the transistor MP14 is maintained off.

[0101] As a result, the connection selection circuit 115 electrically disconnects the node NPG0 from the ground line GL. Similarly, the connection selection circuit 116 electrically disconnects the node NNG0 from the intermediate potential node NRFN. Therefore, in the high voltage operation mode (POC*=L level), the gate voltage control circuit 111 controls the potentials of the gate voltage signals VNG0 and VPG0 by the gate voltage control circuit 110 similar to that of FIG. 5. That is, the gate voltage signals VNG0 and VPG0 are controlled similarly to the first embodiment. As a result, the semiconductor device 101C operates similarly to the semiconductor device 101A, and outputs an output voltage VOUT corresponding to the input signal VIN (0 to 1.8 [V]) with an amplitude of 0 [V] (GND) to 3.3 [V] (VCCQH).

[0102] As described above, in the semiconductor device 101A according to the first embodiment, when the difference between the output voltage VOUT and the bias voltages VREFN, VREFP is smaller than the threshold voltage of the transistor, a period occurs in which both the transistors MN11 and MN12 are off, or both the transistors MP11 and MP12 are off in the gate voltage control circuit 110. This may cause a concern that the potentials of the gate voltage signals VNG0, VPG0 may become unstable. Therefore, when the semiconductor device 101A is operated in a low-voltage operation mode (VCCQH=1.8[V]), there is a concern that the ratio of the period during which the potentials of the gate voltage signals VNG0, VPG0 described above become unstable to the entire period of the transient state during which the output voltage VOUT changes between GND (0[V]) and VCCQH (1.8[V]) increases.

[0103] In contrast, in the semiconductor device 101C according to the third embodiment, in the low-voltage operation mode, the gate voltage signals VNG0 and VPG0 can be controlled to fix the transistors MN0 and MP0 to on. As a result, in the low-voltage operation mode, it is possible to prevent the operation from becoming unstable due to a change in the on-current of the transistors MN0 and MP0.

[0104] In addition, in the semiconductor device 101C according to the third embodiment, the gates of the transistors MN12 and MP12 included in the gate voltage control circuit 110 can be connected to the nodes NN1 and NP1, respectively, as in Fig. 7. That is, by combining the semiconductor device 101B (Fig. 8) according to the second embodiment with the third embodiment, it is also possible to operate the semiconductor device 101C in the same way as the semiconductor device 101B in the high-voltage operation mode.

[0105] In addition, in the first to third embodiments, the arrangement of the transistors MN1 and MN2 can be interchanged, and the transistor MN2 can be arranged on the side of the ground terminal 12. Similarly, the arrangement of the transistors MP1 and MP2 can be interchanged, and the transistor MP2 can be arranged on the side of the power supply terminal 11.

[0106] In the first to third embodiments, an example is assumed in which transistors with a breakdown voltage of 1.8 V are connected in series to set the amplitude of the output voltage VOUT to 3.3 V. For this reason, a configuration example in which three transistors are connected in series between the power supply line PL and the ground line GL and the output node No (output terminal 13) has been described, but it should be noted that the number of transistors connected in series that constitute the output stage is not limited to the examples given above.

[0107] In the first to third embodiments, a configuration example has been described in which one each of MN2, MP2 (first transistor) whose gate receives a voltage corresponding to the input signal VIN, MN0, MP0 (second transistor) whose gate voltage is controlled by the gate voltage control circuits 110, 111, and MN1, MP1 (third transistor) whose gate receives bias voltages VREFP, VREFN has been arranged. However, in order to ensure a withstand voltage between the drain and source, any number of transistors of the same conductivity type may be additionally arranged between the transistors MN2, MP2 and MN1, MP1, and / or between the transistors MN0, MP0 and MN1, MP1. In this case, the gate voltage of the additionally arranged transistors may be controlled in the same manner as any one of the transistors MN2, MP2 (first transistor), the transistors MN0, MP0 (second transistor), or the transistors MN1, MP1 (third transistor).

[0108] Alternatively, the semiconductor device according to this embodiment can be configured without disposing the transistors MN1 and MP1 to whose gates the bias voltages VREFP and VREFN are input.

[0109] FIG. 10 is a circuit diagram illustrating the configuration of a modified example of the semiconductor device according to the present embodiment.

[0110] 10 and 5, the semiconductor device 101D according to the modification is different from the semiconductor device 100A according to the first embodiment (FIG. 5) in that the arrangement of the transistor MN1, the gate of which is input with the bias voltage VREFP, and the transistor MP1, the gate of which is input with the bias voltage VREFP, is omitted. Therefore, the output stage is composed of P-type transistors MP0 and MP2 connected in series between the power supply line PL and the output node No via the node NP1, and N-type transistors MN0 and MN2 connected in series between the ground line GL and the output node No via the node NN1.

[0111] The gate voltages of the transistors MN2 and MP2 are controlled to turn on and off the transistors MN2 and MP2 in a complementary manner in accordance with the input signal VIN, as in the first embodiment. The gates of the transistors MN0 and MP0 are input with gate voltage signals VNG0 and VPG0 generated by a gate voltage control circuit 110 similar to that shown in Fig. 5 or 8. Alternatively, the gates of the transistors MN0 and MP0 may be input with gate voltage signals VNG0 and VPG0 generated by a gate voltage control circuit 111 shown in Fig. 9.

[0112] 10, any number of transistors of the same conductivity type can be additionally arranged between the transistors MN0, MP0 and the transistors MP2, MN2. In this case, the gate voltage of the additionally arranged transistors can be controlled in the same manner as either the transistors MN2, MP2 (first transistors) or the transistors MN0, MP0 (second transistors).

[0113] With regard to the multiple embodiments described above, we would like to confirm that it is intended from the beginning of the application that the configurations described in each embodiment may be appropriately combined, including combinations not mentioned in the specification, to the extent that no inconsistencies or contradictions arise.

[0114] While the present disclosure has been specifically described above based on the embodiments, it goes without saying that the present disclosure is not limited to the embodiments and can be modified in various ways without departing from the spirit of the present disclosure. [Explanation of symbols]

[0115] 11 power supply terminal, 12 ground terminal, 13 output terminal, 15 inverter, 20 level shift circuit, 21, 22 potential conversion circuit, 100A, 100B, 101A to 101D semiconductor device, 110, 111 gate voltage control circuit, 115, 116 connection selection circuit, 120 intermediate potential generation circuit, GL ground line, GND ground potential, NRFN, NRFP intermediate potential node, Ni input node, No output node, PL power supply line, POC* power supply mode signal, R1 to R3 resistor elements, VCCQ low power supply potential, VCCQH high power supply potential, VIN input signal, VINV inverter output signal, VLFP level shift signal, VNG0, VNG2, VPG0, VPG2 gate voltage signal, VOUT output voltage, VREFN, VREFN0, VREFN1, VREFP, VREFP0, VREFP1 bias voltage.

Claims

1. A semiconductor device that generates an output signal having a voltage amplitude larger than that of an input signal at an output terminal, a first P-type transistor and a second P-type transistor connected in series between a power supply line that supplies a first power supply potential and the output terminal; a first N-type transistor and a second N-type transistor connected in series between a reference potential line that supplies a reference potential and the output terminal; the first N-type and P-type transistors have drains electrically connected to the output terminal; a signal for complementarily turning on and off the second N-type and P-type transistors in accordance with the input signal is input to the gates of the second N-type and P-type transistors, respectively; The semiconductor device includes: a gate voltage control circuit for changing the gate voltages of the first P-type and N-type transistors in response to a voltage of the output terminal; the gate voltage control circuit is configured to change the gate voltage of at least one of the first N-type and P-type transistors in response to a change in the voltage of the output terminal while keeping the first P-type or N-type transistor on when the voltage of the output signal changes in response to a change in the logic level of the input signal.

2. the gate voltage control circuit is configured to input the first bias voltage to the gate of the first P-type transistor when the voltage of the output terminal is higher than a predetermined first bias voltage, and to input a voltage according to the voltage of the output terminal to the gate of the first P-type transistor when the voltage of the output terminal is lower than the first bias voltage; 2. The semiconductor device according to claim 1, wherein said first bias voltage is equal to or lower than a breakdown voltage of said first P-type transistor.

3. The semiconductor device includes: a third P-type transistor connected in series with the second P-type transistor between the first P-type transistor and the power supply line; 3. The semiconductor device according to claim 2, wherein said first bias voltage is input to a gate of said third P-type transistor.

4. the gate voltage control circuit is configured to input the second bias voltage to the gate of the first N-type transistor when the voltage of the output terminal is lower than a predetermined second bias voltage, and to input a voltage according to the voltage of the output terminal to the gate of the first N-type transistor when the voltage of the output terminal is higher than the second bias voltage; 2. The semiconductor device according to claim 1, wherein said second bias voltage is equal to or lower than a breakdown voltage of said first N-type transistor.

5. The semiconductor device includes: a third N-type transistor connected in series with the second N-type transistor between the first N-type transistor and the reference potential line; 5. The semiconductor device according to claim 4, wherein said second bias voltage is input to a gate of said third N-type transistor.

6. The gate voltage control circuit includes: a fourth N-type transistor having a source connected to the gate of the first P-type transistor and a drain electrically connected to the output terminal; a fifth N-type transistor having a source connected to the gate of the first P-type transistor and a drain electrically connected to a node supplying the first bias voltage; the first bias voltage is input to a gate of the fourth N-type transistor; 3. The semiconductor device according to claim 2, wherein a gate of said fifth N-type transistor is electrically connected to said output terminal.

7. the semiconductor device operates by selectively applying a first operation mode in which the first power supply potential is set to a first potential and a second operation mode in which the first power supply potential is set to a second potential lower than the first potential; 7. The semiconductor device according to claim 6, wherein the gate voltage control circuit further includes a first connection selection circuit configured to electrically connect the gate of the first P-type transistor to the reference potential line in the second operation mode, while electrically disconnecting the gate of the first P-type transistor from the reference potential line in the first operation mode.

8. The gate voltage control circuit includes: a fourth N-type transistor having a source connected to the gate of the first P-type transistor and a drain electrically connected to the output terminal; a fifth N-type transistor having a source connected to the gate of the first P-type transistor and a drain electrically connected to a node supplying the first bias voltage; the first bias voltage is input to a gate of the fourth N-type transistor; 3. The semiconductor device according to claim 2, wherein a gate of said fifth N-type transistor is electrically connected to a source of said first P-type transistor.

9. The gate voltage control circuit includes: a fourth P-type transistor having a source connected to the gate of the first N-type transistor and a drain electrically connected to the output terminal; a fifth P-type transistor having a source connected to the gate of the first N-type transistor and a drain electrically connected to a node supplying the second bias voltage; the second bias voltage is input to a gate of the fourth P-type transistor; 5. The semiconductor device according to claim 4, wherein the gate of said fifth P-type transistor is electrically connected to said output terminal.

10. the semiconductor device operates by selectively applying a first operation mode in which the first power supply potential is set to a first potential and a second operation mode in which the first power supply potential is set to a second potential lower than the first potential; 10. The semiconductor device of claim 9, wherein the gate voltage control circuit further includes a second connection selection circuit configured to electrically connect the gate of the first N-type transistor to a node that supplies the second bias voltage in the second operation mode, while electrically disconnecting the gate of the first N-type transistor from the node in the first operation mode.

11. The gate voltage control circuit includes: a fourth P-type transistor having a source connected to the gate of the first N-type transistor and a drain electrically connected to the output terminal; a fifth P-type transistor having a source connected to the gate of the first N-type transistor and a drain electrically connected to a node supplying the second bias voltage; the second bias voltage is input to a gate of the fourth P-type transistor; 5. The semiconductor device according to claim 4, wherein a gate of said fifth P-type transistor is electrically connected to a source of said first N-type transistor and to said output terminal.

12. the semiconductor device operates by selectively applying a first operation mode in which the first power supply potential is set to a first potential and a second operation mode in which the first power supply potential is set to a second potential lower than the first potential; 2. The semiconductor device according to claim 1, wherein, when the voltage of the output signal changes in response to a change in the logic level of the input signal, in the first operation mode, the gate voltage control circuit changes at least one of the gate voltage of the first N-type transistor and the gate voltage of the first P-type transistor in accordance with a change in the voltage of the output terminal, while in the second operation mode, the gate voltage control circuit operates to fix the gate voltages of the first N-type transistor and the first P-type transistor regardless of the voltage of the output terminal.

13. The semiconductor device includes: a third P-type transistor connected in series with the second P-type transistor between the first P-type transistor and the power supply line; a third N-type transistor connected in series with the second N-type transistor between the first N-type transistor and the reference potential line; 2. The semiconductor device according to claim 1, wherein a bias voltage lower than a potential difference between the reference potential and the first power supply potential is input to gates of the third P-type transistor and the third N-type transistor to turn on the third P-type transistor and the third N-type transistor.

14. the input signal is set to the reference potential or a second power supply potential lower than the first power supply potential; 2. The semiconductor device according to claim 1, wherein a breakdown voltage of each of said first and second P-type transistors and said first and second N-type transistors is equal to or greater than a potential difference between said second power supply potential and said reference potential.

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