Manufacturing method of semiconductor device

Abstract

To provide a semiconductor device which can be miniaturized and highly integrated.SOLUTION: A transistor 200 includes: a conductor 205 provided in such a way as to be embedded into an insulator 216; an insulator 221 on the insulator 216 and the conductor 205; an insulator 222 on the insulator 221; an insulator 224 on the insulator 222; an oxide 230 on the insulator 224; conductors 242a and 242b on the oxide 230; insulators 271a and 271b on the conductors 242a and 242b; an insulator 250 on the oxide 230; and a conductor 260 on the insulator 250. On the insulators 271a and 271b, the insulator 275 is provided, and the insulator 280 is provided on the insulator 275. The insulators 255 and 250, and the conductor 260 are arranged inside an open provided in the insulator 280 and the insulator 275. An oxide insulator is used for the insulator 250. For the insulators 271a and 271b, a nitride insulator which hardly oxidizes metal is used.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the present invention relates to a semiconductor device, a memory device, and an electronic device each including an oxide semiconductor. Another embodiment of the present invention relates to a method for manufacturing the semiconductor device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device (e.g., a touch sensor), an input / output device (e.g., a touch panel), a driving method thereof, or a manufacturing method thereof.

[0003] In this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, semiconductor circuits, arithmetic devices, and memory devices are all embodiments of semiconductor devices. Display devices (such as liquid crystal display devices and light-emitting display devices), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, and the like may be considered to include semiconductor devices. [Background technology]

[0004] In recent years, the development of semiconductor devices has progressed, and LSIs, CPUs, memories, etc. are mainly used in semiconductor devices. A CPU is a collection of semiconductor elements that have semiconductor integrated circuits (at least transistors and memories) that are chipped by processing a semiconductor wafer and on which electrodes that serve as connection terminals are formed.

[0005] Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and used as components in a variety of electronic devices.

[0006] In addition, a technology for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface is attracting attention. Such transistors are widely used in electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors, but oxide semiconductors are also attracting attention as other materials.

[0007] It is also known that a transistor using an oxide semiconductor has an extremely small leakage current in a non-conducting state. For example, Patent Document 1 discloses a low-power consumption CPU that utilizes the property of a transistor using an oxide semiconductor that the leakage current is small. For example, Patent Document 2 discloses a memory device that can retain stored data for a long period of time by utilizing the property of a transistor using an oxide semiconductor that the leakage current is small.

[0008] Furthermore, Patent Document 3 discloses a transistor with a fine structure in which a source electrode layer and a drain electrode layer are provided in contact with the upper surface of an oxide semiconductor. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] JP 2012-257187 A [Patent Document 2] JP 2011-151383 A [Patent Document 3] International Publication No. 2016-125052 Summary of the Invention [Problem to be solved by the invention]

[0010] An object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a semiconductor device with high operation speed. Another object of one embodiment of the present invention is to provide a semiconductor device having favorable electrical characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device in which variation in electrical characteristics of transistors is small. Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device. Another object of one embodiment of the present invention is to provide a semiconductor device with high on-state current. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption. Another object of one embodiment of the present invention is to provide a novel semiconductor device. Another object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device with high productivity. Another object of one embodiment of the present invention is to provide a method for manufacturing a novel semiconductor device.

[0011] Another object of one embodiment of the present invention is to provide a storage device with a large storage capacity.Another object of one embodiment of the present invention is to provide a storage device with a high operating speed.Another object of one embodiment of the present invention is to provide a storage device with low power consumption.Another object of one embodiment of the present invention is to provide a novel storage device.

[0012] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description of the specification, drawings, and claims. [Means for solving the problem]

[0013] One embodiment of the present invention includes forming an oxide, a first conductor on the oxide, and a second conductor on the first conductor on a substrate, forming a first insulator covering the oxide, the first conductor, and the second conductor, forming an opening in the first insulator, dividing the second conductor into a third conductor and a fourth conductor overlapping the opening, forming a second insulator covering the oxide and the first insulator, forming a third insulator on the second insulator, and processing the second insulator and the third insulator by a dry etching method to form a fourth insulator in contact with a side surface of the first insulator, a side surface of the third conductor, and a side surface of the fourth conductor, and a fifth insulator in contact with a side surface and a top surface of the fourth insulator. a fourth insulator and a fifth insulator are used as masks to process the first conductor using a dry etching method, the first conductor is divided into a fifth conductor and a sixth conductor, the fifth insulator is removed using isotropic etching, the oxide is subjected to a heat treatment in an atmosphere containing oxygen, a sixth insulator is formed to cover the oxide, the first insulator, and the fourth insulator, a seventh conductor is formed on the sixth insulator, the sixth insulator and the seventh conductor are processed using CMP processing, a seventh insulator and an eighth conductor are formed in the opening, a nitride insulator is formed as the second insulator, and an oxide insulator is formed as the third insulator.

[0014] In the above, the second insulator is preferably formed by depositing silicon nitride using a PEALD method.

[0015] In the above, the third insulator is preferably formed by depositing silicon oxide using a PEALD method.

[0016] In the above, the first conductor is preferably formed by depositing tantalum nitride using a sputtering method.

[0017] In the above, the second conductor is preferably formed by depositing tungsten by sputtering.

[0018] In the above, the oxide is preferably formed by forming an oxide containing indium, gallium, and zinc by a sputtering method. Effect of the Invention

[0019] According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device with high operation speed can be provided. According to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with less variation in electrical characteristics of transistors can be provided. According to one embodiment of the present invention, a highly reliable semiconductor device can be provided. According to one embodiment of the present invention, a semiconductor device with large on-state current can be provided. According to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. According to one embodiment of the present invention, a novel semiconductor device can be provided. According to one embodiment of the present invention, a method for manufacturing a semiconductor device with high productivity can be provided. According to one embodiment of the present invention, a method for manufacturing a novel semiconductor device can be provided.

[0020] According to one embodiment of the present invention, a storage device having a large storage capacity can be provided. Alternatively, according to one embodiment of the present invention, a storage device having a high operating speed can be provided. Alternatively, according to one embodiment of the present invention, a storage device having low power consumption can be provided. Alternatively, according to one embodiment of the present invention, a novel storage device can be provided.

[0021] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims. [Brief description of the drawings]

[0022] [Figure 1] Fig. 1A is a plan view showing an example of a semiconductor device, and Figs. 1B to 1D are cross-sectional views showing an example of the semiconductor device. [Diagram 2]2A and 2B are cross-sectional views showing an example of a semiconductor device. [Diagram 3] 3A to 3C are cross-sectional views showing an example of a semiconductor device. [Figure 4] 4A to 4D are cross-sectional views showing an example of a semiconductor device. [Diagram 5] Fig. 5A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Figs. 5B to 5D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 6] Fig. 6A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Figs. 6B to 6D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 7] Fig. 7A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Figs. 7B to 7D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 8] Fig. 8A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Figs. 8B to 8D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 9] Fig. 9A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Figs. 9B to 9D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 10] Fig. 10A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 10B to Fig. 10D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 11] Fig. 11A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 11B to Fig. 11D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 12] Fig. 12A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 12B to Fig. 12D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 13] Fig. 13A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 13B to Fig. 13D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 14] 14A to 14C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 15] Fig. 15A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 15B to Fig. 15D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 16] 16A to 16C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 17] Fig. 17A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 17B to Fig. 17D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 18] Fig. 18A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 18B to Fig. 18D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 19] FIG. 19 is a block diagram illustrating an example of a storage device. [Figure 20] 20A and 20B are a schematic diagram and a circuit diagram showing an example of a memory device. [Figure 21] 21(A) and 21(B) are schematic diagrams showing an example of a storage device. [Figure 22] FIG. 22 is a circuit diagram illustrating an example of a memory device. [Diagram 23] FIG. 23 is a cross-sectional view showing an example of a storage device. [Figure 24] FIG. 24 is a cross-sectional view showing an example of a storage device. [Diagram 25] 25A to 25C are circuit diagrams showing an example of a memory device. [Figure 26] 26(A) and 26(B) are diagrams showing an example of a semiconductor device. [Figure 27] 27(A) and 27(B) are diagrams showing an example of an electronic component. [Figure 28] 28(A) and 28(B) are diagrams showing an example of an electronic device, and FIGS. 28(C) to 28(E) are diagrams showing an example of a mainframe computer. [Figure 29] FIG. 29 is a diagram showing an example of space equipment. [Diagram 30] FIG. 30 is a diagram illustrating an example of a storage system applicable to a data center. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0023] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that the modes and details of the present invention can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0024] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and the repeated explanations are omitted. In addition, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be used.

[0025] In addition, for ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0026] In this specification, the ordinal numbers "first" and "second" are used for convenience and do not limit the number of components or the order of the components (e.g., the order of processes or the order of stacking). In addition, an ordinal number attached to a component in one part of this specification may not match an ordinal number attached to the same component in another part of this specification or in the claims.

[0027] The words "film" and "layer" can be interchanged depending on the circumstances. For example, the term "conductive layer" can be interchanged with the term "conductive film". Or, for example, the term "insulating film" can be interchanged with the term "insulating layer". Furthermore, the term "conductor" can be interchanged with the term "conductive layer" or the term "conductive film" depending on the circumstances. Furthermore, the term "insulating body" can be interchanged with the term "insulating layer" or the term "insulating film" depending on the circumstances.

[0028] The openings include, for example, grooves, slits, etc. Furthermore, a region in which an opening is formed may be referred to as an opening portion.

[0029] In addition, in the drawings used in the embodiments of this specification, the sidewall of the insulator at the opening portion of the insulator is shown to be perpendicular or approximately perpendicular to the substrate surface or the surface on which the insulator is formed; however, the sidewall may be tapered.

[0030] In this specification, the term "tapered shape" refers to a shape in which at least a part of the side of the structure is inclined with respect to the substrate surface or the surface to be formed. For example, the term refers to a shape having a region in which the angle between the inclined side and the substrate surface or the surface to be formed (hereinafter, sometimes referred to as the taper angle) is less than 90°. The side of the structure and the substrate surface do not necessarily need to be completely flat, and may be substantially planar with a slight curvature or substantially planar with a slight unevenness.

[0031] (Embodiment 1) In this embodiment, a semiconductor device including an oxide semiconductor and a method for manufacturing the semiconductor device will be described with reference to FIGS.

[0032] <Example of semiconductor device configuration> A configuration example of a semiconductor device will be described with reference to FIG. 1 to FIG. 4. FIG. 1(A) to FIG. 1(D) are a plan view and a cross-sectional view of a semiconductor device (transistor 200). FIG. 1(A) is a plan view of the semiconductor device. Also, FIG. 1(B) to FIG. 1(D) are cross-sectional views of the semiconductor device. Here, FIG. 1(B) is a cross-sectional view of a portion indicated by a dashed line A1-A2 in FIG. 1(A) and is also a cross-sectional view of the transistor 200 in the channel length direction. Also, FIG. 1(C) is a cross-sectional view of a portion indicated by a dashed line A3-A4 in FIG. 1(A) and is also a cross-sectional view of the transistor 200 in the channel width direction. Also, FIG. 1(D) is a cross-sectional view of a portion indicated by a dashed line A5-A6 in FIG. 1(A) and is also a cross-sectional view of the transistor 200 in the channel width direction. Note that some elements are omitted in the plan view of FIG. 1(A) for clarity. 2A to 4D are enlarged cross-sectional views of the transistor 200 in the channel length direction.

[0033] The transistor 200 has a conductor 205 (conductor 205a and conductor 205b) embedded in the insulator 216, an insulator 221 on the insulator 216 and the conductor 205, an insulator 222 on the insulator 221, an insulator 224 on the insulator 222, an oxide 230 (oxide 230a and oxide 230b) on the insulator 224, a conductor 242a (conductor 242a1 and conductor 242a2) and a conductor 242b (conductor 242b1 and conductor 242b2) on the oxide 230, an insulator 271a on the conductor 242a, an insulator 271b on the conductor 242b, an insulator 250 on the oxide 230, and a conductor 260 (conductor 260a and conductor 260b) on the insulator 250.

[0034] An insulator 275 is provided on the insulators 271a and 271b, and an insulator 280 is provided on the insulator 275. The insulator 255, the insulator 250, and the conductor 260 are disposed inside openings provided in the insulator 280 and the insulator 275. An insulator 282 is provided on the insulator 280 and the conductor 260. An insulator 283 is provided on the insulator 282. An insulator 215 is provided below the insulator 216 and the conductor 205. An insulator 255 is provided between the insulator 242a2, the conductor 242b2, the insulator 271a, the insulator 271b, the insulator 275, and the insulator 280 and the insulator 250.

[0035] The oxide 230 has a region that functions as a channel formation region of the transistor 200. The conductor 260 has a region that functions as a first gate electrode (upper gate electrode) of the transistor 200. The insulator 250 has a region that functions as a first gate insulator of the transistor 200. The conductor 205 has a region that functions as a second gate electrode (lower gate electrode) of the transistor 200. The insulator 224, the insulator 222, and the insulator 221 each have a region that functions as a second gate insulator of the transistor 200.

[0036] The conductor 242a has a region functioning as one of a source electrode or a drain electrode of the transistor 200. The conductor 242b has a region functioning as the other of the source electrode or the drain electrode of the transistor 200.

[0037] The conductor 242a has a laminated structure of a conductor 242a1 and a conductor 242a2 on the conductor 242a1, and the conductor 242b has a laminated structure of a conductor 242b1 and a conductor 242b2 on the conductor 242b1. The conductor 242a1 and the conductor 242b1 in contact with the oxide 230b are preferably conductors that are difficult to oxidize, such as metal nitrides. This can prevent the conductor 242a and the conductor 242b from being excessively oxidized by the oxygen contained in the oxide 230b. In addition, the conductor 242a2 and the conductor 242b2 are preferably conductors such as metal layers that have higher conductivity than the conductor 242a1 and the conductor 242b1. This allows the conductor 242a and the conductor 242b to function as wiring or electrodes with high conductivity. In this manner, a semiconductor device can be provided in which the conductor 242a and the conductor 242b functioning as wiring or electrodes are provided in contact with the upper surface of the oxide 230 functioning as an active layer.

[0038] The insulator 255 is preferably an insulator that is difficult to oxidize, such as a nitride. The insulator 255 is formed in a sidewall shape by anisotropic etching in contact with the side wall of an opening provided in the insulator 280 or the like (here, the side wall of the opening corresponds to, for example, the side surface of the insulator 280 or the like in the opening). The insulator 255 is formed in contact with the side surface of the conductor 242a2 and the side surface of the conductor 242b2, and has a function of protecting the conductor 242a2 and the conductor 242b2. As will be described in detail later, after the conductor is divided into the conductor 242a1 and the conductor 242b1, it is preferable to perform a heat treatment in an atmosphere containing oxygen before forming the insulator 250. At this time, since the insulator 255 is formed in contact with the side surface of the conductor 242a2 and the side surface of the conductor 242b2, the conductor 242a2 and the conductor 242b2 can be prevented from being excessively oxidized.

[0039] The openings provided in the insulator 280 and the insulator 275 overlap the region between the conductor 242a2 and the conductor 242b2. In a top view, the side surface of the insulator 280 at the opening coincides or approximately coincides with the side surface of the conductor 242a2 and the side surface of the conductor 242b2. Also, a part of the upper surface of the conductor 242a1 contacts the conductor 242a2, and a part of the upper surface of the conductor 242b1 contacts the conductor 242b2. Therefore, the insulator 255 contacts another part of the upper surface of the conductor 242a1, another part of the upper surface of the conductor 242b1, the side surface of the conductor 242a2, and the side surface of the conductor 242b2 within the above opening. 1(B) and 1(C), a protrusion is formed on a portion of the insulator 255 that contacts the upper surface of the conductor 242a1, the upper surface of the conductor 242b1, or the upper surface of the insulator 222. The protrusion of the insulator 255 protrudes toward the center of the opening more than other portions. Therefore, the protrusion of the insulator 255, a portion of the conductor 242a1, and a portion of the conductor 242b1 are formed to protrude into the opening.

[0040] Furthermore, insulator 250 contacts the upper surface of oxide 230, the side surface of conductor 242a1, the side surface of conductor 242b1, and the side surface of insulator 255. Note that in the above opening, the protruding portion of insulator 255, a portion of conductor 242a1, and a portion of conductor 242b1 are formed to protrude, and therefore the shape of insulator 250 reflects the shapes of the protruding portion of insulator 255, a portion of conductor 242a1, and a portion of conductor 242b1.

[0041] As described above, the conductors 242a1 and 242b1 can be formed to protrude from the conductors 242a2 and 242b2 to the same extent as the protruding portion of the insulator 255. As a result, as shown in FIG. 2B, in a cross-sectional view of the transistor 200 in the channel length direction, the distance L2 between the conductor 242a1 and the conductor 242b1 is smaller than the distance L1 between the conductor 242a2 and the conductor 242b2. With this configuration, it is possible to shorten the distance between the source and the drain, and accordingly shorten the channel length. Therefore, the frequency characteristics of the transistor 200 can be improved. In this way, by miniaturizing the semiconductor device, a semiconductor device with improved operating speed can be provided.

[0042] The oxide 230 preferably has an oxide 230a on the insulator 224 and an oxide 230b on the oxide 230a. By having the oxide 230a below the oxide 230b, it is possible to suppress the diffusion of impurities from a structure formed below the oxide 230a to the oxide 230b.

[0043] In this embodiment, the oxide 230 has a two-layer structure of the oxide 230a and the oxide 230b, but is not limited thereto. The oxide 230 may have a single layer structure of the oxide 230b, or a stacked structure of three or more layers.

[0044] In the oxide 230b, a channel formation region and a source region and a drain region sandwiching the channel formation region are formed in the transistor 200. At least a part of the channel formation region overlaps with the conductor 260. The source region overlaps with the conductor 242a, and the drain region overlaps with the conductor 242b. Note that the source region and the drain region can be interchanged.

[0045] The channel formation region is a high-resistance region with a low carrier concentration because it has fewer oxygen vacancies or a lower impurity concentration than the source and drain regions. Therefore, the channel formation region can be said to be i-type (intrinsic) or substantially i-type.

[0046] In addition, the source and drain regions are low-resistance regions with high carrier concentrations due to a large number of oxygen vacancies or high concentrations of impurities such as hydrogen, nitrogen, and metal elements. In other words, the source and drain regions are n-type regions (low-resistance regions) with a high carrier concentration compared to the channel formation region.

[0047] The carrier concentration in the channel formation region is 1×10 18 cm -3 Below, 1×10 17 cm -3 Less than 1×10 16 cm -3 Less than 1×10 15 cm -3 Less than 1×10 14 cm -3 Less than 1×10 13 cm -3 Less than 1×10 12 cm -3 Less than 1×10 11 cm -3 Less than or equal to 1×10 10 cm -3 The lower limit of the carrier concentration in the channel formation region is not particularly limited, but is preferably less than 1×10 -9 cm -3 It can be said that:

[0048] In addition, when the carrier concentration of the oxide 230b is reduced, the impurity concentration in the oxide 230b is reduced to reduce the density of defect states. In this specification and the like, a low impurity concentration and a low density of defect states are referred to as high-purity intrinsic or substantially high-purity intrinsic. An oxide semiconductor (or metal oxide) with a low carrier concentration may be referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor (or metal oxide).

[0049] In order to stabilize the electrical characteristics of the transistor 200, it is effective to reduce the impurity concentration in the oxide 230b. In order to reduce the impurity concentration in the oxide 230b, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like. Note that the impurities in the oxide 230b refer to, for example, anything other than the main component constituting the oxide 230b. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0050] Note that the channel formation region, the source region, and the drain region may each be formed not only with the oxide 230b but also with the oxide 230a.

[0051] In addition, it may be difficult to clearly detect the boundaries between the regions in the oxide 230. The concentrations of the metal elements and impurity elements such as hydrogen and nitrogen detected in each region may change continuously within each region, not limited to a stepwise change from region to region. In other words, the concentrations of the metal elements and impurity elements such as hydrogen and nitrogen may decrease in the region closer to the channel formation region.

[0052] It is preferable to use a metal oxide that functions as a semiconductor (hereinafter also referred to as an oxide semiconductor) for the oxide 230 (the oxide 230a and the oxide 230b).

[0053] The band gap of the metal oxide functioning as a semiconductor is preferably 2 eV or more, more preferably 2.5 eV or more. By using a metal oxide having a large band gap, the off-current of the transistor can be reduced. A transistor having a metal oxide in a channel formation region in this way is called an OS transistor. Since the off-current of the OS transistor is small, the power consumption of the semiconductor device can be sufficiently reduced. Furthermore, since the frequency characteristics of the OS transistor are high, the semiconductor device can operate at high speed.

[0054] The oxide 230 preferably has a metal oxide (oxide semiconductor). Examples of metal oxides that can be used for the oxide 230 include indium oxide, gallium oxide, and zinc oxide. The metal oxide preferably contains at least indium (In) or zinc (Zn). The metal oxide preferably has two or three elements selected from indium, element M, and zinc. The element M is a metal element or semi-metal element having a high bond energy with oxygen, for example, a metal element or semi-metal element having a bond energy with oxygen higher than that of indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M of the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium. In this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements", and the "metal element" described in this specification and the like may include metalloid elements.

[0055] The oxide 230 may be, for example, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide), gallium zinc oxide (Ga-Zn oxide, also written as GZO), aluminum zinc oxide (Al-Zn oxide, also written as AZO), indium aluminum zinc oxide (In-Al-Zn oxide, also written as IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also written as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also written as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also written as IGAZO or IAGZO), or the like. Alternatively, silicon-containing indium tin oxide, gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), or the like can be used.

[0056] By increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements contained in the metal oxide, the field-effect mobility of the transistor can be increased.

[0057] Note that the metal oxide may have one or more metal elements with a large periodic number instead of or in addition to indium. The greater the overlap of the orbits of the metal elements, the greater the carrier conduction in the metal oxide. Therefore, by including a metal element with a large periodic number, the field effect mobility of the transistor may be increased. Examples of metal elements with a large periodic number include metal elements belonging to the 5th period and metal elements belonging to the 6th period. Specific examples of the metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0058] The metal oxide may contain one or more nonmetallic elements. When the metal oxide contains a nonmetallic element, the field-effect mobility of the transistor may be increased. Examples of the nonmetallic element include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0059] In addition, by increasing the ratio of the number of zinc atoms to the total number of atoms of all metal elements contained in the metal oxide, the metal oxide can be made highly crystalline and the diffusion of impurities in the metal oxide can be suppressed, thereby suppressing the fluctuation of the electrical characteristics of the transistor and improving its reliability.

[0060] In addition, by increasing the ratio of the number of atoms of element M to the sum of the number of atoms of all metal elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-current can be obtained. In addition, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.

[0061] As described above, the electrical characteristics and reliability of a transistor vary depending on the composition of the metal oxide applied to the oxide 230. Therefore, by varying the composition of the metal oxide depending on the electrical characteristics and reliability required of a transistor, a semiconductor device that has both excellent electrical characteristics and high reliability can be obtained.

[0062] The oxide 230 preferably has a laminated structure of a plurality of oxide layers with different chemical compositions. For example, in the metal oxide used for the oxide 230a, the atomic ratio of element M to the metal element that is the main component is preferably larger than the atomic ratio of element M to the metal element that is the main component in the metal oxide used for the oxide 230b. In addition, in the metal oxide used for the oxide 230a, the atomic ratio of element M to In is preferably larger than the atomic ratio of element M to In in the metal oxide used for the oxide 230b. This configuration can suppress the diffusion of impurities and oxygen from structures formed below the oxide 230a to the oxide 230b.

[0063] In the metal oxide used for the oxide 230b, the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 230a. With this configuration, the transistor 200 can have large on-state current and high frequency characteristics.

[0064] In addition, since the oxide 230a and the oxide 230b contain a common element other than oxygen as a main component, the defect state density at the interface between the oxide 230a and the oxide 230b can be reduced, and the influence of the interface scattering on the carrier conduction is reduced, so that the transistor 200 can obtain a large on-current and high frequency characteristics.

[0065] Specifically, the oxide 230a may be a metal oxide having a composition of In:M:Zn=1:3:2 [atomic ratio] or a composition close thereto, In:M:Zn=1:3:4 [atomic ratio] or a composition close thereto, or In:M:Zn=1:1:0.5 [atomic ratio] or a composition close thereto. The oxide 230b may be a metal oxide having a composition of In:M:Zn=1:1:1 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:1.2 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:2 [atomic ratio] or a composition close thereto, or In:M:Zn=4:2:3 [atomic ratio] or a composition close thereto. The term "composition close thereto" includes a range of ±30% of the desired atomic ratio. It is preferable to use gallium as the element M. Furthermore, when a single layer of the oxide 230b is provided as the oxide 230, the metal oxide that can be used for the oxide 230a may be applied as the oxide 230b. Furthermore, the compositions of the metal oxide that can be used for the oxide 230a and the oxide 230b are not limited to the above. For example, the composition of the metal oxide that can be used for the oxide 230a may be applied to the oxide 230b. Similarly, the composition of the metal oxide that can be used for the oxide 230b may be applied to the oxide 230a.

[0066] In addition, when a metal oxide film is formed by a sputtering method, the above atomic ratio is not limited to the atomic ratio of the formed metal oxide film, but may be the atomic ratio of a sputtering target used to form the metal oxide film.

[0067] The oxide 230b is preferably crystalline. In particular, it is preferable to use c-axis aligned crystalline oxide semiconductor (CAAC-OS) as the oxide 230b.

[0068] CAAC-OS is a metal oxide having a high crystallinity and a dense structure with few impurities and defects (e.g., oxygen vacancies). In particular, by performing heat treatment at a temperature (e.g., 400° C. or higher and 600° C. or lower) at which the metal oxide does not polycrystallize after formation of the metal oxide, the CAAC-OS can be made to have a dense structure with higher crystallinity. In this way, the density of the CAAC-OS can be increased, and the diffusion of impurities or oxygen in the CAAC-OS can be reduced.

[0069] In addition, since it is difficult to identify clear grain boundaries in CAAC-OS, it is said that the decrease in electron mobility caused by grain boundaries is unlikely to occur. Therefore, metal oxides with CAAC-OS have stable physical properties. Therefore, metal oxides with CAAC-OS are resistant to heat and highly reliable.

[0070] In addition, by using a crystalline oxide such as CAAC-OS as the oxide 230b, it is possible to suppress the extraction of oxygen from the oxide 230b by the source electrode or the drain electrode. As a result, even if a heat treatment is performed, the extraction of oxygen from the oxide 230b can be reduced, and the transistor 200 is stable against high temperatures (so-called thermal budget) in the manufacturing process.

[0071] In a transistor using an oxide semiconductor, if impurities and oxygen vacancies exist in a region in which a channel is formed in the oxide semiconductor, the electrical characteristics are likely to fluctuate and the reliability may be reduced. O H) and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the channel formation region of the oxide semiconductor, the transistor is likely to have normally-on characteristics (a channel exists even when no voltage is applied to the gate electrode, and a current flows through the transistor). Therefore, in the channel formation region of the oxide semiconductor, impurities, oxygen vacancies, and V OIt is preferable that H be reduced as much as possible. In other words, it is preferable that the carrier concentration of a channel formation region in the oxide semiconductor be reduced and the channel formation region be i-type (intrinsic) or substantially i-type.

[0072] In response to this problem, an insulator containing oxygen that is released by heating (hereinafter may be referred to as excess oxygen) is provided near the oxide semiconductor and heat treatment is performed. In this way, oxygen is supplied from the insulator to the oxide semiconductor, and oxygen vacancies and V O H can be reduced. However, if an excessive amount of oxygen is supplied to the source region or the drain region, this may cause a decrease in the on-state current or a decrease in the field-effect mobility of the transistor 200. Furthermore, if the amount of oxygen supplied to the source region or the drain region varies within the substrate surface, the characteristics of a semiconductor device having the transistor may vary. Furthermore, if oxygen supplied from the insulator to the oxide semiconductor diffuses into a conductor such as a gate electrode, a source electrode, or a drain electrode, the conductor may be oxidized and its conductivity may be impaired, which may adversely affect the electrical characteristics and reliability of the transistor.

[0073] Therefore, in an oxide semiconductor, the channel formation region preferably has a reduced carrier concentration and is i-type or substantially i-type, whereas the source and drain regions preferably have a high carrier concentration and are n-type. O It is preferable to reduce H in the source and drain regions. Also, it is preferable to prevent an excessive amount of oxygen from being supplied to the source and drain regions. O It is preferable to prevent the amount of H from being excessively reduced. In addition, it is preferable to have a structure that suppresses a decrease in the conductivity of the conductor 260, the conductor 242a, the conductor 242b, and the like. For example, it is preferable to have a structure that suppresses oxidation of the conductor 260, the conductor 242a, the conductor 242b, and the like. Note that hydrogen in the oxide semiconductor is V O H can be formed, so V O To reduce the amount of H, it is necessary to reduce the hydrogen concentration.

[0074] Therefore, in this embodiment, the semiconductor device is configured to reduce the hydrogen concentration in the channel formation region, suppress the oxidation of the conductor 242a, the conductor 242b, and the conductor 260, and suppress the reduction in the hydrogen concentration in the source and drain regions.

[0075] The insulator 250 in contact with the channel formation region in the oxide 230b preferably has a function of capturing or fixing hydrogen. This can reduce the hydrogen concentration in the channel formation region of the oxide 230b. Therefore, the V O By reducing H, the channel formation region can be made i-type or substantially i-type.

[0076] 2A, the insulator 250 preferably has a layered structure of an insulator 250a in contact with the oxide 230, an insulator 250b on the insulator 250a, and an insulator 250c on the insulator 250b. In this case, it is preferable that the insulator 250a has a function of capturing hydrogen or fixing hydrogen.

[0077] An example of an insulator having the function of capturing or fixing hydrogen is a metal oxide having an amorphous structure. For example, it is preferable to use a metal oxide such as magnesium oxide or an oxide containing one or both of aluminum and hafnium as the insulator 250a. In such a metal oxide having an amorphous structure, oxygen atoms have dangling bonds, and the dangling bonds may have the property of capturing or fixing hydrogen. In other words, it can be said that a metal oxide having an amorphous structure has a high ability to capture or fix hydrogen.

[0078] It is also preferable to use a high dielectric constant (high-k) material for the insulator 250a. An example of a high-k material is an oxide containing one or both of aluminum and hafnium. By using a high-k material for the insulator 250a, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulator. It is also possible to reduce the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator.

[0079] From the above, it is preferable to use an oxide containing one or both of aluminum and hafnium as the insulator 250a, and it is more preferable to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium. Since an amorphous film of aluminum oxide can be formed relatively easily using the ALD method, it is more preferable to use aluminum oxide having an amorphous structure. In this embodiment, an aluminum oxide film is used as the insulator 250a. In this case, the insulator 250a is an insulator containing at least oxygen and aluminum. Moreover, the aluminum oxide has an amorphous structure. In this case, the insulator 250a has an amorphous structure.

[0080] Next, it is preferable that the insulator 250b is a thermally stable insulator such as silicon oxide or silicon oxynitride. In this specification and the like, an oxynitride refers to a material whose composition contains more oxygen than nitrogen, and a nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, when silicon oxynitride is described, it refers to a material whose composition contains more oxygen than nitrogen, and when silicon nitride oxide is described, it refers to a material whose composition contains more nitrogen than oxygen.

[0081] 3B, a structure may be used in which an insulator 250d is provided on the insulator 250b. In this case, an insulator that can be used for the insulator 250a can be provided as the insulator 250d. For example, hafnium oxide can be used as the insulator 250d. Here, by providing the insulator 250d between the insulator 250c and the insulator 250b, hydrogen contained in the insulator 250b and the like can be more effectively captured and fixed.

[0082] In order to suppress oxidation of the conductor 242a, the conductor 242b, and the conductor 260, it is preferable to provide a barrier insulator against oxygen near each of the conductor 242a, the conductor 242b, and the conductor 260. In the semiconductor device described in this embodiment, the insulators are, for example, the insulator 250a, the insulator 250c, the insulator 250d, the insulator 255, and the insulator 275.

[0083] In this specification, a barrier insulator refers to an insulator having barrier properties. In this specification, having barrier properties refers to having a property of preventing the permeation of a corresponding substance (also referred to as low permeability). For example, an insulator with barrier properties has a property that makes it difficult for a corresponding substance to diffuse into the insulator. In addition, for example, an insulator with barrier properties has a function of capturing or fixing (also referred to as gettering) a corresponding substance inside the insulator.

[0084] Examples of the barrier insulator against oxygen include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate). For example, the insulators 250a, 250c, 250d, 255, and 275 are each preferably a single-layer structure or a multilayer structure of the barrier insulator against oxygen. For example, when the insulator 255 has a multilayer structure, it can have a two-layer structure of an aluminum oxide film and a silicon nitride film on the aluminum oxide film.

[0085] The insulator 250a and the insulator 255 preferably have a barrier property against oxygen. The insulator 250a and the insulator 255 preferably have a lower oxygen permeability than at least the insulator 280. The insulator 250a has a region in contact with the side surface of the conductor 242a1 and the side surface of the conductor 242b1. The insulator 255 has a region in contact with the upper surface of the conductor 242a1, the upper surface of the conductor 242b1, the side surface of the conductor 242a2, and the side surface of the conductor 242b2. The insulator 250a also contacts the side surface of the insulator 255. Since the insulator 250a and the insulator 255 have a barrier property against oxygen, it is possible to suppress the side surfaces of the conductor 242a and the conductor 242b from being oxidized and the formation of an oxide film on the side surface. This makes it possible to suppress a decrease in the on-current or a decrease in the field effect mobility of the transistor 200.

[0086] The insulator 250a is provided in contact with the top surface and side surfaces of the oxide 230b, the side surfaces of the oxide 230a, the side surfaces of the insulator 224, and the top surface of the insulator 222. The insulator 250a has a barrier property against oxygen, which can suppress oxygen from being desorbed from the channel formation region of the oxide 230b when a heat treatment or the like is performed. Therefore, the formation of oxygen vacancies in the oxide 230a and the oxide 230b can be reduced.

[0087] Furthermore, by providing the insulator 250a and the insulator 255, even if an excessive amount of oxygen is contained in the insulator 280, the oxygen can be prevented from being excessively supplied to the oxide 230a and the oxide 230b, and an appropriate amount of oxygen can be supplied to the oxide 230a and the oxide 230b. Therefore, it is possible to prevent the source region and the drain region from being excessively oxidized, and to prevent a decrease in the on-state current or a decrease in the field-effect mobility of the transistor 200.

[0088] An oxide containing one or both of aluminum and hafnium has a barrier property against oxygen, and therefore can be suitably used as the insulator 250a.

[0089] Silicon nitride also has a barrier property against oxygen, and can therefore be suitably used as the insulator 255. In this case, the insulator 255 is an insulator containing at least nitrogen and silicon. The insulator 255 also preferably has a barrier property against hydrogen. This can prevent impurities such as hydrogen contained in the conductors 242a2 and 242b2 from diffusing into the oxide 230b.

[0090] The insulator 250c also preferably has a barrier property against oxygen. The insulator 250c is provided between the channel formation region of the oxide 230 and the conductor 260, and between the insulator 280 and the conductor 260. This configuration can suppress the oxygen contained in the channel formation region of the oxide 230 from diffusing to the conductor 260 and forming oxygen vacancies in the channel formation region of the oxide 230. In addition, it can suppress the oxygen contained in the oxide 230 and the oxygen contained in the insulator 280 from diffusing to the conductor 260 and oxidizing the conductor 260. The insulator 250c is preferably at least less permeable to oxygen than the insulator 280. For example, it is preferable to use a silicon nitride film as the insulator 250c. In this case, the insulator 250c is an insulator having at least nitrogen and silicon.

[0091] Moreover, the insulator 250c preferably has a barrier property against hydrogen, which can prevent impurities such as hydrogen contained in the conductor 260 from diffusing into the oxide 230b.

[0092] It is preferable that the insulator 275 also has a barrier property against oxygen. The insulator 275 is provided between the insulator 280 and the conductor 242a, and between the insulator 280 and the conductor 242b. This configuration can suppress the oxygen contained in the insulator 280 from diffusing into the conductor 242a and the conductor 242b. Therefore, it is possible to suppress the conductor 242a and the conductor 242b from being oxidized by the oxygen contained in the insulator 280, which increases the resistivity and reduces the on-current. It is preferable that the insulator 275 is at least less permeable to oxygen than the insulator 280. For example, it is preferable to use silicon nitride as the insulator 275. In this case, the insulator 275 is an insulator having at least nitrogen and silicon.

[0093] To suppress a decrease in the hydrogen concentration in the source and drain regions in the oxide 230, it is preferable to provide a barrier insulator against hydrogen near each of the source and drain regions. In the semiconductor device described in this embodiment, the barrier insulator against hydrogen is, for example, the insulator 275.

[0094] Examples of the barrier insulator against hydrogen include oxides such as aluminum oxide, hafnium oxide, and tantalum oxide, and nitrides such as silicon nitride. For example, the insulator 275 is preferably a single-layer structure or a multilayer structure of the above-mentioned barrier insulator against hydrogen.

[0095] By providing the insulator 275 as described above, it is possible to reduce the diffusion of hydrogen in the source and drain regions to the outside, and therefore it is possible to suppress the reduction in the hydrogen concentration in the source and drain regions. Therefore, it is possible to make the source and drain regions n-type.

[0096] With the above structure, the channel formation region can be made i-type or substantially i-type, and the source region and drain region can be made n-type, so that a semiconductor device having good electrical characteristics can be provided. Furthermore, with the above structure, the semiconductor device can have good electrical characteristics even when miniaturized or highly integrated. Furthermore, miniaturizing the transistor 200 can improve frequency characteristics. Specifically, the cutoff frequency can be improved.

[0097] The insulators 250a to 250d function as part of the first gate insulator. The insulators 250a to 250d are provided in an opening formed in the insulator 280 together with the insulator 255 and the conductor 260. In order to miniaturize the transistor 200, it is preferable that the thicknesses of the insulators 250a to 250d are each thin. The thicknesses of the insulators 250a to 250d are each preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5.0 nm, more preferably 0.5 nm to 5.0 nm, more preferably 1.0 nm to less than 5.0 nm, and further preferably 1.0 nm to 3.0 nm. Note that each of the insulators 250a to 250d may have a region having the above-mentioned thickness at least in a part thereof.

[0098] In order to make the thickness of the insulators 250a to 250d as thin as described above, it is preferable to form the insulators 250a to 250d and the insulator 255 in the openings of the insulator 280, etc., by using the atomic layer deposition (ALD) method. In addition, in order to provide the insulators 250a to 250d and the insulator 255 in the openings of the insulator 280, etc., it is preferable to form the insulators by using the ALD method. The ALD method includes a thermal ALD method in which the reaction between a precursor and a reactant is performed only by thermal energy, and a plasma enhanced ALD method in which a plasma excited reactant is used. In the PEALD method, the use of plasma may make it possible to form the film at a lower temperature, which may be preferable.

[0099] The ALD method can deposit atoms one layer at a time, and therefore has the following advantages: extremely thin films can be formed, films can be formed on structures with high aspect ratios, films can be formed with fewer defects such as pinholes, films can be formed with excellent coverage, films can be formed at low temperatures, etc. Therefore, the insulator 255 and the insulator 250 can be formed with good coverage on the side surfaces of the opening formed in the insulator 280 and the side ends of the conductors 242a and 242b, and with the above-mentioned thin film thickness.

[0100] Some precursors used in the ALD method contain carbon and the like. Therefore, films formed by the ALD method may contain more impurities such as carbon than films formed by other film formation methods. The amount of impurities can be quantified using secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), or Auger electron spectroscopy (AES).

[0101] In the above, the insulator 250 has been described as having a three-layer structure of the insulators 250a to 250c or a four-layer structure of the insulators 250a to 250d, but the present invention is not limited to this. The insulator 250 can have at least one of the insulators 250a to 250d. By configuring the insulator 250 as one, two, or three layers of the insulators 250a to 250d, the manufacturing process of the semiconductor device can be simplified and productivity can be improved.

[0102] For example, as shown in FIG. 3A, the insulator 250 may have a two-layer structure. In this case, it is preferable that the insulator 250 has a laminated structure of an insulator 250a and an insulator 250c on the insulator 250a. At least one of the insulators 250a and 250c may be made of a high-k material. This allows the equivalent oxide thickness (EOT) to be reduced while maintaining the thickness of the insulators 250a and 250c at a level that suppresses leakage current.

[0103] In addition to the above-described structure, in this embodiment, the semiconductor device is preferably configured to suppress hydrogen from being mixed into the transistor 200 or the like. For example, an insulator having a function of suppressing diffusion of hydrogen is preferably provided so as to cover one or both of the top and bottom of the transistor 200 or the like. In the semiconductor device described in this embodiment, the insulator is, for example, the insulator 283, the insulator 282, the insulator 222, the insulator 221, or the like. In addition, the insulator 215 provided under the transistor 200 may have a structure similar to either one or both of the insulators 282 and 283. In this case, the insulator 215 may have a stacked structure of the insulators 282 and 283, or may have a structure in which the insulator 282 is on the bottom and the insulator 283 is on the top, or may have a structure in which the insulator 282 is on the top and the insulator 283 is on the bottom.

[0104] It is preferable that one or more of the insulators 283, 282, 222, and 221 function as a barrier insulator that suppresses diffusion of impurities such as water and hydrogen from the substrate side or from above the transistor 200 to the transistor 200. Therefore, it is preferable that one or more of the insulators 283, 282, 222, and 221 have an insulating material that has a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), and copper atoms (through which the above impurities are difficult to permeate). Alternatively, it is preferable that the insulators have an insulating material that has a function of suppressing diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules) (through which the above oxygen is difficult to permeate).

[0105] The insulators 283, 282, 222, and 221 each preferably have an insulator having a function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen, and may be, for example, aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and zirconium (hafnium zirconium oxide), gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon nitride oxide. For example, the insulators 283 and 221 are preferably made of silicon nitride or the like, which has a higher hydrogen barrier property. For example, the insulator 282 is preferably made of aluminum oxide or the like, which has a high ability to capture or fix hydrogen. For example, the insulator 222 is preferably made of hafnium oxide or the like, which is a high dielectric constant (high-k) material, and has a high ability to capture or fix hydrogen.

[0106] With such a structure, impurities such as water and hydrogen can be prevented from diffusing from an interlayer insulating film arranged above the insulator 283 to the transistor 200 and the like. Furthermore, impurities such as water and hydrogen can be prevented from diffusing from an interlayer insulating film arranged below the insulator 221 to the transistor 200 and the like. Furthermore, hydrogen contained in the insulators 280, 224, and 250 can be captured and fixed to the insulator 282 or the insulator 222. Furthermore, by providing the insulators 282 and 283, oxygen contained in the insulator 280 and the like can be prevented from diffusing upward from the transistor 200 and the like. Furthermore, by providing the insulators 222 and 221, oxygen contained in the insulator 224 and the like can be prevented from diffusing downward from the transistor 200 and the like. In this way, by using a structure in which the transistor 200 is surrounded from above and below by insulators having a function of preventing the diffusion of impurities such as water and hydrogen and oxygen, the diffusion of excess oxygen and hydrogen to the oxide semiconductor can be reduced. This makes it possible to improve the electrical characteristics and reliability of the semiconductor device.

[0107] Furthermore, it is preferable to use silicon nitride or the like, which has a higher hydrogen barrier property, for the insulators 255, 275, and 250c. It is also preferable to use aluminum oxide or the like, which has a higher ability to capture or fix hydrogen, for the insulator 250a.

[0108] Here, it is preferable that a region of the insulator 275 that does not overlap with the oxide 230 contacts the insulator 222, a side end of the insulator 275 contacts the insulator 255, and an upper end of the insulator 255 and upper ends of the insulators 250a to 250c contact the insulator 282. With the above-mentioned configuration, in a region sandwiched between the insulator 283 and the insulator 221, the insulator 280 is separated from the oxide 230 by the insulator 275, the insulator 280 is separated from the insulator 250b by the insulator 255 and the insulator 250a, the conductor 260 is separated from the insulator 250b by the insulator 250c, and the conductors 242a2 and 242b2 are separated from the insulator 250b by the insulator 255 and the insulator 250a.

[0109] This can suppress the diffusion of impurities such as water and hydrogen contained in the insulator 280 to the oxide 230 and the insulator 250b. Also, it can suppress the diffusion of impurities such as water and hydrogen contained in the conductor 260 to the oxide 230 via the insulator 250b. Also, it can suppress the diffusion of impurities such as water and hydrogen contained in the conductor 242a2 and the conductor 242b2 to the oxide 230 via the insulator 250b. For example, even if a contact plug is formed in contact with the upper surface of the conductor 242a2 and the conductor 242b2 and impurities such as water and hydrogen diffuse to the conductor 242a2 and the conductor 242b2 via the contact plug, it can reduce the diffusion of the impurities such as water and hydrogen to the oxide 230. Also, it is possible to capture and fix the hydrogen contained in the insulator 250a and the insulator 250b to the insulator 282. With such a configuration, it is possible to further reduce the diffusion of hydrogen to the oxide semiconductor. As a result, it is possible to improve the electrical characteristics and reliability of the semiconductor device.

[0110] In the transistor 200, the conductor 205 is arranged to overlap with the oxide 230 and the conductor 260. Here, the conductor 205 is preferably provided by being embedded in an opening formed in the insulator 216. The conductor 205 is preferably provided to extend in the channel width direction as shown in Figures 1(A) and 1(C). With such a structure, when a plurality of transistors are provided, the conductor 205 functions as a wiring.

[0111] As shown in Figures 1(B) and 1(C), it is preferable that the conductor 205 has a conductor 205a and a conductor 205b. The conductor 205a is provided in contact with the bottom surface and the side wall of the opening. The conductor 205b is provided so as to fill the recess of the conductor 205a formed along the opening. Here, the height of the upper surface of the conductor 205 coincides or approximately coincides with the height of the upper surface of the insulator 216.

[0112] Here, the conductor 205a preferably has a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), copper atoms, etc. Alternatively, it preferably has a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules, etc.).

[0113] By using a conductive material having a function of reducing hydrogen diffusion for the conductor 205a, it is possible to prevent impurities such as hydrogen contained in the conductor 205b from diffusing into the oxide 230 via the insulator 216 and the like. In addition, by using a conductive material having a function of suppressing oxygen diffusion for the conductor 205a, it is possible to suppress the conductor 205b from being oxidized and its conductivity from decreasing. Examples of conductive materials having a function of suppressing oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. The conductor 205a can have a single-layer structure or a multilayer structure of the above conductive materials. For example, the conductor 205a preferably has titanium nitride.

[0114] The conductor 205b is preferably made of a conductive material mainly composed of tungsten, copper, or aluminum. For example, the conductor 205b preferably contains tungsten.

[0115] The conductor 205 can function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260. In particular, by applying a negative potential to the conductor 205, the Vth of the transistor 200 can be increased and the off-current can be reduced. Therefore, applying a negative potential to the conductor 205 can reduce the drain current when the potential applied to the conductor 260 is 0 V, compared to not applying a negative potential.

[0116] Moreover, the electrical resistivity of the conductor 205 is designed taking into consideration the potential applied to the conductor 205, and the film thickness of the conductor 205 is set according to the electrical resistivity. Moreover, the film thickness of the insulator 216 is approximately the same as that of the conductor 205. Here, it is preferable to make the film thicknesses of the conductor 205 and the insulator 216 thin within the range permitted by the design of the conductor 205. By making the film thickness of the insulator 216 thin, the absolute amount of impurities such as hydrogen contained in the insulator 216 can be reduced, and therefore the diffusion of the impurities into the oxide 230 can be reduced.

[0117] In the above, a laminated structure of the conductor 205a and the conductor 205b is shown, but the present invention is not limited to this, and the conductor 205 may have a single layer structure or a laminated structure of three or more layers. For example, when the conductor 205 has a three-layer laminated structure, the laminated structure of the conductor 205a and the conductor 205b may further include a conductor having the same material as the conductor 205a on the conductor 205b. In this case, the conductor may be formed so that the upper surface of the conductor 205b is lower than the top of the conductor 205a, and the recess formed by the conductor 205a and the conductor 205b is filled.

[0118] The insulator 224, together with the insulators 221 and 222, functions as a second gate insulator.

[0119] The insulator 224 in contact with the oxide 230 preferably contains, for example, silicon oxide or silicon oxynitride, which allows oxygen to be supplied from the insulator 224 to the oxide 230, thereby reducing oxygen vacancies.

[0120] Also, it is preferable that the insulator 224 is processed into an island shape, similar to the oxide 230. Thus, when a plurality of transistors 200 are provided, the insulators 224 are provided with approximately the same size for each transistor 200. As a result, the amount of oxygen supplied from the insulator 224 to the oxide 230 in each transistor 200 becomes approximately the same. Therefore, it is possible to suppress the variation in the electrical characteristics of the transistors 200 within the substrate surface. However, this is not limited thereto, and similar to the insulator 222, the insulator 224 may be configured not to be patterned.

[0121] The insulator 224 may have a laminated structure of two or more layers. In this case, the laminated structure is not limited to being made of the same material, and may be made of different materials.

[0122] It is preferable to use a conductive material that is difficult to oxidize or a conductive material that has a function of suppressing the diffusion of oxygen as the conductor 242a, the conductor 242b, and the conductor 260. Examples of the conductive material include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductor 242a, the conductor 242b, and the conductor 260. When a conductive material containing metal and nitrogen is used as the conductor 242a, the conductor 242b, and the conductor 260, the conductor 242a, the conductor 242b, and the conductor 260 are conductors that have at least a metal and nitrogen.

[0123] In FIG. 1B, the conductors 242a and 242b are shown as having a two-layer structure. The conductor 242a is a laminated film of a conductor 242a1 and a conductor 242a2 on the conductor 242a1, and the conductor 242b is a laminated film of a conductor 242b1 and a conductor 242b2 on the conductor 242b1. In this case, it is preferable to use a conductive material that is difficult to oxidize or a conductive material that has a function of suppressing the diffusion of oxygen as the layer in contact with the oxide 230b (the conductor 242a1 and the conductor 242b1). This can suppress a decrease in the conductivity of the conductors 242a and 242b. In addition, it can suppress the extraction of oxygen from the oxide 230b, which can prevent an excessive amount of oxygen vacancy from being formed. In addition, it is preferable to use a material that easily absorbs (removes) hydrogen for the layers in contact with the oxide 230b (the conductor 242a1 and the conductor 242b1), since the hydrogen concentration in the oxide 230 can be reduced.

[0124] As the conductors 242a1 and 242b1, it is preferable to use a metal nitride, for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum. In one aspect of the present invention, a nitride containing tantalum is particularly preferable. Also, for example, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, or the like may be used. These materials are preferable because they are conductive materials that are difficult to oxidize, or materials that maintain conductivity even when they absorb oxygen.

[0125] Note that hydrogen contained in the oxide 230b may diffuse into the conductor 242a1 or the conductor 242b1. In particular, by using a nitride containing tantalum for the conductor 242a1 and the conductor 242b1, hydrogen contained in the oxide 230b may easily diffuse into the conductor 242a1 or the conductor 242b1, and the diffused hydrogen may combine with nitrogen contained in the conductor 242a1 or the conductor 242b1. In other words, hydrogen contained in the oxide 230b may be absorbed by the conductor 242a1 or the conductor 242b1.

[0126] Moreover, it is preferable that the conductor 242a2 and the conductor 242b2 have higher conductivity than the conductor 242a1 and the conductor 242b1. For example, it is preferable that the film thickness of the conductor 242a2 and the conductor 242b2 is larger than the film thickness of the conductor 242a1 and the conductor 242b1. As the conductor 242a2 and the conductor 242b2, a conductor that can be used for the conductor 205b may be used. By adopting the above-mentioned structure, it is possible to reduce the resistance of the conductor 242a2 and the conductor 242b2. As a result, it is possible to improve the operating speed of the semiconductor device according to this embodiment.

[0127] For example, tantalum nitride or titanium nitride can be used as the conductor 242a1 and the conductor 242b1, and tungsten can be used as the conductor 242a2 and the conductor 242b2.

[0128] In order to prevent the conductivity of the conductors 242a and 242b from decreasing, it is preferable to use a crystalline oxide such as CAAC-OS as the oxide 230b. In particular, it is preferable to use a metal oxide containing indium, zinc, and one or more selected from gallium, aluminum, and tin. By using CAAC-OS, it is possible to prevent the conductor 242a or conductor 242b from extracting oxygen from the oxide 230b. It is also possible to prevent the conductivity of the conductor 242a and conductor 242b from decreasing.

[0129] As shown in Fig. 1B and Fig. 1C, the insulator 255 is disposed in an opening formed in the insulator 280 or the like, and contacts the side of the insulator 280, the side of the insulator 275, the side of the insulator 271a, the side of the insulator 271b, the side of the conductor 242a2, the side of the conductor 242b2, the upper surface of the conductor 242a1, the upper surface of the conductor 242b1, and the upper surface of the insulator 222. In other words, the insulator 255 can be said to be formed in a sidewall shape in contact with the side wall of the opening formed in the insulator 280 or the like. Note that a protruding portion is formed in the portion of the insulator 255 that contacts the upper surface of the conductor 242a1, the upper surface of the conductor 242b1, or the upper surface of the insulator 222, and is shaped to protrude toward the center of the opening more than other portions.

[0130] The insulator 255 is formed in contact with the side surface of the conductor 242a2 and the side surface of the conductor 242b2, and is an inorganic insulator that protects the conductor 242a2 and the conductor 242b2. Since the insulator 255 is exposed to an oxidizing atmosphere, it is preferable that the insulator 255 is an inorganic insulator that is not easily oxidized. Furthermore, since the insulator 255 is in contact with the conductor 242a2 and the conductor 242b2, it is preferable that the insulator 255 is an inorganic insulator that is not easily oxidized. Therefore, it is preferable that the insulator 255 is made of an insulating material that can be used for the insulator 250c having a barrier property against oxygen. For example, silicon nitride can be used as the insulator 255.

[0131] By using such an insulator 255, even if a heat treatment is performed in an oxygen-containing atmosphere after the conductor is divided into conductor 242a1 and conductor 242b1 and before the insulator 250 is formed, the conductor 242a2 and the conductor 242b2 are not excessively oxidized.

[0132] The thickness of the insulator 255 is preferably 0.5 nm to 20 nm, more preferably 0.5 nm to 10 nm, and more preferably 0.5 nm to 3 nm. By setting the thickness of the insulator 255 as described above, it is possible to suppress excessive oxidation of the conductor 242a2 and the conductor 242b2. The insulator 255 may have a region with the thickness as described above at least in a part. Since the insulator 255 is provided in contact with the side wall of the opening formed in the insulator 280 or the like, it is preferable to form the film using an ALD method or the like that has good coverage. If the thickness of the insulator 255 is excessively thick, the time required for forming the insulator 255 by the ALD method becomes longer and the productivity decreases, so it is preferable to set the thickness of the insulator 255 to about the above range. Here, the thickness of the insulator 255 refers to the thickness in the A1-A2 direction above the protruding portion of the insulator 255.

[0133] The insulator 255 may have a laminated structure of two or more layers. In this case, at least one layer may be an inorganic insulator that is not easily oxidized. For example, as shown in FIG. 3(C), a laminated structure of an insulator 255b and an insulator 255a on the insulator 255b may be used. It can also be considered that the insulator 255a is disposed inside the insulator 255b. Here, the lower surface of the insulator 255a may contact the insulator 255b. The insulator 255a may be made of the inorganic insulator that is not easily oxidized, and the insulator 255b may be made of an insulator that can be used for the insulator 250b (e.g., silicon oxide). It is preferable that the insulator 255b has a lower dielectric constant than the insulator 255a. In this way, by making the insulator 255 have a two-layer structure and increasing the film thickness, the distance between the conductor 260 and the conductor 242a or the conductor 242b can be increased, and the parasitic capacitance can be reduced.

[0134] The insulator 255 also functions as a mask when dividing the conductor 242a1 and the conductor 242b1. Therefore, as shown in FIG. 1B and other drawings, in a cross-sectional view of the transistor 200, it is preferable that ends of the protrusions of the insulator 255 coincide or roughly coincide with the side ends of the conductor 242a1 and the conductor 242b1.

[0135] In addition, when the side ends are aligned or approximately aligned in cross-sectional view, and when the top surface shapes are aligned or approximately aligned, it can be said that at least a part of the contours of the stacked layers overlap in top view. For example, this includes a case where the lower part of the side end of the upper layer contacts the upper part of the side end of the lower layer. It also includes a case where the upper layer and the lower layer are processed using the same mask pattern or a mask pattern with parts of the same mask. It also includes a case where the lower layer is processed using the upper layer as a mask. However, strictly speaking, the contours may not overlap, and a part of the upper layer may be located inside the lower layer, or a part of the upper layer may be located outside the lower layer. In this case, it is also said that the side ends are aligned or approximately aligned, or the top surface shapes are aligned or approximately aligned.

[0136] Here, the portion of the conductor 242a1 on which the insulator 255 is formed on the upper surface is formed to protrude toward the conductor 260 side more than the conductor 242a2. Similarly, the portion of the conductor 242b1 on which the insulator 255 is formed on the upper surface is formed to protrude toward the conductor 260 side more than the conductor 242b2. As shown in FIG. 2B, in a cross-sectional view of the transistor 200 in the channel length direction, the distance L2 between the conductor 242a1 and the conductor 242b1 is smaller than the distance L1 between the conductor 242a2 and the conductor 242b2. Here, the difference between L1 and L2 can be two or more times the film thickness of the insulator 255.

[0137] The distance L2 between the conductor 242a1 and the conductor 242b1 is preferably fine because it is reflected in the channel length of the transistor 200. For example, the distance L2 is preferably 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and is preferably 1 nm or more, or 5 nm or more. For example, the distance L2 is more preferably about 1 nm or more and 20 nm or less. By adopting such a configuration, it is possible to shorten the distance between the source and the drain, and accordingly shorten the channel length. Therefore, the on-current of the transistor 200 can be increased, the subthreshold swing value (sometimes written as S value) can be reduced, and the frequency characteristics can be improved. Here, the S value refers to the amount of change in the gate voltage in the subthreshold region that changes the drain current by one order of magnitude with a constant drain voltage. In this way, by miniaturizing the semiconductor device, a semiconductor device with improved operating speed can be provided.

[0138] 4A, a recess may be formed in a portion of the oxide 230b that is exposed from the conductor 242a1 and the conductor 242b1. In other words, on the upper surface of the oxide 230b, a region sandwiched between the conductor 242a1 and the conductor 242b1 may be lower in height than a region overlapping with the conductor 242a1 and a region overlapping with the conductor 242b1.

[0139] 2A, the opposing side surfaces of the conductor 242a1 and the conductor 242b1 and the opposing side surfaces of the conductor 242a2 and the conductor 242b2 are perpendicular or approximately perpendicular to the top surface of the oxide 230b, but the present invention is not limited to this. For example, as shown in FIG. 4B, the opposing side surfaces of the conductor 242a1 and the conductor 242b1 and the opposing side surfaces of the conductor 242a2 and the conductor 242b2 may be tapered. In this case, the side surfaces of the insulator 271a, the insulator 271b, the insulator 275, and the insulator 280 may be tapered.

[0140] Furthermore, the taper angle of the conductors 242a1 and 242b1 may be configured to be more acute than the taper angle of the conductors 242a2 and 242b2.

[0141] Also, as shown in FIG. 4(C), the upper part of the side of the insulator 255 may have a tapered shape. Also, as shown in FIG. 4(C), the upper part of the insulator 280 may also have a tapered shape that is continuous or approximately continuous with the tapered shape of the side of the insulator 255. Also, as shown in FIG. 4(C), the upper parts of the insulator 255 and the insulator 280 may have curved surfaces. Here, the insulator 250a may come into contact with the tapered parts of the upper part of the insulator 255 and the upper part of the insulator 280. In this case, if the upper parts of the insulator 255 and the insulator 280 have curved surfaces, the insulator 250a can be formed with good coverage.

[0142] 4(D), the transistor 200 may have the structure shown in FIG 4(A) to FIG 4(C). That is, there is a case where a recess is formed in a portion of the oxide 230b exposed from the conductors 242a1 and 242b1, the side surfaces of the conductors 242a1 and 242b1 and the side surfaces of the conductors 242a2 and 242b2 are tapered, and an upper portion of the side surface of the insulator 255 is tapered.

[0143] The insulators 271a and 271b are inorganic insulators that function as etching stoppers when the conductors 242a2 and 242b2 are processed, and protect the conductors 242a2 and 242b2. Since the insulators 271a and 271b are in contact with the conductors 242a2 and 242b2, it is preferable that the insulators 271a and 271b are inorganic insulators that are unlikely to oxidize the conductors 242a and 242b. Therefore, as shown in FIG. 2A, it is preferable that the insulator 271a has a layered structure of an insulator 271a1 and an insulator 271a2 on the insulator 271a1, and the insulator 271b has a layered structure of an insulator 271b1 and an insulator 271b2 on the insulator 271b1. Here, the insulators 271a1 and 271b1 are preferably made of a nitride insulator that can be used for the insulator 250c so as to prevent the conductors 242a2 and 242b2 from being oxidized, and the insulators 271a2 and 271b2 are preferably made of an oxide insulator that can be used for the insulator 250b so as to function as an etching stopper.

[0144] Here, the insulator 271a1 contacts the upper surface of the conductor 242a2 and a part of the insulator 275, and the insulator 271b1 contacts the upper surface of the conductor 242b2 and a part of the insulator 275. The insulator 271a2 contacts the upper surface of the insulator 271a1 and the lower surface of the insulator 275, and the insulator 271b2 contacts the upper surface of the insulator 271b1 and the lower surface of the insulator 275. For example, silicon nitride can be used as the insulators 271a1 and 271b1, and silicon oxide can be used as the insulators 271a2 and 271b2.

[0145] Since the insulators that are the basis of the insulators 271a and 271b function as masks for the conductors that are the basis of the conductors 242a and 242b, the conductors 242a and 242b do not have curved surfaces between their side surfaces and top surfaces. As a result, the ends of the conductors 242a and 242b where the side surfaces and top surfaces intersect are angular. By making the ends of the conductors 242a and 242b where the side surfaces and top surfaces intersect angular, the cross-sectional areas of the conductors 242a and 242b are larger than when the ends have curved surfaces. Furthermore, by using a nitride insulator that does not easily oxidize metal for the insulators 271a1 and 271b1, it is possible to prevent the conductors 242a and 242b from being excessively oxidized. As a result, the resistance of the conductors 242a and 242b is reduced, and the on-current of the transistor can be increased.

[0146] 1(B) and 1(C), the conductor 260 is disposed in an opening formed in the insulator 280 and the insulator 275. The conductor 260 is disposed in the opening so as to cover the upper surface of the insulator 222, the side surface of the insulator 224, the side surface of the oxide 230a, the side surface of the oxide 230b, and the upper surface of the oxide 230b via the insulator 250. The upper surface of the conductor 260 is disposed so as to be flush or approximately flush with the top of the insulator 250, the top of the insulator 255, and the upper surface of the insulator 280.

[0147] In the opening in which the conductor 260 and the insulator 250 are disposed, the sidewall of the opening may be perpendicular or approximately perpendicular to the upper surface of the insulator 222, or may be tapered. By making the sidewall tapered, the coverage of the insulators 255 and 250 provided in the opening of the insulator 280 is improved, and defects such as voids can be reduced.

[0148] The conductor 260 functions as a first gate electrode of the transistor 200. Here, the conductor 260 is preferably provided to extend in the channel width direction as shown in Figure 1 (A) and Figure 1 (C) . With this structure, when a plurality of transistors are provided, the conductor 260 functions as a wiring.

[0149] 1C, in a cross-sectional view in the channel width direction of the transistor 200, a curved surface may be formed between the side surface of the oxide 230b and the top surface of the oxide 230b. In other words, the end of the side surface and the end of the top surface may be curved (hereinafter also referred to as rounded).

[0150] The radius of curvature of the curved surface is preferably greater than 0 nm and smaller than the film thickness of the oxide 230b in the region overlapping with the conductor 242a and the conductor 242b, or smaller than half the length of the region not having the curved surface. Specifically, the radius of curvature of the curved surface is greater than 0 nm and less than 20 nm, preferably greater than 1 nm and less than 15 nm, and more preferably greater than 2 nm and less than 10 nm. By forming the curved surface in this manner, the coverage of the oxide 230b by the insulator 250 and the conductor 260 can be improved.

[0151] In this specification, the structure of a transistor in which the electric field of at least the first gate electrode electrically surrounds the channel formation region is called a surrounded channel (S-channel) structure. The S-channel structure disclosed in this specification has a structure different from the Fin type structure and the planar type structure. On the other hand, the S-channel structure disclosed in this specification can be regarded as a type of Fin type structure. In this specification, the Fin type structure refers to a structure in which the gate electrode is disposed so as to surround at least two or more sides of the channel (specifically, two, three, or four sides, etc.). By adopting the Fin type structure and the S-channel structure, it is possible to obtain a transistor that is more resistant to the short channel effect, in other words, in which the short channel effect is less likely to occur.

[0152] By making the transistor 200 have the above-mentioned S-channel structure, the channel formation region can be electrically surrounded. Note that the S-channel structure is a structure that electrically surrounds the channel formation region, and therefore it can be said to be substantially the same as a GAA (Gate All Around) structure or a LGAA (Lateral Gate All Around) structure. By making the transistor 200 have the S-channel structure, the GAA structure, or the LGAA structure, the channel formation region formed at or near the interface between the oxide 230 and the gate insulator can be the entire bulk of the oxide 230. Therefore, it is possible to improve the current density flowing through the transistor, and therefore it is expected to improve the on-current of the transistor or the field effect mobility of the transistor.

[0153] In this embodiment, the insulator 224 is provided in an island shape. Therefore, as shown in FIG. 1C, at least a part of the lower surface of the conductor 260 can be provided below the lower surface of the oxide 230b. This allows the conductor 260 to be provided facing the upper surface and side surface of the oxide 230b, so that the electric field of the conductor 260 can be applied to the upper surface and side surface of the oxide 230b. By providing the insulator 224 in an island shape in this manner, the transistor 200 can have an S-channel structure.

[0154] 1C is an example of a transistor having an S-channel structure, but the semiconductor device of one embodiment of the present invention is not limited to this. For example, the transistor structure that can be used in one embodiment of the present invention may be one or more selected from a planar structure, a fin structure, and a GAA structure.

[0155] In FIG. 1B and other figures, the conductor 260 is shown to have a two-layer structure. Here, the conductor 260 preferably has a conductor 260a and a conductor 260b arranged on the conductor 260a. For example, the conductor 260a is preferably arranged so as to surround the bottom and side surfaces of the conductor 260b. In this case, it is preferable to use a conductive material that is not easily oxidized or a conductive material that has a function of suppressing the diffusion of oxygen as the conductor 260a.

[0156] The conductor 260a is preferably made of a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, copper atoms, etc. Alternatively, it is preferably made of a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules).

[0157] Furthermore, since the conductor 260a has a function of suppressing the diffusion of oxygen, it is possible to suppress the conductor 260b from being oxidized and its conductivity from being reduced by oxygen contained in the insulator 280, etc. As a conductive material having a function of suppressing the diffusion of oxygen, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like.

[0158] Moreover, it is preferable that the conductor 260b is a conductor having high conductivity. For example, the conductor 260b may be a conductive material mainly composed of tungsten, copper, or aluminum. The conductor 260b may have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above-mentioned conductive material.

[0159] In the transistor 200, the conductor 260 is formed in a self-aligned manner so as to fill an opening formed in the insulator 280 or the like. By forming the conductor 260 in this manner, the conductor 260 can be arranged so as to overlap the region between the conductor 242a1 and the conductor 242b1 without alignment.

[0160] The insulators 216 and 280 each preferably have a dielectric constant lower than that of the insulator 222. By using a material with a low dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced.

[0161] For example, insulator 216 and insulator 280 each preferably comprise one or more of silicon oxide, silicon oxynitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon- and nitrogen-doped silicon oxide, and silicon oxide with vacancies.

[0162] In particular, silicon oxide and silicon oxynitride are preferred because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are preferred because they can easily form a region containing oxygen that is desorbed by heating.

[0163] Additionally, the top surfaces of the insulators 216 and 280 may each be flattened.

[0164] It is preferable that the concentration of impurities such as water and hydrogen is reduced in the insulator 280. For example, it is preferable that the insulator 280 has an oxide containing silicon, such as silicon oxide or silicon oxynitride.

[0165] <Materials for semiconductor devices> Constituent materials that can be used in the semiconductor device will be described below. Each layer constituting the semiconductor device may have a single layer structure or a multilayer structure.

[0166] <<Substrate>> As the substrate on which the transistor is formed, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate can be used. As the insulating substrate, for example, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as an yttria stabilized zirconia substrate), and a resin substrate can be mentioned. As the semiconductor substrate, for example, a semiconductor substrate made of silicon or germanium, and a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide can be mentioned. Furthermore, as the semiconductor substrate, a semiconductor substrate having an insulator region inside the semiconductor substrate, for example, an SOI (Silicon On Insulator) substrate, can be mentioned. As the conductive substrate, for example, a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate can be mentioned. As the substrate, for example, a substrate having a metal nitride, a substrate having a metal oxide, a substrate having a conductor or semiconductor provided on an insulating substrate, a substrate having a conductor or insulator provided on a semiconductor substrate, and a substrate having a semiconductor or insulator provided on a conductive substrate can be mentioned. Alternatively, one or more types of elements may be provided on the substrate, such as a capacitor element, a resistor element, a switch element, a light-emitting element, and a memory element.

[0167] <<Insulators>> Examples of the insulator include insulating oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides.

[0168] For example, as transistors become smaller and more highly integrated, problems such as leakage current can occur due to thinner gate insulators. By using a high-k material for the insulator that functions as the gate insulator, it is possible to reduce the voltage required for transistor operation while maintaining the physical film thickness. On the other hand, by using a material with a low dielectric constant for the insulator that functions as the interlayer film, it is possible to reduce the parasitic capacitance that occurs between wiring. Therefore, it is best to select materials according to the function of the insulator.

[0169] Examples of insulators with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium.

[0170] Examples of insulators with a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide having voids, and resin.

[0171] In addition, the transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen. As the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing one or more of boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum can be used in a single layer or a stacked layer. Specifically, as the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride can be used.

[0172] The insulator that functions as the gate insulator is preferably an insulator having a region containing oxygen that is released by heating. For example, by using a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with the oxide 230, oxygen vacancies in the oxide 230 can be compensated for.

[0173] <<Conductors>> As the conductor, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal elements as a component, or an alloy combining the above-mentioned metal elements. As the conductor, for example, tantalum nitride, titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, and oxide containing lanthanum and nickel can be mentioned. In addition, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, and oxide containing lanthanum and nickel are preferable because they are conductive materials that are difficult to oxidize, or materials that maintain conductivity even when oxygen is absorbed. Alternatively, a semiconductor having high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.

[0174] When a conductor with a layered structure is used, for example, a layered structure combining the material containing the metal element described above and a conductive material containing oxygen, a layered structure combining the material containing the metal element described above and a conductive material containing nitrogen, or a layered structure combining the material containing the metal element described above and a conductive material containing oxygen and a conductive material containing nitrogen may be applied.

[0175] In addition, when an oxide is used for the channel formation region of a transistor, a conductor functioning as a gate electrode preferably has a stacked structure in which a material containing a metal element and a conductive material containing oxygen are combined. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0176] In particular, it is preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed as a conductor functioning as a gate electrode. The conductive material containing the metal element and nitrogen described above may also be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may also be used. Indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide to which silicon is added may also be used. Indium gallium zinc oxide containing nitrogen may also be used. By using such a material, hydrogen contained in the metal oxide in which the channel is formed may be captured. Alternatively, hydrogen mixed in from an external insulator may be captured.

[0177] <<Metal oxides>> A metal oxide that functions as a semiconductor (oxide semiconductor) is preferably used as the oxide 230. Metal oxides that can be used as the oxide 230 of one embodiment of the present invention are described below.

[0178] The metal oxide preferably contains at least indium or zinc. In particular, it is preferable that the metal oxide contains indium and zinc. In addition to these, it is preferable that the metal oxide contains aluminum, gallium, yttrium, tin, antimony, etc. In addition, it may contain one or more elements selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc.

[0179] Here, the case where the metal oxide is an In-M-Zn oxide having indium, element M, and zinc is considered. The element M is aluminum, gallium, yttrium, tin, or antimony. Other elements applicable to the element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt. However, there are cases where the element M may be a combination of a plurality of the above elements. In particular, the element M is preferably one or more selected from gallium, aluminum, yttrium, and tin.

[0180] In this specification and the like, metal oxides containing nitrogen may also be collectively referred to as metal oxides. Furthermore, metal oxides containing nitrogen may also be referred to as metal oxynitrides.

[0181] In the following, In-Ga-Zn oxide will be described as an example of a metal oxide.

[0182] Examples of the crystal structure of an oxide semiconductor include amorphous (including completely amorphous), c-axis-aligned crystalline (CAAC), nanocrystalline (nc), cloud-aligned composite (CAC), single crystal, and polycrystal.

[0183] Note that oxide semiconductors may be classified differently from the above when focusing on their structures. For example, oxide semiconductors are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, amorphous-like oxide semiconductors (a-like OS), and amorphous oxide semiconductors.

[0184] Here, the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described in detail.

[0185] [CAAC-OS] CAAC-OS is an oxide semiconductor having a plurality of crystalline regions, each of which has a c-axis aligned in a specific direction. The specific direction is the thickness direction of the CAAC-OS film, the normal direction of the surface on which the CAAC-OS film is formed, or the normal direction of the surface of the CAAC-OS film. The crystalline region is a region having periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, the crystalline region is also a region with a uniform lattice arrangement. CAAC-OS has a region in which a plurality of crystalline regions are connected in the ab-plane direction, and the region may have distortion. The distortion refers to a portion in which the direction of the lattice arrangement changes between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement in the region in which the plurality of crystalline regions are connected. In other words, CAAC-OS is an oxide semiconductor having a c-axis aligned and no clear orientation in the ab-plane direction.

[0186] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the maximum diameter of the crystalline region may be about several tens of nm.

[0187] The CAAC-OS is an oxide semiconductor with high crystallinity and no clear crystal grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to a decrease in electron mobility due to crystal grain boundaries. In addition, since the crystallinity of an oxide semiconductor can be decreased by the inclusion of impurities or the generation of defects, the CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, the physical properties of an oxide semiconductor having the CAAC-OS are stable. Therefore, an oxide semiconductor having the CAAC-OS is resistant to heat and has high reliability. In addition, the CAAC-OS is stable against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, the use of the CAAC-OS in an OS transistor can increase the degree of freedom in the manufacturing process.

[0188] [nc-OS] The nc-OS has periodic atomic arrangement in a microscopic region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has microcrystals. Note that the size of the microcrystals is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore the microcrystals are also called nanocrystals. Furthermore, the nc-OS does not exhibit regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film. Therefore, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor depending on the analysis method.

[0189] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a void or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Moreover, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0190] Next, the above-mentioned CAC-OS will be described in detail, with reference to its material composition.

[0191] [CAC-OS] CAC-OS is, for example, a material configuration in which elements constituting a metal oxide are unevenly distributed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof. In the following, a state in which one or more metal elements are unevenly distributed in a metal oxide and the regions having the metal elements are mixed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof, is also referred to as a mosaic or patch state.

[0192] Furthermore, CAC-OS is a composite metal oxide in which the material is separated into a first region and a second region, forming a mosaic structure, and the first region is distributed throughout the film (hereinafter, also referred to as a cloud structure). In other words, CAC-OS is a composite metal oxide in which the first region and the second region are mixed together.

[0193] In addition, the CAC-OS in In-Ga-Zn oxide refers to a structure in which a region (first region) mainly composed of In and a region (second region) mainly composed of Ga are arranged randomly in a mosaic pattern in a material structure containing In, Ga, Zn, and O. Therefore, it is presumed that the CAC-OS has a structure in which metal elements are distributed non-uniformly.

[0194] The CAC-OS can be formed, for example, by a sputtering method under conditions where the substrate is not heated. When the CAC-OS is formed by a sputtering method, any one or more selected from an inert gas (typically argon), oxygen gas, and nitrogen gas can be used as the film formation gas. The lower the flow rate ratio of oxygen gas to the total flow rate of film formation gas during film formation, the more preferable it is. For example, the flow rate ratio of oxygen gas to the total flow rate of film formation gas during film formation is set to 0% or more and less than 30%, preferably 0% or more and 10% or less.

[0195] Here, the first region is a region with higher conductivity than the second region. In other words, the first region exhibits conductivity as a metal oxide when carriers flow through the first region. Therefore, the first region is distributed in a cloud-like shape in the metal oxide, thereby realizing a high field-effect mobility (μ).

[0196] On the other hand, the second region has higher insulating properties than the first region, that is, the second region is distributed in the metal oxide, thereby making it possible to suppress leakage current.

[0197] Therefore, when CAC-OS is used in a transistor, the conductivity due to the first region and the insulation due to the second region act complementarily, giving the CAC-OS a switching function (On / Off function). In other words, CAC-OS has a conductive function in part of the material and an insulating function in part of the material, and the material as a whole functions as a semiconductor. By separating the conductive function from the insulating function, it is possible to maximize both functions. Therefore, by using CAC-OS in a transistor, it is possible to achieve a high on-current (I on ), high field effect mobility (μ), and good switching operation can be achieved.

[0198] In addition, a transistor using CAC-OS has high reliability, making it ideal for various semiconductor devices such as display devices.

[0199] Oxide semiconductors have a variety of structures and each structure has different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0200] <<Other semiconductor materials>> The semiconductor layer of the transistor may be made of a semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor), such as a semiconductor of an element such as silicon or a compound semiconductor such as gallium arsenide.

[0201] In addition, it is preferable to use, for example, a transition metal chalcogenide that functions as a semiconductor in the semiconductor layer of the transistor. Specific examples of transition metal chalcogenides that can be applied to the semiconductor layer of the transistor include molybdenum sulfide (representatively MoS2), molybdenum selenide (representatively MoSe2), molybdenum tellurium (representatively MoTe2), tungsten sulfide (representatively WS2), tungsten selenide (representatively WSe2), tungsten tellurium (representatively WTe2), hafnium sulfide (representatively HfS2), hafnium selenide (representatively HfSe2), zirconium sulfide (representatively ZrS2), and zirconium selenide (representatively ZrSe2). By applying the above-mentioned transition metal chalcogenide to the semiconductor layer of the transistor, a semiconductor device with a large on-current can be provided.

[0202] <Example of a method for manufacturing a semiconductor device> An example of a method for manufacturing a semiconductor device of one embodiment of the present invention will be described with reference to Figures 5A to 18D. Here, the case of manufacturing the semiconductor device illustrated in Figures 1A to 1D will be described as an example.

[0203] (A) in each figure shows a plan view. (B) in each figure shows a cross-sectional view corresponding to the portion indicated by the dashed line A1-A2 in (A) of each figure, and is also a cross-sectional view in the channel length direction of the transistor 200. (C) in each figure shows a cross-sectional view corresponding to the portion indicated by the dashed line A3-A4 in (A) of each figure, and is also a cross-sectional view in the channel width direction of the transistor 200. (D) in each figure shows a cross-sectional view corresponding to the portion indicated by the dashed line A5-A6 in (A) of each figure, and is also a cross-sectional view in the channel width direction of the transistor 200. Note that in the plan view in (A) of each figure, some elements are omitted for clarity. Also, Figs. 14(A) to 14(C) are cross-sectional views corresponding to the portion indicated by the dashed line A3-A4. Figs. 16(A) to 16(C) are enlarged cross-sectional views in the channel length direction of the transistor 200.

[0204] In the following, insulating materials for forming insulators, conductive materials for forming conductors, or semiconductor materials for forming semiconductors can be formed as films by appropriately using a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an ALD method, or the like.

[0205] There are three types of sputtering: RF sputtering, which uses a high-frequency power source for the sputtering power supply, DC sputtering, which uses a direct current power source, and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is mainly used when depositing insulating films, while DC sputtering is mainly used when depositing metal conductive films. Pulsed DC sputtering is mainly used when depositing compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0206] CVD methods can be classified into plasma CVD (PECVD) methods that use plasma, thermal CVD (TCVD: Thermal CVD) methods that use heat, photo CVD (Photo CVD) methods that use light, etc. They can also be further classified into metal CVD (MCVD: Metal CVD) methods and metal organic CVD (MOCVD: Metal Organic CVD) methods depending on the source gas used.

[0207] The plasma CVD method can obtain a high-quality film at a relatively low temperature. Moreover, the thermal CVD method is a film formation method that can reduce plasma damage to the object to be processed because it does not use plasma. For example, wiring, electrodes, elements (transistors, capacitive elements, etc.) included in a semiconductor device may be charged up by receiving electric charge from plasma. At this time, the wiring, electrodes, elements, etc. included in the semiconductor device may be destroyed by the accumulated electric charge. On the other hand, in the case of the thermal CVD method that does not use plasma, such plasma damage does not occur, so the yield of the semiconductor device can be increased. Furthermore, in the thermal CVD method, plasma damage does not occur during film formation, so a film with few defects can be obtained.

[0208] As the ALD method, a thermal ALD method in which a reaction between a precursor and a reactant is carried out using only thermal energy, a PEALD method in which a plasma-excited reactant is used, or the like can be used.

[0209] The CVD method and the ALD method are different from the sputtering method in which particles emitted from a target or the like are deposited. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio. However, since the ALD method has a relatively slow film formation speed, it may be preferable to use it in combination with other film formation methods such as the CVD method, which has a fast film formation speed.

[0210] In addition, in the CVD method, a film of any composition can be formed by changing the flow rate ratio of the raw material gases. For example, in the CVD method, a film with a continuously changing composition can be formed by changing the flow rate ratio of the raw material gases while forming a film. When forming a film while changing the flow rate ratio of the raw material gases, the time required for film formation can be shortened compared to the case of forming a film using multiple film formation chambers because no time is required for transportation or pressure adjustment. Therefore, the productivity of semiconductor devices can be increased in some cases.

[0211] In addition, in the ALD method, a film of any composition can be formed by simultaneously introducing multiple different precursors, or by controlling the number of cycles of each precursor when multiple different precursors are introduced.

[0212] First, a substrate (not shown) is prepared, and the insulator 215 is formed on the substrate (see FIGS. 5A to 5D). As described above, the insulator 215 can be an insulator similar to one or more of the stacked films of the insulators 224, 282, and 283. The insulator 215 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. It is preferable to use a sputtering method, which does not require the use of molecules containing hydrogen in the deposition gas, because the hydrogen concentration in the insulator 215 can be reduced.

[0213] Next, the insulator 216 is formed over the insulator 215. The insulator 216 is preferably formed by a sputtering method. By using a sputtering method that does not require the use of molecules containing hydrogen in the deposition gas, the hydrogen concentration in the insulator 216 can be reduced. However, the deposition of the insulator 216 is not limited to the sputtering method, and a CVD method, an MBE method, a PLD method, an ALD method, or the like may be used as appropriate. In this embodiment, silicon oxide is deposited as the insulator 216 by a sputtering method.

[0214] It is preferable that the insulators 215 and 216 are successively formed without exposure to the air. For example, a multi-chamber film formation apparatus can be used. This allows the insulators 215 and 216 to be formed with reduced hydrogen in the films, and further reduces the inclusion of hydrogen in the films between film formation steps.

[0215] Next, an opening is formed in the insulator 216, reaching the insulator 215. The opening may be formed by wet etching, but dry etching is preferable for fine processing. For the insulator 215, it is preferable to select an insulator that functions as an etching stopper film when etching the insulator 216 to form a groove. For example, when silicon oxide or silicon oxynitride is used for the insulator 216 that forms the groove, the insulator 215 may be made of silicon nitride, aluminum oxide, hafnium oxide, or the like.

[0216] After the opening is formed, a conductive film that becomes the conductor 205a is formed. The conductive film that becomes the conductor 205a preferably contains a conductor that has a function of suppressing oxygen permeation. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, it can be a laminated film of a conductor that has a function of suppressing oxygen permeation and tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy. The conductive film that becomes the conductor 205a can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0217] In this embodiment, titanium nitride is formed as the conductive film that becomes the conductor 205a. By using such a metal nitride as the lower layer of the conductor 205b, it is possible to prevent the conductor 205b from being oxidized by the insulator 216 or the like. Even if a metal that easily diffuses, such as copper, is used as the conductor 205b, it is possible to prevent the metal from diffusing out of the conductor 205a.

[0218] Next, a conductive film to be the conductor 205b is formed. As the conductive film to be the conductor 205b, tantalum, tungsten, titanium, molybdenum, aluminum, copper, a molybdenum-tungsten alloy, or the like can be used. The conductive film can be formed by a plating method, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, tungsten is formed as the conductive film to be the conductor 205b.

[0219] Next, CMP processing is performed to remove parts of the conductive film that becomes the conductor 205a and the conductive film that becomes the conductor 205b, and to expose the insulator 216 (see Figures 5(A) to 5(D)). As a result, the conductor 205a and the conductor 205b remain only in the openings. Note that the CMP processing may remove parts of the insulator 216.

[0220] Next, the insulator 221 is formed over the insulator 216 and the conductor 205 (see FIGS. 6A to 6D).

[0221] The insulator 221 may be an insulator having a barrier property against oxygen, hydrogen, and water. The insulator 221 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In this embodiment, a silicon nitride film is formed as the insulator 221 by a PEALD method.

[0222] Next, the insulator 222 is formed over the insulator 221 (see FIGS. 6A to 6D).

[0223] As the insulator 222, an insulator containing one or both of an oxide of aluminum and hafnium may be formed. Note that, as the insulator containing one or both of an oxide of aluminum and hafnium, for example, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used. Alternatively, hafnium zirconium oxide is preferably used. An insulator containing one or both of an oxide of aluminum and hafnium has a barrier property against oxygen, hydrogen, and water. When the insulator 222 has a barrier property against hydrogen and water, the hydrogen and water contained in the structure provided around the transistor are prevented from diffusing into the inside of the transistor through the insulator 222, and the generation of oxygen vacancies in the oxide 230 can be suppressed.

[0224] The insulator 222 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In this embodiment, hafnium oxide is formed as the insulator 222 by an ALD method.

[0225] Next, an insulating film 224f is formed over the insulator 222 (see FIGS. 6A to 6D). As the insulating film 224f, an insulator corresponding to the insulator 224 may be used.

[0226] The insulating film 224f can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In this embodiment, a silicon oxide film is formed as the insulating film 224f by a sputtering method. By using a sputtering method that does not require the use of molecules containing hydrogen in the film formation gas, the hydrogen concentration in the insulating film 224f can be reduced. Since the insulating film 224f will come into contact with the oxide 230a in a later process, it is preferable that the hydrogen concentration is reduced in this manner.

[0227] Note that heat treatment may be performed before the insulating film 224f is formed. The heat treatment may be performed under reduced pressure, and the insulating film 224f may be formed continuously without exposure to air. By performing such treatment, moisture and hydrogen adsorbed on the surface of the insulator 222 can be removed, and the moisture and hydrogen concentrations in the insulator 222 can be further reduced. Here, by providing the insulator 221 in contact with the lower surface of the insulator 222, impurities such as moisture or hydrogen can be prevented from entering from below the insulator 221 by the heat treatment. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower. In this embodiment, the temperature of the heat treatment is 250° C.

[0228] Next, an oxide film 230af is formed on the insulating film 224f, and an oxide film 230bf is formed on the oxide film 230af (see FIGS. 6(A) to 6(D)). A metal oxide corresponding to the oxide 230a may be used as the oxide film 230af, and a metal oxide corresponding to the oxide 230b may be used as the oxide film 230bf. It is preferable that the oxide films 230af and 230bf are successively formed without being exposed to the air environment. By forming the oxide films 230af and 230bf without exposing them to the air, it is possible to prevent impurities or moisture from the air environment from adhering to the oxide films 230af and 230bf, and it is possible to keep the interface or the vicinity of the interface between the oxide films 230af and 230bf clean.

[0229] The oxide film 230af and the oxide film 230bf can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In the present embodiment, the oxide film 230af and the oxide film 230bf are formed by a sputtering method.

[0230] For example, when the oxide film 230af and the oxide film 230bf are formed by sputtering, oxygen or a mixture of oxygen and a noble gas is used as the sputtering gas. By increasing the ratio of oxygen contained in the sputtering gas, the amount of excess oxygen in the oxide film to be formed can be increased. When the oxide film is formed by sputtering, an In-M-Zn oxide target or the like can be used.

[0231] In particular, when the oxide film 230af is formed, part of the oxygen contained in the sputtering gas may be supplied to the insulating film 224f. Therefore, the ratio of oxygen contained in the sputtering gas is preferably 70% or more, more preferably 80% or more, and further preferably 100%.

[0232] When the oxide film 230bf is formed by a sputtering method, an oxygen-excessive oxide semiconductor is formed when the ratio of oxygen contained in the sputtering gas is more than 30% and less than or equal to 100%, preferably 70% to 100%. A transistor using an oxygen-excessive oxide semiconductor for a channel formation region can have relatively high reliability. However, one embodiment of the present invention is not limited thereto. When the oxide film 230bf is formed by a sputtering method, an oxygen-deficient oxide semiconductor is formed when the ratio of oxygen contained in the sputtering gas is 1% to 30%, preferably 5% to 20%,. A transistor using an oxygen-deficient oxide semiconductor for a channel formation region can have relatively high field-effect mobility. When the oxide film 230bf is formed while the substrate is heated, the crystallinity of the oxide film can be improved.

[0233] In this embodiment, the oxide film 230af is formed by sputtering using an oxide target with In:Ga:Zn=1:3:2 [atomic ratio] or an oxide target with In:Ga:Zn=1:3:4 [atomic ratio]. The oxide film 230bf is formed by sputtering using an oxide target with In:Ga:Zn=1:1:1 [atomic ratio], an oxide target with In:Ga:Zn=1:1:1.2 [atomic ratio], an oxide target with In:Ga:Zn=4:2:4.1 [atomic ratio], or an oxide target with In:Ga:Zn=1:1:2 [atomic ratio]. Each oxide film may be formed according to the characteristics required for the oxide 230a and the oxide 230b by appropriately selecting the film formation conditions and the atomic ratio.

[0234] Note that the insulating film 224f, the oxide film 230af, and the oxide film 230bf are preferably formed by a sputtering method without exposure to the air. For example, it is preferable to use a multi-chamber film forming apparatus. This can reduce hydrogen from being mixed into the insulating film 224f, the oxide film 230af, and the oxide film 230bf between film forming steps.

[0235] Next, it is preferable to perform a heat treatment. The heat treatment may be performed within a temperature range in which the oxide film 230af and the oxide film 230bf are not polycrystallized. The temperature of the heat treatment is preferably 100° C. or higher, 250° C. or higher, or 350° C. or higher, and 650° C. or lower, 600° C. or lower, or 550° C. or lower.

[0236] The heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, it is preferable to set the oxygen gas concentration to about 20%. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in the nitrogen gas or inert gas atmosphere, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the desorbed oxygen.

[0237] In addition, the gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and even more preferably 0.05 ppb or less. By using a highly purified gas to perform the heat treatment, it is possible to prevent moisture and the like from being taken into the oxide film 230af and the oxide film 230bf as much as possible.

[0238] In this embodiment, the heat treatment is performed at a temperature of 450° C. for one hour with a flow rate ratio of nitrogen gas and oxygen gas set to 4:1. By such a heat treatment including oxygen gas, impurities such as carbon, water, and hydrogen in the oxide film 230af and the oxide film 230bf can be reduced. By reducing the impurities in the film in this manner, the crystallinity of the oxide film 230af and the oxide film 230bf can be improved, and a denser and more compact structure can be obtained. This increases the crystalline region in the oxide film 230af and the oxide film 230bf, and reduces the in-plane variation of the crystalline region in the oxide film 230af and the oxide film 230bf. Therefore, the in-plane variation of the electrical characteristics of the transistor can be reduced.

[0239] Furthermore, by performing the heat treatment, hydrogen in the insulator 216, the insulating film 224f, the oxide film 230af, and the oxide film 230bf is absorbed into the insulator 222. In other words, hydrogen in the insulator 216, the insulating film 224f, the oxide film 230af, and the oxide film 230bf diffuses into the insulator 222. Therefore, the hydrogen concentration in the insulator 222 increases, but the hydrogen concentrations in the insulator 216, the insulating film 224f, the oxide film 230af, and the oxide film 230bf decrease. Note that by providing the insulator 221 in contact with the lower surface of the insulator 222, it is possible to prevent impurities such as moisture or hydrogen from entering from below the insulator 221 during the heat treatment.

[0240] In particular, the insulating film 224f (the future insulator 224) functions as a second gate insulator of the transistor 200, and the oxide film 230af and the oxide film 230bf (the future oxide 230a and the oxide 230b) function as a channel formation region of the transistor 200. The transistor 200 formed using the insulating film 224f, the oxide film 230af, and the oxide film 230bf in which the hydrogen concentrations are reduced has good reliability, which is preferable.

[0241] Next, a conductive film 242_1f is formed on the oxide film 230bf, and a conductive film 242_2f is formed on the conductive film 242_1f (see FIGS. 6A to 6D). The conductive film 242_1f may be a conductor corresponding to the conductors 242a1 and 242b1, and the conductive film 242_2f may be a conductor corresponding to the conductors 242a2 and 242b2. After the oxide film 230bf is formed, the conductive film 242_1f is formed on and in contact with the oxide film 230bf without an etching process or the like, so that the upper surface of the oxide film 230bf can be protected by the conductive film 242_1f. This can reduce diffusion of impurities into the oxide 230 that constitutes a transistor, thereby improving the electrical characteristics and reliability of the semiconductor device.

[0242] The conductive film 242_1f and the conductive film 242_2f can each be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0243] In this embodiment, tantalum nitride is formed as the conductive film 242_1f by a sputtering method, and tungsten is formed as the conductive film 242_2f. Note that heat treatment may be performed before the formation of the conductive film 242_1f. The heat treatment may be performed under reduced pressure, and the conductive film 242_1f may be formed in succession without exposure to air. By performing such treatment, moisture and hydrogen adsorbed on the surface of the oxide 230b can be removed, and the moisture and hydrogen concentrations in the oxide 230a and the oxide 230b can be further reduced. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower. In this embodiment, the temperature of the heat treatment is 250° C.

[0244] Next, the insulating film 271f is formed over the conductive film 242_1f (see FIGS. 6A to 6D). The insulating film 271f can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulating film 271f is preferably an insulating film having a function of suppressing oxygen permeation. For example, the insulating film 271f may be a stacked film of a silicon nitride film and a silicon oxide film on the silicon nitride film formed by a sputtering method.

[0245] Here, when the insulating film 271f is a laminated film, it is preferable to deposit the films successively without exposing them to the air environment. By depositing the films without exposing them to the air, the interface or the vicinity of the interface of the laminated film of the insulating film 271f can be kept clean. It is more preferable to deposit the films from the conductive film 242_1f to the insulating film 271f successively without exposing them to the air environment.

[0246] Note that heat treatment may be performed before the insulating film 271f is formed. The heat treatment may be performed under reduced pressure, and the insulating film 271f may be formed successively without exposure to air. By performing such treatment, moisture and hydrogen adsorbed on the surfaces of the conductive films 242_1f and 242_2f can be removed, and the moisture and hydrogen concentrations in the conductive films 242_1f and 242_2f can be reduced. The temperature of the heat treatment is preferably higher than or equal to 100° C. and lower than or equal to 400° C. In this embodiment, the temperature of the heat treatment is 250° C.

[0247] Next, the insulating film 224f, the oxide film 230af, the oxide film 230bf, the conductive film 242_1f, the conductive film 242_2f, and the insulating film 271f are processed into island shapes using lithography to form the insulator 224, the oxide 230a, the oxide 230b, the conductor 242_1, the conductor 242_2, and the insulator 271 (see Figures 7(A) to 7(D)).

[0248] The above processing can be performed using a dry etching method or a wet etching method. Processing using the dry etching method is suitable for fine processing. The insulating film 224f, the oxide film 230af, the oxide film 230bf, the conductive film 242_1f, the conductive film 242_2f, and the insulating film 271f may be processed under different conditions.

[0249] Here, it is preferable to process the insulator 224, the oxide 230a, the oxide 230b, the conductor 242_1, the conductor 242_2, and the insulator 271 into an island shape collectively. In this case, it is preferable that the side end of the conductor 242_1 and the side end of the conductor 242_2 coincide or approximately coincide with the side end of the oxide 230a and the oxide 230b. Furthermore, it is preferable that the side end of the insulator 224 coincide or approximately coincide with the side end of the oxide 230. Furthermore, it is preferable that the side end of the insulator 271 coincide or approximately coincide with the side end of the conductor 242_2. With such a structure, the number of steps for manufacturing a semiconductor device according to one embodiment of the present invention can be reduced. Therefore, a method for manufacturing a semiconductor device with high productivity can be provided.

[0250] The insulator 224, the oxide 230a, the oxide 230b, the conductor 242_1, the conductor 242_2, and the insulator 271 are formed to at least partially overlap with the conductor 205. The insulator 222 is exposed in a region where the insulator 222 does not overlap with the insulator 224, the oxide 230a, the oxide 230b, the conductor 242_1, the conductor 242_2, or the insulator 271.

[0251] 7(B), the side surfaces of the insulator 224, the oxide 230a, the oxide 230b, the conductor 242_1, the conductor 242_2, and the insulator 271 may be tapered. The taper angle of the side surfaces of the insulator 224, the oxide 230a, the oxide 230b, the conductor 242_1, the conductor 242_2, and the insulator 271 may be, for example, greater than or equal to 60° and less than 90°. By tapering the side surfaces in this manner, the coverage of the insulator 275 and the like can be improved in subsequent steps, and defects such as voids can be reduced.

[0252] Furthermore, without being limited to the above, the side surfaces of the insulator 224, the oxide 230a, the oxide 230b, the conductor 242_1, the conductor 242_2, and the insulator 271 may be perpendicular or approximately perpendicular to the top surface of the insulator 222. With such a configuration, it is possible to reduce the area and increase the density when providing multiple transistors.

[0253] In the lithography method, first, the resist is exposed through a mask. Next, the exposed area is removed or left using a developer to form a resist mask. Next, a conductor, a semiconductor, an insulator, or the like can be processed into a desired shape by etching through the resist mask. For example, a resist mask can be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like. Also, a liquid immersion technique may be used in which a liquid (e.g., water) is filled between the substrate and the projection lens and exposure is performed. Also, an electron beam or an ion beam may be used instead of the light described above. When an electron beam or an ion beam is used, a mask may not be used in some cases.

[0254] In addition, the resist mask that is no longer needed after processing can be removed by performing a dry etching process such as ashing using oxygen plasma (hereinafter sometimes referred to as oxygen plasma treatment), a wet etching process, a dry etching process followed by a wet etching process, or a wet etching process followed by a dry etching process.

[0255] Furthermore, a hard mask made of an insulator or a conductor may be used under the resist mask. When using a hard mask, an insulating film or a conductive film that will be the hard mask material is formed on the insulating film 271f, a resist mask is formed thereon, and the hard mask material is etched to form a hard mask of a desired shape. Etching of the insulating film 271f and the like may be performed after removing the resist mask, or may be performed while leaving the resist mask. In the latter case, the resist mask may disappear during etching. The hard mask may be removed by etching after etching of the oxide film 230bf and the like. On the other hand, if the material of the hard mask does not affect the subsequent process or can be used in the subsequent process, it is not necessarily necessary to remove the hard mask.

[0256] Also, a SOC (Spin On Carbon) film and a SOG (Spin On Glass) film may be formed between the workpiece and the resist mask. By using the SOC film and the SOG film as a mask, it is possible to improve adhesion with the resist mask and improve the durability of the mask pattern. For example, a SOC film, a SOG film, and a resist mask can be formed in this order on the workpiece, and then a lithography method can be performed.

[0257] As the etching gas for the dry etching process, an etching gas containing a halogen can be used, and specifically, an etching gas containing one or more of fluorine, chlorine, and bromine can be used. For example, as the etching gas, C4F6 gas, C5F6 gas, C4F8 gas, CF4 gas, SF6 gas, CHF3 gas, CH2F2 gas, Cl2 gas, BCl3 gas, SiCl4 gas, or BBr3 gas can be used alone or in a mixture of two or more gases. In addition, oxygen gas, carbon dioxide gas, nitrogen gas, helium gas, argon gas, hydrogen gas, or hydrocarbon gas can be appropriately added to the above etching gas. In addition, depending on the object to be processed in the dry etching process, a gas containing a hydrocarbon gas or hydrogen gas without containing a halogen gas can be used as the etching gas. As the hydrocarbon used in the etching gas, methane (CH4), ethane (C2H6), propane (C3H8), butane (C4H 10 ), ethylene (C2H4), propylene (C3H6), acetylene (C2H2), and propyne (C3H4) can be used. The etching conditions can be appropriately set according to the target to be etched.

[0258] As the dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes can be configured to apply a high frequency voltage to one of the parallel plate electrodes. Alternatively, it can be configured to apply a plurality of different high frequency voltages to one of the parallel plate electrodes. Alternatively, it can be configured to apply a high frequency voltage of the same frequency to each of the parallel plate electrodes. Alternatively, it can be configured to apply a high frequency voltage of different frequencies to each of the parallel plate electrodes. Alternatively, a dry etching apparatus having a high density plasma source can be used. As the dry etching apparatus having a high density plasma source, for example, an inductively coupled plasma (ICP) etching apparatus can be used. The etching apparatus can be appropriately set according to the object to be etched.

[0259] In addition, in the above etching step, the insulator 271 can function as an etching stopper that protects the conductor 242_2. For example, if a metal hard mask is formed on the insulator 271 in the above etching step, it may be difficult to obtain an etching selectivity with respect to the conductor 242_2 when removing the hard mask. However, by forming the insulator 271 on the conductor 242_2, the insulator 271 can function as an etching stopper that protects the conductor 242_2 in the etching process for removing the hard mask. This can prevent a curved surface from being formed between the side surface and the top surface of the conductor 242_2, so that the conductors 242a2 and 242b2 that are formed later have corner-shaped ends where the side surface and the top surface intersect. The corner-shaped ends where the side surface and the top surface of the conductor 242_2 intersect increase the cross-sectional area of ​​the conductor 242_2 compared to when the ends have a curved surface. Furthermore, excessive oxidation of the conductor 242_2 can be prevented by using a nitride insulator that does not easily oxidize metal for the insulator 271. This reduces the resistance of the conductor 242a2 and the conductor 242b2, thereby increasing the on-state current of the transistor.

[0260] Furthermore, by processing the insulator 224 into an island shape, insulator 275 can be provided in contact with the side surface of insulator 224 and the upper surface of insulator 222 in a process described below. That is, insulator 224 can be separated from insulator 280 by insulator 275. With this configuration, it is possible to prevent impurities such as excessive amounts of oxygen and hydrogen from being mixed into oxide 230 from insulator 280 via insulator 224.

[0261] Furthermore, by processing the insulator 224 into an island shape, when multiple transistors 200 are provided, the insulators 224 are provided with approximately the same size for each transistor 200. As a result, the amount of oxygen supplied from the insulator 224 to the oxide 230 in each transistor 200 becomes approximately the same. This makes it possible to suppress variation in the electrical characteristics of the transistors 200 within the substrate surface. However, this is not limited to the above, and the insulator 224 may be configured not to be patterned, similar to the insulator 222.

[0262] Next, the insulator 275 is formed to cover the insulator 224, the oxide 230a, the oxide 230b, the conductor 242_1, the conductor 242_2, and the insulator 271, and then the insulator 280 is formed over the insulator 275 (see FIGS. 8(A) to 8(D)). The insulators described above may be used as the insulators 275 and 280.

[0263] Here, it is preferable that the insulator 275 contacts the upper surface of the insulator 222 .

[0264] It is preferable to form an insulator having a flat upper surface as the insulator 280 by forming an insulating film to be the insulator 280 and performing a CMP process on the insulating film. Note that a silicon nitride film may be formed on the insulator 280 by, for example, a sputtering method, and the CMP process may be performed until the silicon nitride reaches the insulator 280.

[0265] Insulator 275 and insulator 280 can each be deposited using, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0266] It is preferable to use an insulator having a function of suppressing oxygen permeation for the insulator 275. For example, it is preferable to form a silicon nitride film as the insulator 275 by using a PEALD method. Alternatively, it is preferable to form an aluminum oxide film as the insulator 275 by using a sputtering method and then form a silicon nitride film thereon by using a PEALD method. By making the insulator 275 have the above structure, it is possible to improve the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen.

[0267] In this manner, the oxide 230a, the oxide 230b, the conductor 242_1, and the conductor 242_2 can be covered with the insulator 275 having a function of suppressing the diffusion of oxygen. This makes it possible to reduce the direct diffusion of oxygen from the insulator 280 to the insulator 224, the oxide 230a, the oxide 230b, the conductor 242_1, and the conductor 242_2 in a later process.

[0268] It is also preferable to form a silicon oxide film as the insulator 280 by a sputtering method. The insulating film to be the insulator 280 can be formed by a sputtering method in an atmosphere containing oxygen, so that the insulator 280 contains excess oxygen. The hydrogen concentration in the insulator 280 can be reduced by using a sputtering method that does not require the use of molecules containing hydrogen in the deposition gas. Note that a heat treatment may be performed before the deposition of the insulating film. The heat treatment may be performed under reduced pressure, and the insulating film may be deposited continuously without exposure to the air. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the insulator 275, etc., can be removed, and the moisture concentration and hydrogen concentration in the oxide 230a, the oxide 230b, and the insulator 224 can be further reduced. The heat treatment conditions described above can be used for the heat treatment.

[0269] The insulator 280 may have a laminated structure. For example, an insulator functioning as an etching stopper may be provided on the silicon oxide film. As the insulator functioning as an etching stopper, any insulator that can be used for the insulator 283 or the like may be used appropriately.

[0270] Next, the conductor 242_2, the insulator 271, the insulator 275, and the insulator 280 are processed by lithography to form openings reaching the conductor 242_1 and the insulator 222 (see FIGS. 9A to 9D). Here, the conductor 242_2 is divided to form the conductor 242a2 and the conductor 242b2, and the insulator 271 is divided to form the insulator 271a and the insulator 271b. The opening reaching the conductor 242_1 is formed in a region where the oxide 230b and the conductor 205 overlap. In a cross-sectional view of the transistor 200 in the channel length direction, the width of the opening is L1, which corresponds to the distance L1 between the conductor 242a2 and the conductor 242b2 shown in FIG. 2B. In other words, the width of the opening is greater than the distance L2 between the conductor 242a1 and the conductor 242b1 shown in FIG. 2B.

[0271] The lithography method can be appropriately used according to the above-mentioned methods. In order to finely process the openings in the insulator 280, it is preferable to use a lithography method using a short-wavelength light such as EUV light or an electron beam.

[0272] For example, a lithography method can be performed by forming an SOC film, an SOG film, and a resist mask in this order on the insulator 280. A resist mask having an opening is formed using short-wavelength light such as EUV light or an electron beam, and the SOG film, the SOC film, the insulator 280, the insulator 275, the insulator 271, and the conductor 242_2 are processed using the resist mask.

[0273] The above processing is preferably performed using a dry etching method. The dry etching method is capable of anisotropic etching, and is therefore suitable for forming an opening with a high aspect ratio and a width L1 as shown in FIG. 2(B). The above description can be referred to for the conditions of the dry etching method and the dry etching apparatus. Also, the etching processes of the SOG film, the SOC film, the insulator 280, the insulator 275, the insulator 271, and the conductor 242_2 may be performed under different conditions.

[0274] For example, CF4 can be used as an etching gas for etching an SOG film. For example, H2 and N2 can be used as an etching gas for etching an SOC film. For example, when silicon oxide is used for the insulator 280, C4F8, C4F6, O2, and Ar can be used as etching gases. For example, when silicon nitride is used for the insulator 275, CH2F2, O2, and Ar can be used as etching gases. For example, when a laminated film of silicon nitride and silicon oxide is used for the insulator 271, an etching process can be performed in an ICP etching device using CHF3 and O2 as etching gases.

[0275] Also, for example, when tungsten is used for the conductor 242_2 and tantalum nitride is used for the conductor 242_1, an etching process can be performed in an ICP etching device using CF4, Cl2, and O2 as etching gases. Here, the conductor 242_2 is etched so as to overlap an opening having a width L1 formed in the insulator 280 or the like, so that the distance between the divided conductors 242a2 and 242b2 is L1.

[0276] Here, in order to form the conductors 242a1 and 242b1 with a distance L2 between them below the conductors 242a2 and 242b2 in a later step, the etching process in this step needs to be stopped at the upper surface of the conductor 242_1. Therefore, in this step, the etching process is performed using an ICP etching device under conditions where the etching rate of the conductor 242_2 relative to the etching rate of the conductor 242_1 (hereinafter referred to as the etching selectivity of the conductor 242_2) is large.

[0277] By lowering the bias power applied to the lower electrode of the ICP etching apparatus, the ion incident energy can be reduced, and the etching rate of the conductor 242_1 can be reduced. For example, the bias power applied to the lower electrode of the ICP etching apparatus may be set to less than 50 W, preferably about 25 W or less. However, the present invention is not limited to this, and the bias power applied to the lower electrode of the ICP etching apparatus may be set to 50 W or more. By increasing the bias power, the recesses formed on the side surfaces of the conductor 242a2 and the conductor 242b2 can also be reduced. In this case, the bias power may be set to 100 W, for example.

[0278] In addition, by using CF4, Cl2, and O2 as the etching gas, the tungsten of the conductor 242_2 becomes a highly volatile reaction product such as WF6 or WOCl, and the etching rate of the conductor 242_2 increases. On the other hand, the tantalum nitride on the surface of the conductor 242_1 becomes a very low volatile reaction product such as tantalum oxide or tantalum oxynitride, and etching is suppressed. Therefore, it is preferable to increase the flow rate ratio of oxygen gas in the etching gas. For example, the flow rate ratio of oxygen gas in the etching gas may be set to 35% or more.

[0279] By performing the etching process on the conductor 242_2 under the above conditions, the conductor 242_1 can be divided into the conductor 242a2 and the conductor 242b2 without excessive etching. This allows processing to be performed as designed even in a semiconductor device having a fine structure.

[0280] The SOC film may be removed by performing a dry etching process such as ashing using oxygen plasma, a wet etching process, a dry etching process followed by a wet etching process, or a wet etching process followed by a dry etching process.

[0281] In addition, the processing of the insulator 271 and the conductor 242_2, and the removal of the SOC film can be performed successively without exposure to the outside air. For example, a multi-chamber etching apparatus may be used to perform the processing without exposure to the outside air.

[0282] In the manner described above, the conductor 242_2, the insulator 271, the insulator 275, and the insulator 280 can be processed to form an opening with a width L1.

[0283] Next, an insulating film 255A is formed to cover the insulator 280, the conductor 242_1, and the insulator 222 (see FIGS. 10A to 10D). The insulating film 255A is an insulating film that will become the insulator 255 in a later process, and the above-mentioned nitride insulators, or the like, can be used. The insulating film 255A can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0284] Since the insulating film 255A is formed along the openings formed in the conductor 242a2, the conductor 242b2, the insulator 271, the insulator 275, and the insulator 280, it is preferable that the insulating film 255A has good coverage. Therefore, it is preferable that the insulating film 255A is formed using an ALD method or the like that has good coverage. For example, it is preferable that the insulating film 255A is formed of silicon nitride using the PEALD method.

[0285] Next, the insulating film 256A is deposited over the insulating film 255A (see FIGS. 10A to 10D). The insulating film 256A can be formed using an oxide insulator that can be used for the insulator 250b or the like. The insulating film 256A can be deposited by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0286] The insulating film 256A, like the insulating film 255A, is formed along the openings formed in the conductor 242a2, the conductor 242b2, the insulator 271, the insulator 275, and the insulator 280, and therefore preferably has good coverage. Therefore, the insulating film 256A is preferably formed using an ALD method or the like that has good coverage. For example, it is preferable to form a silicon oxide film as the insulating film 256A using the PEALD method. Note that the formation of the insulating film 255A and the formation of the insulating film 256A can be performed consecutively without exposure to the outside air. For example, a multi-chamber type film forming apparatus may be used to perform the process without exposure to the outside air.

[0287] Next, a part of the insulating film 255A and the insulating film 256A is removed by anisotropic etching to form the sidewall-shaped insulators 255 and 256 in contact with the side walls of the openings (see FIGS. 11(A) to 11(D)). As a result, the insulator 255 is formed in contact with the side surface of the insulator 280, the side surface of the insulator 275, the side surface of the insulator 271a, the side surface of the insulator 271b, the side surface of the conductor 242a2, the side surface of the conductor 242b2, the upper surface of the conductor 242_1, and the upper surface of the insulator 222. As shown in FIGS. 11(B) and 11(C), a protruding portion is formed in a portion of the insulator 255 in contact with the upper surface of the conductor 242_1 or the upper surface of the insulator 222. The protruding portion of the insulator 255 has a shape that protrudes toward the center of the opening formed in the insulator 280 or the like more than other portions. That is, the insulator 255 has a so-called L-shape when viewed in cross section in the channel length direction.

[0288] 11(B) and 11(C), the lower surface of the insulator 256 contacts the upper surface of the protruding portion of the insulator 255, and one side surface of the insulator 256 contacts the side surface of the insulator 255. In addition, the other side surface of the insulator 256 is formed to coincide or approximately coincide with the end of the protruding portion of the insulator 255 in a top view.

[0289] In a cross-sectional view in the channel length direction, the insulators 255 and 256 are formed in an opening with a width L1, so if the distance between the insulator 256 on the A1 side and the insulator 256 on the A2 side is L2, L2 is shorter than L1. Here, the distance L2 can also be considered as the distance between the end of the protruding portion of the insulator 255 on the A1 side and the end of the protruding portion of the insulator 255 on the A2 side.

[0290] It is preferable to use a dry etching method for anisotropic etching of the insulating film 255A and the insulating film 256A. The above description can be referred to for the conditions of the dry etching method and the dry etching apparatus. For example, when silicon nitride is used for the insulating film 255A and silicon oxide is used for the insulating film 256A, the etching process can be performed in an ICP etching apparatus using CHF3 and O2 as etching gases.

[0291] Furthermore, in etching the insulating film 255A and the insulating film 256A, the generated ions may collide with the corners of the edges of the openings of the insulator 280 and the insulator 255. As a result, the corners may be polished to a tapered shape as shown in Fig. 4(C) etc. For example, the corners can be easily removed by including an easily ionized gas such as argon in the etching gas or by applying a bias voltage to the electrode on the substrate side.

[0292] Next, the portions of the conductor 242_1 exposed from the insulator 255 and the insulator 256 are removed by anisotropic etching to form the conductor 242a1 and the conductor 242b1 (see FIGS. 12A to 12D). In other words, the conductor 242_1 is processed using the insulators 255 and 256 as masks, and the conductor 242_1 is divided into the conductor 242a1 and the conductor 242b1. By processing the conductor 242_1 using the insulators 255 and 256 as masks in this manner, the end of the protruding portion of the insulator 255 is formed to coincide or approximately coincide with the side end of the conductor 242a1 and the side end of the conductor 242b1 in a cross-sectional view of the transistor 200. As a result, the distance between the conductor 242a1 and the conductor 242b1 also becomes L2 in a cross-sectional view in the channel length direction.

[0293] For the anisotropic etching, it is preferable to use a dry etching method. The above description can be referred to for the conditions of the dry etching method and the dry etching apparatus. For example, when tantalum nitride is used for the conductor 242_1, the etching process can be performed in an ICP etching apparatus using Cl2 and Ar as etching gas.

[0294] As described above, by forming the insulator 255 and the insulator 256 over the conductor 242_1 by using anisotropic etching and dividing the conductor 242_1 using the insulator 255 and the insulator 256 as a mask, the insulator 255 and the insulator 256 functioning as a mask can be formed in a self-aligned manner. As a result, the number of masks and the number of steps can be reduced in the manufacturing process of the semiconductor device described in this embodiment. Therefore, a highly productive method for manufacturing a semiconductor device can be provided.

[0295] In addition, by using the above method, the island-shaped oxide 230 can be exposed to a dry etching atmosphere only when the conductor 242_1 is processed. In other words, the upper surface of the island-shaped oxide 230 can be prevented from being exposed to a dry etching atmosphere when the insulator 255 and the insulator 256 are formed. This can reduce damage (e.g., damage due to ion collision) caused by dry etching to the oxide 230b that functions as a channel formation region of the transistor 200. In the dry etching process of the conductor 242_1, the bias power can be lowered halfway through to further reduce damage to the oxide 230. However, as shown in FIG. 4(A), a recess may be formed in a portion of the oxide 230 exposed from the conductor 242a1 and the conductor 242b1.

[0296] After processing the conductor 242_1, an ashing process using oxygen plasma may be performed. By performing such an oxygen plasma process, impurities generated in the above etching process and diffused into the oxide 230, etc. can be removed. The impurities include those originating from components contained in the workpiece of the above etching process and components contained in the gas used in the etching process. For example, chlorine, fluorine, tantalum, silicon, hafnium, etc. can be included. In particular, as shown in the above etching process, if chlorine gas is used in processing the conductor 242_1, the oxide 230 is exposed to an atmosphere containing chlorine gas, so it is preferable to remove the chlorine attached to the oxide 230. By removing the impurities attached to the oxide 230 in this manner, the electrical characteristics and reliability of the transistor can be improved.

[0297] Furthermore, by performing the oxygen plasma treatment, at least a part of the insulator 255 may be oxidized. In other words, the insulator 255 may contain oxygen. In this case, a region with a high oxygen concentration is observed in the insulator 255 by performing a composition analysis on the insulator 255 using SIMS or the like. Note that as the oxidation of the insulator 255 progresses, at least a part of the insulator 255 may become silicon oxynitride or silicon nitride oxide after the transistor 200 is formed.

[0298] The processing of the insulating film 255A, the insulating film 256A, and the conductor 242_1 and the oxygen plasma treatment can be performed successively without exposure to the outside air. For example, the processing can be performed by using a multi-chamber etching apparatus without exposure to the outside air.

[0299] Next, it is preferable to perform isotropic etching to selectively remove the insulator 256 (see FIGS. 13A to 13D). As the isotropic etching, for example, a wet etching method may be used. Here, in the isotropic etching, it is preferable that the etching rate of the insulator 256 is sufficiently higher than the etching rate of the insulator 255. Furthermore, it is preferable that the etching rate of the insulator 256 is sufficiently higher than the etching rate of the oxide 230.

[0300] By performing isotropic etching as described above, it is possible to remove the insulator 256 and leave the insulator 255. As a result, in an opening formed in the insulator 280 or the like, the protruding portion of the insulator 255, a part of the conductor 242a1, and a part of the conductor 242b1 are formed so as to protrude.

[0301] As described above, by forming the insulator 280 into a layered structure and forming a film of an insulator that functions as an etching stopper on the upper surface, the upper surface of the insulator 280 can be prevented from being etched in the above-mentioned isotropic etching.

[0302] Although the above describes an example in which the insulator 256 is removed after the conductor 242_1 is processed, the present invention is not limited thereto. For example, after the insulator 255 and the insulator 256 are formed, the insulator 256 can be removed by isotropic etching, and then the conductor 242_1 can be processed. This can prevent the upper surface of the oxide 230b from being exposed to the isotropic etching of the insulator 256. Therefore, damage (e.g., damage by an etchant) that the oxide 230b that functions as a channel formation region of the transistor 200 receives due to the isotropic etching can be reduced. Note that when the insulator 255 and the insulator 256 are formed, the insulator 255 is formed in an L-shape in a cross-sectional view, and therefore the conductor 242_1 may be processed using the L-shaped insulator 255 as a mask.

[0303] In this manner, the oxidation-resistant conductors 242a1 and 242b1 are formed under the conductive conductors 242a2 and 242b2, and the oxidation-resistant insulator 255 is formed in contact with the side surfaces of the conductive conductors 242a2 and 242b2. With this configuration, the conductive conductors 242a2 and 242b2, which have good conductivity, can be used as the source electrode and drain electrode of the transistor 200, so that the frequency characteristics of the transistor 200 and the operating speed of the semiconductor device can be improved. In addition, the conductive conductors 242a1 and 242b1 can be formed to protrude from the conductive conductors 242a2 and 242b2 to the same extent as the protruding portion of the insulator 255, so that the distance between the source and drain can be shortened and the channel length can be shortened accordingly. Therefore, the on-current of the transistor 200 can be increased, the S value can be reduced, and the frequency characteristics can be improved.

[0304] In addition, a cleaning process may be performed to remove impurities that have adhered to the surface of the oxide 230b in the etching process. The cleaning method may be a wet cleaning using a cleaning solution (also called a wet etching process), a plasma process using plasma, or a heat treatment, and the above cleaning methods may be combined as appropriate. Note that the cleaning process may deepen the grooves.

[0305] The wet cleaning may be performed using an aqueous solution of one or more of ammonia water, oxalic acid, phosphoric acid, and hydrofluoric acid diluted with carbonated water or pure water, pure water, carbonated water, etc. Alternatively, ultrasonic cleaning may be performed using these aqueous solutions, pure water, or carbonated water. Alternatively, these cleaning methods may be combined as appropriate.

[0306] 11(C), as shown in FIG. 14(A), in a cross-sectional view in the channel width direction, a part of the insulator 255 may be formed in contact with a side surface of the insulator 224, a side surface of the oxide 230, a side surface of the conductor 242_1, and an upper surface of the insulator 222, and an insulator 256 may be formed on the insulator 255. In this case, as shown in FIG. 14(B), in a cross-sectional view in the channel width direction, in a process related to FIG. 13(C), as shown in FIG. 14(B), in a cross-sectional view in the channel width direction, a part of the insulator 255 may be formed in contact with a side surface of the insulator 224, a side surface of the oxide 230, a side surface of the conductor 242_1, and an upper surface of the insulator 222. Furthermore, as shown in FIG. 14(C), in the transistor 200, a part of the insulator 255 may be formed in contact with a side surface of the oxide 230 and a side surface of the insulator 224. At this time, in the transistor 200, the insulator 250 is not in contact with a side surface of the oxide 230 and a side surface of the insulator 224.

[0307] In this specification, an aqueous solution of hydrofluoric acid diluted with pure water may be called diluted hydrofluoric acid, and an aqueous solution of ammonia water diluted with pure water may be called diluted ammonia water. The concentration and temperature of the aqueous solution are appropriately adjusted depending on the impurities to be removed and the configuration of the semiconductor device to be cleaned. The ammonia concentration of the diluted ammonia water is preferably 0.01% to 5%, more preferably 0.1% to 0.5%. The hydrogen fluoride concentration of the diluted hydrofluoric acid is preferably 0.01 ppm to 100 ppm, more preferably 0.1 ppm to 10 ppm.

[0308] In addition, for ultrasonic cleaning, a frequency of 200 kHz or more is preferably used, and a frequency of 900 kHz or more is more preferably used. By using such a frequency, damage to the oxide 230b and the like can be reduced.

[0309] The above cleaning process may be performed multiple times, and the cleaning solution may be changed for each cleaning process. For example, a first cleaning process may be performed using diluted hydrofluoric acid or diluted ammonia water, and a second cleaning process may be performed using pure water or carbonated water.

[0310] In the present embodiment, the cleaning process is performed by wet cleaning using diluted ammonia water. By performing the cleaning process, impurities attached to the surfaces of the oxides 230a, 230b, etc. or diffused inside the oxides 230a, 230b, etc. can be removed. Furthermore, the crystallinity of the oxides 230a, 230b, etc. can be improved.

[0311] It is preferable to perform a heat treatment after the etching or cleaning. The temperature of the heat treatment is preferably 100°C or more, 250°C or more, or 350°C or more, and 650°C or less, 600°C or less, 550°C or less, or 400°C or less. The heat treatment is performed in an atmosphere of nitrogen gas or inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. The heat treatment is preferably performed in an atmosphere containing oxygen, for example, at a flow rate ratio of nitrogen gas to oxygen gas of 4:1 and at a temperature of 350°C for 1 hour. This allows oxygen to be supplied to the oxide 230a and the oxide 230b, thereby reducing oxygen deficiency. In addition, by performing such a heat treatment, the crystallinity of the oxide 230b can be improved. Furthermore, the supplied oxygen reacts with hydrogen remaining in the oxide 230a and the oxide 230b, and the hydrogen can be removed as H2O (dehydrated). As a result, hydrogen remaining in the oxide 230a and the oxide 230b is recombined with the oxygen vacancies to form V O It is possible to suppress the formation of H. This can improve the electrical characteristics of the transistor provided with the oxide 230 and improve reliability. In addition, it is possible to suppress variation in the electrical characteristics of a plurality of transistors formed on the same substrate. Note that the heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in an oxygen atmosphere, the heat treatment may be performed continuously in a nitrogen atmosphere without exposure to the air. Note that, although an example in which the heat treatment is performed after the removal of the insulator 256 is described in this embodiment, the present invention is not limited to this. It is also possible to adopt a configuration in which the insulator 256 is removed after the heat treatment.

[0312] As described above, the insulator 255 having an inorganic insulator that is difficult to oxidize is provided in contact with the side surface of the conductor 242a2 and the side surface of the conductor 242b2. This makes it possible to prevent the conductors 242a2 and 242b2 from being excessively oxidized by the heat treatment, even if the conductors 242a2 and 242b2 are made of a tungsten film that is relatively easily oxidized.

[0313] When a heat treatment is performed while the conductor 242a and the conductor 242b are in contact with the oxide 230b, the sheet resistance may decrease in the region of the oxide 230b overlapping with the conductor 242a and the region of the oxide 230b overlapping with the conductor 242b. The carrier concentration may also increase. Therefore, the resistance of the region of the oxide 230b overlapping with the conductor 242a and the region of the oxide 230b overlapping with the conductor 242b can be reduced in a self-aligned manner.

[0314] Next, an insulating film 250A to become the insulator 250 is formed so as to fill the openings formed in the insulator 280 and the like (see FIGS. 15(A) to 15(D)). Here, the insulating film 250A contacts the insulator 280, the insulator 255, the conductor 242a1, the conductor 242b1, the insulator 222, the insulator 224, the oxide 230a, and the oxide 230b. Note that in the openings formed in the insulator 280 and the like, the protruding portion of the insulator 255, a part of the conductor 242a1, and a part of the conductor 242b1 are formed so as to protrude, so that the shape of the insulating film 250A reflects the shapes of the protruding portion of the insulator 255, a part of the conductor 242a1, and a part of the conductor 242b1.

[0315] The insulating film 250A can be formed by sputtering, CVD, MBE, PLD, or ALD. For example, the insulating film 250A is preferably formed by ALD. As with the insulator 250 described above, the insulating film 250A is preferably formed to a thin thickness, and it is necessary to reduce the variation in thickness. In contrast, the ALD method is a film formation method in which a precursor and a reactant (e.g., an oxidizing agent) are alternately introduced, and the thickness can be adjusted by the number of times this cycle is repeated, so that precise thickness adjustment is possible. In addition, the insulating film 250A needs to be formed with good coverage on the bottom and side surfaces of the opening. By using the ALD method, layers of atoms can be deposited one by one on the bottom and side surfaces of the opening, so that the insulating film 250A can be formed with good coverage on the opening.

[0316] In addition, when the insulating film 250A is formed by the ALD method, ozone (O3), oxygen (O2), water (H2O), etc. can be used as an oxidizing agent. By using ozone (O3), oxygen (O2), etc. that do not contain hydrogen as an oxidizing agent, the amount of hydrogen that diffuses into the oxide 230b can be reduced.

[0317] The insulator 250 can have a laminated structure as shown in FIG. 2(A) and the like. Hereinafter, a method for forming an insulating film 250A when the insulator 250 has a three-layer structure of an insulator 250a, an insulator 250b, and an insulator 250c, similar to FIG. 2(A), will be described with reference to FIG. 16(A) to FIG. 16(C). In FIG. 16(A) to FIG. 16(C), the insulating film 250A has an insulating film 250Aa, an insulating film 250Ab on the insulating film 250Aa, and an insulating film 250Ac on the insulating film 250Ab.

[0318] First, an insulating film 250Aa serving as the insulator 250a is formed so as to fill an opening formed in the insulator 280 or the like, and then an insulating film 250Ab is formed on the insulating film 250Aa (see FIG. 16(A)). In this embodiment, an aluminum oxide film is formed as the insulating film 250Aa by a thermal ALD method, and a silicon oxide film is formed as the insulating film 250Ab by a PEALD method.

[0319] Next, it is preferable to perform microwave treatment in an atmosphere containing oxygen (see FIG. 16(B)). Here, microwave treatment refers to treatment using, for example, an apparatus having a power source that generates high-density plasma using microwaves. In addition, in this specification and the like, microwave refers to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less.

[0320] In the microwave treatment, it is preferable to use a microwave treatment device having a power source that generates high-density plasma using microwaves. Here, the frequency of the microwave treatment device is preferably 300 MHz or more and 300 GHz or less, more preferably 2.4 GHz or more and 2.5 GHz or less, and can be, for example, 2.45 GHz. By using high-density plasma, high-density oxygen radicals can be generated. In addition, the power of the power source that applies microwaves of the microwave treatment device is preferably 1000 W or more and 10000 W or less, more preferably 2000 W or more and 5000 W or less. In addition, the microwave treatment device may have a power source that applies RF to the substrate side. In addition, by applying RF to the substrate side, oxygen ions generated by high-density plasma can be efficiently guided into the oxide 230b.

[0321] The microwave treatment is preferably carried out under reduced pressure, and the pressure is preferably 10 Pa to 1000 Pa, and more preferably 300 Pa to 700 Pa. The treatment temperature is preferably 750° C. or less, more preferably 500° C. or less, and can be, for example, about 250° C. After the oxygen plasma treatment, a heat treatment may be carried out continuously without exposure to the outside air. The temperature of the heat treatment is, for example, preferably 100° C. to 750° C., and more preferably 300° C. to 500° C.

[0322] Also, for example, the microwave treatment can be performed using oxygen gas and argon gas. Here, the oxygen flow ratio (O2 / (O2+Ar)) is greater than 0% and less than 100%. Preferably, the oxygen flow ratio (O2 / (O2+Ar)) is greater than 0% and less than 50%. More preferably, the oxygen flow ratio (O2 / (O2+Ar)) is greater than 10% and less than 40%. More preferably, the oxygen flow ratio (O2 / (O2+Ar)) is greater than 10% and less than 30%. In this way, by performing the microwave treatment in an atmosphere containing oxygen, the carrier concentration in the oxide 230b can be reduced. Also, by preventing an excessive amount of oxygen from being introduced into the chamber in the microwave treatment, the carrier concentration in the oxide 230b can be prevented from being excessively reduced.

[0323] By performing microwave processing in an atmosphere containing oxygen, oxygen gas can be turned into plasma using microwaves or high frequency waves such as RF, and the oxygen plasma can be applied to the region of the oxide 230b between the conductors 242a and 242b. O H can be split into oxygen vacancies and hydrogen, and the hydrogen can be removed from the region. Here, when forming the structure shown in FIG. 2(A) or the like, it is preferable to use an insulating film (such as aluminum oxide) having a function of capturing or fixing hydrogen as the insulating film 250Aa. With such a configuration, hydrogen generated by microwave treatment can be captured or fixed by the insulating film 250Aa. In this way, V included in the channel formation region can be removed. O As a result, oxygen vacancies in the channel formation region and V O By supplying oxygen radicals generated by the oxygen plasma to the oxygen vacancies formed in the channel formation region, the oxygen vacancies in the channel formation region can be further reduced, and the carrier concentration can be reduced.

[0324] The oxygen injected into the channel formation region can be in various forms, such as oxygen atoms, oxygen molecules, oxygen ions, and oxygen radicals (also called O radicals, which are atoms, molecules, or ions with an unpaired electron). The oxygen injected into the channel formation region may be in one or more of the above forms, and is particularly preferably in the form of oxygen radicals. In addition, the film quality of the insulator 250 can be improved, thereby improving the reliability of the transistor.

[0325] On the other hand, the oxide 230b has a region that overlaps with either the conductors 242a or 242b. This region can function as a source region or a drain region. Here, the conductors 242a and 242b preferably function as a shielding film against the action of microwaves, high frequencies such as RF, oxygen plasma, etc., when performing microwave processing in an atmosphere containing oxygen. For this reason, the conductors 242a and 242b preferably have a function of shielding electromagnetic waves of 300 MHz or more and 300 GHz or less, for example, 2.4 GHz or more and 2.5 GHz or less.

[0326] The conductors 242a, 242b shield the effects of microwaves, high frequency waves such as RF, oxygen plasma, etc., so that these effects do not extend to the areas of the oxide 230b that overlap with either of the conductors 242a, 242b. This allows the microwave treatment to reduce the V O Since there is no reduction in H and no excessive supply of oxygen, a decrease in the carrier concentration can be prevented.

[0327] Moreover, an insulator 255 having a barrier property against oxygen is provided in contact with the side surfaces of the conductors 242a2 and 242b2. Furthermore, an insulating film 250Aa and an insulating film 250Ab are provided to cover the conductors 242a1 and 242b1 and the insulator 255. This makes it possible to suppress the formation of an oxide film on the side surfaces of the conductors 242a and 242b by microwave processing.

[0328] In this manner, oxygen vacancies and V OBy removing H, the channel formation region can be made i-type or substantially i-type. Furthermore, the supply of excess oxygen to the region that functions as the source region or drain region can be suppressed, and the conductivity (state of being a low resistance region) before the microwave treatment can be maintained. This suppresses fluctuations in the electrical characteristics of the transistor, and suppresses variations in the electrical characteristics of the transistor within the substrate surface.

[0329] In addition, in the microwave treatment, thermal energy may be directly transferred to the oxide 230b due to electromagnetic interaction between the microwaves and the molecules in the oxide 230b. The oxide 230b may be heated by this thermal energy. Such a heating treatment may be called microwave annealing. By performing the microwave treatment in an atmosphere containing oxygen, an effect equivalent to that of oxygen annealing may be obtained. In addition, if the oxide 230b contains hydrogen, it is considered that the thermal energy is transferred to the hydrogen in the oxide 230b, and the activated hydrogen is released from the oxide 230b.

[0330] Furthermore, by modifying the film quality of the insulating film 250Aa and the insulating film 250Ab by microwave processing, it is possible to suppress the diffusion of hydrogen, water, impurities, etc. Therefore, it is possible to suppress the diffusion of hydrogen, water, impurities, etc. into the oxide 230b, the oxide 230a, etc. through the insulator 250 by a post-process such as the deposition of a conductive film that becomes the conductor 260, or a post-process such as heat treatment. In this way, by improving the film quality of the insulator 250, it is possible to improve the reliability of the transistor.

[0331] Next, an insulating film 250Ac is formed on the insulating film 250Ab (see FIG. 16C). In this embodiment, silicon nitride is formed as the insulating film 250Ac by the PEALD method. In this manner, the insulating film 250A having the insulating films 250Aa to 250Ac can be formed.

[0332] In the above, an example in which the microwave treatment is performed after the insulating film 250Ab is formed has been shown, but the present invention is not limited to this. It is also possible to configure the microwave treatment to be performed after the insulating film 250Ac is formed. Alternatively, it is also possible to configure the microwave treatment to be performed before the insulating film 250Aa is formed.

[0333] Also, a heat treatment may be performed while maintaining the reduced pressure state after the microwave treatment. By performing such a treatment, hydrogen in the insulating film, the oxide 230b, and the oxide 230a can be efficiently removed. Also, some of the hydrogen may be gettered to the conductors 242a and 242b. Alternatively, a step of performing a heat treatment may be repeated multiple times while maintaining the reduced pressure state after the microwave treatment. By repeatedly performing the heat treatment, hydrogen in the insulating film, the oxide 230b, and the oxide 230a can be more efficiently removed. The heat treatment temperature is preferably 300° C. or more and 500° C. or less. Also, the microwave treatment, i.e., microwave annealing, may serve as the heat treatment. If the oxide 230b, etc. is sufficiently heated by microwave annealing, the heat treatment may not be performed.

[0334] In addition, as shown in FIG. 3(A), when the insulator 250 is made to have a laminated structure of the insulator 250a and the insulator 250c, the insulating film 250Ab may not be formed in the above process. In addition, as shown in FIG. 3(B), when the insulator 250 is made to have a laminated structure of the insulator 250a, the insulator 250b, the insulator 250c, and the insulator 250d, after the microwave treatment in FIG. 16(B), an insulating film to be the insulator 250d may be formed, and then another microwave treatment may be performed to form the insulating film 250Ac. Here, hafnium oxide may be formed by the thermal ALD method as the insulating film to be the insulator 250d. In this way, the microwave treatment in an atmosphere containing oxygen may be performed multiple times (at least two times or more).

[0335] Next, a conductive film 260A to be the conductor 260a and a conductive film 260B to be the conductor 260b are sequentially formed (see FIGS. 17A to 17D). The conductive film 260A and the conductive film 260B can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, a plating method, or an ALD method. In this embodiment, titanium nitride is formed as the conductive film 260A by the ALD method, and tungsten is formed as the conductive film 260B by the CVD method.

[0336] Next, the insulating film 250A, the conductive film 260A, and the conductive film 260B are polished by CMP until the insulator 280 is exposed. That is, the portions of the insulating film 250A, the conductive film 260A, and the conductive film 260B exposed from the openings are removed. As a result, the insulator 250 and the conductor 260 (the conductor 260a and the conductor 260b) are formed in the openings overlapping with the conductor 205 (see FIGS. 18(A) to 18(D)).

[0337] As a result, the insulator 250 is provided in the opening in contact with the insulator 255, the conductor 242a1, the conductor 242b1, the oxide 230, the insulator 224, and the insulator 222. The conductor 260 is also arranged to fill the opening via the insulator 250. In this manner, the transistor 200 is formed.

[0338] As described above, when the insulator 280 has a laminated structure and an insulator functioning as an etching stopper is provided on the upper surface, it is preferable to remove the insulator functioning as an etching stopper by the CMP process. This makes it possible to prevent the insulator functioning as an etching stopper from hindering the addition of oxygen when oxygen is added to the insulator 280 in a later process.

[0339] Next, the insulator 282 is formed over the insulator 255, the insulator 250, the conductor 260, and the insulator 280. The insulator 282 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The insulator 282 is preferably formed by a sputtering method. By using a sputtering method that does not require the use of molecules containing hydrogen in the deposition gas, the hydrogen concentration in the insulator 282 can be reduced.

[0340] Furthermore, by forming the insulator 282 in an oxygen-containing atmosphere using a sputtering method, oxygen can be added to the insulator 280 while the insulator 282 is being formed. This allows the insulator 280 to contain excess oxygen. At this time, it is preferable to form the insulator 282 while heating the substrate. Here, by oxidizing a portion of the insulator 255 as described above, oxygen supplied to the insulator 280 can be diffused to the oxide 230b through the insulator 255 and the insulator 250, and an appropriate amount of oxygen can be supplied to the oxide 230b.

[0341] In this embodiment, an aluminum oxide film is formed as the insulator 282 by a sputtering method using an aluminum target in an atmosphere containing oxygen gas. The amount of oxygen injected into the layer below the insulator 282 can be controlled by the magnitude of the RF power applied to the substrate by the sputtering method. For example, the smaller the RF power, the smaller the amount of oxygen injected into the layer below the insulator 282, and the amount of oxygen is likely to be saturated even if the film thickness of the insulator 282 is thin. Also, the larger the RF power, the larger the amount of oxygen injected into the layer below the insulator 282. By reducing the RF power, the amount of oxygen injected into the insulator 280 can be suppressed. Also, the insulator 282 may be formed in a two-layer laminate structure. At this time, for example, the lower layer of the insulator 282 is formed without applying RF power to the substrate, and the upper layer of the insulator 282 is formed by applying RF power to the substrate.

[0342] The RF frequency is preferably 10 MHz or more, typically 13.56 MHz. The higher the RF frequency, the less damage can be caused to the substrate.

[0343] Furthermore, heat treatment may be performed before the formation of the insulator 282. The heat treatment may be performed under reduced pressure, and the insulator 282 may be formed successively without exposure to air. By performing such treatment, moisture and hydrogen adsorbed on the surface of the insulator 280 can be removed and the moisture and hydrogen concentrations in the insulator 280 can be further reduced. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower. In this embodiment, the temperature of the heat treatment is 250° C.

[0344] Next, the insulator 283 is formed over the insulator 282. The insulator 283 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The insulator 283 is preferably formed by a sputtering method. By using a sputtering method that does not require the use of molecules containing hydrogen in the deposition gas, the hydrogen concentration in the insulator 283 can be reduced. In this embodiment, silicon nitride is formed as the insulator 283 by a sputtering method.

[0345] Here, it is preferable to successively form the insulators 282 and 283 without exposing them to the air environment. By forming the films without exposing them to the air, impurities or moisture from the air environment can be prevented from adhering to the insulators 282 and 283, and the interface or the vicinity of the interface between the insulators 282 and 283 can be kept clean.

[0346] After the insulator 283 is formed, a heat treatment may be performed. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower. By performing the heat treatment, hydrogen contained in the insulator 280, the insulator 250, and the oxide 230 is absorbed into the insulator 282. In other words, hydrogen contained in the insulator 280, the insulator 250, and the oxide 230 diffuses into the insulator 282. Therefore, the hydrogen concentration in the insulator 282 increases, but the hydrogen concentrations in the insulator 280, the insulator 250, and the oxide 230 decrease. By providing the insulator 283 in contact with the upper surface of the insulator 282, impurities such as moisture or hydrogen can be prevented from entering from above the insulator 283 during the heat treatment. By performing the heat treatment, hydrogen contained in the insulator 216, the insulator 224, and the oxide 230 is absorbed into the insulator 222. In other words, hydrogen contained in the insulator 216, the insulator 224, and the oxide 230 diffuses into the insulator 222. Therefore, the hydrogen concentration in the insulator 222 increases, but the hydrogen concentrations in the insulator 216, the insulator 224, and the oxide 230 decrease. By providing the insulator 221 in contact with the lower surface of the insulator 222, impurities such as moisture or hydrogen can be prevented from entering from below the insulator 221 during the heat treatment.

[0347] In this manner, the semiconductor device shown in FIG. 1 can be manufactured.

[0348] In the semiconductor device according to this embodiment, a conductor on an oxide semiconductor has a two-layer structure, in which a conductor that is difficult to oxidize is used in the lower layer and a conductor with high conductivity is used in the upper layer, so that a conductor that functions as an electrode or a wiring is provided in contact with the upper surface of the oxide semiconductor. The conductor functions as a source electrode and a drain electrode of an OS transistor. In the semiconductor device according to this embodiment, the distance between the conductors in the lower layer of the source electrode and the drain electrode is made shorter than the distance between the conductors in the upper layer of the source electrode and the drain electrode, and miniaturization is achieved, so that the frequency characteristics and the operating speed of the semiconductor device can be improved. In addition, in the semiconductor device according to this embodiment, an insulator that functions as a protective film is provided in contact with the side surface of the conductor in the upper layer of the source electrode and the drain electrode. This makes it possible to suppress excessive oxidation of the upper layers of the source electrode and the drain electrode.

[0349] The semiconductor device according to this embodiment has an OS transistor. Since the off-state current of the OS transistor is small, a semiconductor device or memory device with low power consumption can be realized. Furthermore, since the OS transistor has high frequency characteristics, a semiconductor device or memory device with high operation speed can be realized. Furthermore, by using an OS transistor, a semiconductor device with favorable electrical characteristics, a semiconductor device with little variation in the electrical characteristics of transistors, a semiconductor device with large on-state current, and a highly reliable semiconductor device or memory device can be realized.

[0350] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in the case where a plurality of configuration examples are shown in one embodiment mode in this specification, the configuration examples can be combined as appropriate.

[0351] (Embodiment 2) In this embodiment, a comparison between the OS transistor described in the above embodiment and a transistor having silicon in a channel formation region (also referred to as a Si transistor) will be described.

[0352] [OS transistor] For the OS transistor, an oxide semiconductor with a low carrier concentration is preferably used. For example, the carrier concentration of a channel formation region of the oxide semiconductor is 1×10 18 cm -3 Less than or equal to 1×10 17 cm -3 less than 1×10 16 cm -3 less than 1×10 13 cm -3 less than 1×10 10 cm -3 Less than 1 x 10 -9 cm -3 The above is the case. Note that in order to reduce the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, an oxide semiconductor having a low impurity concentration and a low density of defect states is referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may be referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.

[0353] In addition, a highly-purified intrinsic or substantially highly-purified intrinsic oxide semiconductor may have a low density of trap states because of its low density of defect states. In addition, charges trapped in the trap states of the oxide semiconductor take a long time to disappear and may behave as if they were fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0354] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in a nearby film. Examples of impurities include hydrogen and nitrogen. Note that an impurity in an oxide semiconductor refers to, for example, any element other than the main component constituting the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0355] In addition, when impurities and oxygen vacancies are present in a channel formation region of an oxide semiconductor, the electrical characteristics of an OS transistor are likely to fluctuate, and the reliability may be reduced. In addition, an OS transistor is prone to defects in which hydrogen enters an oxygen vacancy in an oxide semiconductor (hereinafter referred to as V O H) and generate electrons that act as carriers. Also, in the channel formation region, V O When H is formed, the donor concentration in the channel formation region may increase. As the donor concentration in the channel formation region increases, the threshold voltage may vary. For this reason, if oxygen vacancies are present in the channel formation region of an oxide semiconductor, the transistor is likely to have normally-on characteristics (characteristics in which a channel exists and current flows through the transistor even when no voltage is applied to the gate electrode). Therefore, in the channel formation region of an oxide semiconductor, impurities, oxygen vacancies, and V O It is preferable that H is reduced as much as possible.

[0356] The band gap of the oxide semiconductor is preferably larger than that of silicon (typically 1.1 eV), and is preferably 2 eV or more, more preferably 2.5 eV or more, and further preferably 3.0 eV or more. By using an oxide semiconductor having a band gap larger than that of silicon, the off-state current (also referred to as Ioff) of a transistor can be reduced.

[0357] Furthermore, in Si transistors, as transistors are miniaturized, a short channel effect (also referred to as a short channel effect: SCE) occurs. This makes miniaturization of Si transistors difficult. One of the factors that causes the short channel effect is the small band gap of silicon. On the other hand, an OS transistor uses an oxide semiconductor, which is a semiconductor material with a wide band gap, and therefore the short channel effect can be suppressed. In other words, an OS transistor is a transistor that does not have the short channel effect or has an extremely small short channel effect.

[0358] The short channel effect is a degradation of electrical characteristics that becomes evident as transistors become smaller (reduced channel length). Specific examples of short channel effects include a decrease in threshold voltage, an increase in S value, and an increase in leakage current.

[0359] Additionally, the characteristic length is widely used as an index of resistance to the short channel effect. The characteristic length is an index of how easily the potential of the channel formation region bends. The smaller the characteristic length, the steeper the potential rises, meaning that the device is more resistant to the short channel effect.

[0360] The OS transistor is an accumulation-type transistor, and the Si transistor is an inversion-type transistor. Therefore, compared with the Si transistor, the OS transistor has a smaller characteristic length between the source region and the channel formation region and between the drain region and the channel formation region. Therefore, the OS transistor is more resistant to the short-channel effect than the Si transistor. That is, when it is desired to manufacture a transistor with a short channel length, the OS transistor is more suitable than the Si transistor.

[0361] Even when the carrier concentration of the oxide semiconductor is reduced to the point where the channel formation region becomes i-type or substantially i-type, the conduction band minimum of the channel formation region is lowered in a short-channel transistor due to the conduction-band-lowering (CBL) effect, so that the energy difference between the conduction band minimum of the source or drain region and the channel formation region can be reduced to 0.1 eV or more and 0.2 eV or less. As a result, the channel formation region of the OS transistor can be n - The source and drain regions are n-type regions. + The domain of type, n + / n - / n + accumulation-type junction-less transistor structure, or + / n - / n + This can also be regarded as an accumulation-type non-junction transistor structure.

[0362] By making the OS transistor have the above structure, the semiconductor device can have good electrical characteristics even if the semiconductor device is miniaturized or highly integrated. For example, even if the gate length of the OS transistor is 20 nm or less, 15 nm or less, 10 nm or less, 7 nm or less, or 6 nm or less, and 1 nm or more, 3 nm or more, or 5 nm or more, good electrical characteristics can be obtained. On the other hand, since a short channel effect occurs in a Si transistor, it may be difficult to make the gate length 20 nm or less or 15 nm or less. Therefore, the OS transistor can be suitably used as a transistor having a shorter channel length than that of a Si transistor. Note that the gate length is the length of the gate electrode in the direction in which carriers move inside the channel formation region during transistor operation, and refers to the width of the bottom surface of the gate electrode in a plan view of the transistor.

[0363] Furthermore, by miniaturizing the OS transistor, the frequency characteristics of the transistor can be improved. Specifically, the cutoff frequency of the transistor can be improved. When the gate length of the OS transistor is within the above range, the cutoff frequency of the transistor can be set to 50 GHz or higher, preferably 100 GHz or higher, and more preferably 150 GHz or higher, for example, in a room temperature environment.

[0364] As described above, compared to Si transistors, OS transistors have excellent advantages such as a smaller off-state current and the ability to form transistors with a short channel length.

[0365] The configurations, structures, methods, and the like described in this embodiment can be used in appropriate combination with the configurations, structures, methods, and the like described in other embodiments.

[0366] (Embodiment 3) In this embodiment, a memory device including a transistor of one embodiment of the present invention will be described with reference to FIGS.

[0367] In this embodiment, a configuration example of a memory device using a memory cell having the transistor described in the above embodiment will be described, which includes a layer having stacked memory cells and a layer having a functional circuit having a function of amplifying and outputting a data potential held in the memory cell.

[0368] [Storage device configuration example] FIG. 19 illustrates a block diagram of a storage device of one embodiment of the present invention.

[0369] 19 includes a drive circuit 21 and a memory array 20. The memory array 20 includes a plurality of memory cells 10 and a functional layer 50 including a plurality of functional circuits 51.

[0370] 19 shows an example in which the memory array 20 has a plurality of memory cells 10 arranged in a matrix of m rows and n columns (m and n are integers of 2 or more). Also, Fig. 19 shows an example in which a functional circuit 51 is provided for each wiring BL that functions as a bit line, and an example in which the functional layer 50 has n functional circuits 51 provided corresponding to the n wirings BL.

[0371] In FIG. 19, the memory cell 10 in the first row and first column is indicated as memory cell 10[1,1], and the memory cell 10 in the mth row and nth column is indicated as memory cell 10[m,n]. In addition, in the present embodiment and the like, an arbitrary row may be indicated as the ith row. In addition, an arbitrary column may be indicated as the jth column. Thus, i is an integer between 1 and m, and j is an integer between 1 and n. In addition, in the present embodiment and the like, the memory cell 10 in the ith row and jth column is indicated as memory cell 10[i,j]. In addition, in the present embodiment and the like, when "i+α" (α is a positive or negative integer) is indicated, "i+α" is not less than 1 and does not exceed m. Similarly, when "j+α" is indicated, "j+α" is not less than 1 and does not exceed n.

[0372] The memory array 20 also includes m wirings WL extending in the row direction, m wirings PL extending in the row direction, and n wirings BL extending in the column direction. In the present embodiment and the like, the first wiring WL (first row) is indicated as wiring WL[1], and the mth wiring WL (mth row) is indicated as wiring WL[m]. Similarly, the first wiring PL (first row) is indicated as wiring PL[1], and the mth wiring PL (mth row) is indicated as wiring PL[m]. Similarly, the first wiring BL (first column) is indicated as wiring BL[1], and the nth wiring BL (nth column) is indicated as wiring BL[n].

[0373] The memory cells 10 in the i-th row are electrically connected to the wiring WL in the i-th row (wiring WL[i]) and the wiring PL in the i-th row (wiring PL[i]). The memory cells 10 in the j-th column are electrically connected to the wiring BL in the j-th column (wiring BL[j]).

[0374] A DOSRAM (registered trademark) (Dynamic Oxide Semiconductor Random Access Memory) can be applied to the memory array 20. DOSRAM is a RAM having 1T (transistor) 1C (capacitance) type memory cells, and refers to a memory in which the access transistor is an OS transistor. In the off state of the OS transistor, the current flowing between the source and drain, that is, the leakage current, is extremely small. In the DOSRAM, by turning off (non-conducting) the access transistor, it is possible to hold the charge corresponding to the data held in the capacitance element (capacitor) for a long time. Therefore, the frequency of the refresh operation can be reduced in the DOSRAM compared to the DRAM composed of a transistor (Si transistor) having silicon in the channel formation region. As a result, it is possible to achieve low power consumption. In addition, since the frequency characteristic of the OS transistor is high, reading and writing of the storage device can be performed at high speed. This makes it possible to provide a storage device with a high operating speed.

[0375] 19, multiple memory arrays 20[1] to 20[m] can be stacked. The memory arrays 20[1] to 20[m] of the memory array 20 can be arranged in a vertical direction to the substrate surface on which the driving circuit 21 is provided, thereby improving the memory density of the memory cells 10.

[0376] The wiring BL functions as a bit line for writing and reading data. The wiring WL functions as a word line for controlling the on / off (conducting or non-conducting) of an access transistor functioning as a switch. The wiring PL functions as a constant potential line connected to a capacitance element. Note that a wiring CL (not shown) can be separately provided as a wiring having a function of transmitting a back-gate potential to the back-gate of the OS transistor which is the access transistor. The wiring PL may also have a function of transmitting the back-gate potential.

[0377] The memory cells 10 of each of the memory arrays 20[1] to 20[m] are connected to the functional circuit 51 via wiring BL. The wiring BL can be arranged in a vertical direction to the substrate surface on which the driving circuit 21 is provided. By providing the wiring BL extending from the memory cells 10 of the memory arrays 20[1] to 20[m] in a vertical direction to the substrate surface, the length of the wiring between the memory array 20 and the functional circuit 51 can be shortened. Therefore, the signal propagation distance between the two circuits connected to the bit line can be shortened, and the resistance and parasitic capacitance of the bit line can be significantly reduced, thereby reducing power consumption and signal delay. In addition, the memory device can be operated even if the capacitance of the capacitive element of the memory cell 10 is reduced.

[0378] The functional circuit 51 has a function of amplifying the data potential held in the memory cell 10 and outputting it to the sense amplifier 46 of the driver circuit 21 via a wiring GBL (not shown) described later. This configuration makes it possible to amplify a slight potential difference of the wiring BL when reading data. The wiring GBL can be arranged in a vertical direction of the substrate surface on which the driver circuit 21 is provided, similar to the wiring BL. By providing the wiring BL and wiring GBL extending from the memory cell 10 of the memory arrays 20[1] to 20[m] in a vertical direction of the substrate surface, the length of the wiring between the functional circuit 51 and the sense amplifier 46 can be shortened. Therefore, the signal propagation distance between two circuits connected to the wiring GBL can be shortened, and the resistance and parasitic capacitance of the wiring GBL are significantly reduced, thereby realizing a reduction in power consumption and signal delay.

[0379] The wiring BL is provided in contact with the semiconductor layer of the transistor included in the memory cell 10. Alternatively, the wiring BL is provided in contact with a region that functions as the source or drain of the semiconductor layer of the transistor included in the memory cell 10. Alternatively, the wiring BL is provided in contact with a conductor that is provided in contact with a region that functions as the source or drain of the semiconductor layer of the transistor included in the memory cell 10. In other words, the wiring BL can be said to be a wiring for electrically connecting one of the source or drain of the transistor included in the memory cell 10 in each layer of the memory array 20 to the functional circuit 51 in the vertical direction.

[0380] The memory array 20 can be provided overlapping the drive circuit 21. By providing the drive circuit 21 and the memory array 20 overlapping, the signal propagation distance between the drive circuit 21 and the memory array 20 can be shortened. Therefore, the resistance and parasitic capacitance between the drive circuit 21 and the memory array 20 can be reduced, and the power consumption and signal delay can be reduced. In addition, the storage device 300 can be made smaller.

[0381] The functional circuit 51 uses OS transistors similar to the transistors in the memory cells 10 of the DOSRAM, and can be freely arranged on a circuit using Si transistors similar to the memory arrays 20[1] to 20[m], and can be easily integrated. By configuring the functional circuit 51 to amplify signals, the circuits in the subsequent stage, such as the sense amplifier 46, can be made smaller, and the memory device 300 can be made smaller.

[0382] The drive circuit 21 includes a PSW 22 (power switch), a PSW 23, and a peripheral circuit 31. The peripheral circuit 31 includes a peripheral circuit 41, a control circuit 32, and a voltage generating circuit 33.

[0383] In the storage device 300, each circuit, each signal, and each voltage can be appropriately selected or omitted as necessary. Alternatively, other circuits or other signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0384] Moreover, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are power gating control signals. Signals PON1 and PON2 may be generated by the control circuit 32.

[0385] The control circuit 32 is a logic circuit having a function of controlling the overall operation of the memory device 300. For example, the control circuit performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the memory device 300. Alternatively, the control circuit 32 generates a control signal for the peripheral circuit 41 so that this operation mode is executed.

[0386] The voltage generating circuit 33 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 33. For example, when an H-level signal is given to the signal WAKE, the signal CLK is input to the voltage generating circuit 33, and the voltage generating circuit 33 generates a negative voltage.

[0387] The peripheral circuit 41 is a circuit for writing and reading data to and from the memory cells 10. The peripheral circuit 41 is also a circuit for outputting various signals for controlling the functional circuit 51. The peripheral circuit 41 has a row decoder 42, a column decoder 44, a row driver 43, a column driver 45, an input circuit 47, an output circuit 48, and a sense amplifier 46.

[0388] The row decoder 42 and the column decoder 44 have a function of decoding the signal ADDR. The row decoder 42 is a circuit for specifying a row to be accessed, and the column decoder 44 is a circuit for specifying a column to be accessed. The row driver 43 has a function of selecting the wiring WL specified by the row decoder 42. The column driver 45 has a function of writing data to the memory cell 10, a function of reading data from the memory cell 10, a function of holding the read data, and the like.

[0389] The input circuit 47 has a function of holding a signal WDA. The data held by the input circuit 47 is output to the column driver 45. The output data of the input circuit 47 is data (Din) to be written to the memory cell 10. The data (Dout) read from the memory cell 10 by the column driver 45 is output to the output circuit 48. The output circuit 48 has a function of holding Dout. In addition, the output circuit 48 has a function of outputting Dout to the outside of the memory device 300. The data output from the output circuit 48 is the signal RDA.

[0390] The PSW22 has a function of controlling the supply of VDD to the peripheral circuit 31. The PSW23 has a function of controlling the supply of VHM to the row driver 43. Here, the high power supply voltage of the memory device 300 is VDD, and the low power supply voltage is GND (ground potential). Also, VHM is a high power supply voltage used to set the word line to a high level, and is higher than VDD. The on / off of the PSW22 is controlled by a signal PON1, and the on / off of the PSW23 is controlled by a signal PON2. In FIG. 19, the number of power domains to which VDD is supplied in the peripheral circuit 31 is one, but it may be multiple. In this case, a power switch may be provided for each power supply domain.

[0391] A memory array 20 having memory arrays 20[1] to 20[m] (m is an integer of 2 or more) and a functional layer 50 can be provided by stacking multiple layers of memory arrays 20 on a driving circuit 21. By stacking multiple layers of memory arrays 20, the memory density of the memory cells 10 can be increased. Fig. 20(A) shows a perspective view of a storage device 300 having a functional layer 50 and five layers (m=5) of memory arrays 20[1] to 20[5] stacked on a driving circuit 21.

[0392] In Fig. 20(A), the memory array 20 provided in the first layer is shown as memory array 20[1], the memory array 20 provided in the second layer is shown as memory array 20[2], and the memory array 20 provided in the fifth layer is shown as memory array 20[5]. Fig. 20(A) also shows wiring WL, wiring PL, and wiring CL extending in the X direction, and wiring BL extending in the Z direction (the direction perpendicular to the substrate surface on which the drive circuit is provided). Note that, in order to make the drawing easier to understand, the wiring WL and wiring PL of each memory array 20 are partially omitted.

[0393] 20(B) is a schematic diagram for explaining a configuration example of a functional circuit 51 connected to the wiring BL shown in FIG. 20(A) and memory cells 10 included in the memory arrays 20[1] to 20[5] connected to the wiring BL. FIG. 20(B) also illustrates a wiring GBL provided between the functional circuit 51 and the driver circuit 21. Note that a configuration in which multiple memory cells (memory cells 10) are electrically connected to one wiring BL is also referred to as a "memory string." Note that in the drawings, the wiring GBL may be illustrated with a thick line to improve visibility.

[0394] 20B illustrates an example of a circuit configuration of a memory cell 10 connected to a wiring BL. The memory cell 10 includes a transistor 11 and a capacitor 12. The transistor 11, the capacitor 12, and each wiring (such as a wiring BL and a wiring WL) may also be referred to as a wiring BL[1] and a wiring WL[1], for example, a wiring BL and a wiring WL. Here, the transistor 11 corresponds to the transistor 200 described in Embodiment 1.

[0395] In the memory cell 10, one of the source and the drain of the transistor 11 is connected to a wiring BL. The other of the source and the drain of the transistor 11 is connected to one electrode of a capacitor 12. The other electrode of the capacitor 12 is connected to a wiring PL. The gate of the transistor 11 is connected to a wiring WL. The back gate of the transistor 11 is connected to a wiring CL.

[0396] The wiring PL is a wiring that applies a constant potential to hold the potential of the capacitor 12. The wiring CL is a wiring that applies a constant potential to control the threshold voltage of the transistor 11. The wiring PL and the wiring CL may have the same potential. In this case, by connecting the two wirings, the number of wirings connected to the memory cell 10 can be reduced.

[0397] The wiring GBL shown in Fig. 20(B) is provided so as to electrically connect between the driver circuit 21 and the functional layer 50. Fig. 21(A) shows a schematic diagram of a memory device 300 in which a functional circuit 51 and memory arrays 20[1] to 20[m] are used as a repeating unit 70. Note that, although one wiring GBL is shown in Fig. 21(A), the wiring GBL may be provided as appropriate according to the number of functional circuits 51 provided in the functional layer 50.

[0398] The wiring GBL is provided in contact with a semiconductor layer of a transistor included in the functional circuit 51. Alternatively, the wiring GBL is provided in contact with a region that functions as a source or drain of a semiconductor layer of a transistor included in the functional circuit 51. Alternatively, the wiring GBL is provided in contact with a conductor that is provided in contact with a region that functions as a source or drain of a semiconductor layer of a transistor included in the functional circuit 51. In other words, the wiring GBL can be said to be a wiring for electrically connecting one of the source or drain of a transistor included in the functional circuit 51 in the functional layer 50 to the driver circuit 21 in the vertical direction.

[0399] The repeating unit 70 including the functional circuit 51 and the memory arrays 20[1] to 20[m] may be further stacked. The memory device 300A of one embodiment of the present invention can have repeating units 70[1] to 70[p] (p is an integer of 2 or more) as shown in FIG. 21B. The wiring GBL is connected to the functional layer 50 included in the repeating unit 70. The wiring GBL may be provided as appropriate depending on the number of functional circuits 51.

[0400] In one embodiment of the present invention, OS transistors are stacked, and wirings functioning as bit lines are arranged in a direction perpendicular to the substrate surface on which the driver circuit 21 is provided. By providing the wirings functioning as bit lines extending from the memory array 20 in a direction perpendicular to the substrate surface, the length of the wirings between the memory array 20 and the driver circuit 21 can be shortened. As a result, the parasitic capacitance of the bit lines can be significantly reduced.

[0401] In addition, one embodiment of the present invention includes a functional layer 50 having a functional circuit 51 that has a function of amplifying and outputting a data potential held in a memory cell 10 in a layer in which the memory array 20 is provided. With this configuration, a slight potential difference of a wiring BL that functions as a bit line when reading data can be amplified to drive a sense amplifier 46 included in a driver circuit 21. Since circuits such as a sense amplifier can be miniaturized, the memory device 300 can be miniaturized. In addition, the memory device 300 can be operated even if the capacitance of the capacitor 12 included in the memory cell 10 is reduced.

[0402] In the above, an example in which the memory cell 10 has a 1T (transistor) 1C (capacitor) type configuration has been shown, but the present invention is not limited to this. For example, as shown in FIG. 25(A), a 3T1C type memory cell may be used in a storage device. The memory cell shown in FIG. 25(A) has transistors 11a, 11b, and 11c and a capacitive element 12a. Here, the transistors 11a, 11b, and 11c can have the same configuration as the transistor 11, and the capacitive element 12a can have the same configuration as the capacitive element 12. A RAM with such a configuration may be called NOSRAM (registered trademark) (Nonvolatile Oxide Semiconductor RAM).

[0403] As shown in FIG. 25A, one of the source and drain of the transistor 11a is electrically connected to one of the electrodes of the capacitor 12a and the first gate of the transistor 11b. One of the source and drain of the transistor 11b is electrically connected to one of the source and drain of the transistor 11c. Wirings may be provided as appropriate for the first gate, the other of the source and drain, and the second gate of the transistor 11a, the other of the source and drain, and the second gate of the transistor 11b, the first gate, the other of the source and drain, and the second gate of the transistor 11c, and the other of the electrode of the capacitor 12a. The structure of the memory device can also be modified as appropriate in accordance with these wirings.

[0404] Alternatively, as shown in FIG. 25B, a 2T1C type memory cell may be formed without providing the transistor 11c and having only the transistors 11a and 11b and the capacitor element 12a.

[0405] When the parasitic capacitances of the transistors 11a and 11b are sufficiently large, the capacitor 12a may not be provided as shown in Fig. 25C. In this case, the memory cell is formed of only the transistors 11a and 11b.

[0406] [Example of configuration of memory array 20 and functional circuit 51] 22, a configuration example of the functional circuit 51 described in FIG. 19 to FIG. 21 and a configuration example of the sense amplifier 46 included in the memory array 20 and the driver circuit 21 will be described. FIG. 22 illustrates the driver circuit 21 connected to wirings GBL (wirings GBL_A, GBL_B) connected to functional circuits 51 (functional circuits 51_A, 51_B) connected to memory cells 10 (memory cells 10_A, 10_B) connected to different wirings BL (wirings BL_A, BL_B). As the driver circuit 21 illustrated in FIG. 22, in addition to the sense amplifier 46, a precharge circuit 71_A, a precharge circuit 71_B, a switch circuit 72_A, a switch circuit 72_B, and a write / read circuit 73 are illustrated.

[0407] Transistors 52_a, 52_b, 53_a, 53_b, 54_a, 54_b, 55_a, and 55_b are illustrated as the functional circuits 51_A and 51_B. The transistors 52_a, 52_b, 53_a, 53_b, 54_a, 54_b, 55_a, and 55_b illustrated in Fig. 22 are OS transistors similar to the transistor 11 included in the memory cell 10. The functional layer 50 including the functional circuit 51 can be stacked on the driver circuit 21 similar to the memory arrays 20[1] to 20[m].

[0408] The wiring BL_A is connected to the gate of the transistor 52_a, and the wiring BL_B is connected to the gate of the transistor 52_b. The wiring GBL_A is connected to one of the sources or drains of the transistors 53_a and 54_a. The wiring GBL_B is connected to one of the sources or drains of the transistors 53_b and 54_b. The wirings GBL_A and GBL_B are provided in the vertical direction like the wirings BL_A and BL_B, and are connected to the transistors of the driver circuit 21. As shown in FIG. 22, the selection signal MUX, the control signal WE, and the control signal RE are respectively provided to the gates of the transistors 53_a, 53_b, 54_a, 54_b, 55_a, and 55_b.

[0409] The transistors 81_1 to 81_6 and 82_1 to 82_4 constituting the sense amplifier 46, precharge circuit 71_A, and precharge circuit 71_B shown in Fig. 22 are composed of Si transistors. The switches 83_A to 83_D constituting the switch circuit 72_A and switch circuit 72_B can also be composed of Si transistors. One of the sources or drains of the transistors 53_a, 53_b, 54_a, and 54_b is connected to the transistors or switches constituting the precharge circuit 71_A, precharge circuit 71_B, sense amplifier 46, and switch circuit 72_A.

[0410] The precharge circuit 71_A includes n-channel transistors 81_1 to 81_3. The precharge circuit 71_A is a circuit for precharging the wirings BL_A and BL_B to an intermediate potential VPC that corresponds to a potential VDD / 2 between a high power supply potential (VDD) and a low power supply potential (VSS) in response to a precharge signal provided to a precharge line PCL1.

[0411] The precharge circuit 71_B has n-channel transistors 81_4 to 81_6. The precharge circuit 71_B is a circuit for precharging the wirings GBL_A and GBL_B to an intermediate potential VPC that corresponds to a potential VDD / 2 between VDD and VSS in response to a precharge signal provided to a precharge line PCL2.

[0412] The sense amplifier 46 includes p-channel transistors 82_1 and 82_2 and n-channel transistors 82_3 and 82_4 connected to the wiring VHH or the wiring VLL. The wiring VHH or the wiring VLL is a wiring having a function of applying VDD or VSS. The transistors 82_1 to 82_4 are transistors that configure an inverter loop. The potentials of the precharged wirings BL_A and BL_B change when the memory cells 10_A and 10_B are selected, and the potentials of the wirings GBL_A and GBL_B are set to VDD or VSS in response to the change. The potentials of the wirings GBL_A and GBL_B can be output to the outside via the switches 83_C and 83_D, and the write / read circuit 73. The wirings BL_A and BL_B, and the wirings GBL_A and GBL_B correspond to a bit line pair. The write / read circuit 73 controls writing of a data signal in response to a signal EN_data.

[0413] The switch circuit 72_A is a circuit for controlling the conduction state between the sense amplifier 46 and the wiring GBL_A and wiring GBL_B. The switch circuit 72_A is switched on or off under the control of a switching signal CSEL1. When the switches 83_A and 83_B are n-channel transistors, the switching signal CSEL1 is turned on at a high level and turned off at a low level. The switch circuit 72_B is a circuit for controlling the conduction state between the write / read circuit 73 and the bit line pair connected to the sense amplifier 46. The switch circuit 72_B is switched on or off under the control of a switching signal CSEL2. The switches 83_C and 83_D may operate in the same manner as the switches 83_A and 83_B.

[0414] 22, the memory device 300 can be configured such that the memory cell 10, the functional circuit 51, and the sense amplifier 46 are connected via wirings BL and GBL that are provided in the vertical direction to form the shortest distance. Although the number of functional layers 50 having transistors that configure the functional circuit 51 increases, the load of the wirings BL is reduced, thereby shortening the write time and making it easier to read data.

[0415] 22, each transistor in the functional circuits 51_A and 51_B is controlled according to control signals WE and RE and a selection signal MUX. Each transistor can output the potential of the wiring BL to the drive circuit 21 via the wiring GBL according to the control signal and the selection signal. The functional circuits 51_A and 51_B can function as a sense amplifier composed of OS transistors. With this configuration, a slight potential difference of the wiring BL can be amplified during reading to drive the sense amplifier 46 using Si transistors.

[0416] <Memory cell configuration example> An example of the configuration of a memory cell 10 used in the above storage device will be described with reference to FIG.

[0417] In FIG. 23, the X direction is parallel to the channel width direction of the illustrated transistor, the Y direction is perpendicular to the X direction, and the Z direction is perpendicular to the X and Y directions.

[0418] As illustrated in FIG. 23, the memory cell 10 includes a transistor 11 and a capacitor 12. An insulator 285 is provided over the transistor 11, and an insulator 284 is provided over the insulator 285. The insulator 285 and the insulator 284 may be made of an insulator that can be used for the insulator 216. The transistor 11 has a similar structure to the transistor 200 described in the above embodiment, and the same components are denoted by the same reference numerals. For details of the transistor 200, the above embodiment can be referred to. A conductor 240 is provided in contact with one of the source and drain (conductor 242a) of the transistor 11. The conductor 240 extends in the Z direction and functions as a wiring BL.

[0419] The capacitor 12 includes a conductor 153 on the conductor 242b, an insulator 154 on the conductor 153, and a conductor 160 (conductor 160a and conductor 160b) on the insulator 154.

[0420] At least a portion of the conductor 153, the insulator 154, and the conductor 160 is disposed inside the openings provided in the insulators 271b, 275, 280, 282, 283, and 285, respectively. The ends of the conductors 153, 154, and 160 are located at least on the insulator 282, and preferably on the insulator 285. The insulator 154 is provided so as to cover the end of the conductor 153. This allows the conductors 153 and 160 to be electrically insulated from each other.

[0421] The deeper the openings provided in the insulators 271b, 275, 280, 282, 283, and 285 are (that is, the thicker one or more of the insulators 271b, 275, 280, 282, 283, and 285 are), the larger the capacitance of the capacitance element 12. By increasing the capacitance per unit area of ​​the capacitance element 12, miniaturization or high integration of the semiconductor device can be achieved.

[0422] The conductor 153 has a region that functions as one electrode (lower electrode) of the capacitor 12. The insulator 154 has a region that functions as a dielectric of the capacitor 12. The conductor 160 has a region that functions as the other electrode (upper electrode) of the capacitor 12. The capacitor 12 constitutes a MIM (Metal-Insulator-Metal) capacitor.

[0423] In addition, the conductor 242 b provided so as to overlap the oxide 230 functions as a wiring electrically connected to the conductor 153 of the capacitor 12 .

[0424] The conductor 153 and the conductor 160 of the capacitor 12 can be formed using various conductors that can be used for the conductor 205 or the conductor 260. The conductor 153 and the conductor 160 are preferably formed using a film formation method with good coverage such as an ALD method or a CVD method. For example, the conductor 153 can be made of titanium nitride or tantalum nitride formed using an ALD method or a CVD method.

[0425] Furthermore, the upper surface of the conductor 242b2 contacts the lower surface of the conductor 153. Here, by using a conductive material with good conductivity as the conductor 242b2, the contact resistance between the conductor 153 and the conductor 242b can be reduced.

[0426] Also, the conductor 160a may be made of titanium nitride formed by ALD or CVD, and the conductor 160b may be made of tungsten formed by CVD. If the adhesion of tungsten to the insulator 154 is sufficiently high, the conductor 160 may have a single layer structure of tungsten formed by CVD.

[0427] A high-dielectric (high-k) material (a material with a high relative dielectric constant) is preferably used for the insulator 154 of the capacitor 12. The insulator 154 is preferably formed by a film formation method with good coverage, such as an ALD method or a CVD method.

[0428] Examples of high-k dielectric insulators include oxides, oxynitrides, oxynitrides, and nitrides containing one or more metal elements selected from aluminum, hafnium, zirconium, and gallium. Silicon may also be contained in the oxides, oxynitrides, oxynitrides, or nitrides. Insulators made of the above materials may also be stacked.

[0429] For example, examples of the insulator made of a high dielectric constant (high-k) material include aluminum oxide, hafnium oxide, zirconium oxide, oxide having aluminum and hafnium, oxynitride having aluminum and hafnium, oxide having silicon and hafnium, oxynitride having silicon and hafnium, oxide having silicon and zirconium, oxynitride having silicon and zirconium, oxide having hafnium and zirconium, and oxynitride having hafnium and zirconium. By using such a high-k material, the insulator 154 can be made thick enough to suppress the leakage current, and the capacitance of the capacitance element 12 can be sufficiently secured.

[0430] In addition, it is preferable to use insulators made of the above materials in a laminated manner, and it is preferable to use a laminated structure of a high dielectric constant (high-k) material and a material having a higher dielectric strength than the high dielectric constant (high-k) material. For example, an insulator in which zirconium oxide, aluminum oxide, and zirconium oxide are laminated in this order can be used as the insulator 154. Also, for example, an insulator in which zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide are laminated in this order can be used. Also, for example, an insulator in which hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide are laminated in this order can be used. By using an insulator having a relatively high dielectric strength such as aluminum oxide in a laminated manner, the dielectric strength is improved and electrostatic breakdown of the capacitance element 12 can be suppressed.

[0431] The deeper the openings provided in the insulators 271b, 275, 280, 282, 283, and 285 are (i.e., the thicker one or more of the insulators 271b, 275, 280, 282, 283, and 285 are), the larger the capacitance of the capacitance element 12 can be. Here, since the insulators 271b, 275, 282, and 283 function as barrier insulators, it is preferable to set the film thickness according to the barrier properties required for the semiconductor device. In addition, since the film thickness of the conductor 260 functioning as a gate electrode is determined according to the film thickness of the insulator 280, it is preferable to set the film thickness of the insulator 280 according to the film thickness of the conductor 260 required for the semiconductor device.

[0432] Therefore, it is preferable to set the capacitance of the capacitor 12 by adjusting the thickness of the insulator 285. For example, the thickness of the insulator 285 may be set in the range of 50 nm to 250 nm, and the depth of the opening may be set to about 150 nm to 350 nm. By forming the capacitor 12 in such a range, the capacitor 12 can have a sufficient capacitance, and the height of one layer in a semiconductor device in which multiple memory cell layers are stacked can be prevented from becoming excessively high. Note that a configuration may be adopted in which the capacitance of the capacitor provided in each memory cell is different in each of the multiple memory cell layers. In this configuration, for example, the thickness of the insulator 285 provided in each memory cell layer may be different.

[0433] In an opening provided in the insulator 285 or the like in which the capacitive element 12 is disposed, the sidewall of the opening may be perpendicular or approximately perpendicular to the upper surface of the insulator 222, or may be tapered. By making the sidewall tapered, the coverage of the conductor 153 or the like provided in the opening of the insulator 285 or the like can be improved, and defects such as voids can be reduced.

[0434] Moreover, the conductor 242a provided so as to overlap the oxide 230 functions as wiring electrically connected to the conductor 240. For example, in Fig. 23, the upper surface and side end of the conductor 242a are electrically connected to the conductor 240 extending in the Z direction. In particular, in Fig. 23, the upper surface and side end of the conductor 242a2 and the side end of the conductor 242a1 are in contact with the conductor 240.

[0435] Since the conductor 240 directly contacts at least one of the upper surface and the side end of the conductor 242a, there is no need to provide a separate electrode for connection, and therefore the area occupied by the memory array can be reduced. Furthermore, the integration degree of the memory cells is improved, and the memory capacity of the memory device can be increased. It is preferable that the conductor 240 contacts a part of the upper surface and the side end of the conductor 242a. The contact resistance between the conductor 240 and the conductor 242a can be reduced by the conductor 240 contacting multiple surfaces of the conductor 242a. In particular, as shown in FIG. 23, the contact resistance between the conductor 240 and the conductor 242a can be further reduced by the conductor 240 contacting a part of the upper surface and the side end of the highly conductive conductor 242a2.

[0436] Conductor 240 is disposed within openings formed in insulators 216 , 221 , 222 , 275 , 280 , 282 , 283 , 285 , and 284 .

[0437] The conductor 240 preferably has a laminated structure of the conductor 240a and the conductor 240b. For example, as shown in Fig. 23, the conductor 240 can have a structure in which the conductor 240a is provided in contact with the inner wall of the opening, and the conductor 240b is provided further inside. That is, the conductor 240a is disposed closer to the insulators 216, 221, 222, 275, 280, 282, 283, 285, and 284 than the conductor 240b. The conductor 240a also contacts the upper surface and side end of the conductor 242a.

[0438] The conductor 240a is preferably made of a conductive material that has a function of suppressing the permeation of impurities such as water and hydrogen. The conductor 240a can have a single-layer structure or a multi-layer structure using one or more of tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, and ruthenium oxide, for example. This can suppress impurities such as water and hydrogen from being mixed into the oxide 230 through the conductor 240.

[0439] In addition, since the conductor 240 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, the conductor 240b can be made of a conductive material containing tungsten, copper, or aluminum as a main component.

[0440] For example, it is preferable to use titanium nitride as the conductor 240a and tungsten as the conductor 240b. In this case, the conductor 240a is a conductor containing titanium and nitrogen, and the conductor 240b is a conductor containing tungsten.

[0441] The conductor 240 may have a single-layer structure or a laminated structure of three or more layers.

[0442] 23, it is preferable that the insulator 241 is provided in contact with the side surface of the conductor 240. Specifically, the insulator 241 is provided in contact with the inner walls of the openings of the insulators 216, 221, 222, 275, 280, 282, 283, 285, and 284. The insulator 241 is also formed on the side surfaces of the insulator 224, the oxide 230, and the conductor 242a, which are formed to protrude into the opening. Here, at least a part of the conductor 242a is exposed from the insulator 241 and is in contact with the conductor 240. In other words, the conductor 240 is provided so as to fill the inside of the opening through the insulator 241.

[0443] 23, the uppermost portion of the insulator 241 formed below the conductor 242a is preferably located below the upper surface of the conductor 242a. This configuration allows the conductor 240 to contact at least a portion of the side end of the conductor 242a. The insulator 241 formed below the conductor 242a preferably has an area in contact with the side surface of the oxide 230. This configuration can prevent impurities such as water and hydrogen contained in the insulator 280 from entering the oxide 230 through the conductor 240.

[0444] The insulator 241 may be a barrier insulating film that can be used for the insulator 275, etc. For example, the insulator 241 may be an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide. This configuration can prevent impurities such as water and hydrogen contained in the insulator 280, etc. from mixing with the oxide 230 through the conductor 240. Silicon nitride is particularly suitable because it has high blocking properties against hydrogen. In addition, it can prevent oxygen contained in the insulator 280 from being absorbed by the conductor 240.

[0445] 23 shows a structure in which the insulator 241 is a single layer, the present invention is not limited to this, and the insulator 241 may have a laminated structure of two or more layers.

[0446] When the insulator 241 has a two-layer structure, a barrier insulating film against oxygen may be used for the first layer in contact with the inner wall of the opening of the insulator 280, etc., and a barrier insulating film against hydrogen may be used for the second layer inside the first layer. For example, aluminum oxide formed by the ALD method may be used for the first layer, and silicon nitride formed by the PEALD method may be used for the second layer. This configuration can suppress oxidation of the conductor 240 and further reduce the intrusion of hydrogen from the conductor 240 into the oxide 230, etc. This can improve the electrical characteristics and reliability of the transistor 11.

[0447] In the opening in which the conductor 240 and the insulator 241 are disposed, the sidewall of the opening may be perpendicular or approximately perpendicular to the upper surface of the insulator 222, or may be tapered. By making the sidewall tapered, the coverage of the insulator 241 and the like provided in the opening is improved.

[0448] <Configuration example of storage device 300> An example of the configuration of the storage device 300 will be described with reference to FIG.

[0449] The memory device 300 has a driving circuit 21 which is a layer having transistors 310 and the like, a functional layer 50 which is a layer having transistors 52, 53, 54, 55 and the like on the driving circuit 21, and memory arrays 20[1] to 20[m] on the functional layer 50 (only memory arrays 20[1] and 20[2] are shown in FIG. 24 ). Note that the transistor 52 corresponds to the transistors 52_a and 52_b, the transistor 53 corresponds to the transistors 53_a and 53_b, the transistor 54 corresponds to the transistors 54_a and 54_b, and the transistor 55 corresponds to the transistors 55_a and 55_b.

[0450] 24 illustrates a transistor 310 included in the driver circuit 21. The transistor 310 is provided over a substrate 311 and includes a conductor 316 functioning as a gate, an insulator 315 functioning as a gate insulator, a semiconductor region 313 including a part of the substrate 311, and a low-resistance region 314a and a low-resistance region 314b functioning as a source region or a drain region. The transistor 310 may be a p-channel transistor or an n-channel transistor. As the substrate 311, for example, a single crystal silicon substrate can be used.

[0451] Here, in the transistor 310 shown in FIG. 24, a semiconductor region 313 (a part of a substrate 311) in which a channel is formed has a convex shape. Also, a conductor 316 is provided so as to cover the side and upper surface of the semiconductor region 313 via an insulator 315. Note that the conductor 316 may be made of a material that adjusts the work function. Such a transistor 310 is also called a FIN type transistor because it uses a convex portion of a semiconductor substrate. Note that an insulator that contacts the upper portion of the convex portion and functions as a mask for forming the convex portion may be provided. Also, although a case where a convex portion is formed by processing a part of a semiconductor substrate has been shown here, a semiconductor film having a convex shape may be formed by processing an SOI (Silicon on Insulator) substrate.

[0452] Note that the transistor 310 illustrated in FIG. 24 is just an example and is not limited to this structure. Any appropriate transistor can be used depending on the circuit configuration or driving method.

[0453] Between each structure, a wiring layer having an interlayer film, wiring, plugs, etc. may be provided. Also, a plurality of wiring layers may be provided according to the design. Also, in this specification, the wiring and the plug electrically connected to the wiring may be integrated. That is, there are cases where a part of the conductor functions as the wiring, and cases where a part of the conductor functions as the plug.

[0454] For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order as an interlayer film over the transistor 310. A conductor 328 or the like is embedded in the insulator 320 and the insulator 322. A conductor 330 or the like is embedded in the insulator 324 and the insulator 326. The conductor 328 and the conductor 330 function as contact plugs or wirings.

[0455] The insulator functioning as an interlayer film may also function as a planarizing film that covers the uneven shape underneath. For example, the top surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to improve the flatness.

[0456] 24 illustrates transistors 52, 53, and 55 included in the functional layer 50. The transistors 52, 53, and 55 have a similar configuration to the transistor 11 included in the memory cell 10. The transistors 52, 53, and 55 have their sources and drains connected in series to each other.

[0457] An insulator 208 is provided over the transistors 52, 53, and 55, and a conductor 207 is provided in an opening formed in the insulator 208. Further, an insulator 210 is provided over the insulator 208, and a conductor 209 is provided in an opening formed in the insulator 210. Further, an insulator 212 is provided over the insulator 210, and an insulator 214 is provided over the insulator 212. A part of a conductor 240 provided in the memory array 20[1] is embedded in the openings formed in the insulators 212 and 214. Here, the insulators 208 and 210 can be made of an insulator that can be used for the insulator 216. The insulator 212 can be made of an insulator that can be used for the insulator 283. The insulator 214 can be made of an insulator that can be used for the insulator 282.

[0458] The bottom surface of the conductor 207 is in contact with the top surface of the conductor 260 of the transistor 52. The top surface of the conductor 207 is in contact with the bottom surface of the conductor 209. The top surface of the conductor 209 is in contact with the bottom surface of the conductor 240 provided in the memory array 20[1]. With this configuration, the conductor 240 corresponding to the wiring BL and the gate of the transistor 52 can be electrically connected to each other.

[0459] Each of the memory arrays 20[1] to 20[m] includes a plurality of memory cells 10. The conductor 240 of each memory cell 10 is electrically connected to the conductor 240 in the upper layer and the conductor 240 in the lower layer.

[0460] 24, adjacent memory cells 10 share a conductor 240. In addition, in the adjacent memory cells 10, the configuration on the right side and the configuration on the left side are arranged symmetrically with respect to the conductor 240.

[0461] Here, the conductor 160 functioning as the upper electrode of the capacitor 12 in the lower layer (for example, the layer of the memory array 20[1]) and the conductor 261 functioning as the second gate electrode of the transistor 11 in the upper layer (for example, the layer of the memory array 20[2]) can be formed in the same layer. In other words, the conductor 160 of the capacitor 12 in the lower layer and the conductor 261 of the transistor 11 in the upper layer can be formed so as to be embedded in an opening formed in the same insulator 216. The conductor 160 of the capacitor 12 in the lower layer and the conductor 261 of the transistor 11 in the upper layer are formed by processing one conductive film, resulting in the above-mentioned configuration. At this time, the conductor 160 of the capacitor 12 in the lower layer has the same material as the conductor 261 of the transistor 11 in the upper layer.

[0462] As described above, by simultaneously forming the conductor 160 of the capacitor 12 in the lower layer and the conductor 261 of the transistor 11 in the upper layer, the manufacturing process of the memory device according to this embodiment can be reduced, and the productivity of the memory device can be improved.

[0463] In the above-mentioned memory array 20, a plurality of memory arrays 20[1] to 20[m] can be stacked. The memory arrays 20[1] to 20[m] of the memory array 20 can be arranged in the vertical direction of the substrate surface on which the driving circuit 21 is provided, thereby improving the memory density of the memory cells 10. The memory array 20 can be fabricated by repeatedly using the same manufacturing process in the vertical direction. The storage device 300 can reduce the manufacturing cost of the memory array 20.

[0464] This embodiment mode can be combined with other embodiment modes as appropriate.

[0465] (Embodiment 4) In this embodiment, an example of a chip on which a memory device of one embodiment of the present invention is mounted will be described with reference to FIG.

[0466] 26(A) and 26(B) are implemented with multiple circuits (systems). A technology for integrating multiple circuits (systems) on a single chip in this way is sometimes called a system on chip (SoC).

[0467] As shown in FIG. 26(A), a chip 1200 includes a CPU 1211, a GPU 1212, one or more analog arithmetic units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.

[0468] 26(B), the chip 1200 is provided with bumps (not shown) and is connected to a first surface of a package substrate 1201. In addition, a plurality of bumps 1202 are provided on the back surface of the first surface of the package substrate 1201 and is connected to a motherboard 1203.

[0469] The motherboard 1203 may be provided with a storage device such as a DRAM 1221 and a flash memory 1222. For example, the DOSRAM described in the above embodiment can be used for the DRAM 1221. This allows the DRAM 1221 to consume less power, operate at a higher speed, and have a larger capacity.

[0470] The CPU 1211 preferably has a plurality of CPU cores. The GPU 1212 preferably has a plurality of GPU cores. The CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data. Alternatively, a memory common to the CPU 1211 and the GPU 1212 may be provided in the chip 1200. The memory may be the above-mentioned DOSRAM. The GPU 1212 is suitable for parallel calculation of a large amount of data and may be used for image processing or multiplication and accumulation. By providing the GPU 1212 with an image processing circuit or a multiplication and accumulation circuit using the OS transistor described in the previous embodiment, it becomes possible to execute image processing or multiplication and accumulation with low power consumption.

[0471] In addition, by providing the CPU 1211 and GPU 1212 on the same chip, the wiring between the CPU 1211 and GPU 1212 can be shortened, and data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories of the CPU 1211 and GPU 1212, and transfer of calculation results from the GPU 1212 to the CPU 1211 after calculation in the GPU 1212 can be performed quickly.

[0472] The analog calculation unit 1213 has one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. The analog calculation unit 1213 may also be provided with the above-mentioned product-sum calculation circuit.

[0473] The memory controller 1214 has a circuit that functions as a controller for the DRAM 1221 and a circuit that functions as an interface for the flash memory 1222 .

[0474] The interface 1215 has an interface circuit with externally connected devices such as a display device, a speaker, a microphone, a camera, and a controller. The controller includes a mouse, a keyboard, a game controller, etc. As such an interface, a USB (Universal Serial Bus), an HDMI (registered trademark) (High-Definition Multimedia Interface), etc. can be used.

[0475] The network circuit 1216 includes a circuit for connecting to a network such as a LAN (Local Area Network), and may also include a circuit for network security.

[0476] The above circuits (systems) can be formed in the same manufacturing process in the chip 1200. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the manufacturing process, and the chip 1200 can be manufactured at low cost.

[0477] A package substrate 1201 on which a chip 1200 having a GPU 1212 is provided, a motherboard 1203 on which a DRAM 1221 and a flash memory 1222 are provided, can be called a GPU module 1204.

[0478] The GPU module 1204 has the chip 1200 using SoC technology, so that its size can be reduced. In addition, since it excels in image processing, it is suitable for use in portable electronic devices such as smartphones, tablet terminals, laptop PCs, and portable (portable) game consoles. In addition, a product-sum operation circuit using the GPU 1212 can execute techniques such as a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), an autoencoder, a deep Boltzmann machine (DBM), and a deep belief network (DBN), so that the chip 1200 can be used as an AI chip, and the GPU module 1204 can be used as an AI system module.

[0479] This embodiment mode can be combined with other embodiment modes as appropriate.

[0480] (Embodiment 5) In this embodiment, electronic components, electronic devices, mainframes, space equipment, and data centers (also referred to as data centers (DCs)) in which the semiconductor device described in the above embodiment can be used will be described. The electronic components, electronic devices, mainframes, space equipment, and data centers using the semiconductor device of one embodiment of the present invention are effective in achieving high performance, such as low power consumption.

[0481] [Electronic components] FIG. 27A shows a perspective view of a substrate (mounting substrate 704) on which an electronic component 700 is mounted. The electronic component 700 shown in FIG. 27A has a semiconductor device 710 in a mold 711. FIG. 27A omits some parts in order to show the inside of the electronic component 700. The electronic component 700 has lands 712 on the outside of the mold 711. The lands 712 are electrically connected to electrode pads 713, and the electrode pads 713 are electrically connected to the semiconductor device 710 via wires 714. The electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on the printed circuit board 702 to complete the mounting substrate 704.

[0482] The semiconductor device 710 also includes a drive circuit layer 715 and a memory layer 716. The memory layer 716 is configured by stacking a plurality of memory cell arrays. The stacked configuration of the drive circuit layer 715 and the memory layer 716 can be a monolithic stacked configuration. In the monolithic stacked configuration, each layer can be connected without using a through electrode technology such as TSV (Through Silicon Via) and a bonding technology such as Cu-Cu direct bonding. By configuring the drive circuit layer 715 and the memory layer 716 as a monolithic stack, for example, a so-called on-chip memory configuration in which a memory is directly formed on a processor can be configured. By configuring the on-chip memory, it is possible to increase the speed of the operation of the interface between the processor and the memory.

[0483] In addition, by configuring an on-chip memory, it is possible to reduce the size of connection wiring, etc., compared to technologies that use through electrodes such as TSV, and it is also possible to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, making it possible to improve the memory bandwidth (also called memory bandwidth).

[0484] In addition, it is preferable that the memory cell arrays in the memory layer 716 are formed using OS transistors and the memory cell arrays are monolithically stacked. By forming the memory cell arrays in a monolithic stacked configuration, it is possible to improve either or both of the memory bandwidth and the memory access latency. Note that the bandwidth is the amount of data transferred per unit time, and the access latency is the time from access to the start of data exchange. Note that in the case of a configuration using Si transistors in the memory layer 716, it is difficult to form a monolithic stacked configuration compared to OS transistors. Therefore, it can be said that the OS transistor has a superior structure to the Si transistor in the monolithic stacked configuration.

[0485] The semiconductor device 710 may also be referred to as a die. In this specification and the like, a die refers to a chip piece obtained by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and cutting it into a dice shape in the manufacturing process of a semiconductor chip. Examples of semiconductor materials that can be used for the die include silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0486] 27B shows a perspective view of the electronic component 730. The electronic component 730 is an example of a SiP (System in Package) or MCM (Multi Chip Module). The electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 710 provided on the interposer 731.

[0487] The electronic component 730 shows an example in which the semiconductor device 710 is used as a high bandwidth memory (HBM). The semiconductor device 735 can be used in an integrated circuit such as a central processing unit (CPU), a graphics processing unit (GPU), or a field programmable gate array (FPGA).

[0488] For example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used as the package substrate 732. For example, a silicon interposer or a resin interposer can be used as the interposer 731.

[0489] The interposer 731 has a plurality of wirings and functions to electrically connect a plurality of integrated circuits having different terminal pitches. The plurality of wirings are provided in a single layer or in multiple layers. The interposer 731 also functions to electrically connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer may be called a "rewiring substrate" or an "intermediate substrate." In some cases, a through electrode may be provided in the interposer 731, and the integrated circuits and the package substrate 732 may be electrically connected using the through electrode. In addition, in a silicon interposer, a TSV may be used as the through electrode.

[0490] In HBM, many wirings need to be connected to realize a wide memory bandwidth. For this reason, the interposer that mounts HBM requires fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer that mounts HBM.

[0491] In addition, in SiP and MCM using silicon interposers, the reliability is less likely to decrease due to the difference in the expansion coefficient between the integrated circuit and the interposer. In addition, since the surface of the silicon interposer is highly flat, connection failure between the integrated circuit mounted on the silicon interposer and the silicon interposer is less likely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional mounting) in which multiple integrated circuits are arranged side by side on the interposer.

[0492] On the other hand, when a silicon interposer, TSV, or the like is used to electrically connect multiple integrated circuits with different terminal pitches, a space is required for the width of the terminal pitch. Therefore, when trying to reduce the size of the electronic component 730, the width of the terminal pitch becomes a problem, and it may be difficult to provide many wirings required to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacking configuration using OS transistors is preferable. A composite structure may be formed by combining a memory cell array stacked using TSV and a monolithic stacking memory cell array.

[0493] A heat sink (heat dissipation plate) may be provided so as to overlap the electronic component 730. When providing a heat sink, it is preferable to align the height of an integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the height of the semiconductor device 710 and the height of the semiconductor device 735.

[0494] In order to mount the electronic component 730 on another substrate, electrodes 733 may be provided on the bottom of the package substrate 732. Fig. 27(B) shows an example in which the electrodes 733 are formed of solder balls. By providing solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be realized. The electrodes 733 may also be formed of conductive pins. By providing conductive pins in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be realized.

[0495] The electronic component 730 can be mounted on other substrates using various mounting methods, including, but not limited to, BGA and PGA, such as, for example, SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[0496] [Electronic equipment] Next, a perspective view of an electronic device 6500 is shown in FIG. 28A. The electronic device 6500 shown in FIG. 28A is a portable information terminal that can be used as a smartphone. The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, a control device 6509, and the like. Note that the control device 6509 includes, for example, one or more selected from a CPU, a GPU, and a memory device. The semiconductor device of one embodiment of the present invention can be applied to the display portion 6502, the control device 6509, and the like.

[0497] An electronic device 6600 shown in FIG. 28B is an information terminal that can be used as a notebook personal computer. The electronic device 6600 includes a housing 6611, a keyboard 6612, a pointing device 6613, an external connection port 6614, a display portion 6615, a control device 6616, and the like. Note that the control device 6616 includes, for example, one or more selected from a CPU, a GPU, and a storage device. The semiconductor device of one embodiment of the present invention can be applied to the display portion 6615, the control device 6616, and the like. Note that the use of the semiconductor device of one embodiment of the present invention for the control device 6509 and the control device 6616 described above is preferable because power consumption can be reduced.

[0498] [Large computer] Next, Figure 28(C) shows a perspective view of the large scale computer 5600. The large scale computer 5600 shown in Figure 28(C) has a rack 5610 housing a plurality of rack-mounted computers 5620. The large scale computer 5600 may also be called a supercomputer.

[0499] The computer 5620 can have the configuration shown in the perspective view of Fig. 28(D), for example. In Fig. 28(D), the computer 5620 has a motherboard 5630, and the motherboard 5630 has a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has a connection terminal 5623, a connection terminal 5624, and a connection terminal 5625, each of which is connected to the motherboard 5630.

[0500] A PC card 5621 shown in Fig. 28(E) is an example of a processing board including a CPU, a GPU, a storage device, and the like. The PC card 5621 has a board 5622. The board 5622 also has a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629. Note that, although semiconductor devices other than the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 are illustrated in Fig. 28(E), for those semiconductor devices, the following description of the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 may be referred to.

[0501] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of a motherboard 5630, and functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0502] The connection terminals 5623, 5624, and 5625 can be interfaces for supplying power and inputting signals to the PC card 5621, for example. They can also be interfaces for outputting signals calculated by the PC card 5621, for example. Examples of the standards for the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). In addition, when a video signal is output from the connection terminals 5623, 5624, and 5625, examples of the standards for each include HDMI (registered trademark).

[0503] The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.

[0504] The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 and the board 5622 can be electrically connected to each other by, for example, soldering the terminals to wiring provided on the board 5622 by a reflow method. Examples of the semiconductor device 5627 include an FPGA, a GPU, and a CPU. For example, the electronic component 730 can be used as the semiconductor device 5627.

[0505] The semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected to each other by, for example, soldering the terminals to wiring provided on the board 5622 by a reflow method. The semiconductor device 5628 can be, for example, a memory device. For example, the electronic component 700 can be used as the semiconductor device 5628.

[0506] The mainframe 5600 can also function as a parallel computer. By using the mainframe 5600 as a parallel computer, it is possible to perform large-scale calculations necessary for learning and inference of artificial intelligence, for example.

[0507] [Space equipment] The semiconductor device of one embodiment of the present invention can be suitably used in space equipment, such as equipment for processing and storing data.

[0508] The semiconductor device of one embodiment of the present invention can include an OS transistor. The OS transistor has small changes in electrical characteristics due to radiation exposure. In other words, the OS transistor has high resistance to radiation and can be preferably used in an environment where radiation may be incident. For example, the OS transistor can be preferably used in outer space.

[0509] Fig. 29 shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 includes a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. In Fig. 29, a planet 6804 is shown in outer space. Note that outer space refers to an altitude of 100 km or more, for example, but the outer space described in this specification may include the thermosphere, mesosphere, and stratosphere.

[0510] 29, a battery management system (also referred to as BMS) or a battery control circuit may be provided for the secondary battery 6805. The use of an OS transistor in the battery management system or the battery control circuit is preferable because it has low power consumption and high reliability even in space.

[0511] Furthermore, outer space is an environment with radiation levels 100 times higher than on the ground. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, as well as particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0512] When sunlight is irradiated onto the solar panel 6802, power required for the operation of the artificial satellite 6800 is generated. However, for example, in a situation where the solar panel is not irradiated with sunlight or where the amount of sunlight irradiated onto the solar panel is small, the amount of power generated is small. Therefore, there is a possibility that the power required for the operation of the artificial satellite 6800 is not generated. In order to operate the artificial satellite 6800 even under a situation where the generated power is small, it is preferable to provide a secondary battery 6805 in the artificial satellite 6800. Note that the solar panel may be called a solar cell module.

[0513] The artificial satellite 6800 can generate a signal. The signal is transmitted via an antenna 6803, and can be received by, for example, a receiver installed on the ground or another artificial satellite. By receiving the signal transmitted by the artificial satellite 6800, the position of the receiver that received the signal can be measured. As described above, the artificial satellite 6800 can constitute a satellite positioning system.

[0514] The control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device. Note that the semiconductor device according to one embodiment of the present invention is preferably used for the control device 6807. The OS transistor has smaller fluctuations in electrical characteristics due to radiation exposure than a Si transistor. That is, the OS transistor has high reliability even in an environment where radiation may be incident, and can be preferably used.

[0515] The artificial satellite 6800 can also be configured to have a sensor. For example, by configuring the artificial satellite 6800 to have a visible light sensor, the artificial satellite 6800 can have a function of detecting sunlight reflected from an object on the ground. Or, by configuring the artificial satellite 6800 to have a thermal infrared sensor, the artificial satellite 6800 can have a function of detecting thermal infrared rays emitted from the earth's surface. From the above, the artificial satellite 6800 can have a function as, for example, an earth observation satellite.

[0516] Note that in this embodiment, an artificial satellite is given as an example of space equipment, but the present invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.

[0517] As described above, OS transistors have the excellent advantages of being able to achieve a wider memory bandwidth and having higher radiation resistance than Si transistors.

[0518] [Data Center] The semiconductor device according to one embodiment of the present invention can be suitably used in a storage system applied to a data center or the like. The data center is required to perform long-term management of data, such as by ensuring the immutability of the data. In order to manage data for a long period of time, it is necessary to increase the size of the building, for example, by installing storage and servers for storing a huge amount of data, by securing a stable power source for holding the data, or by securing cooling equipment required for holding the data.

[0519] By using the semiconductor device of one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and to miniaturize the semiconductor device that stores data. This makes it possible to miniaturize the storage system, the power source for storing data, and the cooling equipment. As a result, it is possible to reduce the space required for the data center.

[0520] In addition, the semiconductor device of one embodiment of the present invention consumes less power, and thus heat generation from the circuit can be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0521] Fig. 30 shows a storage system applicable to a data center. A storage system 7000 shown in Fig. 30 has a plurality of servers 7001sb as a host 7001 (illustrated as Host Computer). It also has a plurality of storage devices 7003md as a storage 7003 (illustrated as Storage). The host 7001 and storage 7003 are shown connected via a storage area network 7004 (illustrated as SAN: Storage Area Network) and a storage control circuit 7002 (illustrated as Storage Controller).

[0522] The host 7001 corresponds to a computer that accesses data stored in the storage 7003. The hosts 7001 may be connected to each other via a network.

[0523] Although the storage 7003 uses flash memory to shorten the data access speed, that is, the time required to store and output data, this time is significantly longer than the time required by DRAM that can be used as cache memory in the storage 7003. In a storage system, in order to solve the problem of the long access speed of the storage 7003, a cache memory is usually provided in the storage 7003 to shorten the data storage and output.

[0524] The above-mentioned cache memory is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003, and then output to the host 7001 or the storage 7003.

[0525] By using OS transistors as transistors for storing data in the cache memory, the frequency of refresh can be reduced and power consumption can be reduced by holding a potential corresponding to the data. In addition, by stacking memory cell arrays, the storage can be made smaller.

[0526] Note that the application of the semiconductor device of one embodiment of the present invention to any one or more selected from electronic components, electronic devices, mainframes, space equipment, and data centers is expected to have an effect of reducing power consumption. As a result, while energy demand is expected to increase with the performance or integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention can reduce emissions of greenhouse gases such as carbon dioxide (CO2). In addition, the semiconductor device of one embodiment of the present invention is also effective as a measure against global warming because of its low power consumption.

[0527] The configurations, structures, methods, and the like described in this embodiment can be used in appropriate combination with the configurations, structures, methods, and the like described in other embodiments. [Explanation of symbols]

[0528] ADDR signal BL[1] Wiring BL[j] Wiring BL[n] Wiring BL_A wiring BL_B wiring BL wiring BW signal CE signal CLK signal EN_data signal GBL_A wiring GBL_B wiring GBL wiring GW signal MUX Select Signal PL[1] Wiring PL[i] wiring PL[m] Wiring PL wiring RDA signal RE control signal VHH wiring VLL wiring VPC intermediate potential WAKE signal WDA signal WE control signal WL[1] Wiring WL[i] Wiring WL[m] Wiring WL wiring 10[1,1] memory cell 10[i,j] memory cell 10[m,n] memory cells 10_A Memory Cell 10_B Memory Cell 10 Memory Cells 11a Transistor 11b Transistor 11c Transistor 11 Transistor 12a Capacitive element 12 Capacitive element 20[1] Memory array 20[2] Memory array 20[5] Memory array 20[m] memory array 20 Memory Array 21 Drive circuit 22 PSW 23 PSW 31 Peripheral circuits 32 Control circuit 33 Voltage Generation Circuit 41 Peripheral circuits 42 Line Decoder 43 Line Driver 44 Column Decoder 45 row driver 46 Sense Amplifier 47 Input circuit 48 Output circuit 50 Functional Layers 51_A Functional circuit 51_B Functional circuit 51 Functional Circuit 52_a Transistor 52_b Transistor 52 Transistor 53_a Transistor 53_b Transistor 53 Transistor 54_a Transistor 54_b Transistor 54 Transistor 55_a Transistor 55_b Transistor 55 Transistor 70[1] Repeating unit 70 repeat units 71_A Precharge circuit 71_B Precharge circuit 72_A Switch circuit 72_B Switch circuit 73 Write / read circuit 81_1 Transistor 81_3 Transistor 81_4 Transistor 81_6 Transistor 82_1 Transistor 82_2 Transistor 82_3 Transistor 82_4 Transistor 83_A Switch 83_B Switch 83_C Switch 83_D Switch 153 Conductors 154 Insulators 160a Conductor 160b conductor 160 Conductors 200 Transistors 205a Conductor 205b Conductor 205 Conductors 207 Conductors 208 Insulator 209 Conductors 210 Insulators 212 Insulators 214 Insulators 215 Insulators 216 Insulators 221 Insulators 222 Insulators 224f Insulating film 224 Insulators 230a Oxide 230af oxide film 230b Oxide 230bf oxide film 230 Oxides 240a Conductor 240b conductor 240 Conductors 241 Insulators 242_1 Conductor 242_1f Conductive film 242_2 Conductors 242_2f Conductive film 242a Conductor 242b Conductor 250a Insulator 250A Insulating Film 250Aa insulating film 250Ab Insulating Film 250Ac Insulating Film 250b insulator 250c insulator 250d insulation 250 Insulator 255a Insulator 255A Insulating film 255b Insulator 255 Insulator 256A Insulating film 256 Insulator 260a Conductor 260A Conductive Film 260b conductor 260B Conductive film 260 Conductors 261 Conductors 271a Insulators 271b Insulators 271f Insulating film 271 Insulators 275 Insulators 280 Insulator 282 Insulators 283 Insulators 284 Insulators 285 Insulators 300A storage device 300 storage device 310 Transistor 311 Substrate 313 Semiconductor area 314a Low resistance area 314b Low resistance region 315 Insulators 316 Conductors 320 Insulator 322 Insulators 324 Insulators 326 Insulators 328 Conductors 330 Conductors 700 Electronic Components 702 Printed Circuit Board 704 Mounting Board 710 Semiconductor Devices 711 Mold 712 rand 713 Electrode Pads 714 Wire 715 Drive Circuit Layer 716 Memory layer 730 Electronic Components 731 Interposer 732 Package Substrate 733 Electrode 735 Semiconductor Devices 1200 chips 1201 Package substrate 1202 Bump 1203 Motherboard 1204 GPU Module 1211 CPU 1212 GPU 1213 Analog Calculation Unit 1214 Memory Controller 1215 Interface 1216 Network Circuit 1221 DRAM 1222 Flash Memory 5600 large computer 5610 Rack 5620 Calculator 5621 PC Card 5622 Board 5623 Connection terminal 5624 Connection terminal 5625 Connection terminal 5626 Semiconductor equipment 5627 Semiconductor equipment 5628 Semiconductor equipment 5629 Connection terminal 5630 Motherboard 5631 Slots 6500 Electronic equipment 6501 Case 6502 Display section 6503 Power button 6504 Button 6505 Speaker 6506 Microphone 6507 Camera 6508 Light source 6509 Control Unit 6600 Electronic equipment 6611 Case 6612 Keyboard 6613 Pointing Device 6614 External connection port 6615 Display section 6616 Control Unit 6800 satellite 6801 Aircraft 6802 Solar Panel 6803 Antenna 6804 Planet 6805 Secondary battery 6807 Control Unit 7000 Storage System 7001sb Server 7001 Host 7002 Storage control circuit 7003md storage device 7003 Storage

Claims

1. forming an oxide on a substrate, a first conductor on the oxide, and a second conductor on the first conductor; forming a first insulator over the oxide, the first conductor, and the second conductor; forming an opening in the first insulator; the second conductor is divided into a third conductor and a fourth conductor in a region overlapping with the opening; depositing a second insulator over the oxide and the first insulator, the second insulator comprising a nitride insulator; depositing a third insulator having an oxide insulator on the second insulator; processing the second insulator and the third insulator to form a fourth insulator in contact with a side surface of the first insulator, a side surface of the third conductor, and a side surface of the fourth conductor, and a fifth insulator in contact with a side surface and an upper surface of the fourth insulator; processing the first conductor using the fourth insulator and the fifth insulator as a mask, and dividing the first conductor into a fifth conductor and a sixth conductor; removing the fifth insulator; The oxide is subjected to a heat treatment in an atmosphere containing oxygen, depositing a sixth insulator to cover the oxide, the first insulator, the fourth insulator, a side surface of the fifth conductor, and a side surface of the sixth conductor; depositing a seventh conductor on the sixth insulator; A method for manufacturing a semiconductor device, comprising: processing the sixth insulator and the seventh conductor by CMP treatment to form a seventh insulator and an eighth conductor inside the opening.

2. In claim 1, the second insulator is formed by depositing silicon nitride using a PEALD method.

3. In claim 2, the third insulator is formed by depositing silicon oxide using a PEALD method.

4. In claim 1, The method for manufacturing a semiconductor device, wherein the first conductor is formed by depositing tantalum nitride by sputtering.

5. In claim 4, the second conductor is formed by depositing tungsten by sputtering.

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