Photoelectric conversion device, apparatus, and laminate

Abstract

To achieve both optical characteristics and miniaturization of a photoelectric conversion device.SOLUTION: The photoelectric conversion device has a first substrate having a photoelectric conversion element and a second substrate having an amplifying transistor for amplifying electrons, which are signal charges output from the photoelectric conversion element. The photoelectric conversion element includes an N-type semiconductor region for storing the electrons. The amplifying transistor is a P-type MOS transistor.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present invention relates to a photoelectric conversion device, a device, and a laminate. [Background technology]

[0002] In photoelectric conversion devices, various pixel configurations have been considered to improve image quality. Patent Document 1 describes a solid-state imaging element configured to suppress 1 / f noise by forming an amplifying transistor with a P-type MOS transistor (PMOS). Patent Document 2 describes an imaging device configured to separate a substrate including a photoelectric conversion element from a substrate including an amplifying transistor and stack the substrates to miniaturize pixels while ensuring the transistor size. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2005-268295 A [Patent Document 2] International Publication No. 2020 / 105713 Summary of the Invention [Problem to be solved by the invention]

[0004] However, the solid-state imaging device described in Patent Document 1 has a hole-accumulation type photoelectric conversion element, which requires a longer transfer time to a floating diffusion (FD) section compared to an electron-accumulation type photoelectric conversion element with high mobility, and is not suitable for high-speed imaging.

[0005] An object of the present invention is to provide a photoelectric conversion device that can be driven at high speed, can effectively suppress 1 / f noise in pixels, and is suitable for miniaturization. [Means for solving the problem]

[0006] According to one disclosure of the present specification, there is provided a photoelectric conversion device comprising a first substrate having a photoelectric conversion element and a second substrate having an amplifying transistor that amplifies electrons, which are signal charges output from the photoelectric conversion element, wherein the photoelectric conversion element has an N-type semiconductor region that accumulates the electrons, and the amplifying transistor is a P-type MOS transistor. Effect of the Invention

[0007] According to the present invention, in a photoelectric conversion device having a pixel structure suitable for miniaturization, it is possible to output a high-quality signal with high speed driving and suppressed 1 / f noise of the pixel. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram illustrating a photoelectric conversion device according to an embodiment. [Diagram 2] FIG. 1 is a circuit diagram illustrating a photoelectric conversion device according to a first embodiment; [Diagram 3] FIG. 1 is a circuit diagram illustrating a photoelectric conversion device according to a first embodiment; [Figure 4] FIG. 1 is a circuit diagram illustrating a photoelectric conversion device according to a first embodiment; [Diagram 5] FIG. 1 is a cross-sectional view illustrating a photoelectric conversion device according to a first embodiment. [Figure 6] 1 is a cross-sectional view illustrating a method for manufacturing a photoelectric conversion device according to a first embodiment. [Figure 7] 1 is a cross-sectional view illustrating a method for manufacturing a photoelectric conversion device according to a first embodiment. [Figure 8] 1 is a cross-sectional view illustrating a method for manufacturing a photoelectric conversion device according to a first embodiment. [Figure 9] 1 is a cross-sectional view illustrating a method for manufacturing a photoelectric conversion device according to a first embodiment. [Figure 10] 1 is a cross-sectional view illustrating a method for manufacturing a photoelectric conversion device according to a first embodiment. [Figure 11] 1 is a cross-sectional view illustrating a method for manufacturing a photoelectric conversion device according to a first embodiment. [Figure 12] 11A to 11C are cross-sectional views illustrating a method for manufacturing a photoelectric conversion device according to a second embodiment. [Figure 13] 11A to 11C are cross-sectional views illustrating a method for manufacturing a photoelectric conversion device according to a second embodiment. [Figure 14] FIG. 11 is a circuit diagram illustrating a photoelectric conversion device according to a third embodiment. [Figure 15] FIG. 11 is a circuit diagram illustrating a photoelectric conversion device according to a third embodiment. [Figure 16] FIG. 11 is a circuit diagram illustrating a photoelectric conversion device according to a third embodiment. [Figure 17] 11A to 11C are cross-sectional views illustrating a method for manufacturing a photoelectric conversion device according to a third embodiment. [Figure 18] 11A to 11C are cross-sectional views illustrating a method for manufacturing a photoelectric conversion device according to a third embodiment. [Figure 19] FIG. 13 is a schematic diagram illustrating a device according to a fourth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Each embodiment will be described below with reference to the drawings. Note that the following embodiments do not limit the invention according to the claims. Although a plurality of features are described in the embodiments, not all of these features are necessarily essential to the invention, and the features may be combined in any manner. Furthermore, in the attached drawings, the same or similar configurations are given the same reference numbers, and duplicated descriptions are omitted. Furthermore, in each embodiment described below, a sensor for imaging will be mainly described as an example of a photoelectric conversion device. However, each embodiment is not limited to a sensor for imaging, and can be applied to other examples of photoelectric conversion devices. For example, there are an imaging device, a distance measuring device (a device for distance measurement using focus detection or TOF (Time Of Flight), a photometric device (a device for measuring the amount of incident light, etc.), and the like.

[0010] In this specification, terms indicating specific directions or positions (for example, "upper", "lower", "right", "left" and other terms including these terms) are used as necessary. The use of these terms is for the purpose of facilitating understanding of the embodiments with reference to the drawings, and the technical scope of the present invention is not limited by the meaning of these terms.

[0011] Metallic members such as wiring and pads described in this specification may be composed of a single metal element or may be a mixture (alloy). For example, wiring described as copper wiring may be composed of a single copper element or may be composed mainly of copper and further contain other components. Also, for example, a pad connected to an external terminal may be composed of a single aluminum element or may be composed mainly of aluminum and further contain other components. The copper wiring and aluminum pads shown here are examples and can be changed to various metals. Also, the wiring and pads shown here are examples of metallic members used in semiconductor devices and can be applied to other metallic members.

[0012] In this specification, a "pixel transistor" is a transistor for reading out a signal charge output from a photoelectric conversion element according to the amount of received light, and is a transistor that can be shared by multiple photoelectric conversion elements (pixels). For example, a pixel transistor includes at least an amplifier transistor that amplifies and outputs the signal charge output from the photoelectric conversion element.

[0013] In this specification, the phrase "electrically connecting component A and component B" does not necessarily mean that component A and component B are directly connected to each other. For example, even if another component C is connected between component A and component B, it is sufficient that they are electrically connected to each other.

[0014] A configuration common to the photoelectric conversion devices according to the respective embodiments of the present invention will be described with reference to FIG.

[0015] FIG. 1 is an example of a block diagram showing a schematic configuration of a photoelectric conversion device 1 applied to each embodiment.

[0016] 1, the photoelectric conversion device 1 includes three substrates: a first substrate 10, a second substrate 20, and a third substrate 30. The photoelectric conversion device 1 has a three-dimensional structure formed by bonding these three substrates together. The first substrate 10, the second substrate 20, and the third substrate 30 are stacked in this order.

[0017] The first substrate 10 has a first semiconductor member 11 provided with a plurality of pixels 12 that perform photoelectric conversion. The plurality of pixels 12 are arranged in a matrix in a pixel region 13 of the first substrate 10. Each of the plurality of pixels 12 includes an electron accumulation type photoelectric conversion element, and outputs a pixel signal according to the amount of incident light. The photoelectric conversion element also includes an N-type semiconductor region that accumulates electrons.

[0018] The second substrate 20 has a second semiconductor member 21 provided with a readout circuit 22 that outputs a pixel signal based on the charge output from the pixel 12. The readout circuit 22 includes a pixel transistor. The second substrate 20 also has a plurality of control lines 23 extending in the row direction and a plurality of vertical output lines 24 extending in the column direction. The control lines 23 are connected to a vertical drive circuit 33 described later. Each of the vertical output lines 24 is connected to the readout circuits 22 arranged in the column direction and forms a signal line common to these readout circuits 22. The vertical output lines 24 are connected to a column signal processing unit 34 described later.

[0019] The third substrate 30 has a third semiconductor member 31 provided with a logic circuit 32 that processes pixel signals. The logic circuit 32 has, for example, a vertical drive circuit 33, a column signal processing unit 34, a horizontal drive circuit 35, an output circuit 36, and a system control unit 37.

[0020] The vertical drive circuit 33 is a control circuit having a function of receiving a control signal supplied from the system control unit 37, generating a control signal for driving the pixels 12 and the readout circuit 22, and supplying the control signal to the pixels 12 and the readout circuit 22 via a control line 23. The signal read out from the readout circuit 22 on a row-by-row basis is input to a column signal processing unit 34 via a vertical output line 24.

[0021] The column signal processing unit 34 has a plurality of column circuits, each of which includes a processing circuit and a signal holding circuit, provided in correspondence with each of the vertical output lines 24. The processing circuit has a function of performing predetermined signal processing on pixel signals output via the corresponding output line. Examples of the signal processing performed by the processing circuit include amplification processing, correction processing using correlated double sampling (CDS), and analog-to-digital conversion (AD conversion). The signal holding circuit functions as a memory for holding the pixel signals processed by the processing circuit.

[0022] The horizontal drive circuit 35 is a control circuit having a function of receiving a control signal supplied from the system control unit 37, generating a control signal for reading out pixel signals from the column signal processing unit 34, and supplying the control signal to the column signal processing unit 34. The horizontal drive circuit 35 sequentially scans the column circuits of each column of the column signal processing unit 34, and outputs the pixel signals held in each of them to the output circuit 36.

[0023] The output circuit 36 ​​has an external interface circuit, and is a circuit for outputting the signals processed by the column signal processing unit 34 to the outside of the photoelectric conversion device 1. Note that the external interface circuit included in the output circuit 36 ​​is not particularly limited.

[0024] The system control unit 37 is a control circuit that generates control signals for controlling the operations of the vertical drive circuit 33, the column signal processing unit 34, the horizontal drive circuit 35, etc., and supplies them to each functional block.

[0025] As described above, each embodiment of the present invention is based on the schematic configuration of a photoelectric conversion device 1 in which three substrates are three-dimensionally stacked as described in Fig. 1. The substrate on which the photoelectric conversion elements are formed and the substrate on which the pixel transistors are formed are separated, and the respective substrates are stacked. By doing so, it is possible to ensure space for arranging the pixel transistors even when the pixel pitch is reduced, and this can be considered to be a photoelectric conversion device configuration suitable for miniaturization.

[0026] The schematic configuration of this photoelectric conversion device 1 can be applied to each of the embodiments described below.

[0027] First embodiment The configuration of a photoelectric conversion device 1 according to a first embodiment of the present invention will be described with reference to Fig. 2 to Fig. 11. Note that the same components as those in Fig. 1 are given the same reference numerals, and the description of these components may be omitted or simplified. The schematic configuration of the photoelectric conversion device 1 according to this embodiment is as described in Fig. 1.

[0028] In the following, the photoelectric conversion device 1 having the schematic configuration shown in FIG. 1 will be described, focusing on characteristic aspects of this embodiment.

[0029] 2 to 4 are examples of circuit diagrams of the pixel 12 and the readout circuit 22 according to this embodiment. FIG. 2 is a circuit diagram in the case where the output of one pixel 12 is input to one readout circuit 22. Alternatively, a plurality of pixels 12 may share one readout circuit 22, and the number of pixels 12 connected to one readout circuit 22 can be changed to any number. More specifically, FIG. 3 shows a case where two pixels 12 share one readout circuit 22, and FIG. 4 shows a case where four pixels 12 share one readout circuit 22. Here, "shared" refers to the output of a plurality of pixels 12 being input to a common readout circuit 22.

[0030] 2 to 4 have components in common. Therefore, in order to distinguish the components of each pixel 12 from one another, an identification number (1, 2, 3, 4) is added to the end of the reference number of the component of each pixel 12. In the following, when it is necessary to distinguish the components of each pixel 12 from one another, an identification number is added to the end of the reference number of the component of each pixel 12. However, when it is not necessary to distinguish the components of each pixel 12 from one another, the identification number at the end of the reference number of the component of each pixel 12 is omitted.

[0031] A detailed explanation will be given below using FIG. 2, which shows the simplest circuit configuration.

[0032] In the following description, a set of any number of pixels 12 connected to one readout circuit 22 will be referred to as a unit pixel 25. Fig. 2 shows a unit pixel 25(m,n) arranged in the mth row and nth column out of the multiple unit pixels 25. m is an integer from 1 to M, and n is an integer from 1 to N. The circuit configuration of the other unit pixels 25 may be similar to that of the unit pixel 25(m,n).

[0033] 2, the unit pixel 25(m,n) has a photoelectric conversion element PD1, a floating diffusion portion FD1, a transfer transistor TR1, a reset transistor M2, and an amplification transistor M3. The unit pixel 25(m,n) further has a selection transistor M4 and a floating diffusion (FD) capacitance switching transistor M5. Note that, as will be described in detail later, the FD capacitance switching transistor M5 may not be arranged. Also, the selection transistor M4 may not be arranged.

[0034] 2, the reset transistor M2, the amplification transistor M3, the selection transistor M4, and the FD capacitance switching transistor M5 each correspond to a "pixel transistor." The transfer transistor TR1 transfers electrons, which are signal charges output from the photoelectric conversion element PD1, to the amplification transistor M3. The amplification transistor M3 amplifies the electrons, which are signal charges output from the photoelectric conversion element PD1.

[0035] The photoelectric conversion element PD1 is, for example, a photodiode. The photoelectric conversion element PD1 has an anode connected to a reference voltage node and a cathode connected to the source of the transfer transistor TR1. The drain of the transfer transistor TR1 is connected to the drain of the FD capacitance switching transistor M5 and the gate of the amplification transistor M3. The second substrate 20 also has a node to which the drain of the transfer transistor TR1, the drain of the FD capacitance switching transistor M5, and the gate of the amplification transistor M3 are connected. The floating diffusion portion FD1 includes a part of the capacitance component (FD capacitance) and functions as a charge holding portion. The FD capacitance includes the floating diffusion portion FD1 and a parasitic capacitance included in the electrical path from the floating diffusion portion FD1 to the gate of the amplification transistor M3. The source of the FD capacitance switching transistor M5 is connected to the drain of the reset transistor M2. The source of the reset transistor M2 is connected to a node VRES. The node VRES can be set to a voltage in a range larger than the reference voltage GND and smaller than the power supply voltage VDD (first power supply voltage) according to the reset operation of the photoelectric conversion element PD1 and the floating diffusion portion FD1. However, there are limitations to the set voltage range of the node VRES, which will be described later. The drain of the amplifying transistor M3 is connected to a reference voltage node. In this example, the reference voltage node is set to a ground potential. The source of the amplifying transistor M3 is connected to a drain of the selection transistor M4. The source of the selection transistor M4 is connected to a vertical output line 24n. A column current source 40 is connected to the vertical output line 24n.

[0036] The first substrate 10 includes a photoelectric conversion element PD1, a transfer transistor TR1, and a floating diffusion region FD1, the second substrate 20 includes a reset transistor M2, an amplifying transistor M3, a selection transistor M4, and an FD capacitance switching transistor M5, and the third substrate includes a column current source 40.

[0037] The names of the source and drain of a MOS transistor may differ depending on the conductivity type of the transistor and the function of interest. Some or all of the names of the source and drain used in this embodiment may be called by the reversed names.

[0038] The photoelectric conversion element PD in this embodiment is formed of an electron accumulation type photodiode that uses electrons as signal charges among electron-hole pairs generated by the incidence of light. Since the mobility of electrons, which act as carriers, is greater than that of holes, the electron accumulation type photodiode can transfer the accumulated charges to the floating diffusion portion FD at a higher speed than a hole accumulation type photodiode, making it an advantageous configuration for high-speed imaging. In addition, the transfer transistor TR is formed of an N-type MOS transistor (NMOS) suitable for transfer in an electron accumulation type photodiode.

[0039] On the other hand, the pixel transistor in this embodiment is formed of a P-type MOS transistor (PMOS). It is known that the 1 / f noise of a PMOS is one to two orders of magnitude smaller than that of an NMOS. It is also known that when a source follower circuit, which will be described later, is configured with a PMOS, the random telegraph signal (RTS) noise is smaller than that of a source follower circuit configured with an NMOS. Furthermore, in this embodiment, the gate of the pixel transistor includes P-type polysilicon.

[0040] From the above, forming the amplifying transistor M3 from a PMOS can be particularly effective in reducing noise generated in the readout circuit 22. In this way, by adopting a PMOS configuration with relatively low noise for the readout circuit 22, noise such as 1 / f and RTS generated in the readout circuit 22 can be effectively suppressed without increasing the gate size of the pixel transistor or increasing the gate oxide film capacitance.

[0041] In the case of the circuit configuration of Fig. 2, the control line 23m of each row includes four signal lines connected to the gate of the transfer transistor TR1, the gate of the reset transistor M2, the gate of the selection transistor M4, and the gate of the FD capacitance switching transistor M5. A control signal TX1m is supplied from the vertical drive circuit 33 to the gate of the transfer transistor TR1 of the unit pixel 25 of the mth row. A control signal RSTm is supplied from the vertical drive circuit 33 to the gate of the reset transistor M2 of the unit pixel 25 of the mth row. A control signal SELm is supplied from the vertical drive circuit 33 to the gate of the selection transistor M4 of the unit pixel 25 of the mth row. A control signal FDGm is supplied from the vertical drive circuit 33 to the gate of the FD capacitance switching transistor M5 of the unit pixel 25 of the mth row.

[0042] The photoelectric conversion element PD1 converts incident light into an electric charge according to the amount of light (photoelectric conversion) and accumulates the generated electric charge. When the transfer transistor TR1 is turned on, it transfers the electric charge Q of the signal charge held by the photoelectric conversion element PD1 to the floating diffusion FD1. The electric charge Q transferred from the photoelectric conversion element PD1 is held in the FD capacitance. As a result, when the FD capacitance is C, the floating diffusion FD1 becomes a voltage V according to the amount of the electric charge transferred from the photoelectric conversion element PD1 by charge-voltage conversion based on Q=CV.

[0043] The FD capacitance switching transistor M5 is used to switch the capacitance value of the FD capacitance. In general, pixel signals are small when shooting in dark places. If the FD capacitance is large when performing charge-voltage conversion, the voltage V converted by the amplification transistor M3 will be small. On the other hand, in bright places, the pixel signal is large, so if the FD capacitance is not large, the charge of the photoelectric conversion element PD1 will saturate in the floating diffusion region FD1. Furthermore, the FD capacitance is increased so that the voltage V converted by the amplification transistor M3 does not become too large.

[0044] Considering these, when the FD capacitance switching transistor M5 is turned on, the gate capacitance of the FD capacitance switching transistor M5 increases, and the overall FD capacitance increases. On the other hand, when the FD capacitance switching transistor M5 is turned off, the overall FD capacitance decreases. In this way, by switching the FD capacitance switching transistor M5 on and off, the capacitance value of the FD capacitance can be made variable, and the conversion efficiency can be switched. Note that the FD capacitance switching transistor M5 may not be disposed in the readout circuit 22, and the drain of the reset transistor M2 may be connected to the floating diffusion portion FD1.

[0045] When the selection transistor M4 is turned on, it connects the amplification transistor M3 to the vertical output line 24n. The amplification transistor M3 has a drain connected to a reference potential GND and a source supplied with a bias current from the column current source 40 via the selection transistor M4, forming an amplification section (source follower circuit) with the gate as an input node. As a result, the amplification transistor M3 outputs a signal based on the voltage of the floating diffusion section FD to the vertical output line 24n via the selection transistor M4. In this sense, the amplification transistor M3 and the selection transistor M4 are an output section that outputs a pixel signal according to the amount of charge held in the floating diffusion section FD1.

[0046] The reset transistor M2 has a function of controlling the supply of a voltage VRES (second power supply voltage) to the floating diffusion FD1 in order to reset the floating diffusion FD as a charge holding section. When the reset transistor M2 is turned on, it resets the floating diffusion FD1 to a voltage corresponding to the voltage VRES (second power supply voltage). At this time, it is also possible to reset the photoelectric conversion element PD1 to a voltage corresponding to the voltage VRES (second power supply voltage) by simultaneously turning on the transfer transistor TR1.

[0047] The voltage VRES (second power supply voltage) can be set to a voltage range that is greater than the reference voltage GND and smaller than the power supply voltage VDD (first power supply voltage). That is, the voltage VRES (second power supply voltage) supplied to the reset transistor M2 is greater than the reference voltage GND and smaller than the power supply voltage VDD (first power supply voltage). However, it is necessary to appropriately adjust the voltage fluctuation range of the floating diffusion portion FD1 in response to light incident on the photoelectric conversion element PD1 so that it falls within the linear response range of the source follower circuit configured by the amplifying transistor M3 and the column current source 40. In other words, it is necessary to set the MOS transistor (assumed to be a PMOS here) that serves as a constant current load included in the column current source 40 that configures the source follower circuit to a state in which it is always driven in the saturation region regardless of the degree of light incident on the photoelectric conversion element PD1. That is, the closer the voltage VRES (second power supply voltage) is to the power supply voltage VDD (first power supply voltage), the more difficult it becomes for the column current source 40 to operate when shooting in a dark place where the pixel signal is small, and the linear response to light incidence may be lost. Therefore, it may be necessary to set an appropriate voltage VRES (second power supply voltage). Note that the power supply voltage VDD (first power supply voltage) supplied to the amplification transistor M3 is different from the node VRES (second power supply voltage) supplied to the reset transistor M2.

[0048] Furthermore, when the voltage VRES (second power supply voltage) is lowered from the power supply voltage VDD (first power supply voltage), the reset voltage of the photoelectric conversion element PD1 may decrease. Therefore, an appropriate negative bias is applied to the anode (connected to the reference potential in FIG. 2) of the photoelectric conversion element PD1. By doing so, even when the voltage VRES (second power supply voltage) is lowered from the power supply voltage VDD (first power supply voltage), a reset operation equivalent to that performed by the power supply voltage VDD (first power supply voltage) can be performed.

[0049] As described above, by appropriately controlling the pixel transistor, a signal corresponding to the reset voltage of the floating diffusion portion FD and a signal corresponding to the amount of light incident on the photoelectric conversion element PD are read out from each unit pixel 25.

[0050] FIG. 5 is an example of a cross-sectional view corresponding to one unit pixel 25 of the photoelectric conversion device 1 according to this embodiment.

[0051] 5, the photoelectric conversion device 1 according to this embodiment has a first substrate 10, a second substrate 20, and a third substrate 30. The first substrate 10, the second substrate 20, and the third substrate 30 are laminated in this order.

[0052] The first substrate 10 has a first semiconductor member 11 and a first insulating film 130. A photoelectric conversion element PD and a floating diffusion portion FD are arranged on the first semiconductor member 11. Here, the photoelectric conversion element PD includes an N-type semiconductor region 110. In addition, a gate 120 of the transfer transistor TR is arranged on the first insulating film 130.

[0053] The second substrate 20 has a second semiconductor member 21 and a second insulating film 230. A first source / drain region 211 of the pixel transistor is disposed on the second semiconductor member 21. Furthermore, a first gate 220 of the pixel transistor and wiring structures 240, 250 are disposed on the second insulating film 230. Furthermore, an element isolation region 201 may be disposed on the second semiconductor member 21.

[0054] The third substrate 30 has a third semiconductor member 31 and a third insulating film 310. A MOS transistor including a gate and the like are provided on the third semiconductor member 31, and predetermined signal processing units such as an AD conversion circuit unit and a current source 40 can be disposed thereon. In addition, wiring structures 320 and 350 are disposed on the third insulating film 310.

[0055] The first substrate 10, the second substrate 20, and the third substrate 30 can be electrically connected to each other by wiring structures 240, 250, 320, and 350 arranged inside the first insulating film 130, the second semiconductor member 21, the second insulating film 230, and the third insulating film 310. The wiring structures 250 and 350, and the second insulating film 230 and the third insulating film 310 are stacked to face each other, and the wiring structures 250 and 350 are electrically connected to each other. The wiring structure 240 that penetrates the depth position of the second substrate 20 is electrically connected to the floating diffusion portion FD. Furthermore, the wiring structure 240 is electrically connected to the first gate 220.

[0056] The first semiconductor member 11 has a first surface 140 and a second surface 150, and the first surface 140 serves as a light-receiving surface. The first semiconductor member 11, the first insulating film 130, the second semiconductor member 21, the second insulating film 230, the third insulating film 310, and the third semiconductor member 31 are laminated in this order in the direction from the first surface 140 side toward the second surface 150 side.

[0057] Furthermore, on the first semiconductor member 11, optical structures (not shown) such as an inner lens, a color filter layer, and a microlens may be arranged in this order from the first surface 140 side.

[0058] As described above, the photoelectric conversion device according to this embodiment is a stacked sensor and also a back-illuminated sensor.

[0059] Next, a method for manufacturing the photoelectric conversion device according to this embodiment will be described with reference to Fig. 6 to Fig. 11. Fig. 6 to Fig. 11 are examples of cross-sectional views showing the steps of the method for manufacturing the photoelectric conversion device according to this embodiment.

[0060] First, as shown in FIG. 6, a photoelectric conversion element PD and a floating diffusion portion FD are formed in the first semiconductor member 11. An element isolation region (not shown) may also be formed in the first semiconductor member 11. Here, an N-type semiconductor region 110 is formed inside the photoelectric conversion element PD. The floating diffusion portion FD includes an N-type semiconductor region. A gate 120 of the transfer transistor TR is formed on the second surface 150. Here, the gate 120 is formed of N-type polysilicon. Here, the N-type polysilicon can be formed by introducing a dopant gas during film formation using, for example, a low-pressure CVD method. It can also be formed by injecting N-type impurities using an ion implantation method after the polysilicon film is formed. Thereafter, a first insulating film 130 is formed on the second surface 150. Here, the first semiconductor member 11 is, for example, a silicon substrate.

[0061] 7, the second semiconductor member 21 is disposed on the first insulating film 130. Here, for example, the first semiconductor member 11 and the second semiconductor member 21 can be bonded via the first insulating film 130, which is a silicon oxide film.

[0062] 8, the second semiconductor member 21 is thinned. Furthermore, an element isolation region 201 and a first well region 202 are formed in the second semiconductor member 21. Here, the first well region 202 is electrically isolated by the element isolation region 201. Note that the first well region 202 includes an N-type semiconductor region.

[0063] Thereafter, a P-type first polysilicon layer 220A is formed on the second semiconductor member 21 for forming the gate of a pixel transistor. Here, the P-type polysilicon can be formed by introducing a dopant gas during film formation using, for example, a low-pressure CVD method. It can also be formed by injecting P-type impurities using an ion implantation method after the formation of a polysilicon film.

[0064] 9, a first gate 220 of a transistor is formed on the second semiconductor member 21 using photolithography and etching techniques. After the first gate 220 is formed, a P-type first source / drain region 211 is formed in the second semiconductor member 21 using ion implantation techniques. This forms a P-type pixel transistor having a first gate 220 containing P-type polysilicon. That is, a reset transistor M2, an amplification transistor M3, a selection transistor M4, an FD capacitance switching transistor M5, and the like for driving the photoelectric conversion element PD and the floating diffusion portion FD formed in the first semiconductor member 11 are formed in the second semiconductor member 21.

[0065] 10, after the pixel transistors are formed, a second insulating film 230 is formed on the second semiconductor member 21. Thereafter, wiring structures 240, 250 are formed inside the second insulating film 230. The wiring structure 240 is formed so as to penetrate the second substrate 20 at a depth position. The wiring structure 240 is electrically connected to the floating diffusion region FD and the first gate 220. That is, the first semiconductor member 11 and the second semiconductor member 21 are electrically connected by the wiring structure 240.

[0066] Here, the pixel transistor formed in the second semiconductor member 21 is not limited to a method of forming it after laminating the first semiconductor member 11 and the second semiconductor member 21. It is also possible to bond the first semiconductor member 11 and the second semiconductor member 21 after previously forming the pixel transistor in the second semiconductor member 21. Note that the structure shown in FIG. 10 may be a laminate including the first substrate 10 and the second substrate 20.

[0067] Thereafter, as shown in FIG. 11, the third substrate 30 in which the third insulating film 310 and the wiring structures 320, 350 are formed on the third semiconductor member 31 is laminated on the second substrate 20. That is, the third substrate 30 is laminated on a laminate including the first substrate 10 and the second substrate 20. The second substrate 20 and the third substrate 30 are laminated so that the wiring structures 250 and 350 and the second insulating film 230 and the third insulating film 310 face each other, and the wiring structures 250 and 350 are electrically connected. Here, for example, the wiring structures 250, 350 include a conductive material mainly made of Cu, and the second insulating film 230 and the third insulating film 310 include a silicon oxide film. Thereby, the second substrate 20 and the third substrate 30 can be bonded by the metal bonding of Cu-Cu and the covalent bond of the silicon oxide film. Here, the second insulating film 230 and the third insulating film 310 are not limited to silicon oxide films, and can be composed of a plurality of films.

[0068] Furthermore, the method of laminating the second substrate 20 and the third substrate 30 is not limited to the Cu-Cu metal bonding and the covalent bond of the silicon oxide film, but may also be bonding between insulating films.

[0069] Moreover, the first semiconductor member 11 is thinned after the second substrate 20 and the third substrate 30 are laminated. After that, optical structures such as an inner lens, a color filter layer, and a microlens may be formed on the first surface 140.

[0070] Thus, in the photoelectric conversion device 1 according to this embodiment, the photoelectric conversion element PD includes an N-type semiconductor region 110, and the pixel transistor included in the readout circuit 22 is formed of a PMOS. When MOS transistors of different conductivity types are formed on the same substrate, physical space is required to electrically separate the well regions of the transistors of each conductivity type, making the configuration difficult to miniaturize.

[0071] 5, the pixel 12 and the pixel transistor included in the readout circuit 22 are formed on different substrates that are physically separated from each other. Therefore, there is no need to provide additional space for separation in the well regions of the two elements (pixel 12 and pixel transistor) structurally. In other words, when the photoelectric conversion element PD is formed of an electron storage photodiode, even if the pixel transistor is formed of a PMOS, the layout efficiency is less likely to decrease compared to the case of an NMOS.

[0072] Furthermore, when forming MOS transistors of different conductivity types on the same substrate, mask switching is required when forming the MOS transistors. However, when only a single conductivity type MOS transistor is formed on each substrate and the substrates are stacked, mask switching is not required when forming the MOS transistors.

[0073] Therefore, according to this embodiment, the electron accumulation type photoelectric conversion element is formed on the first substrate, and the amplifying transistor is formed as a PMOS on the second substrate, which makes it possible to provide a photoelectric conversion device that is suitable for miniaturization, can be driven at high speed, and can effectively suppress 1 / f noise in pixels.

[0074] Second Embodiment The configuration of a photoelectric conversion device 1 according to a second embodiment of the present invention will be described with reference to Fig. 12 and Fig. 13. Fig. 12 and Fig. 13 are examples of process cross-sectional views showing a manufacturing method for the photoelectric conversion device 1 according to this embodiment. Note that the same components as those in the first embodiment are given the same reference numerals, and the description of these components may be omitted or simplified.

[0075] In this embodiment, the conductivity type of the PMOS gate is different from that in the first embodiment. In the first embodiment, an example was given in which the gate of the pixel transistor included in the readout circuit 22 is formed of P-type polysilicon. However, in this embodiment, an example will be described in which the gate of the pixel transistor is formed of N-type polysilicon. Note that FIG. 1 showing a schematic configuration of the photoelectric conversion device 1 in this embodiment, FIGS. 2 to 4 showing an example of the pixel 12 and readout circuit 22, and FIGS. 5 to 7 showing schematic cross sections are similar to those in the first embodiment.

[0076] Hereinafter, a method for manufacturing the photoelectric conversion device 1 in which the gates of the pixel transistors included in the readout circuit 22 of this embodiment are formed from N-type polysilicon will be described. Note that the process up to laminating the second semiconductor member 21 is similar to that of the first embodiment, and therefore a description thereof will be omitted.

[0077] As shown in FIG. 12, an element isolation region 201 and a first well region 202 are formed in the second semiconductor member 21. Here, the first well region 202 includes an N-type semiconductor region. Then, a second polysilicon layer 221A is formed on the second semiconductor member 21 by N-type polysilicon. Here, the N-type polysilicon can be formed by introducing a dopant gas during film formation using, for example, a low-pressure CVD method. It can also be formed by injecting N-type impurities using an ion implantation method after the polysilicon film is formed. Next, a hard mask layer 225A that functions as a mask when patterning the gate is formed is formed on the second polysilicon layer 221A.

[0078] Next, as shown in FIG. 13, the second gate 221 and a hard mask layer 225 are formed on the gate by using photolithography and etching techniques. After that, a P-type first source / drain region 211 is formed by using ion implantation techniques. At this time, the hard mask layer 225 serves as a mask during source / drain implantation, suppressing the implantation of P-type impurities into the second gate 221. This makes it possible to form a P-type transistor having a low-resistance N-type polysilicon gate. Here, the P-type impurity concentration during ion implantation performed to form the P-type first source / drain region 211 is made relatively lower than the N-type impurity concentration in the second gate 221. By doing so, it is also possible to form a P-type transistor having an N-type gate without using the hard mask layer 225.

[0079] As described above, according to this embodiment, the electron accumulation type photoelectric conversion element is formed on the first substrate, and the amplifying transistor is formed as a PMOS on the second substrate. By doing so, it is possible to provide a photoelectric conversion device that is suitable for miniaturization, can be driven at high speed, and can effectively suppress 1 / f noise of pixels.

[0080] The conductivity type of the polysilicon of the gate can be a parameter that determines the threshold voltage of the MOS transistor including the gate, depending on the work function difference with the semiconductor substrate facing the gate via an insulating film. By appropriately setting the conductivity type of the polysilicon of the gate of the pixel transistor included in the readout circuit 22, it becomes possible to effectively control the threshold voltage even under conditions where the voltage width applied to the gate is limited.

[0081] Third embodiment The configuration of a photoelectric conversion device 1 according to a third embodiment of the present invention will be described with reference to Fig. 14 to Fig. 18. Note that the same components as those in the first and second embodiments are denoted by the same reference numerals, and the description of these components may be omitted or simplified.

[0082] In this embodiment, the conductivity type of the pixel transistor is different from that of the first and second embodiments. In the first and second embodiments, an example in which the pixel transistors are all PMOS is given. However, in this embodiment, an example in which the pixel transistors include two MOS transistors of different conductivity types, NMOS and PMOS, will be described. Note that FIG. 1 showing the schematic configuration of the photoelectric conversion device 1 and FIGS. 5 to 7 showing the schematic cross sections are similar to those of the first and second embodiments. However, the circuit configuration of the unit pixel 25 is different from that of the first and second embodiments.

[0083] 14 to 16 are examples of circuit diagrams of the pixel 12 and the readout circuit 22 according to this embodiment. Here, an example will be described in which, in the MOS transistors included in the readout circuit 22, the reset transistor M2 and the FD capacitance switching transistor M5 are formed of NMOS, and the amplification transistor M3 and the selection transistor M4 are formed of PMOS. In this example, the reset transistor M2 and the FD capacitance switching transistor M5 can be formed with the same conductivity type as the transfer transistor TR included in the pixel 12. Furthermore, a PMOS, which is effective in reducing 1 / f and RTS noise, can be applied to the amplification transistor M3, and this can be an effective configuration for miniaturization and low noise of the readout circuit 22.

[0084] It should be noted that the combination of the conductivity types of the pixel transistors included in the readout circuit 22 is not limited to the example described here.

[0085] 14 is a circuit diagram in the case where one pixel 12 corresponds to one readout circuit 22. In this embodiment as well, the number of pixels 12 connected to one readout circuit 22 can be changed to any number. More specifically, FIG. 15 shows a case where two pixels 12 share one readout circuit 22, and FIG. 16 shows a case where four pixels 12 share one readout circuit 22. Here, "shared" refers to the output of multiple pixels 12 being input to a common readout circuit 22.

[0086] 14 to 16 have common components. Therefore, in order to distinguish the components of each pixel 12 from one another, an identification number (1, 2, 3, 4) is added to the end of the reference numeral of the components of each pixel 12.

[0087] Hereinafter, a method for manufacturing the photoelectric conversion device 1 in which the readout circuit 22 of this embodiment includes MOS transistors of two different conductivity types, NMOS and PMOS, will be described. Figures 17 and 18 are examples of process cross-sectional views showing the method for manufacturing the photoelectric conversion device 1 according to this embodiment. Note that the process up to laminating the semiconductor member 21 is similar to that of the first embodiment, and therefore a description thereof will be omitted.

[0088] As shown in FIG. 17, an element isolation region 201, a second well region 203, and a third well region 204 are formed in the second semiconductor member 21. Here, the second well region 203 and the third well region 204 each include a semiconductor region having a different polarity. Also, the third polysilicon layer 222A and the fourth polysilicon layer 223A can each be a polysilicon layer of any conductive type. Here, the polysilicon can be formed by using, for example, a low-pressure CVD method. After the polysilicon film is formed, impurities are injected into any region by ion implantation using a photolithography technique, thereby forming N-type and P-type polysilicon layers. Next, a hard mask layer 225A that functions as a mask when patterning the gate is formed on the third polysilicon layer 222A and the fourth polysilicon layer 223A.

[0089] Next, as shown in FIG. 18, the third gate 222, the fourth gate 223, and a hard mask layer 225 are formed on each gate by using photolithography and etching techniques. After that, the second source / drain region 212 having a polarity different from that of the second well region 203 is formed by using ion implantation techniques. Similarly, the third source / drain region 213 having a polarity different from that of the third well region 204 is formed. At this time, the hard mask layer 225 serves as a mask during source / drain implantation, and suppresses the implantation of impurities having a polarity different from that of the gate into the third gate 222 and the fourth gate 223. This makes it possible to form a transistor having a low-resistance polysilicon gate. Here, the impurity concentration during ion implantation performed to form the second source / drain region 212 of an arbitrary conductivity type is relatively lower than the impurity concentration of the conductivity type different from that of the second source / drain region in the third gate 222. By doing so, it is also possible to form a transistor having a gate of an arbitrary polarity without using the hard mask layer 225.

[0090] For example, in the case of this embodiment, the gates of the reset transistor M2 and the FD capacitance switching transistor M5, which are formed of NMOS, are made of N-type polysilicon. Furthermore, the gates of the amplification transistor M3 and the selection transistor M4, which are formed of PMOS, may be made of P-type polysilicon.

[0091] The subsequent steps are the same as those in the first embodiment, and therefore the description will be omitted.

[0092] As described above, according to this embodiment, the electron accumulation type photoelectric conversion element is formed on the first substrate, and the amplifying transistor is formed as a PMOS on the second substrate. By doing so, it is possible to provide a photoelectric conversion device that is suitable for miniaturization, can be driven at high speed, and can effectively suppress 1 / f noise of pixels.

[0093] Fourth embodiment The fourth embodiment is applicable to any of the first to third embodiments. FIG. 19(a) is a schematic diagram for explaining an apparatus 9191 including a semiconductor device 930 of this embodiment. The photoelectric conversion device of each of the above-mentioned embodiments can be used for the semiconductor device 930. The apparatus 9191 including the semiconductor device 930 will be explained in detail. The semiconductor device 930 can include a package 920 that houses the semiconductor device 910 in addition to the semiconductor device 910. The package 920 can include a base to which the semiconductor device 910 is fixed, and a cover such as glass that faces the semiconductor device 910. The package 920 can further include a bonding member such as a bonding wire or a bump that connects a terminal provided on the base and a terminal provided on the semiconductor device 910.

[0094] The device 9191 can include at least one of an optical device 940, a control device 950, a processing device 960, a display device 970, a storage device 980, and a mechanical device 990. The optical device 940 corresponds to the semiconductor device 930. The optical device 940 is, for example, a lens, a shutter, or a mirror. The control device 950 controls the semiconductor device 930. The control device 950 is, for example, a semiconductor device such as an ASIC.

[0095] The processing device 960 processes the signal output from the semiconductor device 930. The processing device 960 is a semiconductor device such as a CPU or ASIC for configuring an AFE (analog front end) or a DFE (digital front end). The display device 970 is an EL display device or a liquid crystal display device that displays information (images) obtained by the semiconductor device 930. The storage device 980 is a magnetic device or a semiconductor device that stores information (images) obtained by the semiconductor device 930. The storage device 980 is a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive.

[0096] The mechanical device 990 has a moving part or a propulsion part such as a motor or an engine. In the device 9191, the signal output from the semiconductor device 930 is displayed on the display device 970, or transmitted to the outside by a communication device (not shown) included in the device 9191. For this purpose, the device 9191 preferably further includes a memory device 980 and a processing device 960 in addition to the memory circuit and arithmetic circuit included in the semiconductor device 930. The mechanical device 990 may be controlled based on the signal output from the semiconductor device 930.

[0097] The device 9191 is also suitable for electronic devices such as information terminals (e.g., smartphones and wearable devices) with a photographing function and cameras (e.g., interchangeable lens cameras, compact cameras, video cameras, and surveillance cameras). The mechanical device 990 in the camera can drive components of the optical device 940 for zooming, focusing, and shutter operation. Alternatively, the mechanical device 990 in the camera can move the semiconductor device 930 for vibration isolation operation.

[0098] The device 9191 may be transportation equipment such as a vehicle, a ship, or an aircraft. The mechanical device 990 in the transportation equipment may be used as a moving device. The device 9191 as a transportation equipment is suitable for transporting the semiconductor device 930 or for assisting and / or automating driving (piloting) by using a photographing function. The processing device 960 for assisting and / or automating driving (piloting) can perform processing for operating the mechanical device 990 as a moving device based on information obtained by the semiconductor device 930. Alternatively, the device 9191 may be a medical device such as an endoscope, a measuring device such as a distance measuring sensor, an analytical device such as an electron microscope, an office machine such as a copier, or an industrial device such as a robot.

[0099] According to the above-described embodiment, it is possible to obtain good pixel characteristics. Therefore, the value of the semiconductor device can be increased. In this case, increasing the value corresponds to at least one of adding functions, improving performance, improving characteristics, improving reliability, improving manufacturing yield, reducing environmental load, reducing costs, reducing size, and reducing weight.

[0100] Therefore, if the semiconductor device 930 according to this embodiment is used in the equipment 9191, the value of the equipment can be improved. For example, by mounting the semiconductor device 930 on a transport equipment, excellent performance can be obtained when photographing the outside of the transport equipment or measuring the external environment. Therefore, in manufacturing and selling the transport equipment, it is advantageous to decide to mount the semiconductor device according to this embodiment on the transport equipment in order to improve the performance of the transport equipment itself. In particular, the semiconductor device 930 is suitable for transport equipment that performs driving assistance and / or automatic driving of the transport equipment using information obtained by the semiconductor device.

[0101] The photoelectric conversion system and the moving object of this embodiment will be described with reference to FIGS. 19(b) and 19(c).

[0102] FIG. 19(a) shows an example of a photoelectric conversion system related to an in-vehicle camera. The photoelectric conversion system 8 has a photoelectric conversion device 1. The photoelectric conversion device 1 is a photoelectric conversion device (imaging device) described in any of the above embodiments. The photoelectric conversion system 8 has an image processing unit 801 that performs image processing on a plurality of image data acquired by the photoelectric conversion device 1, and a parallax acquisition unit 802 that calculates parallax (phase difference of parallax images) from the plurality of image data acquired by the photoelectric conversion system 8. The photoelectric conversion system 8 also has a distance acquisition unit 803 that calculates a distance to an object based on the calculated parallax, and a collision determination unit 804 that determines whether or not there is a possibility of collision based on the calculated distance. Here, the parallax acquisition unit 802 and the distance acquisition unit 803 are examples of distance information acquisition means that acquire distance information to an object. That is, the distance information is information related to the parallax, the defocus amount, the distance to the object, and the like. The collision determination unit 804 may determine the possibility of collision using any of these distance information. The distance information acquisition means may be realized by dedicated hardware, a software module, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a combination of these.

[0103] The photoelectric conversion system 8 is connected to a vehicle information acquisition device 810, and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The photoelectric conversion system 8 is also connected to a control ECU 820, which is a control device that outputs a control signal to generate a braking force for the vehicle based on the judgment result of the collision judgment unit 804. The photoelectric conversion system 8 is also connected to an alarm device 830 that issues an alarm to the driver based on the judgment result of the collision judgment unit 804. For example, when the judgment result of the collision judgment unit 804 indicates that there is a high possibility of a collision, the control ECU 820 performs vehicle control to avoid a collision and reduce damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 830 warns the user by sounding an alarm, displaying alarm information on the screen of a car navigation system, etc., and vibrating the seat belt or steering wheel.

[0104] In this embodiment, the surroundings of the vehicle, for example the front or rear, are imaged by the photoelectric conversion system 8. Fig. 19(c) shows the photoelectric conversion system when imaging the area in front of the vehicle (imaging range 850). A vehicle information acquisition device 810 sends an instruction to the photoelectric conversion system 8 or the photoelectric conversion device 1. This configuration can further improve the accuracy of distance measurement.

[0105] Although the above describes an example of control to prevent collision with other vehicles, the present invention can also be applied to control of automatic driving by following other vehicles, control of automatic driving to prevent deviation from lanes, etc. Furthermore, the photoelectric conversion system is not limited to vehicles such as the vehicle itself, but can be applied to moving bodies (moving devices) such as ships, aircraft, and industrial robots. In addition, the present invention can be applied not only to moving bodies, but also to a wide range of devices that use object recognition, such as intelligent transport systems (ITS).

[0106] The above-described embodiments can be modified as appropriate without departing from the technical concept. The disclosure of this specification includes not only what is described in this specification, but also all matters that can be understood from this specification and the drawings attached hereto. The disclosure of this specification also includes the complement of the concepts described in this specification. In other words, if this specification contains a statement that "A is greater than B," for example, this specification can be said to disclose that "A is not greater than B" even if the statement that "A is not greater than B" is omitted. This is because when it is stated that "A is greater than B," it is assumed that the case in which "A is not greater than B" is taken into consideration.

[0107] The disclosure of this embodiment includes the following configurations and methods.

[0108] (Configuration 1) A photoelectric conversion device comprising a first substrate having a photoelectric conversion element and a second substrate having an amplifying transistor that amplifies electrons, which are signal charges output from the photoelectric conversion element, wherein the photoelectric conversion element has an N-type semiconductor region that accumulates the electrons, and the amplifying transistor is a P-type MOS transistor.

[0109] (Configuration 2) The photoelectric conversion device according to configuration 1, wherein the first substrate has a transfer transistor that transfers the electrons to the amplification transistor, the transfer transistor being an N-type MOS transistor.

[0110] (Configuration 3) The photoelectric conversion device described in configuration 1 or 2, characterized in that the second substrate has a reset transistor, a selection transistor, and an FD capacitance switching transistor, and the reset transistor, the selection transistor, and the FD capacitance switching transistor are P-type MOS transistors.

[0111] (Configuration 4) The photoelectric conversion device according to any one of configurations 1 to 3, wherein the gate of the amplifying transistor is made of P-type polysilicon.

[0112] (Configuration 5) The photoelectric conversion device according to any one of configurations 1 to 3, wherein the gate of the amplifying transistor is made of N-type polysilicon.

[0113] (Configuration 6) A photoelectric conversion device described in any one of configurations 1, 2, 4, or 5, characterized in that the second substrate has a reset transistor, a selection transistor, and an FD capacitance switching transistor, the selection transistor being a P-type MOS transistor, and the reset transistor and the FD capacitance switching transistor being N-type MOS transistors.

[0114] (Configuration 7) The photoelectric conversion device according to any one of configurations 1 to 6, wherein the second substrate is laminated on the first substrate.

[0115] (Configuration 8) The photoelectric conversion device according to any one of configurations 1 to 7, further comprising a third substrate having a logic circuit for processing a pixel signal output from the amplifying transistor.

[0116] (Configuration 9) The photoelectric conversion device described in any one of configurations 1 to 8, characterized in that the second substrate has a reset transistor, and a first power supply voltage supplied to the reset transistor is different from a second power supply voltage supplied to the amplification transistor.

[0117] (Configuration 10) A photoelectric conversion device described in any one of configurations 1 to 9, characterized in that the second substrate has a reset transistor, and a first power supply voltage supplied to the reset transistor is greater than a reference voltage and less than a second power supply voltage supplied to the amplification transistor.

[0118] (Configuration 11) The photoelectric conversion device according to configuration 10, wherein a negative bias is applied to the anode of the photoelectric conversion element.

[0119] (Configuration 12) The photoelectric conversion device according to configuration 8, wherein the third substrate is laminated on the second substrate.

[0120] (Structure 13) A photoelectric conversion device described in any one of structures 1 to 12, characterized in that the first substrate has a floating diffusion region, and a wiring structure that penetrates a depth position of the second substrate is electrically connected to the floating diffusion region.

[0121] (Configuration 14) The photoelectric conversion device according to configuration 13, wherein the wiring structure is electrically connected to the gate of the amplifying transistor.

[0122] (Configuration 15) An apparatus including a photoelectric conversion device according to any one of configurations 1 to 14, further including at least one of an optical device corresponding to the photoelectric conversion device, a control device controlling the photoelectric conversion device, a processing device processing a signal output from the photoelectric conversion device, a display device displaying information obtained by the photoelectric conversion device, a memory device storing information obtained by the photoelectric conversion device, and a mechanical device operating based on the information obtained by the photoelectric conversion device.

[0123] (Structure 16) A laminate comprising a first substrate having a photoelectric conversion element and a second substrate having an amplifying transistor that amplifies electrons, which are signal charges output from the photoelectric conversion element, wherein the photoelectric conversion element has an N-type semiconductor region that accumulates the electrons, and the amplifying transistor is a P-type MOS transistor.

[0124] (Configuration 17) The stack described in Configuration 16, further comprising a third substrate having a logic circuit for processing a pixel signal output from the amplification transistor, the third substrate being stacked on the second substrate. [Explanation of symbols]

[0125] 10 First board 20 Second board 110 N-type semiconductor region PD photoelectric conversion element M3 Amplifying transistor

Claims

1. A first substrate having a photoelectric conversion element, A second substrate having an amplification transistor that amplifies electrons, which are signal charges output from the photoelectric conversion element, and a selection transistor that can be electrically connected to the source of the amplification transistor, A photoelectric conversion device comprising: The photoelectric conversion element includes an N-type semiconductor region that accumulates the electrons, The amplification transistor and the selection transistor are P-type MOS transistors A photoelectric conversion device characterized by the above.

2. The first substrate has a transfer transistor that transfers the electrons to the amplification transistor, and the transfer transistor is an N-type MOS transistor. The photoelectric conversion device according to claim 1, characterized in that.

3. The second substrate has a reset transistor and an FD capacitance switching transistor, and the reset transistor and the FD capacitance switching transistor are P-type MOS transistors. The photoelectric conversion device according to claim 1, characterized in that.

4. The gate of the amplification transistor is formed of P-type polysilicon. The photoelectric conversion device according to claim 1, characterized in that.

5. The gate of the amplification transistor is formed of N-type polysilicon. The photoelectric conversion device according to claim 1, characterized in that.

6. The second substrate has a reset transistor and an FD capacitance switching transistor, and the reset transistor and the FD capacitance switching transistor are N-type MOS transistors. The photoelectric conversion device according to claim 1, characterized in that.

7. The second substrate has a reset transistor and an FD capacitance switching transistor, and the reset transistor and the FD capacitance switching transistor are MOS transistors of different conductivity types. The photoelectric conversion device according to claim 1, characterized in that.

8. The second substrate is laminated on the first substrate. The photoelectric conversion device according to claim 1, characterized in that.

9. The first substrate has a first semiconductor member on which the photoelectric conversion element is disposed and a first insulating film, and the second substrate has a second semiconductor member on which the source region of the amplification transistor is disposed and a second insulating film. The photoelectric conversion device according to claim 1, characterized in that they are arranged in the order of the first semiconductor member, the first insulating film, the second semiconductor member, and the second insulating film.

10. The photoelectric conversion device according to claim 1, further comprising a third substrate having a logic circuit that processes a pixel signal output from the amplification transistor.

11. The photoelectric conversion device according to claim 1, wherein the second substrate has a reset transistor, and a first power supply voltage supplied to the reset transistor is different from a second power supply voltage supplied to the amplification transistor.

12. The photoelectric conversion device according to claim 1, wherein the second substrate has a reset transistor, the first power supply voltage supplied to the reset transistor is greater than a reference voltage, and is smaller than the second power supply voltage supplied to the amplification transistor.

13. The photoelectric conversion device according to claim 12, wherein a negative bias is applied to an anode of the photoelectric conversion element.

14. The photoelectric conversion device according to claim 10, wherein the third substrate is laminated on the second substrate.

15. The photoelectric conversion device according to claim 1, wherein the first substrate has a floating diffusion portion, and a wiring structure penetrating a depth position of the second substrate is electrically connected to the floating diffusion portion.

16. The photoelectric conversion device according to claim 15, wherein the wiring structure is electrically connected to a gate of the amplification transistor.

17. An apparatus comprising the photoelectric conversion device according to any one of claims 1 to 16, further comprising: an optical device corresponding to the photoelectric conversion device; a control device that controls the photoelectric conversion device; a processing device that processes a signal output from the photoelectric conversion device; a display device that displays information obtained by the photoelectric conversion device; a storage device that stores information obtained by the photoelectric conversion device; and a mechanical device that operates based on information obtained by the photoelectric conversion device.

18. A first substrate having a photoelectric conversion element; A second substrate having an amplification transistor that amplifies electrons which are signal charges output from the photoelectric conversion element, and a selection transistor electrically connectable to a source of the amplification transistor; A laminate comprising: The photoelectric conversion element includes an N-type semiconductor region that accumulates the electrons; The amplification transistor and the selection transistor are P-type MOS transistors. The laminate is characterized by the above.

19. A laminate according to claim 18, comprising a third substrate having a logic circuit that processes a pixel signal output from the amplification transistor, wherein the third substrate is laminated on the second substrate.

Images