Semiconductor device and method of manufacturing the same

Abstract

To provide a technology that is advantageous for improving characteristics of a semiconductor device in which a plurality of semiconductor layers are laminated.SOLUTION: Provided is a semiconductor device in which a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer are laminated. A first structure is arranged between the first semiconductor layer and the second semiconductor layer opposed to each other, and a second structure is arranged between the second semiconductor layer and the third semiconductor layer opposed to each other. A region with a plurality of elements arranged on the third semiconductor layer is defined as a first region, and a region between the first region and a peripheral edge part of the third semiconductor layer is defined as a second region. An opening part penetrating through the third semiconductor layer, the second structure, and the second semiconductor layer from the third semiconductor layer to a pad electrode arranged on the first structure to expose the pad electrode is arranged in the second region. An insulator part penetrating through the second semiconductor layer from a second principal surface to a third principal surface is arranged between the first region and the opening part on the second semiconductor layer.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a solid-state imaging element in which a plurality of semiconductor substrates are stacked. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2020 / 105713 [Patent Document 2] JP 2019-220703 A Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a technique that is advantageous for improving the characteristics of a semiconductor device in which a plurality of semiconductor layers are stacked. [Means for solving the problem]

[0005] In view of the above problem, a semiconductor device according to an embodiment of the present invention is a semiconductor device in which a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer are stacked, the second semiconductor layer being disposed between the first semiconductor layer and the third semiconductor layer, a first structure including a first insulating layer being disposed between a first main surface of the first semiconductor layer and a second main surface of the second semiconductor layer which face each other, a second structure including a second insulating layer being disposed between a third main surface of the second semiconductor layer and a fourth main surface of the third semiconductor layer which face each other, and a plurality of elements are disposed in the third semiconductor layer in an orthogonal projection with respect to the fourth main surface. a first region in which the third semiconductor layer is disposed, and a second region in which the first region and a peripheral portion of the third semiconductor layer are disposed, and an opening is disposed in the second region from a fifth main surface of the third semiconductor layer opposite the fourth main surface to a pad electrode disposed on the first structure, penetrating the third semiconductor layer, the second structure, and the second semiconductor layer to expose the pad electrode, and an insulator portion is disposed between the first region and the opening of the second semiconductor layer in an orthogonal projection onto the third main surface. Effect of the Invention

[0006] According to the present invention, it is possible to provide a technique that is advantageous for improving the characteristics of a semiconductor device in which a plurality of semiconductor layers are stacked. [Brief description of the drawings]

[0007] [Figure 1] 1 is a plan view showing a configuration example of a semiconductor device according to an embodiment of the present invention; [Diagram 2] FIG. 2 is a cross-sectional view showing a configuration example of the semiconductor device in FIG. [Diagram 3] FIG. 2 is a plan view showing a configuration example of the semiconductor device in FIG. [Figure 4] FIG. 2 is a plan view showing a configuration example of the semiconductor device in FIG. [Diagram 5] FIG. 2 is a cross-sectional view showing a configuration example of the semiconductor device in FIG. [Figure 6] FIG. 2 is a cross-sectional view showing a configuration example of the semiconductor device in FIG. [Figure 7]FIG. 2 is a cross-sectional view showing a configuration example of the semiconductor device in FIG. [Figure 8] FIG. 8 is a circuit diagram showing a configuration example of the protection element in FIG. 7. [Figure 9] FIG. 2 is a cross-sectional view showing a configuration example of the semiconductor device in FIG. [Figure 10] 7A to 7C are cross-sectional views showing an example of a method for manufacturing the semiconductor device in FIG. 6. [Figure 11] 7A to 7C are cross-sectional views showing an example of a method for manufacturing the semiconductor device in FIG. 6. [Figure 12] 7A to 7C are cross-sectional views showing an example of a method for manufacturing the semiconductor device in FIG. 6. [Figure 13] 7A to 7C are cross-sectional views showing an example of a method for manufacturing the semiconductor device in FIG. 6. [Figure 14] 7A to 7C are cross-sectional views showing an example of a method for manufacturing the semiconductor device in FIG. 6. [Figure 15] 7A to 7C are cross-sectional views showing an example of a method for manufacturing the semiconductor device in FIG. 6. [Figure 16] FIG. 2 is a cross-sectional view showing a configuration example of the semiconductor device in FIG. [Figure 17] 17 is a cross-sectional view showing an example of the arrangement of the conductive members in FIG. 16. [Figure 18] 17 is a cross-sectional view showing an example of the arrangement of the conductive members in FIG. 16. [Figure 19] 17 is a cross-sectional view showing an example of the arrangement of the conductive members in FIG. 16. [Figure 20] 17 is a cross-sectional view showing an example of the arrangement of the conductive members in FIG. 16. [Figure 21] 17 is a cross-sectional view showing an example of the arrangement of the conductive members in FIG. 16. [Figure 22] 17 is a cross-sectional view showing an example of the arrangement of the conductive members in FIG. 16. [Diagram 23] 12 is a cross-sectional view showing a modified example of the manufacturing method of FIG. 11. [Figure 24] 12 is a cross-sectional view showing a modified example of the manufacturing method of FIG. 11. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, the embodiments will be described in detail with reference to the attached drawings. Note that the following embodiments do not limit the invention according to the claims. Although the embodiments describe a number of features, not all of these features are essential to the invention, and the features may be combined in any manner. Furthermore, in the attached drawings, the same reference numbers are used for the same or similar configurations, and duplicated descriptions are omitted.

[0009] A semiconductor device and a method for manufacturing the semiconductor device according to an embodiment of the present disclosure will be described with reference to Figures 1 to 23. Figure 1 is a plan view showing a structure of a semiconductor device 1 in an embodiment of the present invention. Figure 1 shows the semiconductor device 1 for one chip. The semiconductor device 1 includes a region 2 and a region 3 (regions 3a and 3b) from the center to the end of the chip. Each of the regions 2 and 3 will be described later.

[0010] FIG. 2 is a cross-sectional structure between A and B shown in FIG. 1. In the semiconductor device 1, a semiconductor layer 1001, a semiconductor layer 1002, and a semiconductor layer 1003 are stacked. As shown in FIG. 2, the semiconductor layer 1002 is disposed between the semiconductor layer 1001 and the semiconductor layer 1003. A structure 1015 including an insulating layer is disposed between the main surface 11 of the semiconductor layer 1001 and the main surface 12 of the semiconductor layer 1002, which face each other. The structure 1015 includes a structure 1010 formed on the main surface 11 of the semiconductor layer 1001 when manufacturing the semiconductor layer 1, and a structure 1020 formed on the main surface 12 of the semiconductor layer 1002. A structure 1025 including an insulating layer is disposed between the main surface 13 of the semiconductor layer 1002 and the main surface 14 of the semiconductor layer 1003, which face each other. The structure 1025 includes a structure 1021 formed on the main surface 13 of the semiconductor layer 1002 when manufacturing the semiconductor layer 1, and a structure 1030 formed on the main surface 14 of the semiconductor layer 1003. Here, the semiconductor layer 1001 has the main surface 11 and the main surface (not numbered), the semiconductor layer 1002 has the main surface 12 and the main surface 13, and the semiconductor layer 1003 has the main surface 14 and the main surface 15. For example, in the semiconductor layer 1001, the main surface 11 is the surface opposite to the main surface (not numbered), in the semiconductor layer 1002, the main surface 12 is the surface opposite to the main surface 13, and in the semiconductor layer 1003, the main surface 14 is the surface opposite to the main surface 15. For example, the main surface 11, the main surface 12, and the main surface 14 can also be referred to as the front surface, and the main surface (not numbered), the main surface 13, and the main surface 15 can also be referred to as the back surface. For example, the front surface can be the side on which a transistor gate is provided or the side on which the structures 1015 and 1025 are provided.

[0011] 2, in the orthogonal projection onto the main surface 14 of the semiconductor layer 1003, a region in which a plurality of elements 305 are arranged in the semiconductor layer 1003 is referred to as region 2, and a region between region 2 and the peripheral portion of the semiconductor layer 1003 (semiconductor device 1) is referred to as region 3. In addition, in the orthogonal projection onto the main surface 14 of the semiconductor layer 1003, region 3 may be described as being divided into region 3a in which an insulator portion 206 (described later) is arranged, and region 3b arranged between the insulator portion 206 and the peripheral portion of the semiconductor device 1.

[0012] In the semiconductor layer 1001, a diffusion layer 101 and a shallow trench isolation (not shown) are arranged in a region 2. In the structure 1010 arranged on the main surface 11 of the semiconductor layer 1001, a gate electrode 102, an insulating layer 103, a wiring layer and a via (hereinafter referred to as a wiring pattern 104), etc. are arranged in a region 2. In the structure 1010, a pad electrode 105 and the like are arranged in a region 3. The diffusion layer 101 and the gate electrode 102 constitute a transistor 106. The transistor 106 and the pad electrode 105 can be electrically connected. The pad electrode 105 is arranged to electrically connect the semiconductor device 1 and a device arranged outside the semiconductor device 1 and to exchange signals and the like. In addition, a bonding pad 107 embedded in the insulating layer 103 is arranged on the surface of the structure 1010.

[0013] In the semiconductor layer 1002, a diffusion layer 204 and the like are arranged in the region 2. In the structure 1020, a gate electrode 201, an insulating layer 202, a wiring layer, and a via (hereinafter referred to as a wiring pattern 203) and the like are arranged in the region 2. The diffusion layer 204 and the gate electrode 201 constitute a transistor 205. The transistor 205 includes, for example, an amplifier transistor that amplifies a signal output from a photoelectric conversion element arranged in the semiconductor layer 1003 described later. The wiring pattern 203 and the gate electrode 201, and the wiring pattern 203 and the diffusion layer 204 are electrically connected via conductive members included in the wiring pattern 203 arranged in contact holes. In the structure 1020, a bonding pad 208 embedded in the insulating layer 202 is arranged on the surface facing the semiconductor layer 1001. The structure 1021 includes an insulating layer. The structures 1010 and 1020 are bonded to each other at the surfaces of the insulating layers 103 and 202 and at the surfaces of the bonding pads 107 and 208 , respectively, to form the structure 1015 .

[0014] Furthermore, the semiconductor layer 1002 is provided with insulator portions 206 and 207 penetrating the semiconductor layer 1002 from the main surface 12 to the main surface 13. Here, the insulator portion 206 indicates a member disposed in the region 3a, and the insulator portion 207 indicates a member disposed in the region 2. The insulator portion 206 and the insulator portion 207 can be formed at the same time. The insulator portion 206 and the insulator portion 207 may be made of the same material.

[0015] In the semiconductor layer 1003, a photodiode 303, a floating diffusion 304, and the like are arranged in the region 2. In the structure 1030, a gate electrode 301, an insulating layer 302, and the like are arranged in the region 2. The gate electrode 301, the photodiode 303, and the floating diffusion 304 constitute a photoelectric conversion element. In this manner, the multiple elements 305 arranged in the semiconductor layer 1003 include a photoelectric conversion element. The photoelectric conversion elements can be arranged in the region 2 of the semiconductor layer 1003 to form multiple rows and multiple columns. In other words, the region 2 can be a region in which multiple photoelectric conversion elements are arranged in a matrix. Also, the so-called peripheral region arranged around the region 2 in which multiple photoelectric conversion elements are arranged in a matrix can be the region 3. In the semiconductor layer 1003, an insulator portion 306 penetrating the semiconductor layer 1003 from the main surface 14 to the main surface 15 is arranged at least in the regions 3a and 3b. For example, the plurality of elements 305 arranged in the semiconductor layer 1003 include photoelectric conversion elements. Next, an element circuit including a transistor 205 that amplifies a signal output from the photoelectric conversion elements arranged in the semiconductor layer 1003 is arranged on the main surface 12 of the semiconductor layer 1002. Furthermore, a drive circuit including a transistor 106 for driving the plurality of elements 305 arranged in the semiconductor layer 1003 and the element circuit arranged in the semiconductor layer 1002 may be arranged on the main surface 11 of the semiconductor layer 1001.

[0016] A structure 1031 including an optical element is disposed on the main surface 15 opposite to the main surface 14 on which the element 305 of the semiconductor layer 1003 is formed. The structure 1031 may include optical elements such as a light-shielding layer, an inner-layer lens, a color filter, and a microlens. These optical elements may be formed using the insulator portion 306 formed in the region 3b as a reference point for alignment. The structure 1021 and the structure 1030 are bonded on the surfaces of the insulating layers to form a structure 1025.

[0017] An element such as the transistor 205 arranged in the semiconductor layer 1002 and an element such as the element 305 arranged in the semiconductor layer 1003 can be electrically connected via the plug electrode 5 and the wiring pattern 203. As described above, the structure 1015 includes the wiring pattern 203 arranged in the insulating layer 202. A plug electrode 5 for connecting the photoelectric conversion element (element 305) and the wiring pattern 203 is arranged penetrating the structure 1025 and the semiconductor layer 1002. In the orthogonal projection of the semiconductor layer 1002 onto the main surface 13, an insulator portion 207 is arranged in the semiconductor layer 1002, surrounding the plug electrode 5 and penetrating the semiconductor layer 1002 from the main surface 12 to the main surface 13. The plug electrode 5 is formed in the insulator portion 207 in the semiconductor layer 1002. This maintains insulation between the semiconductor layer 1002 and the plug electrode 5. The semiconductor layer 1002 can be formed thin in consideration of the processing stability and resistance stability of the through via in which the plug electrode 5 is arranged. An element such as a transistor 106 arranged in the semiconductor layer 1001 and an element such as a transistor 205 arranged in the semiconductor layer 1002 are electrically connected via a bonding pad 107 and a bonding pad 208.

[0018] In the region 3a, an opening 6 is arranged from the main surface 15 opposite to the main surface 14 of the semiconductor layer 1003 to the pad electrode 105 arranged on the structure 1015, penetrating the semiconductor layer 1003, the structure 1025, and the semiconductor layer 1002, and exposing the pad electrode 105. The opening 6 also penetrates the structure 1031 to expose the pad electrode 105. In the orthogonal projection of the semiconductor layer 1002 onto the main surface 13, an insulator portion 206 is arranged between the region 2 of the semiconductor layer 1002 and the opening 6, penetrating the semiconductor layer 1002 from the main surface 12 to the main surface 13. It is necessary to maintain insulation between the opening 6 and the semiconductor layer 1002 in which the transistor 205 is arranged. For example, a metal wire connected to the pad electrode 105 for connecting the semiconductor device 1 to an external device of the semiconductor device 1 is arranged in the opening 6. This is because it is necessary to maintain insulation between the wire and the semiconductor layer 1002 even if the wire touches the wall surface of the opening 6. By disposing the insulator portion 206 between the region 2 and the opening 6, it is possible to maintain insulation between the wire and the semiconductor layer 1002. In other words, malfunction of elements such as the transistor 205 disposed in the semiconductor layer 1002 due to signals flowing through the wire is suppressed, and the reliability and other characteristics of the semiconductor device 1 are improved.

[0019] In an orthogonal projection onto the main surface 13 of the semiconductor layer 1002, the insulator portion 206 may be disposed so as to surround the opening 6. By the insulator portion 206 surrounding the opening 6, it is possible to more reliably maintain insulation between the region 2 of the semiconductor layer 1002 and the opening 6. Also, as shown in FIG. 2, the insulator portion 206 may constitute a wall surface of a portion of the opening 6 that penetrates the semiconductor layer 1002. Although the details of the manufacturing method will be described later, the opening 6 may be formed so as to penetrate the insulator portion 206 provided in the semiconductor layer 1002. However, this is not limited thereto, and the insulator portion 206 may be separated from the opening 6 and not constitute a wall surface of the opening 6, like the insulator portion 306 disposed in the semiconductor layer 1003.

[0020] Similarly, in the semiconductor layer 1003, the insulator portion 306 is disposed between the region 2 and the opening 6. In an orthogonal projection onto the main surface 15 of the semiconductor layer 1003, the insulator portion 306 may be disposed so as to surround the opening 6. This makes it possible to maintain insulation between the opening 6 and the region 2 of the semiconductor layer 1003.

[0021] As described above, the semiconductor layer 1002 can be thinned. Therefore, the mechanical strength of the semiconductor layer 1002 can be reduced. From the viewpoint of the mechanical strength of the semiconductor layer 1002, it is advantageous in terms of strength that the width of the region 3a in the region 3 where the insulator portion 206 is arranged is as narrow as possible. For example, in the orthogonal projection of the semiconductor layer 1002 onto the main surface 13, the semiconductor layer 1002 (semiconductor device 1) can have a rectangular shape. Therefore, the width of the region 3a may be, for example, 1 / 100 or less of the length of the short side of the semiconductor layer 1002 (semiconductor device 1). The arrangement of the openings 6 also follows the arrangement of the insulator portion 206.

[0022] So far, the semiconductor device 1 has been described as an example of a so-called photoelectric conversion device in which the element 305 arranged in the semiconductor layer 1003 includes a photoelectric conversion element. However, the present disclosure is not limited to this, and similar effects can be obtained in other semiconductor devices in which three semiconductor layers are stacked. For example, a memory or the like may be mounted in each semiconductor layer.

[0023] 3 is a plan view showing the main surface 13 of the semiconductor layer 1002. The plan view shown in FIG. 3 focuses on the arrangement of the insulator parts 206 and 207, and omits the plug electrode 5 and the like. As described above, the semiconductor device 1 includes the region 2, the region 3a, and the region 3b from the center of the chip toward the periphery. The insulator part 206 penetrating the semiconductor layer 1002 is arranged in the region 3a. Also, an opening 6 for exposing the pad electrode 105 is arranged so as to be surrounded by the insulator part 206.

[0024] 3, a portion of the semiconductor layer 1002 arranged in region 2 and a portion of the semiconductor layer 1002 arranged in region 3b are separated by an insulator portion 206. Also, an insulator portion 207 is provided in the portion of the semiconductor layer 1002 arranged in region 2.

[0025] 3, the region 2 of the semiconductor layer 1002 is surrounded by an insulator portion 206 penetrating the semiconductor layer 1002. In an orthogonal projection onto the main surface 13 of the semiconductor layer 1002, the insulator portion 206 can be said to be disposed continuously with respect to the plurality of openings 6. Therefore, the insulator portion 206 is always present on the path from the region 2 to the region 3b. In this manner, by disposing the insulator portion 206, it is possible to maintain the insulation between the openings 6 and the portion of the semiconductor layer 1002 disposed in the region 2 while maintaining the degree of freedom in the arrangement of the openings 6.

[0026] As described above, from the viewpoint of the mechanical strength of the semiconductor layer 1002, it is advantageous in terms of strength that the width of the region 3a in which the insulator portion 206 is disposed is as narrow as possible. Here, the width of the region 3a is indicated by the length W shown in FIG. 3. For the sake of explanation, the illustrated dimensions are different in FIG. 3, but as described above, the width of the region 3a in which the insulator portion 206 is disposed may be, for example, 1 / 100 or less of the short side width of the chip of the semiconductor device 1. With such a configuration, the arrangement interval of the multiple openings 6 can be made small, making miniaturization possible.

[0027] FIG. 4 is a diagram showing a modified example of the plan view of the main surface 13 of the semiconductor layer 1002 shown in FIG. 3. In the configuration shown in FIG. 4, a plurality of openings 6 are arranged to correspond to a plurality of pad electrodes 105, as in the configuration shown in FIG. 3. Here, attention is paid to the openings 6a and 6b adjacent to each other among the plurality of openings. In an orthogonal projection onto the main surface 13 of the semiconductor layer 1002, the insulator portion 206 includes a portion 206a surrounding the opening 6a and a portion 206b surrounding the opening 6b, and a part of the semiconductor layer 1002 is arranged between the portion 206a and the portion 206b. That is, unlike the configuration shown in FIG. 3, the insulator portion 206 is not arranged continuously, but is arranged intermittently according to the openings 6. However, by arranging the insulator portion 206 to surround the openings 6, insulation between the openings 6 and the portion of the semiconductor layer 1002 arranged in the region 2 can be maintained.

[0028] As shown in Fig. 4, the insulator portions 206 are arranged discontinuously. As a result, the portion of the semiconductor layer 1002 arranged in the region 2 and the portion of the semiconductor layer 1002 arranged between the plurality of openings 6 and the periphery of the semiconductor layer 1002 (for example, region 3b) are continuous with the portion of the semiconductor layer 1002 in the region 3a where the insulator portions 206 are not arranged. In the configuration shown in Fig. 4, the semiconductor layer 1002 in the region 2 and the region 3b are not divided by the insulator portions 206 as in the configuration shown in Fig. 3. As a result, the mechanical strength of the semiconductor layer 1002 can be improved compared to the configuration shown in Fig. 3.

[0029] 4, it is also advantageous for the width (length W) of the region 3a in which the insulator portion 206 is disposed to be as narrow as possible. Therefore, the width of the region 3a may be, for example, 1 / 100 or less of the length of the short side of the semiconductor layer 1002 (semiconductor device 1). In addition, while two openings 6 are disposed in one insulator portion 206 at the corners, two or more openings 6 may be disposed in one insulator portion 206 in other portions as well. This allows for a finer configuration while improving the mechanical strength.

[0030] Fig. 5 is a diagram showing a modified example of the cross-sectional view of the semiconductor device 1 shown in Fig. 2. In the semiconductor device 1 shown in Fig. 5, a member 7 made of a material different from the insulating layer 202 and the insulator portion 206 is disposed in a portion of the structure 1015 that contacts the insulator portion 206. Other configurations may be the same as those shown in Fig. 2, so the member 7 will be described in detail below.

[0031] The member 7 may be made of the same material as the gate electrode 201 of the transistor 205 disposed on the main surface 12 of the semiconductor layer 1002. For example, when forming the gate electrode 201 of the transistor 205 on the main surface 12 of the semiconductor layer 1002, the gate electrode 201 and the member 7 are formed by etching one material layer. A material having a slower etching rate than the insulator portion 206 under the same etching conditions is used as the material of the member 7. For example, when silicon oxide is used as the insulator portion 206, polysilicon, amorphous silicon, single crystal silicon, or the like can be selected as the gate electrode 201 and the member 7.

[0032] In an orthogonal projection onto the main surface 13 of the semiconductor layer 1002, the opening 6 is formed inside the member 7 and the insulator portion 206. As a result, the opening 6 in the semiconductor layer 1002 is surrounded by the insulator portion 206, so that insulation between the opening 6 and the semiconductor layer 1002 can be maintained. Furthermore, in the etching step for forming the opening 6, the insulator portion 206 can be etched using the member 7 as an etch stopper. By temporarily stopping the etching at the member 7, etching of the pad electrode 105 caused by variations in the amount of etching can be suppressed.

[0033] Fig. 6 is a diagram showing a modified example of the cross-sectional view of the semiconductor device 1 shown in Fig. 5. In the configurations shown in Fig. 2 and Fig. 5, the opening 6 can be formed, for example, by using one mask pattern arranged on the structure 1031. On the other hand, in the configuration shown in Fig. 6, the opening 6 is divided into openings 6a, 6b, and 6c having different opening sizes. The openings 6a, 6b, and 6c shown in Fig. 6 can be formed, for example, by using the following process.

[0034] The opening 6a is formed by using the first mask pattern. A large etching selectivity can be obtained between the structure 1031 including optical elements such as an inner lens, a color filter, and a microlens, and the semiconductor layer 1003 made of a semiconductor such as silicon. Therefore, when forming the opening 6a, etching can be stopped accurately at the semiconductor layer 1003.

[0035] Next, the opening 6b is formed using a second mask pattern. The second mask pattern is formed so that the opening is disposed on the inner side than the first mask pattern. As described above, a large etching selectivity is obtained between the insulator portion 206 and the member 7. Therefore, the opening 6b can be etched accurately by the member 7. By this process, in the orthogonal projection onto the main surface 15 of the semiconductor layer 1003, the portion of the opening 6 that penetrates the semiconductor layer 1003, the structure 1025, and the semiconductor layer 1002 (opening 6b) is disposed on the inner side than the portion of the opening 6 that is disposed in the structure 1031 (opening 6a).

[0036] After the openings 6a and 6b are formed, the opening 6c is formed using a third mask pattern. The third mask pattern is formed so that the opening is arranged inside the second mask pattern. When the pad electrode 105 is provided on the structure 1020 formed on the semiconductor layer 1002 of the structure 1015, the opening 6c opens only the structure 1020. When the pad electrode 105 is provided on the structure 1010 formed on the semiconductor layer 1001 of the structure 1015, the opening 6c opens the structure 1020 and the structure 1010. By this process, in the orthogonal projection onto the main surface 15 of the semiconductor layer 1003, the portion of the opening 6 arranged on the structure 1015 (opening 6c) is arranged inside the portion of the opening 6 that penetrates the semiconductor layer 1003, the structure 1025, and the semiconductor layer 1002 (opening 6b).

[0037] In this way, the opening 6 is formed using three etching steps. This makes it possible to suppress excessive etching of the pad electrode 105 caused by etching variations, compared to the case where the opening 6 is formed using a single etching step. In addition, since the opening 6a is larger than the opening 6c, it becomes easier to form wire bonding.

[0038] Fig. 7 is a diagram showing a modified example of the cross-sectional view of the semiconductor device 1 shown in Fig. 2. In the configuration shown in Fig. 7, a protective element 401 is disposed on a pad electrode 105 via a wiring pattern 104. Other configurations may be similar to those shown in Fig. 2, so the following description will be centered on the protective element 401.

[0039] The pad electrode 105 is connected to a device disposed outside the semiconductor device 1. For example, a metal wire is bonded to the pad electrode 105. When the metal wire is bonded, a surge voltage may be input, which may cause, for example, electrical damage to the transistor 106. In addition, the semiconductor device 1 may malfunction due to the intrusion of noise from an external device via the wire. By disposing the protective element 401 on the pad electrode 105, the effects of such electrical damage and intrusion of noise can be reduced. The protective element 401 may be structured to be disposed directly below the pad electrode 105 in terms of a cross-sectional structure.

[0040] 8(a) to 8(c) are circuit diagrams showing configuration examples of the protection element 401. FIG. 8(a) is an example in which a protection diode 402 is arranged between a power supply potential VDD and a potential GND. The protection element 401 suppresses electrical damage to the power supply potential VDD and the potential GND and noise contamination. FIG. 8(b) is an example in which a protection diode 402 is arranged between a signal line 403 and a power supply potential VDD and between the signal line 403 and the potential GND. Electrical damage to an element connected to the signal line 403, for example, the transistor 106, and noise contamination are suppressed. FIG. 8(c) is an example of the protection element 401 in which a P-type transistor 404 and an N-type transistor 405, each of which has a grounded gate electrode, are arranged instead of the protection diode 402 in FIG. 8(b). The configuration of the protection element 401 is not limited to the configuration examples shown in FIGS. 8(a) to 8(c), and an appropriate configuration may be used as appropriate depending on the circuit configuration arranged in the semiconductor device 1.

[0041] FIG. 9 shows an example in which the protective element 401 is disposed in the semiconductor layer 1002. The semiconductor device 1 is supplied with a power supply potential, a control signal for the semiconductor device 1, and the like from an external device via the electrode pad 105. For example, a power supply potential may be connected from the external device to the transistor 205 disposed in the semiconductor layer 1002 via the pad electrode 105, the bonding pad 107, the bonding pad 208, and the like. That is, electrical damage or noise may be mixed in from the external device to the transistor 205. Therefore, the protective element 401 may be disposed in the connection path from the external device to the transistor 205. As in the configuration shown in FIG. 9, by disposing the protective element 401 in the semiconductor layer 1002, electrical damage to the transistor 205 and mixing in noise can be suppressed. Here, the protective element 401 is disposed in the region 2 in FIG. 9, but may be disposed in the region 3 depending on the shape of the insulator portion 206 in the region 3. For example, the protective element 401 may be disposed between the multiple insulator portions 206 shown in FIG. 4.

[0042] The protective element 401 may be disposed in the semiconductor layer 1001 on which the pad electrode 105 is formed on the main surface 11, or may be disposed in the other semiconductor layers 1002 and 1003. A plurality of protective elements 401 may be disposed for one pad electrode 105. In this case, the protective element 401 may be disposed in one of the semiconductor layers 1001 to 1003, or may be disposed in a plurality of semiconductor layers. For example, for one pad electrode 105, the protective element 401 may be disposed in the semiconductor layer 1001 and the semiconductor layer 1002, the semiconductor layer 1002 and the semiconductor layer 1003, or each of the semiconductor layers 1001 to 1003. In addition to the protective element 401, a member made of a material such as an insulator that serves as an isolation structure or a gate electrode of a transistor may be provided in the region 3 including under the pad electrode 105. That is, a pattern made of an insulator or a pattern made of polysilicon may be disposed. This makes it possible to improve the uniformity of the pattern when forming the semiconductor device 1.

[0043] 10(a) to 10(c) to 15(a) and 15(b), a method for manufacturing the semiconductor device 1 will be described. Here, the semiconductor device 1 having the configuration shown in FIG. 6 will be described as an example.

[0044] A semiconductor substrate 1003a that will become the semiconductor layer 1003 is prepared. The semiconductor substrate 1003a may be, for example, a silicon substrate. As shown in FIG. 10(a), an insulator portion 306 is formed in the region that will become the regions 3a and 3b by using a photolithography process, an etching process, and the like. At the time shown in FIG. 10(a), the insulator portion 306 has a shape of a deep trench isolation (DTI) formed in the semiconductor substrate 1003a. After the formation of the DTI, an isolation structure such as a shallow trench isolation (STI) may be formed (not shown). Here, for convenience, the semiconductor layer 1003 before being thinned by the process described below is called the semiconductor substrate 1003a. However, the semiconductor layer 1003 after being thinned may be called the "semiconductor substrate", and the semiconductor substrate 1003a before being thinned may be called the "semiconductor layer". The semiconductor layer 1003 and the semiconductor substrate 1003a essentially represent the same member. The same applies to a semiconductor substrate 1002a described below.

[0045] 10(b), a photodiode 303 is formed using a photolithography process, an ion implantation process, etc. Furthermore, after a gate insulating film (not shown) and polysilicon are formed, a gate electrode 301 is formed using a photolithography process, an etching process, etc.

[0046] After the gate electrode 301 is formed, a floating diffusion 304 is formed using a photolithography process, an ion implantation process, and the like, as shown in FIG. 10(c). As described above, the photodiode 303, the gate electrode 301, and the floating diffusion 304 constitute a photoelectric conversion element. Next, an insulating layer 302 made of silicon oxide or the like is formed. In this manner, a structure 1030 is formed on the main surface 14 of the semiconductor substrate 1003a.

[0047] The semiconductor layer 1002 is processed from a semiconductor substrate 1002a. The semiconductor substrate 1002a may be, for example, a silicon substrate. As shown in FIG. 11(a), a structure 1021 made of silicon oxide or the like is formed on the main surface 13 of the semiconductor substrate 1002.

[0048] Next, as shown in FIG. 11(b), the structure 1021 and the structure 1030 are bonded to each other with the surface of the structure 1021 and the surface of the structure 1030 as bonding surfaces. The surface of the structure 1021 and the surface of the structure 1030 may be a combination of the same material, such as silicon oxide and silicon nitride, or a combination of different materials. This process forms a structure 1025 including the structure 1021 and the structure 1030, and the semiconductor layer 1002 (semiconductor substrate 1002a) and the semiconductor layer 1003 (semiconductor substrate 1003a) are laminated. The bonding method of the structure 1021 and the structure 1030 includes, but is not limited to, a so-called room temperature bonding method in which the surfaces of the structure 1021 and the structure 1030 are activated by plasma irradiation to bond them. For example, the structure 1021 and the structure 1030 may be bonded to each other via a bonding member such as an adhesive.

[0049] After bonding the structure 1021 and the structure 1030, as shown in Fig. 11(c), the semiconductor substrate 1002a is thinned from the main surface 12a side of the semiconductor substrate 1002a to form the semiconductor layer 1002. Examples of the thinning method include a method using a grinder device, a wet etching device, a CMP device, etc. Any suitable method may be used as long as the semiconductor substrate 1002a can be thinned.

[0050] 11(d), an insulator portion 206 is formed in a region of the semiconductor layer 1002 that will become region 3a, and an insulator portion 207 is formed in a portion of the semiconductor layer 1002 that will become region 2. The insulator portion 206 and the insulator portion 207 may be formed simultaneously. For example, a trench is formed in the semiconductor layer 1002 by using a photolithography process, an etching process, or the like, so as to extend from the main surface 12 of the semiconductor layer 1002 to the structure 1021. Next, silicon oxide is filled in the trench formed in the semiconductor layer 1002, and excess silicon oxide is removed by using a CMP device, or the like, to form the insulator portion 206 and the insulator portion 207.

[0051] 12(a), after the insulator portions 206 and 207 are formed, a gate insulating film and polysilicon (or amorphous silicon or single crystal silicon) are formed, and then the gate electrode 201 and member 7 are formed using a photolithography process, an etching process, or the like. The member 7 is formed so as to overlap with the insulator portion 206 in an orthogonal projection onto the main surface 12 of the semiconductor layer 1002. After the gate electrode 201 is formed, a diffusion layer 204 is formed in the semiconductor layer 1002 using a photolithography process, an ion implantation process, or the like.

[0052] 12(b), an insulating layer 202a is formed, and contact holes leading to the gate electrode 201 and the diffusion layer 204, and a plug electrode 5 leading to the gate electrode 301 and the floating diffusion 304 are formed. The plug electrode 5 is formed in the insulator portion 207. This allows the insulation between the semiconductor layer 1002 and the plug electrode 5 to be maintained.

[0053] Furthermore, as shown in FIG. 12(c), an insulating layer 202, a wiring pattern 203, a bonding pad 208, and the like are formed by using appropriate processes. The insulating layer 202 includes the insulating layer 202a described above. Silicon oxide may be used for the insulating layer 202. Silicon nitride, silicon oxynitride, silicon carbide, and the like may also be used for the insulating layer 202 as appropriate. The insulating layer 302 described above may also be made of the same material as the insulating layer 202. The wiring pattern 203 may be formed by a normal aluminum wiring process or copper wiring process. The bonding pad 208 may be formed by a normal copper wiring process. Using such processes, the structure 1020 may be formed.

[0054] 13(a) is a diagram showing a process of forming a structure 1010 on a main surface 11 of a semiconductor layer 1001. The semiconductor layer 1001 may be, for example, a silicon substrate. On the main surface 11 of the semiconductor layer 1001, an STI (not shown), a diffusion layer 101 and a gate electrode 102 constituting a transistor 106, and the like are formed. Then, an insulating layer 103, a wiring pattern 104, a pad electrode 105, a bonding pad 107, and the like are formed. Using such a process, the structure 1010 can be formed.

[0055] Next, as shown in FIG. 13(b), the structure 1010 and the structure 1020 are bonded with the surfaces of the structure 1010 and the structure 1020 as bonding surfaces. The combination of the insulating parts of the surface of the structure 1010 and the surface of the structure 1020 may be made of the same material, such as silicon oxide and silicon nitride, or may be made of different materials. This process forms a structure 1015 including the structure 1010 and the structure 1020, and the semiconductor layer 1001, the semiconductor layer 1002, and the semiconductor layer 1003 (semiconductor substrate 1003a) are laminated. In this bonding process, the insulating layer 103 and the insulating layer 202 are bonded, and at the same time, the bonding pad 107 and the bonding pad 208 are bonded. The bonding method may be, but is not limited to, a so-called room temperature bonding method in which the surfaces of the structure 1010 and the structure 1020 are activated by plasma irradiation and bonded. For example, the structures 1010 and 1020 may be bonded together via a bonding member such as an adhesive.

[0056] After bonding the structures 1010 and 1020, as shown in Fig. 14(a), the semiconductor substrate 1003a is thinned until the insulator portion 306 is exposed from the main surface 15a side of the semiconductor substrate 1003a, thereby forming the semiconductor layer 1003. Examples of the thinning method include a method using a grinder device, a wet etching device, a CMP device, etc. Any suitable method may be used as long as the semiconductor substrate 1003a can be thinned.

[0057] After the semiconductor substrate 1003a is thinned to form the semiconductor layer 1003, as shown in Fig. 14(b), a structure 1031 including optical elements including an inner layer lens, a color filter, a microlens, etc. is formed on the main surface 15 of the semiconductor layer 1003. The structure 1031 may include all of the light-shielding layer, the inner layer lens, the color filter, and the microlens, or may include any one, two, or three of them.

[0058] Next, as shown in Fig. 15(a), the opening 6a is formed in the region that will become the region 3a by using a photolithography process, an etching process, and the like. As described above with reference to Fig. 6, a large etching selectivity can be obtained between the structure 1031 and the semiconductor layer 1003. Therefore, the etching of the opening 6a can be stopped with high accuracy on the main surface 15 of the semiconductor layer 1003. Here, the mask pattern used for etching is not shown.

[0059] After the opening 6a is formed, as shown in FIG. 15(b), the opening 6b is formed inside the opening 6a by using a photolithography process and an etching process. The mask pattern for forming the opening 6b is formed so that the opening is arranged inside the mask pattern for forming the opening 6a. The opening 6b is formed inside the insulator portion 306 in the semiconductor layer 1003. This allows the insulation between the opening 6 and the semiconductor layer 1003 to be maintained. The opening 6b is also formed inside the member 7 in the orthogonal projection onto the main surface 13 of the semiconductor layer 1002. This allows the etching selectivity between the insulator portion 206 and the member 7 to be large in the etching of the opening 6b, so that the etching of the opening 6b can be stopped accurately on the surface of the member 7. The opening 6b is formed inside the insulator portion 206, so that the insulation between the opening 6b and the semiconductor layer 1002 can be maintained.

[0060] In this embodiment, an example is shown in which the insulator portion 206 is etched to form the opening 6b (opening 6). When silicon oxide is used as the insulator portion 206, it is possible to efficiently etch from the structure 1025 in which silicon oxide can be used to the insulator portion 206. In addition, the member 7 that can be formed simultaneously with the gate electrode 201 of the transistor 205 can be used as an etch stopper. However, this is not limited to this, and the insulator portion 206 may be formed away from the opening 6b like the insulator portion 306. In this case, the semiconductor layer 1002 in which silicon or the like is used is etched to form the opening 6b. However, for example, the semiconductor layer 1002 may be etched to form the opening 6b without forming the member 7, using the insulating layer 202 as an etch stopper.

[0061] After the opening 6b is formed, an opening 6c is formed inside the opening 6b using a photolithography process, an etching process, and the like. The mask pattern used to form the opening 6c is formed so that the opening is disposed inside the mask pattern used to form the opening 6b. The pad electrode 105 is exposed by the opening 6c. Through the above processes, the semiconductor device 1 shown in FIG. 6 is manufactured.

[0062] Incidentally, in the semiconductor device 1 in which a plurality of semiconductor layers 1001, 1002, and 1003 are stacked in this manner, moisture and the like may penetrate through the cut surface or opening 6 at the periphery of the chip of the semiconductor device 1, which may cause a decrease in the reliability characteristics of the semiconductor device 1. Therefore, as shown in FIG. 16, a conductive member 501 extending from the structure 1015 to the structure 1025 may be disposed in the region 3. As shown in FIG. 16, the conductive member 501 may penetrate the insulator portion 206. By disposing the conductive member 501, it is possible to suppress the penetration of moisture into the region 2 in which many elements (transistor 105, transistor 205, element 305, etc.) are formed in each of the semiconductor layers 1001 to 1003.

[0063] 17(a) to 17(d) are plan views showing examples of the arrangement of the conductive member 501 on the main surface 13 of the semiconductor layer 1002. In the plan views shown in Fig. 17, attention is focused on the region 2, the opening 6, and the conductive member 501, and other components are omitted as appropriate. The conductive member 501 is arranged in a region 3 between a region 2 in which a plurality of elements 305 are arranged in the semiconductor layer 1003 and the periphery of the semiconductor layer 1002 (which may also be the periphery of the semiconductor device 1, semiconductor layers 1001, 1003) in an orthogonal projection onto the main surface 13 of the semiconductor layer 1002.

[0064] The conductive member 501 may be disposed so as to surround the inside of the outer edge of the semiconductor device 1, as shown in FIG. 17(a). It can also be said that the conductive member 501 surrounds the entire region 2 and the opening 6. In this case, the conductive member 501 may be disposed in the region 3b, as shown in FIG. 17(a), or may be disposed in the region 3a and penetrate the insulator portion 206. The conductive member 501 may be disposed so as to surround the outside of a plurality of openings 6, as shown in FIG. 17(b), or may be disposed so as to surround the outside of each opening 6, as shown in FIG. 17(c). Furthermore, the conductive member 501 may be disposed between the region 2 and the opening 6, as shown in FIG. 17(d), so as to surround the region 2.

[0065] The conductive members 501 may be arranged continuously or intermittently in each pattern as shown in Figures 17(a) to 17(d). In the examples shown in Figures 17(a) to 17(d), the conductive members 501 are shown as surrounding the opening 6 in a single layer, but the conductive members 501 may be arranged in a double or triple layer. Furthermore, the conductive members 501 may be arranged in a combination of the patterns shown in Figures 17(a) to 17(d).

[0066] 12(b) and 12(c) are formed, the conductive member 501 can be formed simultaneously with the plug electrode 5 and the wiring pattern 203. Therefore, the conductive member 501 can be disposed in a desired shape in a desired region of the region 3 (regions 3a and 3b) without increasing the number of processes.

[0067] In the semiconductor device 1 having three or more stacked semiconductor layers, the conductive member 501 extending from the structure 1015 to the structure 1025 is disposed in the region 3. This makes it possible to suppress the intrusion of moisture into the region 2 from the outer edge of the semiconductor device 1 or the wall surface of the opening 6. This improves the reliability of the semiconductor device 1. For example, when the semiconductor device 1 is mounted on a transport device and photographs are taken of the outside of the transport device or the external environment is measured, the intrusion of moisture into the region 2 of the semiconductor device 1 is suppressed, and it is possible to maintain excellent image quality and obtain high measurement accuracy for a long period of time.

[0068] 18(a) to 18(f) to 22(a) and 22(b), examples of the arrangement of the conductive member 501 and the wiring pattern 502 will be further described. In the following examples, a case is shown in which the conductive member 501 surrounds the opening 6 etc. in three layers. However, the number of the conductive members 501 arranged may be one, two, or four or more.

[0069] In the configuration shown in FIG. 18(a), the conductive member 501 is in contact with the wiring pattern 502 disposed in the insulating layer 202 of the structure 1015. The conductive member 501 electrically connects the plurality of wiring patterns 502. However, this is not limited thereto, and the conductive member 501 may not electrically connect some of the wiring patterns 502. For example, as shown in FIG. 18(b), the plurality of conductive members 501 may be connected to each other by the wiring pattern 502. By connecting the conductive member 501 and the wiring pattern 502, which have high moisture resistance, to each other, the moisture resistance can be improved more than when the conductive member 501 and the wiring pattern 502 are not connected to each other.

[0070] In the configuration shown in FIG. 18(c), the conductive member 501 is in contact with the main surface 14 of the semiconductor layer 1003, as in the configurations described above. Meanwhile, a doping layer 503 is formed on the portion of the main surface 14 of the semiconductor layer 1003 with which the conductive member 501 is in contact. The doping layer 503 can be formed simultaneously with the floating diffusion 304 in the process shown in FIG. 10(c). Therefore, the impurity concentration of the portion of the main surface 14 of the semiconductor layer 1003 with which the conductive member 501 is in contact can be the same as the impurity concentration of the floating diffusion 304 arranged in the photoelectric conversion element. By bringing the base structure of the region 3 of the semiconductor layer 1003 closer to the base structure of the region 2, there is an effect of stabilizing the process of forming the structure 1030 on the semiconductor layer 1003. As shown in FIG. 18(c), the doping layer 503 may be arranged for each conductive member 501. Furthermore, as shown in FIG. 18( d ), a plurality of conductive members 501 may be in contact with one doping layer 503 .

[0071] As shown in FIG. 18(e), in the region 3 of the structure 1030, a contact member 504 made of the same material as the gate electrode 301 included in the plurality of elements 305 may be disposed, and the conductive member 501 may be in contact with the contact member 504. In this case, an insulating film 505 made of the same material as the gate insulating film disposed between the gate electrode 201 and the main surface 14 of the semiconductor layer 1003 may be disposed between the contact member 504 and the main surface 14 of the semiconductor layer 1003. The insulating film 505 and the contact member 504 may be formed simultaneously with the gate insulating film and the gate electrode 301 in the step shown in FIG. 10(b). Also, an insulating layer 506 may be disposed in a region of the semiconductor layer 1003 overlapping with the contact member 504. The insulating layer 506 is formed in the same step as an isolation structure such as an STI formed on the main surface 14 of the semiconductor layer 1003. By providing the contact member 504, etching of the semiconductor layer 1003 can be suppressed when forming a trench in which the conductive member 501 is to be buried.

[0072] 18(f), a pattern resembling the gate structure disposed in region 2 may be disposed between conductive member 501 and semiconductor layer 1003. For example, an insulating film 505 formed in the same process as the gate insulating film, a contact member 504 formed in the same process as the gate electrode 301, and an insulating film 507 formed of a material different from the gate insulating film for protecting element 305 such as a transistor may be disposed. By forming a contact structure having the same structure as element 305 disposed in region 2, it is possible to improve the stability of the process, such as stabilizing the etching when forming a trench in which conductive member 501 is embedded.

[0073] As shown in FIG. 19(a), the insulator portion 306 may be disposed in the semiconductor layer 1003, similarly to the semiconductor device 1 shown in FIG. 2. That is, a trench extending through the semiconductor layer 1003 from the main surface 15 to the main surface 14 of the semiconductor layer 1003 may be disposed in the region 3, and an insulator may be embedded in the trench. In addition, for example, the wall surface of the trench may be covered with an insulator and a conductor may be embedded. As the insulator embedded in the trench of the insulator portion 306, aluminum oxide, hafnium oxide, tantalum oxide, or the like formed in a single layer or multiple layers may be formed, and silicon oxide or silicon nitride may be further formed. As described above, the insulator portion 306 maintains the insulation between the semiconductor layer 1003 and the opening 6. In addition, when a conductor is embedded inside the trench covered with an insulator, polysilicon, tungsten, copper, or the like may be embedded. By embedding a conductor, effects such as improvement of moisture resistance and suppression of stray light entering from the outer edge of the semiconductor device 1 or the opening 6 can be obtained. The insulating portion 306 can be formed with a width of, for example, about several tens of nanometers to several hundreds of nanometers.

[0074] Also, as shown in FIG. 19(b), an insulating layer 506 formed in the same process as an isolation structure such as STI formed on the main surface 14 of the semiconductor layer 1003 may be disposed between the insulator 306 and the conductive member 501. By providing the insulating layer 506, it becomes possible to use the insulating layer 506 when forming a trench for the insulator 306, and etching of the structure 1030 can be suppressed. In other words, it is possible to prevent the trench for forming the insulator 306 from being disposed in the structure 1025 (structure 1030). In FIGS. 19(a) and 19(b), an example is shown in which the conductive member 501 is disposed so as to surround the opening 6. However, as described above, the conductive member 501 can also be disposed so as to surround the outer edge portion or the region 2 of the semiconductor device 1. Also, not limited to FIG. 19(b), the uniformity of the pattern can be improved by providing an isolation structure or the like in the region 3 as described above.

[0075] As shown in FIG. 20(a), the conductive member 501 may be in contact with the bonding pad 208 used when bonding the structure 1010 and the structure 1020. The bonding pads 107, 208 may be formed intermittently as shown in FIG. 21(a) in the orthogonal projection onto the main surface 15 of the semiconductor layer 1003, or may be formed continuously as shown in FIG. 21(c). By connecting the conductive member 501 to the bonding pad 208, it is possible to further improve moisture resistance. On the other hand, as shown in FIG. 20(b), the conductive member 501 may be merely close to the bonding pad 208, but may not be in contact with it.

[0076] The bonding pads 107 and 208 are disposed near the conductive member 501. The bonding pads 107 and 208 may be formed intermittently as shown in FIG. 21(a) or continuously as shown in FIG. 21(c). In an orthogonal projection onto the main surface 15 of the semiconductor layer 1003, the bonding pads 107 and 208 may be disposed so as to overlap the conductive member 501 as shown in FIGS. 21(a) and 21(c), or may be disposed at different positions. Furthermore, the bonding pads 107 and 208 may surround the opening 6 in two or more positions as shown in FIGS. 21(b) and 21(d). Moreover, the bonding pads 107 and 208 may be formed in a mixture of intermittent and continuous arrangements in order to form a highly reliable bonding interface. By disposing the bonding pads 107 and 208 in the region 2, the moisture resistance can be improved and at the same time the bonding strength in the region 2 can be increased.

[0077] In the above-described embodiments, an example has been shown in which the pad electrode 105 is disposed on the structure 1010 formed on the semiconductor layer 1001 of the structure 1015. However, the present invention is not limited to this. The pad electrode 105 may be disposed on the structure 1020 formed on the main surface 12 of the semiconductor layer 1002 of the structure 1015. By disposing the pad electrode 105 on the structure 1020 of the structure 1015, the depth of the opening 6 can be made shallow. As a result, mounting defects during wire bonding in the semiconductor device 1 are suppressed. In other words, the reliability of the device using the semiconductor device 1 can be improved.

[0078] In the above-described embodiment, an example was shown in which the pad electrode 105 is disposed closer to the semiconductor layer 1001 than the conductive member 501. However, the present invention is not limited to this. As shown in FIG. 22(b), the structure 1015 may include a conductor portion 508 made of the same material as the pad electrode 105 in the same layer as the pad electrode 105 in the insulating layer 103 or the insulating layer 202, and the conductive member 501 may be in contact with the conductor portion 508. For example, as shown in FIG. 22(b), a trench in which the conductive member 501 is embedded may be formed from the main surface 15 of the semiconductor layer 1003. In this case, by disposing the conductor portion 508 at the same time as the process of forming the pad electrode 105 in the structure 1015, the conductive member 501 can be used as an etch stopper when forming the trench in which the conductive member 501 is embedded. After the trenches are formed, a material such as tungsten is filled in using a CVD method, an ALD method, or the like, to form a moisture-resistant wall of conductive member 501 that extends from semiconductor layer 1003 to structure 1015. In this manner, conductive member 501 may penetrate structure 1025 and further extend to semiconductor layer 1003.

[0079] As described above, a case is considered in which a photoelectric conversion element is arranged in the semiconductor layer 1003 of the semiconductor device 1 and functions as a photoelectric conversion device. Patent Document 2 shows that the occurrence of an afterimage in an image is suppressed by reducing the oxygen concentration of the silicon layer in which the photoelectric conversion element is formed. On the other hand, when the oxygen concentration contained in the silicon layer is low, the mechanical strength of the semiconductor layer is reduced, and defects such as dislocations are likely to occur. However, as described above, the semiconductor device 1 of this embodiment has a configuration in which the semiconductor layer 1003 in which the element 305 including the photoelectric conversion element is arranged, the semiconductor layer 1002, and the semiconductor layer 1001 are stacked. Therefore, the oxygen concentration contained in each of the semiconductor layers 1001 to 1003 can be controlled independently for each semiconductor layer. Hereinafter, the configuration and manufacturing method of the semiconductor device 1 based on this idea will be described.

[0080] The basic configuration of the semiconductor device 1 may be any of the configurations described above. In this embodiment, a plurality of elements 305 including a photoelectric conversion element are arranged in the semiconductor layer 1003, an element circuit including a transistor 205 for amplifying a signal output from the photoelectric conversion element is arranged in the semiconductor layer 1002, and a drive circuit for driving the plurality of elements 305 and the element circuit is arranged in the semiconductor layer 1001. In addition, the description will be given assuming that each of the semiconductor layers 1001 to 1003 is made of silicon.

[0081] As described above, it is necessary to reduce the oxygen concentration in the semiconductor layer 1003 in which the photoelectric conversion element is disposed. Therefore, by using a substrate having an epitaxial layer as the semiconductor substrate 1003a shown in Fig. 10(a), it is possible to effectively reduce the oxygen concentration in the silicon layer 1003 in which the photoelectric conversion element (element 305) is disposed. In this case, by reducing the heat load during the process on the semiconductor substrate 1003a (semiconductor layer 1003), it is possible to suppress the diffusion of oxygen from the bulk of the semiconductor substrate 1003a to the epitaxial layer.

[0082] Also, for example, each semiconductor substrate (semiconductor layer) may be prepared so that the maximum oxygen concentration of the semiconductor substrate 1003a (semiconductor layer 1003) is lower than the maximum oxygen concentration of the semiconductor substrate 1002a (semiconductor layer 1002) and the maximum oxygen concentration of the semiconductor layer 1001. As described above, the semiconductor substrate 1003a is thinned to become the semiconductor layer 1003. The thinned semiconductor layer 1003 that remains is mostly made up of an epitaxial layer portion in which a photoelectric conversion element is disposed. Therefore, even if an epitaxial substrate is selected as the semiconductor substrate 1003a, the maximum oxygen concentration of the semiconductor layer 1003 in the completed semiconductor device 1 may be lower than the maximum oxygen concentrations of the semiconductor layers 1002 and 1003.

[0083] Also, for example, the semiconductor substrate 1003a (semiconductor layer 1003) may be configured such that no trench-type element isolation structure is arranged in region 2 where the multiple elements 305 are arranged. This suppresses the occurrence of dislocations in the semiconductor substrate 1003a (semiconductor layer 1003) due to stress applied to the vicinity of the element isolation structure. In other words, it is possible to suppress the occurrence of defects due to a decrease in mechanical strength in region 2 where the photoelectric conversion elements are arranged, and suppress the deterioration of image quality.

[0084] On the other hand, the oxygen concentration of the semiconductor layers 1001 and 1002 is higher than the oxygen concentration of the semiconductor layer 1003. This suppresses a decrease in mechanical strength in the semiconductor layers 1001 and 1002. For this reason, for example, the semiconductor layer 1001 may be provided with a trench-type element isolation structure for isolating the transistors 106 arranged in the semiconductor layer 1001 from each other. Similarly, the semiconductor layer 1002 may be provided with a trench-type element isolation structure for isolating the transistors 205 arranged in the semiconductor layer 1002 from each other.

[0085] For example, the maximum oxygen concentration on the main surface 15 side of the semiconductor layer 1003 is set to 1×10 17 atoms / cm 3 The maximum oxygen concentration in the semiconductor layer 1002 is set to 1×10 17 atoms / cm 3 From 10 17 atoms / cm 3 The maximum oxygen concentration in the semiconductor layer 1001 is set to 10 17 atoms / cm 3 From central Taiwan to 10 18 atoms / cm 3 In this configuration, the maximum oxygen concentration of the semiconductor layer 1001 is higher than the maximum oxygen concentration of the semiconductor layer 1002, which is higher than the maximum oxygen concentration of the semiconductor layer 1003. With this configuration, it is possible to effectively suppress the occurrence of defects due to a decrease in mechanical strength while suppressing residual images of an image obtained using the semiconductor layer 1. 17 atoms / cm 3 For example, a daichuban is 7×1017 atoms / cm 3 is less than.

[0086] Also, for example, a process of forming an element isolation region or the like in the semiconductor substrate 1002a may be performed before the process of stacking the semiconductor substrate 1003a and the semiconductor substrate 1002a as shown in FIG. 11(b). By performing at least a part of the process for the semiconductor substrate 1002a before stacking the semiconductor substrate 1003a and the semiconductor substrate 1002a, the thermal load on the semiconductor substrate 1003a (semiconductor layer 1003) is reduced. As a result, the movement of oxygen from the bulk of the semiconductor substrate 1003a (semiconductor layer 1003) to the epitaxial layer is suppressed, and an increase in the oxygen concentration of the epitaxial layer in which the photoelectric conversion element is arranged is suppressed. In addition, by reducing the number of processes through which the semiconductor layer 1003 (semiconductor substrate 1003a) passes, the mechanical load on the semiconductor substrate 1003a (semiconductor layer 1003) is reduced. As a result, the occurrence of defects due to a decrease in the mechanical strength of the semiconductor layer 1003 (semiconductor substrate 1003) can be suppressed.

[0087] Furthermore, in order to suppress an increase in the oxygen concentration in the epitaxial layer of the semiconductor substrate 1003a (semiconductor layer 1003), the following manufacturing process may be used. It is effective to reduce the thermal budget of the semiconductor layer 1003. The thermal budget is determined by time, temperature, and the like. Methods for reducing the thermal budget of the semiconductor layer 1003 include, for example, the following methods. In the manufacturing process of the semiconductor device 1, the maximum temperature of the heat treatment applied to the semiconductor layer 1003 (semiconductor substrate 1003a) is set lower than the maximum temperature of the heat treatment applied to the semiconductor layer 1002 (semiconductor substrate 1002a) and the semiconductor layer 1001. Also, for example, the maximum temperature of the heat treatment after the semiconductor substrate 1003a (semiconductor layer 1001) and the semiconductor substrate 1002a (semiconductor layer 1002) are stacked (the process after FIG. 11(b)) is set to be lower than the maximum temperature of the heat treatment applied to each substrate before the semiconductor substrate 1003a (semiconductor layer 1003) and the semiconductor substrate 1002a (semiconductor layer 1002) are stacked.

[0088] Here, as described above, the semiconductor layer 1002 can be formed thin in consideration of the processing stability and resistance stability of the through via in which the plug electrode 5 is disposed. That is, the thinned semiconductor layer 1002 can be thinner than the semiconductor layer 1001 and the semiconductor layer 1003. In this case, the semiconductor layer 1001 may be thicker than the semiconductor layer 1003. Therefore, the semiconductor layer 1001 can also function as a support substrate for the semiconductor device 1.

[0089] Thus, the semiconductor layer 1002 is thinner than the semiconductor layer 1001, and its mechanical strength is easily reduced. Therefore, the maximum oxygen concentration of the semiconductor layer 1002 may be higher than the maximum oxygen concentration of the semiconductor layer 1001 and the maximum oxygen concentration of the semiconductor layer 1003. Even in this case, the maximum oxygen concentration of the semiconductor layer 1001 is higher than the maximum oxygen concentration of the semiconductor layer 1003. In other words, in order to suppress afterimages, the oxygen concentration of the semiconductor layer 1003 is lower than the semiconductor layers 1001 and 1002. For example, the maximum oxygen concentration on the main surface 15 side of the semiconductor layer 1003 is set to 1×10 17 atoms / cm 3 The maximum oxygen concentration of the semiconductor layer 1002 is set to 10 17 atoms / cm 3 From central Taiwan to 10 18 atoms / cm 3 The maximum oxygen concentration in the semiconductor layer 1001 is set to 1×10 17 atoms / cm 3 From 10 17 atoms / cm 3 This suppresses the occurrence of defects in the thin semiconductor layer 1002, which is prone to deterioration in mechanical strength. As a result, the reliability and other characteristics of the semiconductor device 1 are improved. 17 atoms / cm 3 For example, a daichuban is 7×10 17 atoms / cm 3 is less than.

[0090] By taking into consideration the concentration of oxygen contained in the semiconductor layers 1001-1003, image retention is suppressed in the semiconductor device 1 functioning as a photoelectric conversion device. In addition, by using the above-mentioned process, it is possible to suppress the occurrence of defects due to a decrease in the mechanical strength of the semiconductor layers 1001-1003. This can improve the characteristics of the semiconductor device 1, such as the quality of images obtained by the semiconductor device 1 and the reliability of the semiconductor device 1.

[0091] As described above, by performing at least a part of the process for the semiconductor substrate 1002a before laminating the semiconductor substrate 1003a and the semiconductor substrate 1002a, the thermal and mechanical load on the semiconductor substrate 1003a (semiconductor layer 1003) is suppressed. On the other hand, in the process of bonding the semiconductor substrate 1003a (semiconductor layer 1001) and the semiconductor substrate 1002a (semiconductor layer 1002), if unevenness occurs on the surface of the structure 1021 in a process before bonding, the reliability of the bond between the structure 1021 and the structure 1030 may decrease. As a result, the reliability of the semiconductor device 1 may decrease.

[0092] For example, when (a precursor structure of) the insulator portion 207 described above is formed on the main surface 13 of the semiconductor substrate 1002a and then the structure 1021 and the structure 1030 are bonded together, there is a possibility that a step is generated on the surface of the structure 1021 by the insulator portion 207. Therefore, with reference to Figs. 23(a) to 23(d) to Figs. 24(a) and 24(b), a method for flattening the surface of the structure 1021 will be described even when (a precursor structure of) the insulator portion 207 is formed on the structure 1021 before bonding the structure 1021 and the structure 1030. The steps described below are steps that replace the steps shown in Figs. 11(a) to 11(d).

[0093] First, as shown in Fig. 23(a), an insulating layer 1022 and an insulating layer 1023 are disposed as a structure 1021 on a main surface 13 of a semiconductor substrate 1002a. For example, silicon oxide is used for the insulating layer 1022. For example, silicon nitride is used for the insulating layer 1023. The insulating layer 1023 is made of a material different from the insulator 2072 for forming the insulator portion 207 in a later process.

[0094] 23(b), an opening is formed in the insulating layer 1023 through the opening in the mask pattern, and a groove 2071 is formed in the main surface 13 of the semiconductor substrate 1002a. At this time, after the opening is formed in the insulating layer 1023 using the mask pattern, the insulating layer 1022 and the semiconductor substrate 1002a may be etched using the opening formed in the insulating layer 1023 as a mask.

[0095] After forming the grooves 2071, as shown in FIG. 24(c), an insulator 2072 is formed to cover the main surface 13 of the semiconductor substrate 1002a and fill the grooves 2071. The insulator 2072 is made of, for example, silicon oxide. In this manner, different materials are used for the insulating layer 1023 and the insulator 2072. When the insulator 2072 is made of silicon oxide, the insulating layer 1023 may be made of, for example, polysilicon in addition to the above-mentioned silicon oxide.

[0096] After the insulator 2072 is formed, as shown in FIG. 23(d), the insulator 272 is planarized using the insulating layer 1023 as an etching stopper, and the bonding surface, which is the surface of the structure 1021, is formed. The planarization of the insulator 272 is performed, for example, using a CMP device. As described above, since the insulating layer 1023 is made of a material different from the insulator 2072, by setting the planarization conditions to appropriate conditions, etching (polishing) of the insulating layer 1023 is suppressed, and the surface of the structure 1021 becomes flat. The bonding surface, which is the surface of the structure 1021, is formed by the insulating layer 1023 and the insulator 2072 embedded in the groove 2071. In addition, although it depends on the etching conditions for forming the groove 2071 shown in FIG. 23(b), the width of the groove 2071 may have a tapered shape in which the bonding surface side, which is the surface of the structure 1021, is wider. In that case, the insulator part 206 formed through a later process has a tapered shape according to the groove 2071. Note that for the next bonding, silicon oxide may be formed on the insulating layer 1023. Since silicon oxide is formed on a flat surface, it can have a smooth surface. Furthermore, the silicon oxide disposed on the insulating layer 1023 may be subjected to planarization treatment. As a result, a bonding surface with improved flatness can be obtained.

[0097] 24(a), the surface of the structure 1030 formed on the main surface 14 of the semiconductor substrate 1003a is bonded to the above-mentioned bonding surface of the structure 1021 formed on the main surface 13 of the semiconductor substrate 1002. This causes the semiconductor substrate 1003a (semiconductor layer 1003) and the semiconductor substrate 1002a (semiconductor layer 1002) to be stacked. As described above, the bonding surface, which is the surface of the structure 1021, can be formed flat, so that it is possible to prevent a decrease in the bonding strength between the structure 1021 and the structure 1030 caused by unevenness occurring on the surface of the structure 1021.

[0098] After the semiconductor substrate 1003a (semiconductor layer 1003) and the semiconductor substrate 1002a (semiconductor layer 1002) are laminated, the semiconductor substrate 1002a is thinned from the side of the main surface 12a opposite to the main surface 13 on which the structures 1021 are formed. As a result, as shown in FIG. 24(b), the semiconductor layer 1002 including the insulator portion 207 is formed. When thinning the semiconductor substrate 1002a, etching (polishing) may be performed using the insulator 2072 as an etching stopper. The steps thereafter are the steps shown in FIG. 12(a) and subsequent steps.

[0099] In the above example, the case where the insulator portion 207 (precursor structure) is formed on the semiconductor substrate 1002 has been described, but the present invention is not limited to this. For example, the insulator portion 206 (precursor structure) may be formed simultaneously with the formation of the insulator portion 207 (precursor structure).

[0100] 23(a) to 23(d) to 24(a) and 24(b), a decrease in bonding strength can be suppressed in the process of bonding the semiconductor substrate 1003a (semiconductor layer 1003) and the semiconductor substrate 1002a (semiconductor layer 1002). In addition, a part of the process for the semiconductor substrate 1002a can be performed before the semiconductor substrate 1003a and the semiconductor substrate 1002a are laminated. This reduces the process load on the semiconductor layer 1003. In other words, the reliability of the semiconductor device 1 is improved, and the quality of the image obtained by the semiconductor device 1 is improved. As a result, the characteristics of the semiconductor device 1 can be improved.

[0101] The above-described embodiments can be appropriately combined. For example, the step of forming the insulator portion 207 (a precursor structure thereof) before laminating the semiconductor substrate 1002a and the semiconductor substrate 1003a can be incorporated into each of the configurations of the semiconductor device 1 shown in FIG. 2, FIG. 5 to FIG. 7, FIG. 9, and FIG. 16.

[0102] The disclosure of the present specification includes the following semiconductor device and method for manufacturing the semiconductor device.

[0103] (Item 1) A semiconductor device in which a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer are stacked, The second semiconductor layer is disposed between the first semiconductor layer and the third semiconductor layer, a first structure including a first insulating layer is disposed between a first major surface of the first semiconductor layer and a second major surface of the second semiconductor layer that face each other; a second structure including a second insulating layer is disposed between a third major surface of the second semiconductor layer and a fourth major surface of the third semiconductor layer that face each other; In an orthogonal projection onto the fourth main surface, a region in which a plurality of elements are arranged in the third semiconductor layer is defined as a first region, and a region between the first region and a peripheral portion of the third semiconductor layer is defined as a second region; an opening is disposed in the second region, the opening penetrating the third semiconductor layer, the second structure, and the second semiconductor layer from a fifth main surface opposite to the fourth main surface of the third semiconductor layer to a pad electrode disposed on the first structure, and exposing the pad electrode; In an orthogonal projection onto the third main surface, an insulator portion is disposed between the first region of the second semiconductor layer and the opening, the insulator portion penetrating the second semiconductor layer from the second main surface to the third main surface.

[0104] (Item 2) 2. The semiconductor device according to item 1, wherein, in an orthogonal projection onto the third main surface, the insulator portion is disposed so as to surround the opening portion.

[0105] (Item 3) 3. The semiconductor device according to item 2, wherein the insulator portion constitutes a wall surface of the opening portion that penetrates the second semiconductor layer.

[0106] (Item 4) a plurality of pad electrodes including the pad electrode and the opening and a plurality of openings are provided; 4. The semiconductor device according to item 3, wherein, in an orthogonal projection onto the third main surface, the insulator portion is disposed contiguous with the plurality of openings.

[0107] (Item 5) a plurality of pad electrodes including the pad electrode and the opening and a plurality of openings are provided; the plurality of openings include a first opening and a second opening adjacent to each other, In an orthogonal projection onto the third principal surface, the insulator portion includes a first portion surrounding the first opening and a second portion surrounding the second opening, 4. The semiconductor device according to item 3, wherein a part of the second semiconductor layer is disposed between the first portion and the second portion.

[0108] (Item 6) 6. The semiconductor device according to item 5, wherein a portion of the second semiconductor layer arranged in the first region and a portion of the second semiconductor layer arranged between the plurality of openings and a peripheral portion of the second semiconductor layer are continuous with each other through the portion of the second semiconductor layer.

[0109] (Item 7) The semiconductor device according to any one of items 3 to 6, characterized in that a member made of a material different from the first insulating layer and the insulating portion is disposed in a portion of the first structure that contacts the insulating portion.

[0110] (Item 8) A transistor is disposed on the second main surface, 8. The semiconductor device according to item 7, wherein the gate electrode of the transistor and the member are made of the same material.

[0111] (Item 9) 9. The semiconductor device according to item 7 or 8, wherein the member includes at least one of polysilicon, amorphous silicon, and single crystal silicon.

[0112] (Item 10) 10. The semiconductor device according to any one of items 7 to 9, wherein, in an orthogonal projection onto the fifth main surface, a portion of the opening that is disposed in the first structure is disposed on the inner side than a portion of the opening that penetrates the third semiconductor layer, the second structure, and the second semiconductor layer.

[0113] (Item 11) 11. The semiconductor device according to any one of claims 1 to 10, further comprising a conductive member disposed in the second region, the conductive member extending from the first structure through the second semiconductor layer to the second structure.

[0114] (Item 12) Item 12. The semiconductor device according to item 11, wherein the conductive member is arranged to surround the first region.

[0115] (Item 13) 13. The semiconductor device according to item 11 or 12, wherein the conductive member is disposed so as to surround the opening.

[0116] (Item 14) 14. The semiconductor device according to any one of items 1 to 13, wherein the plurality of elements include a photoelectric conversion element.

[0117] (Item 15) an element circuit including a transistor that amplifies a signal output from the photoelectric conversion element is disposed on the second principal surface; Item 15. The semiconductor device according to item 14, wherein a drive circuit for driving the plurality of elements and the element circuit is arranged on the first main surface.

[0118] (Item 16) The insulator portion is a first insulator portion, the first structure includes a wiring pattern disposed in the first insulating layer; a plug electrode for connecting the photoelectric conversion element and the wiring pattern is disposed through the second structure and the second semiconductor layer; The semiconductor device described in item 15, characterized in that, in an orthogonal projection onto the third main surface, the second semiconductor layer has a second insulator portion that surrounds the plug electrode and penetrates the second semiconductor layer from the second main surface to the third main surface.

[0119] (Item 17) Item 17. The semiconductor device according to item 16, wherein the first insulating portion and the second insulating portion are made of the same material.

[0120] (Item 18) the second insulating layer includes a first layer in contact with the second semiconductor layer, and a second layer disposed between the first layer and the third semiconductor layer and in contact with the first layer; Item 18. The semiconductor device according to item 16 or 17, wherein the second layer is made of a material different from that of the second insulating portion.

[0121] (Item 19) the second insulator portion is made of silicon oxide, Item 19. The semiconductor device according to item 18, wherein the second layer is made of silicon nitride or polysilicon.

[0122] (Item 20) 20. The semiconductor device according to any one of items 14 to 19, further comprising a third structure including an optical element disposed on the fifth main surface.

[0123] (Item 21) 21. The semiconductor device according to item 20, wherein the optical element includes at least one of an inner layer lens, a color filter, or a microlens.

[0124] (Item 22) the opening further penetrates the third structure, 22. The semiconductor device according to item 20 or 21, characterized in that, in an orthogonal projection onto the fifth principal surface, a portion of the opening penetrating the third semiconductor layer, the second structure, and the second semiconductor layer is located more inward than a portion of the opening that is located in the third structure.

[0125] (Item 23) the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are made of silicon; a maximum oxygen concentration of the first semiconductor layer is higher than a maximum oxygen concentration of the second semiconductor layer; 23. The semiconductor device according to any one of items 14 to 22, wherein the maximum oxygen concentration of the second semiconductor layer is higher than the maximum oxygen concentration of the third semiconductor layer.

[0126] (Item 24) the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are made of silicon; 23. The semiconductor device according to any one of items 14 to 22, wherein the maximum oxygen concentration of the second semiconductor layer is higher than the maximum oxygen concentration of the first semiconductor layer and the maximum oxygen concentration of the third semiconductor layer.

[0127] (Item 25) Item 25. The semiconductor device according to item 24, wherein the maximum oxygen concentration of the first semiconductor layer is higher than the maximum oxygen concentration of the third semiconductor layer.

[0128] (Item 26) In the orthogonal projection onto the third principal surface, the second semiconductor layer has a rectangular shape; A semiconductor device described in any one of items 1 to 25, characterized in that the width of the area of ​​the second region in which the insulator portion is arranged is 1 / 100 or less of the length of the short side of the second semiconductor layer.

[0129] (Item 27) A semiconductor device in which a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer are stacked, The second semiconductor layer is disposed between the first semiconductor layer and the third semiconductor layer, a first structure including a first insulating layer is disposed between a first major surface of the first semiconductor layer and a second major surface of the second semiconductor layer that face each other; a second structure including a second insulating layer is disposed between a third major surface of the second semiconductor layer and a fourth major surface of the third semiconductor layer that face each other; In an orthogonal projection onto the fourth main surface, a region in which a plurality of elements are arranged in the third semiconductor layer is defined as a first region, and a region between the first region and a peripheral portion of the third semiconductor layer is defined as a second region; A semiconductor device, comprising: a conductive member disposed in the second region, the conductive member extending from the first structure to the second structure.

[0130] (Item 28) 28. The semiconductor device according to item 27, wherein the conductive member is arranged to surround the first region.

[0131] (Item 29) Item 29. The semiconductor device according to item 27 or 28, further comprising an opening arranged in the second region from a fifth main surface of the third semiconductor layer opposite the fourth main surface to a pad electrode arranged on the first structure, penetrating the third semiconductor layer, the second structure, and the second semiconductor layer, and exposing the pad electrode.

[0132] (Item 30) 30. The semiconductor device according to item 29, wherein the conductive member is arranged to surround the opening.

[0133] (Item 31) an insulator portion penetrating the second semiconductor layer from the second main surface to the third main surface is disposed so as to surround the opening in an orthogonal projection onto the third main surface; 31. The semiconductor device according to item 29 or 30, wherein the conductive member penetrates the insulator portion.

[0134] (Item 32) 32. The semiconductor device according to any one of items 29 to 31, wherein the pad electrode is disposed at a position closer to the first semiconductor layer than the conductive member.

[0135] (Item 33) the first structure includes a conductor portion in the first insulating layer, in the same layer as the pad electrode, and made of the same material as the pad electrode; 32. The semiconductor device according to any one of items 29 to 31, wherein the conductive member is in contact with the conductor portion.

[0136] (Item 34) the first structure includes a wiring pattern disposed in the first insulating layer; 34. The semiconductor device according to any one of items 27 to 33, wherein the conductive member is in contact with the wiring pattern.

[0137] (Item 35) A plurality of conductive members including the conductive member are provided, Item 35. The semiconductor device according to item 34, wherein the plurality of conductive members are connected to each other by the wiring pattern.

[0138] (Item 36) 36. The semiconductor device according to any one of items 27 to 35, wherein the conductive member is in contact with the fourth main surface.

[0139] (Item 37) the plurality of elements includes a photoelectric conversion element, Item 37. The semiconductor device according to item 36, wherein the impurity concentration of the portion of the fourth main surface that is in contact with the conductive member is the same as the impurity concentration of a floating diffusion disposed in the photoelectric conversion element.

[0140] (Item 38) a contact member made of the same material as gate electrodes included in the plurality of elements is disposed in the second region of the first structure; 36. The semiconductor device according to any one of items 27 to 35, wherein the conductive member is in contact with the contact member.

[0141] (Item 39) Item 39. The semiconductor device according to item 38, characterized in that an insulating film made of the same material as a gate insulating film arranged between the gate electrode and the fourth main surface is arranged between the contact member and the fourth main surface.

[0142] (Item 40) The semiconductor device according to any one of items 27 to 39, characterized in that a trench is arranged in the second region, the trench extending from a fifth main surface of the third semiconductor layer opposite the fourth main surface toward the fourth main surface.

[0143] (Item 41) Item 41. The semiconductor device according to item 40, wherein an insulator is embedded in the trench.

[0144] (Item 42) Item 41. The semiconductor device according to item 40, wherein the wall surface of the trench is covered with an insulator and a conductor is embedded therein.

[0145] (Item 43) 43. The semiconductor device according to any one of items 40 to 42, wherein the trench penetrates the third semiconductor layer.

[0146] (Item 44) 44. The semiconductor device according to any one of items 40 to 43, wherein the trench is not disposed in the second structure.

[0147] (Item 45) 45. The semiconductor device according to any one of items 27 to 44, wherein the conductive member penetrates the second structure and further extends to the third semiconductor layer.

[0148] (Item 46) A semiconductor device in which a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer are stacked, The second semiconductor layer is disposed between the first semiconductor layer and the third semiconductor layer, A plurality of elements including a photoelectric conversion element are disposed on the third semiconductor layer, an element circuit including a transistor for amplifying a signal output from the photoelectric conversion element is disposed in the second semiconductor layer; a drive circuit for driving the plurality of elements and the element circuit is disposed on the first semiconductor layer; the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are made of silicon; a maximum oxygen concentration of the first semiconductor layer is higher than a maximum oxygen concentration of the second semiconductor layer; A semiconductor device, wherein the second semiconductor layer has a maximum oxygen concentration higher than a maximum oxygen concentration of the third semiconductor layer.

[0149] (Item 47) A semiconductor device in which a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer are stacked, The second semiconductor layer is disposed between the first semiconductor layer and the third semiconductor layer, A plurality of elements including a photoelectric conversion element are disposed on the third semiconductor layer, an element circuit including a transistor for amplifying a signal output from the photoelectric conversion element is disposed in the second semiconductor layer; a drive circuit for driving the plurality of elements and the element circuit is disposed on the first semiconductor layer; the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are made of silicon; A semiconductor device, wherein the second semiconductor layer has a maximum oxygen concentration higher than a maximum oxygen concentration of the first semiconductor layer and a maximum oxygen concentration of the third semiconductor layer.

[0150] (Item 48) Item 48. The semiconductor device according to item 47, wherein the maximum oxygen concentration of the first semiconductor layer is higher than the maximum oxygen concentration of the third semiconductor layer.

[0151] (Item 49) In the third semiconductor layer, a trench type element isolation structure is not arranged in a region in which the plurality of elements are arranged, Item 49. The semiconductor device according to item 47 or 48, wherein the second semiconductor layer has a trench type element isolation structure.

[0152] (Item 50) 50. The semiconductor device according to any one of items 47 to 49, wherein the second semiconductor layer is thinner than the first semiconductor layer and the third semiconductor layer.

[0153] (Item 51) Item 51. The semiconductor device according to item 50, wherein the first semiconductor layer is thicker than the third semiconductor layer.

[0154] (Item 52) A method for manufacturing a semiconductor device in which a first semiconductor layer in which a plurality of elements including a photoelectric conversion element are arranged, a second semiconductor layer in which an element circuit including a transistor that amplifies a signal output from the photoelectric conversion element is arranged, and a third semiconductor layer in which a drive circuit for driving the plurality of elements and the element circuit is arranged, comprising: The second semiconductor layer is disposed between the first semiconductor layer and the third semiconductor layer, A manufacturing method for the semiconductor device, characterized in that, in the manufacturing process of the semiconductor device, a maximum temperature of a heat treatment applied to the third semiconductor layer is lower than a maximum temperature of a heat treatment applied to the first semiconductor layer and the second semiconductor layer.

[0155] (Item 53) A method for manufacturing a semiconductor device in which a first semiconductor layer in which a plurality of elements including a photoelectric conversion element are arranged, a second semiconductor layer in which an element circuit including a transistor that amplifies a signal output from the photoelectric conversion element is arranged, and a third semiconductor layer in which a drive circuit for driving the plurality of elements and the element circuit is arranged, comprising: The second semiconductor layer is disposed between the first semiconductor layer and the third semiconductor layer, The method includes a step of stacking the first semiconductor layer and the second semiconductor layer, a maximum temperature of a heat treatment after the first semiconductor layer and the second semiconductor layer are stacked is lower than a maximum temperature of a heat treatment before the first semiconductor layer and the second semiconductor layer are stacked.

[0156] (Item 54) A method for manufacturing a semiconductor device in which a first semiconductor layer in which a structure including a plurality of elements including a photoelectric conversion element is arranged and a second semiconductor layer in which an element circuit including a transistor for amplifying a signal output from the photoelectric conversion element is arranged are stacked, the method comprising the steps of: providing the first semiconductor layer; forming an insulating layer on a first major surface of the second semiconductor layer; forming an opening in the insulating layer through an opening in a mask pattern and forming a groove in the first main surface; forming an insulator covering the first main surface so as to fill the groove; planarizing the insulator using the insulating layer as an etch stop to form a bonding surface; and bonding a surface of the structure to the bonding surface to stack the first semiconductor layer and the second semiconductor layer. The manufacturing method according to claim 1, wherein the joining surface is constituted by the insulating layer and the insulator embedded in the groove.

[0157] (Item 55) 55. The manufacturing method according to item 54, wherein the insulating layer is made of a material different from the insulator.

[0158] (Item 56) The insulating layer is made of silicon nitride or polysilicon. Item 56. The method according to item 54 or 55, wherein the insulator is made of silicon oxide.

[0159] (Item 57) The method further includes a step of thinning the second semiconductor layer from a side of a second main surface of the second semiconductor layer opposite to the first main surface after laminating the first semiconductor layer and the second semiconductor layer, 57. The manufacturing method according to any one of items 54 to 56, wherein the insulator is used as an etching stopper when thinning the second semiconductor layer.

[0160] (Item 58) preparing a third semiconductor layer in which the plurality of elements and a drive circuit for driving the element circuit are arranged; laminating the second semiconductor layer and the third semiconductor layer; 58. The method for producing a semiconductor device according to any one of items 54 to 57, further comprising:

[0161] (Item 59) Item 59. The manufacturing method according to item 58, further comprising a step of thinning the first semiconductor layer after stacking the second semiconductor layer and the third semiconductor layer.

[0162] (Item 60) 60. The manufacturing method according to any one of items 54 to 59, further comprising the step of forming the element circuit after thinning the second semiconductor layer.

[0163] (Item 61) 61. A manufacturing method according to any one of items 54 to 60, characterized in that the width of the groove has a tapered shape that is wider on the joining surface side.

[0164] The invention is not limited to the above-described embodiments, and various modifications and variations are possible without departing from the spirit and scope of the invention. Accordingly, the following claims are appended to apprise the public of the scope of the invention. [Explanation of symbols]

[0165] 1: semiconductor device, 2, 3: region, 6: opening, 11-15: main surface, 103, 202: insulating layer, 105: pad electrode, 206: insulating portion, 305: element, 1001-1003: semiconductor layer, 1015, 1025: structure

Claims

1. A semiconductor device in which a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer are stacked, wherein the second semiconductor layer is disposed between the first semiconductor layer and the third semiconductor layer, a first structure including a first insulating layer is disposed between a first main surface of the first semiconductor layer and a second main surface of the second semiconductor layer facing each other, a second structure including a second insulating layer is disposed between a third main surface of the second semiconductor layer and a fourth main surface of the third semiconductor layer facing each other, in a orthographic projection onto the fourth main surface, a region where a plurality of elements are disposed in the third semiconductor layer is defined as a first region, and a region between the first region and a peripheral portion of the third semiconductor layer is defined as a second region, in the second region, an opening is disposed that penetrates the third semiconductor layer, the second structure, and the second semiconductor layer from a fifth main surface on the opposite side of the fourth main surface of the third semiconductor layer to a pad electrode disposed in the first structure, exposing the pad electrode, an insulator portion is disposed at the same height as the second semiconductor layer between the first insulating layer and the second insulating layer and between the first region and the opening, in a orthographic projection onto the third main surface, the insulator portion is disposed so as to surround the opening, A semiconductor device, wherein the insulator portion constitutes a wall surface of a portion of the opening that penetrates the second semiconductor layer.

2. A plurality of pad electrodes including the pad electrode and the opening are disposed, The semiconductor device according to claim 1, wherein, in a orthographic projection onto the third main surface, the insulator portion is disposed continuously with respect to the plurality of openings.

3. A plurality of pad electrodes including the pad electrode and the opening are disposed, the plurality of openings include a first opening and a second opening adjacent to each other, in a orthographic projection onto the third main surface, the insulator portion includes a first portion surrounding the first opening and a second portion surrounding the second opening, The semiconductor device according to claim 1, wherein a part of the second semiconductor layer is disposed between the first portion and the second portion.

4. The semiconductor device according to claim 3, wherein a portion of the second semiconductor layer disposed in the first region and a portion of the second semiconductor layer disposed between the plurality of openings and a peripheral portion of the second semiconductor layer are continuous with each other by the part of the second semiconductor layer.

5. The semiconductor device according to claim 1, wherein a member made of a material different from that of the first insulating layer and the insulator portion is disposed at a portion of the first structure in contact with the insulator portion.

6. Transistors are disposed on the second main surface, The semiconductor device according to claim 5, wherein the gate electrode of the transistor and the member are made of the same material.

7. The semiconductor device according to claim 5, wherein the member includes at least one of polysilicon, amorphous silicon, or single crystal silicon.

8. In a orthographic projection onto the fifth main surface, a portion of the opening disposed in the first structure is disposed more inward than a portion of the opening that penetrates the third semiconductor layer, the second structure, and the second semiconductor layer. The semiconductor device according to claim 5, characterized in that.

9. The semiconductor device according to claim 1, further comprising a conductive member that penetrates the second semiconductor layer from the first structure and extends to the second structure in the second region.

10. The semiconductor device according to claim 9, wherein the conductive member is disposed so as to surround the first region.

11. The semiconductor device according to claim 9, wherein the conductive member is disposed so as to surround the opening.

12. The semiconductor device according to claim 1, wherein the plurality of elements include a photoelectric conversion element.

13. An element circuit including a transistor that amplifies a signal output from the photoelectric conversion element is disposed on the second main surface, The semiconductor device according to claim 12, wherein a drive circuit for driving the plurality of elements and the element circuit is disposed on the first main surface.

14. Taking the insulator portion as the first insulator portion, The first structure includes a wiring pattern disposed in the first insulating layer, A plug electrode for connecting the photoelectric conversion element and the wiring pattern is disposed to penetrate the second structure and the second semiconductor layer, In a orthographic projection onto the third main surface, a second insulator portion that surrounds the plug electrode and penetrates the second semiconductor layer from the second main surface to the third main surface is disposed in the second semiconductor layer. The semiconductor device according to claim 13, characterized in that.

15. The semiconductor device according to claim 14, wherein the first insulator portion and the second insulator portion are made of the same material.

16. The second insulating layer includes a first layer in contact with the second semiconductor layer, and a second layer disposed between the first layer and the third semiconductor layer and in contact with the first layer. The semiconductor device according to claim 14, wherein the second layer is made of a material different from that of the second insulator portion.

17. The second insulator portion is made of silicon oxide. The semiconductor device according to claim 16, wherein the second layer is made of silicon nitride or polysilicon.

18. The semiconductor device according to claim 12, further comprising a third structure including an optical element disposed on the fifth main surface.

19. The semiconductor device according to claim 18, wherein the optical element includes at least one of an in-layer lens, a color filter, or a microlens.

20. The opening further penetrates the third structure. In a orthographic projection onto the fifth main surface, a portion of the opening that penetrates the third semiconductor layer, the second structure, and the second semiconductor layer is disposed more inward than a portion of the opening that is disposed in the third structure. The semiconductor device according to claim 18.

21. The first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are made of silicon. The maximum oxygen concentration of the first semiconductor layer is higher than the maximum oxygen concentration of the second semiconductor layer. The semiconductor device according to claim 12, wherein the maximum oxygen concentration of the second semiconductor layer is higher than the maximum oxygen concentration of the third semiconductor layer.

22. The first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are made of silicon. The semiconductor device according to claim 12, wherein the maximum oxygen concentration of the second semiconductor layer is higher than the maximum oxygen concentration of the first semiconductor layer and the maximum oxygen concentration of the third semiconductor layer.

23. The semiconductor device according to claim 22, wherein the maximum oxygen concentration of the first semiconductor layer is higher than the maximum oxygen concentration of the third semiconductor layer.

24. In an orthographic projection onto the third main surface. The second semiconductor layer has a rectangular shape. The semiconductor device according to claim 1, wherein the width of the region in the second region where the insulator portion is disposed is 1 / 100 or less of the length of the short side of the second semiconductor layer.

25. A semiconductor device in which a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer are stacked, The second semiconductor layer is disposed between the first semiconductor layer and the third semiconductor layer, A first structure including a first insulating layer is disposed between the first main surface of the first semiconductor layer and the second main surface of the second semiconductor layer facing each other, A second structure including a second insulating layer is disposed between the third main surface of the second semiconductor layer and the fourth main surface of the third semiconductor layer facing each other, In the orthographic projection onto the fourth main surface, a region in which a plurality of elements are disposed in the third semiconductor layer is defined as a first region, and a region between the first region and the peripheral portion of the third semiconductor layer is defined as a second region, In the second region, an opening is disposed that penetrates the third semiconductor layer, the second structure, and the second semiconductor layer from the fifth main surface on the opposite side of the fourth main surface of the third semiconductor layer to the pad electrode disposed in the first structure, exposing the pad electrode. In the second region, a conductive member extending from the first structure to the second structure is disposed, The semiconductor device, wherein the conductive member does not penetrate the first semiconductor layer.

26. The semiconductor device according to claim 25, wherein the conductive member is disposed so as to surround the first region.

27. The semiconductor device according to claim 25, wherein the conductive member is disposed so as to surround the opening.

28. In the orthographic projection onto the third main surface, an insulator portion is disposed that penetrates the second semiconductor layer from the second main surface to the third main surface so as to surround the opening, The semiconductor device according to claim 25, wherein the conductive member penetrates the insulator portion.

29. The semiconductor device according to claim 25, wherein the pad electrode is disposed at a position closer to the first semiconductor layer than the conductive member.

30. The first structure includes a conductor portion formed of the same material as the pad electrode in the same layer as the pad electrode in the first insulating layer, The semiconductor device according to claim 25, wherein the conductive member is in contact with the conductor portion.

31. The first structure includes a wiring pattern disposed in the first insulating layer. The semiconductor device according to claim 25, wherein the conductive member is in contact with the wiring pattern.

32. A plurality of conductive members including the conductive member are arranged, The semiconductor device according to claim 31, wherein the plurality of conductive members are connected to each other by the wiring pattern.

33. The semiconductor device according to claim 25, wherein the conductive member is in contact with the fourth main surface.

34. The plurality of elements include a photoelectric conversion element, The semiconductor device according to claim 33, wherein an impurity concentration of a portion of the fourth main surface in contact with the conductive member is the same as an impurity concentration of a floating diffusion arranged in the photoelectric conversion element.

35. In the second region of the first structure, a contact member made of the same material as a gate electrode included in the plurality of elements is arranged, The semiconductor device according to claim 25, wherein the conductive member is in contact with the contact member.

36. An insulating film made of the same material as a gate insulating film arranged between the gate electrode and the fourth main surface is arranged between the contact member and the fourth main surface. The semiconductor device according to claim 35, characterized in that

37. The semiconductor device according to claim 25, wherein a trench extending from a fifth main surface opposite to the fourth main surface of the third semiconductor layer toward the fourth main surface is arranged in the second region.

38. The semiconductor device according to claim 37, wherein an insulator is embedded in the trench.

39. The semiconductor device according to claim 37, wherein a wall surface of the trench is covered with an insulator and a conductor is embedded therein.

40. The semiconductor device according to claim 37, wherein the trench penetrates the third semiconductor layer.

41. The semiconductor device according to claim 37, wherein the trench is not arranged in the second structure.

42. The semiconductor device according to claim 25, wherein the conductive member penetrates the second structure and further extends to the third semiconductor layer.

43. A semiconductor device in which a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer are stacked, The second semiconductor layer is arranged between the first semiconductor layer and the third semiconductor layer, A plurality of elements including a photoelectric conversion element are arranged in the third semiconductor layer, An element circuit including a transistor that amplifies a signal output from the photoelectric conversion element is disposed in the second semiconductor layer. A drive circuit for driving the plurality of elements and the element circuit is disposed in the first semiconductor layer. The first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are made of silicon. The maximum oxygen concentration of the first semiconductor layer is higher than the maximum oxygen concentration of the second semiconductor layer. A semiconductor device, wherein the maximum oxygen concentration of the second semiconductor layer is higher than the maximum oxygen concentration of the third semiconductor layer.

44. A semiconductor device in which a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer are stacked, The second semiconductor layer is disposed between the first semiconductor layer and the third semiconductor layer. A plurality of elements including a photoelectric conversion element are disposed in the third semiconductor layer. An element circuit including a transistor that amplifies a signal output from the photoelectric conversion element is disposed in the second semiconductor layer. A drive circuit for driving the plurality of elements and the element circuit is disposed in the first semiconductor layer. The first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are made of silicon. A semiconductor device, wherein the maximum oxygen concentration of the second semiconductor layer is higher than the maximum oxygen concentration of the first semiconductor layer and the maximum oxygen concentration of the third semiconductor layer.

45. The semiconductor device according to claim 44, wherein the maximum oxygen concentration of the first semiconductor layer is higher than the maximum oxygen concentration of the third semiconductor layer.

46. In the third semiconductor layer, a trench-type element isolation structure is not disposed in a region where the plurality of elements are disposed. The semiconductor device according to claim 44, wherein a trench-type element isolation structure is disposed in the second semiconductor layer.

47. The semiconductor device according to claim 44, wherein the second semiconductor layer is thinner than the first semiconductor layer and the third semiconductor layer.

48. The semiconductor device according to claim 47, wherein the first semiconductor layer is thicker than the third semiconductor layer.

49. A method of manufacturing a semiconductor device in which a first semiconductor layer in which a plurality of elements including a photoelectric conversion element are disposed, a second semiconductor layer in which an element circuit including a transistor that amplifies a signal output from the photoelectric conversion element is disposed, and a third semiconductor layer in which a drive circuit for driving the plurality of elements and the element circuit are disposed are stacked. The second semiconductor layer is disposed between the first semiconductor layer and the third semiconductor layer. In the manufacturing process of the semiconductor device, a manufacturing method characterized in that the maximum temperature of the heat treatment applied to the third semiconductor layer is lower than the maximum temperatures of the heat treatments applied to the first semiconductor layer and the second semiconductor layer.

50. A manufacturing method of a semiconductor device in which a first semiconductor layer in which a plurality of elements including a photoelectric conversion element are disposed, a second semiconductor layer in which an element circuit including a transistor that amplifies a signal output from the photoelectric conversion element is disposed, and a third semiconductor layer in which a drive circuit for driving the plurality of elements and the element circuit are disposed are stacked, The second semiconductor layer is disposed between the first semiconductor layer and the third semiconductor layer. Including a step of laminating the first semiconductor layer and the second semiconductor layer, A manufacturing method characterized in that the maximum temperature of the heat treatment after laminating the first semiconductor layer and the second semiconductor layer is lower than the maximum temperature of the heat treatment before laminating the first semiconductor layer and the second semiconductor layer.

51. A manufacturing method of a semiconductor device in which a first semiconductor layer in which a structure including a plurality of elements including a photoelectric conversion element is disposed and a second semiconductor layer in which an element circuit including a transistor that amplifies a signal output from the photoelectric conversion element are stacked, A step of preparing the first semiconductor layer; A step of forming an insulating layer on a first main surface of the second semiconductor layer; A step of forming an opening in the insulating layer through an opening of a mask pattern and forming a groove in the first main surface; A step of forming an insulator covering the first main surface so as to fill the groove; A step of planarizing the insulator using the insulating layer as an etching stopper to form a bonding surface; A step of laminating the first semiconductor layer and the second semiconductor layer by bonding the surface of the structure and the bonding surface, and A manufacturing method characterized in that the bonding surface is constituted by the insulating layer and the insulator embedded in the groove.

52. The manufacturing method according to claim 51, characterized in that the insulating layer is made of a material different from that of the insulator.

53. The insulating layer is made of silicon nitride or polysilicon The manufacturing method according to claim 51, characterized in that the insulator is made of silicon oxide.

54. After laminating the first semiconductor layer and the second semiconductor layer, the method further includes a step of thinning the second semiconductor layer from a side of a second main surface of the second semiconductor layer opposite to the first main surface. The manufacturing method according to claim 51, wherein when thinning the second semiconductor layer, the insulator is used as an etching stopper.

55. A step of preparing a third semiconductor layer in which the plurality of elements and a drive circuit for driving the element circuit are arranged; A step of laminating the second semiconductor layer and the third semiconductor layer; The manufacturing method according to claim 51, further comprising the above steps.

56. The manufacturing method according to claim 55, further comprising a step of thinning the first semiconductor layer after laminating the second semiconductor layer and the third semiconductor layer.

57. The manufacturing method according to claim 51, further comprising a step of forming the element circuit after thinning the second semiconductor layer.

58. The manufacturing method according to claim 51, wherein the groove has a tapered shape that is wider on the side of the bonding surface.

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