Wiring board, semiconductor device, and manufacturing method of the wiring board

Abstract

To provide a wiring board or the like capable of reducing an insertion loss and a reflection loss.SOLUTION: A wiring board includes: a first insulation layer; a first wiring layer provided to the first insulation layer; and a thin film layer that is provided onto one surface of the first insulation layer, and contains a second insulation layer different from the first insulation layer and a second wiring layer. The thin film layer includes: a first pad and a second pad that are provided onto a surface reflected to a surface opposite to the first insulation layer; a first via electrically connected with the first pad; and a second via electrically connected with the second pad. The first wiring layer is thicker than the second wiring layer, and includes a transmission wiring electrically connecting between the first via and the second via.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a wiring board, a semiconductor device, and a method for manufacturing a wiring board. [Background technology]

[0002] For example, a semiconductor device is known in which a wiring board such as an organic interposer is fabricated by forming a thin film layer on an insulating layer of a thermosetting resin, and the wiring board is mounted on a build-up board. Fig. 16 is an explanatory diagram showing an example of a conventional semiconductor device 100. The semiconductor device 100 shown in Fig. 16 has a build-up board 102 and a wiring board 105 mounted on the build-up board 102. The surface of the build-up board 102 has a solder resist 106 that suppresses adhesion of solder when the wiring board 105 is mounted.

[0003] The wiring board 105 has an insulating layer 111, a thin film layer 112, and an adhesive layer 113. The insulating layer 111 has a first conductive layer 114 disposed on one surface of the insulating layer 111, a second conductive layer 115 disposed on the other surface of the insulating layer 111, and a first via 111A that electrically connects the first conductive layer 114 and the second conductive layer 115.

[0004] The first conductive layer 114 has a pad 114A electrically connected to a pad 102A of the build-up substrate 102. The second conductive layer 115 has a pad 115A electrically connected between a first via 111A in the insulating layer 111 and a second via 112A in the thin film layer 112.

[0005] The thin film layer 112 has, for example, a thin film wiring layer in which a wiring layer and an insulating layer are laminated in sequence, a third conductive layer 116 laminated on the thin film wiring layer, and a second via 112A electrically connecting between the wiring layer in the thin film wiring layer and the third conductive layer 116. The thin film wiring layer has a first insulating layer 161, a first wiring layer 162 provided on the first insulating layer 161, a second insulating layer 163 covering the first wiring layer 162 and laminated on the first insulating layer 161, a second wiring layer 164 provided on the second insulating layer 163, and a third insulating layer 165 covering the second wiring layer 164 and laminated on the second insulating layer 163. The third conductive layer 116 has a pad 116A electrically connected to a chip terminal of the chip 103 by solder 118.

[0006] The build-up board 102 has a pad 102A1 (102A) electrically connected to a pad 114A in a first conductive layer 114 on a wiring board 105, and a pad 102A2 (102A) electrically connected to a connector 104 to be mounted. Furthermore, the build-up board 102 has a board via 102C electrically connected to the pad 102A. Furthermore, the build-up board 102 has a transmission wiring 102B electrically connecting between a board via 102C1 (102C) connected to a pad 102A1 connected to a chip 103, and a board via 102C2 (102C) connected to a pad 102A2 connected to a connector 104. Furthermore, the pad 102A1 in the build-up board 102 and the pad 114A of the wiring board 105 are electrically connected by a solder 117. Furthermore, the pads 102A2 in the build-up board 102 and the connector 104 are electrically connected by solder 117.

[0007] Transmission wiring 102B is a line that electrically connects chip 103 mounted on wiring board 105 and connector 104 mounted on build-up board 102, and transmits serial high-speed signals between chip 103 and connector 104. The line / space of transmission wiring 102B is, for example, about 15 μm / 15 μm, and the wiring thickness is, for example, 15 μm.

[0008] Then, chip 103 on wiring board 105 transmits a high-speed signal to connector 104 via the path of pad 116A → second via 112A → pad 115A → first via 111A → pad 114A → solder 117 → pad 102A1 → board via 102C1 → transmission wiring 102B → board via 102C2 → pad 102A2. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] JP 2020-202278 A [Patent Document 2] JP 2015-5612 A [Patent Document 3] JP 2020-47735 A Summary of the Invention [Problem to be solved by the invention]

[0010] However, in the semiconductor device 100, when a high-speed signal is transmitted between the chip 103 and the connector 104, reflection loss and insertion loss of the high-speed signal occur when the high-speed signal passes through a path using the transmission wiring 102B.

[0011] The disclosed technology has been made in view of the above-mentioned points, and has an object to provide a wiring board, a semiconductor device, and a method for manufacturing a wiring board that can reduce reflection loss and insertion loss. [Means for solving the problem]

[0012] In one embodiment, the wiring board disclosed in the present application has a first insulating layer, a first wiring layer provided on the first insulating layer, and a thin film layer provided on one side of the first insulating layer, the thin film layer including a second insulating layer and a second wiring layer different from the first insulating layer. The thin film layer has a first pad and a second pad provided on a surface opposite to the surface facing the first insulating layer, a first via electrically connecting to the first pad, and a second via electrically connecting to the second pad. The first wiring layer is structured to be thicker than the second wiring layer. The first wiring layer has a transmission wiring electrically connecting between the first via and the second via. Effect of the Invention

[0013] According to one aspect of the wiring board disclosed in the present application, it is possible to reduce reflection loss and insertion loss when a high-speed signal passes through. [Brief description of the drawings]

[0014] [Figure 1] FIG. 1 is an explanatory diagram illustrating an example of a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is a schematic cross-sectional view showing an example of a wiring board. [Diagram 3] FIG. 3 is an explanatory diagram showing an example of the dielectric constant and dielectric tangent of each insulating layer. [Figure 4] FIG. 4 is an explanatory diagram showing an example of features of a connector terminal and a chip terminal. [Figure 5A] FIG. 5A is an explanatory diagram showing an example of a preparation step. [Figure 5B] FIG. 5B is an explanatory diagram showing an example of the conductor layer forming step. [Figure 5C] FIG. 5C is an explanatory diagram showing an example of the insulating layer forming step. [Figure 6A] FIG. 6A is an explanatory diagram showing an example of a thin film layer forming step. [Figure 6B] FIG. 6B is an explanatory diagram showing an example of the support carrier peeling step. [Figure 7] FIG. 7 is an explanatory diagram showing an example of a solder forming step. [Figure 8] FIG. 8 is an explanatory diagram showing an example of a wiring board mounting process. [Figure 9] FIG. 9 is an explanatory diagram illustrating an example of a semiconductor device according to a second embodiment. [Figure 10] FIG. 10 is a schematic cross-sectional view showing an example of a wiring board. [Figure 11A] FIG. 11A is an explanatory diagram showing an example of a preparation step. [Figure 11B] FIG. 11B is an explanatory diagram showing an example of the conductor layer forming step. [Figure 11C] FIG. 11C is an explanatory diagram showing an example of the insulating layer forming step. [Figure 12A] FIG. 12A is an explanatory diagram showing an example of an inversion support carrier forming step. [Figure 12B] FIG. 12B is an explanatory diagram showing an example of the support carrier peeling step. [Figure 13A] FIG. 13A is an explanatory diagram showing an example of a thin film layer forming step. [Figure 13B] FIG. 13B is an explanatory diagram showing an example of the inversion support carrier peeling step. [Figure 14] FIG. 14 is an explanatory diagram showing an example of a solder forming step. [Figure 15] FIG. 15 is an explanatory diagram showing an example of a wiring board mounting process. [Figure 16] FIG. 16 is an explanatory diagram showing an example of a conventional semiconductor device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] Hereinafter, embodiments of a wiring board, a semiconductor device, and a method of manufacturing a wiring board disclosed in the present application will be described in detail with reference to the drawings. Note that the present invention is not limited to the embodiments. EXAMPLES

[0016] Fig. 1 is an explanatory diagram showing an example of a semiconductor device 1 of Example 1. The semiconductor device 1 shown in Fig. 1 has a build-up substrate 2 and a wiring substrate 5 on which a plurality of chips 3 and a connector 4 are mounted, and is configured by mounting the wiring substrate 5 on the build-up substrate 2. The surface of the build-up substrate 2 has a solder resist 6 for suppressing adhesion of solder when the wiring substrate 5 is mounted.

[0017] 2 is a schematic cross-sectional view showing an example of wiring board 5. Wiring board 5 has insulating layer 11, thin film layer 12, and adhesive layer 13. The planar shape of wiring board 5 may be, for example, a square shape with sides of 40 mm. However, the planar shape is not limited to this, and wiring board 5 may have any planar shape.

[0018] The insulating layer 11 has a first conductive layer 14 disposed on one surface of the insulating layer 11, a second conductive layer 15 disposed on the other surface of the insulating layer 11, and a first via 11A electrically connecting the first conductive layer 14 and the second conductive layer 15. The insulating layer 11 has a thickness of, for example, about 45 μm to 80 μm. The insulating layer 11 is, for example, a first insulating layer. The first conductive layer 14 is, for example, a first wiring layer.

[0019] The first conductive layer 14 has a pad 14A electrically connected to the build-up substrate 2 and a transmission wiring 20. The first conductive layer 14 is the lowest conductive layer and is covered by the insulating layer 11. The first conductive layer 14 is, for example, a circular pad with a planar shape of about 150 μm in diameter, but may include a wiring pattern. The interval between adjacent first conductive layers 14 can be, for example, about 200 μm. The material of the first conductive layer 14 can be, for example, copper (Cu), etc. The thickness of the first conductive layer 14 can be, for example, about 10 to 20 μm. The second conductive layer 15 has a pad 15A electrically connecting between the first via 11A in the insulating layer 11 and the second via 12A in the thin film layer 12.

[0020] The thin film layer 12 has a thin film wiring layer in which a wiring layer and an insulating layer are laminated in sequence, a third conductive layer 16 laminated on the thin film wiring layer, and, for example, a second via 12A electrically connecting the wiring layer in the thin film wiring layer and the third conductive layer 16. The second via 12A electrically connects between the third conductive layer 16 and the second conductive layer 15. The third conductive layer 16 has a first pad 16A electrically connecting with a chip terminal of the chip 3 and a second pad 16B electrically connecting with a connector terminal of the connector 4.

[0021] The thin-film wiring layer has a first insulating layer 61, a first wiring layer 62 provided on the first insulating layer 61, a second insulating layer 63 covering the first wiring layer 62 and laminated on the first insulating layer 61, a second wiring layer 64 provided on the second insulating layer 63, and a third insulating layer 65 covering the second wiring layer 64 and laminated on the second insulating layer 63. Note that the thin-film wiring layer has a five-layer structure of the first insulating layer 61, the first wiring layer 62, the second insulating layer 63, the second wiring layer 64, and the third insulating layer 65, but is not limited to the five-layer structure and can be appropriately changed.

[0022] The first insulating layer 61 is formed on one side of the insulating layer 11 so as to cover the second conductive layer 15. The first wiring layer 62 is formed on one side of the first insulating layer 61 and is electrically connected to the second conductive layer 15. The second insulating layer 63 is formed on one side of the first insulating layer 61 so as to cover the first wiring layer 62. The second wiring layer 64 is formed on one side of the second insulating layer 63 and is electrically connected to the first wiring layer 62. The third insulating layer 65 is formed on one side of the second insulating layer 63 so as to cover the second wiring layer 64. The thicknesses of the first wiring layer 62 and the second wiring layer 64 in the thin-film wiring layer are, for example, about 1 to 3 μm. The first insulating layer 61, the second insulating layer 63, and the third insulating layer 65 in the thin-film layer 12 correspond to, for example, the second insulating layer. Furthermore, the first wiring layer 62 and the second wiring layer 64 in the thin film layer 12 correspond to, for example, a second wiring layer.

[0023] The transmission wiring 20 in the first conductive layer 14 is disposed in the first conductive layer 14 in the insulating layer 11 in the boundary portion between the insulating layer 11 and the adhesive layer 13. The wiring thickness of the first conductive layer 14 is thicker than the first wiring layer 62 or the second wiring layer 64 in the thin-film wiring layer. The transmission wiring 20 electrically connects between the first via 11A electrically connected to the first via 12A1 (12A) connected to the first pad 16A, and the first via 11A electrically connected to the second via 12A2 (12A) connected to the second pad 16B. In other words, the transmission wiring 20 electrically connects between the chip 3 connected to the first pad 16A and the connector 4 connected to the second pad 16B, and is, for example, a serial transmission path that transmits a serial high-speed signal.

[0024] In this embodiment, for convenience, the third conductive layer 16 side of the wiring board 5 is referred to as the upper side or one side, and the adhesive layer 13 side is referred to as the lower side or the other side. Also, the surface of each part on the third conductive layer 16 side is referred to as one side or upper surface, and the surface on the adhesive layer 13 side is referred to as the other side or lower surface. However, the wiring board 5 can be used upside down or placed at any angle. Also, the planar view refers to the object being viewed from the normal direction of the upper surface of the insulating layer 11, and the planar shape refers to the shape of the object viewed from the normal direction of the upper surface of the insulating layer 11.

[0025] The insulating layer 11 covers the first conductive layer 14. The insulating layer 11 is not limited to a single layer, and may be a laminate of a plurality of insulating resins. The insulating layer 11 is, for example, an insulating layer mainly composed of a non-photosensitive thermosetting resin. Examples of the non-photosensitive thermosetting resin include epoxy resin, imide resin, phenol resin, and cyanate resin. The insulating layer 11 desirably has a reinforcing member such as glass fiber or aramid fiber. The insulating layer 11 may cover only the side surface of the first conductive layer 14, but it is preferable that the insulating layer 11 covers the upper surface and the side surface of the first conductive layer 14. In other words, the lower surface of the first conductive layer 14 is exposed from the lower surface of the insulating layer 11, and the lower surface of the insulating layer 11 and the lower surface of the first conductive layer 14 can be, for example, flush with each other.

[0026] A solder layer 17 is formed on the lower surface of the first conductive layer 14. The material of the solder layer 17 may be, for example, SnBi solder. The thickness of the solder layer 17 may be, for example, about 15 to 25 μm. The solder layer 17 is covered with an adhesive layer 13 formed on the lower surface of the insulating layer 11. The material of the adhesive layer 13 may be, for example, an epoxy-based insulating resin. The thickness of the adhesive layer 13 may be, for example, about 25 to 30 μm. The solder layer 17 and the adhesive layer 13 are not essential components of the wiring board 5, and may be formed when necessary.

[0027] The first via 11A is a via wiring embedded in the insulating layer 11. More specifically, the first via 11A is a via wiring filled in a via hole that penetrates the insulating layer 11 and exposes the upper surface of the first conductive layer 14, and is electrically connected to the first conductive layer 14. The via hole may be an inverted truncated cone-shaped recess in which the diameter of the opening on the thin film layer 12 side is larger than the diameter of the bottom of the opening formed by the upper surface of the first conductive layer 14. The diameter of the opening of the via hole may be, for example, about 60 to 70 μm.

[0028] The upper surface of the first via 11A is exposed from the upper surface of the insulating layer 11. The upper surface of the first via 11A can be flush with the upper surface of the insulating layer 11, for example. The upper surface of the first via 11A is directly bonded to the lower surface of the thin film layer 12. In addition, the lower surface of the first via 11A is directly bonded to the first conductive layer 14 within the insulating layer 11. The material of the first via 11A is, for example, the same material as the first conductive layer 14.

[0029] The first via 11A consists only of a via wiring formed in a via hole of the insulating layer 11. In other words, the first via 11A does not have a wiring pattern integrally formed on the upper surface of the insulating layer 11. The first via 11A and the thin film layer 12 are electrically connected but are not integral. Specifically, in a manufacturing method described later, the thin film layer 12 is formed by sequentially laminating a wiring layer and an insulating layer. The wiring layer in the thin film layer 12 is a high-density wiring pattern (for example, a line / space of about 3 μm / 3 μm) formed by a semi-additive method.

[0030] The wiring layer in the thin film layer 12 is formed on the upper surface of the insulating layer 11. The wiring layer is formed directly on the upper surface of the insulating layer 11, and includes wiring (wiring pattern or pad) electrically connected to the first conductive layer 14 through the first via 11A. That is, a part of the lower surface of the wiring layer in the thin film layer 12 contacts the upper surface of the first via 11A, and the two are electrically connected. For example, copper (Cu) or the like can be used as the material of the wiring layer in the thin film layer 12. The thin film layer 12 is a laminated film in which a plurality of conductor layers are laminated. The thin film layer 12 has a higher wiring density (narrower line / space) than the first conductive layer 14, and is thinner than the first conductive layer 14. In this specification, a wiring layer with a line / space of 8 μm / 8 μm or less is defined as a wiring layer with a high wiring density. The line / space of the thin film layer 12 can be, for example, about 1 μm / 1 μm to 3 μm / 3 μm.

[0031] In addition, the line in line / space refers to the wiring width, and the space refers to the distance between adjacent wirings (wiring distance). For example, if the line / space is described as 2 μm / 2 μm, it means that the wiring width is 2 μm and the distance between adjacent wirings is 2 μm.

[0032] The first insulating layer 61 in the thin film layer 12 is an insulating layer mainly composed of a photosensitive insulating resin. "Mainly composed of a photosensitive insulating resin" means that the layer may contain other components such as a filler in addition to the photosensitive insulating resin. For example, the first insulating layer 61 may contain a filler such as silica (SiO2).

[0033] The first insulating layer 61 in the thin film layer 12 is formed so as to cover the second via 12A. Examples of the photosensitive insulating resin used for the first insulating layer 61 in the thin film layer 12 include phenolic resin and polyimide resin. The thickness of the first insulating layer 61 can be, for example, about 5 to 10 μm. As described above, the thickness of the insulating layer 11 is, for example, about 45 μm to 80 μm, which is considerably thicker than the thickness of the first insulating layer in the thin film layer 12.

[0034] The first wiring layer 62 in the thin film layer 12 is a wiring layer provided on the first insulating layer 61, and includes via wiring and a wiring pattern. The thickness of the first wiring layer 62 is, for example, about 1 to 3 μm. The line / space of the first wiring layer 62 can be, for example, about 1 μm / 1 μm to 3 μm / 3 μm, but it is possible to make the line / space narrower than that of the second via 12A. The first wiring layer 62 includes via wiring filled in the second via 12A that penetrates the first insulating layer 61 and exposes the upper surface of the second conductive layer 15, and a wiring pattern formed on the upper surface of the first insulating layer 61. The second via 12A can be an inverted truncated cone-shaped recess in which the diameter of the opening opened on the second insulating layer 63 side is larger than the diameter of the bottom of the opening formed by the upper surface of the second conductive layer 15. The diameter of the opening of the second via 12A can be, for example, about 10 to 20 μm. The material of the first wiring layer 62 and the thickness of the wiring pattern constituting the first wiring layer 62 can be, for example, similar to that of the second conductive layer 15.

[0035] The second insulating layer 63 in the thin film layer 12 is an insulating layer that covers the first wiring layer 62 and is laminated on the first insulating layer 61, and is an insulating layer that is mainly composed of a photosensitive insulating resin. "Mainly composed of a photosensitive insulating resin" means that the second insulating layer 63 may contain other components such as a filler in addition to the photosensitive insulating resin. For example, the second insulating layer 63 may contain a filler such as silica (SiO2).

[0036] The second insulating layer 63 in the thin film layer 12 is formed so as to cover the second via 12A. Examples of the photosensitive insulating resin used for the second insulating layer 63 in the thin film layer 12 include phenolic resin and polyimide resin. The thickness of the second insulating layer 63 can be, for example, about 5 to 10 μm. As described above, the thickness of the insulating layer 11 is, for example, about 45 μm to 80 μm, which is considerably thicker than the thickness of the second insulating layer 63 in the thin film layer 12.

[0037] The second wiring layer 64 in the thin film layer 12 is a wiring layer provided on the second insulating layer 63, and includes via wiring and a wiring pattern. The thickness of the second wiring layer 64 is, for example, about 1 to 3 μm. The line / space of the second wiring layer 64 can be, for example, about 1 μm / 1 μm to 3 μm / 3 μm, but it is possible to make the line / space narrower than that of the second via 12A. The second wiring layer 64 includes via wiring filled in the second via 12A that penetrates the second insulating layer 63 and exposes the upper surface of the first wiring layer 62, and a wiring pattern formed on the upper surface of the second insulating layer 63. The second via 12A can be an inverted truncated cone-shaped recess in which the diameter of the opening opened on the third insulating layer 65 side is larger than the diameter of the bottom of the opening formed by the upper surface of the second wiring layer 64. The diameter of the opening of the second via 12A may be, for example, about 10 to 20 μm. The material of the second wiring layer 64 and the thickness of the wiring pattern constituting the second wiring layer 64 may be, for example, similar to that of the second conductive layer 15. The lines / spaces of the wiring pattern constituting the second wiring layer 64 may be, for example, similar to that of the first wiring layer 62.

[0038] The third insulating layer 65 in the thin film layer 12 is an insulating layer that covers the second wiring layer 64 and is laminated on the second insulating layer 63, and is an insulating layer that is mainly composed of a photosensitive insulating resin. "Mainly composed of a photosensitive insulating resin" means that the layer may contain other components such as a filler in addition to the photosensitive insulating resin. For example, the third insulating layer 65 may contain a filler such as silica (SiO2).

[0039] The third insulating layer 65 in the thin film layer 12 is formed so as to cover the second via 12A. Examples of the photosensitive insulating resin used for the third insulating layer 65 in the thin film layer 12 include phenolic resin and polyimide resin. The thickness of the third insulating layer 65 can be, for example, about 5 to 10 μm. As described above, the thickness of the insulating layer 11 is, for example, about 45 μm to 80 μm, which is considerably thicker than the thickness of the third insulating layer 65 in the thin film layer 12.

[0040] The third conductive layer 16, which is the uppermost conductive layer in the thin film layer 12, is formed on one side of the third insulating layer 65, which is the uppermost insulating layer in the thin film layer 12. The third conductive layer 16 includes via wiring and pads 16A, 16B protruding from the upper surface of the uppermost insulating layer. The thickness of the third conductive layer 16 (including the pad portion protruding from the upper surface of the uppermost insulating layer) can be, for example, about 10 μm. The planar shape of the first pad 16A constituting the third conductive layer 16 can be, for example, a circle with a diameter of about 20 to 30 μm. The pitch of the first pads 16A constituting the third conductive layer 16 can be, for example, about 40 to 50 μm. The first pads 16A constituting the third conductive layer 16 can be used to electrically connect to electronic components such as the chip 3.

[0041] The planar shape of the second pads 16B constituting the third conductive layer 16 may be, for example, a rectangle of 0.1 mm×0.1 mm to 2 mm×2 mm. The pitch of the second pads 16B constituting the third conductive layer 16 may be, for example, about 0.1 mm to 2 mm. The second pads 16B constituting the third conductive layer 16 may be used for electrical connection with the connector 4.

[0042] A surface treatment layer (not shown) may be formed on the surfaces (only the upper surfaces, or the upper surfaces and side surfaces) of the pads 16A and 16B constituting the third conductive layer 16. Examples of the surface treatment layer include an Au layer, a Ni / Au layer (a metal layer in which a Ni layer and an Au layer are laminated in this order), and a Ni / Pd / Au layer (a metal layer in which a Ni layer, a Pd layer, and an Au layer are laminated in this order). In addition, the surface treatment layer may be formed by performing an oxidation prevention treatment such as an OSP (Organic Solderability Preservative) treatment on the surfaces (only the upper surfaces, or the upper surfaces and side surfaces) of the pads 16A and 16B constituting the third conductive layer 16.

[0043] 3 is an explanatory diagram showing an example of the dielectric constant and dielectric tangent of each insulating layer. The dielectric constant of the insulating layer in the thin film layer 12, the dielectric constant of the insulating layer 11, and the dielectric constant of the adhesive layer 13 are in the range of 3.2 to 4.6. In contrast, the dielectric tangent in the thin film layer 12 is in the range of 0.01 to 0.06, the dielectric tangent of the insulating layer 11 is in the range of 0.004 to 0.02, and the dielectric tangent of the adhesive layer 13 is in the range of 0.004 to 0.02.

[0044] 4 is an explanatory diagram showing an example of the characteristics of the connector terminal 4A and the chip terminal 3A. The chip terminal 3A connected to the first pad 16A has a circular shape, an electrode size in the range of 20 μm to 100 μm in diameter, an electrode thickness in the range of 5 μm to 20 μm, and an electrode pitch in the range of 30 μm to 200 μm. In contrast, the connector terminal 4A connected to the second pad 16B has a rectangular shape, an electrode size in the range of 0.1×0.1 mm to 2×2 mm, an electrode thickness in the range of 5 μm to 20 μm, and an electrode pitch in the range of 0.1 mm to 2 mm.

[0045] The build-up board 2 is a multilayer wiring board in which wiring layers and insulating layers are laminated on a core layer (not shown), and can be produced by, for example, a well-known build-up method. Each wiring layer in the build-up board 2 has a lower wiring density (wider line / space) than the wiring layer of the wiring board 5. The line / space of each wiring layer in the build-up board 2 can be, for example, about 20 μm / 20 μm.

[0046] A plurality of chips 3 and a connector 4 are flip-chip mounted on the wiring board 5. The chip 3 is, for example, a thinned semiconductor substrate made of silicon or the like on which a semiconductor integrated circuit (not shown) and the like are formed. A chip terminal 3A electrically connected to the semiconductor integrated circuit (not shown) is formed on the circuit formation surface of the semiconductor substrate. The connector 4 is, for example, a connector that serially transmits high-speed signals between the chip 3 and the connector 4. The connector 4 is formed with a connector terminal 4A.

[0047] The chip terminals 3A of the chip 3 are electrically connected to the first pads 16A in the third conductive layer 16 of the wiring board 5 through the solder bumps 18. For example, SnBi solder can be used as the material of the solder bumps 18. For example, the chips 3 include memories (DRAMs (Dynamic Random Access Memory) and logic (CPUs (Central Processing Units)). In addition, one or two chips 3 may be mounted on the wiring board 5, or four or more chips 3 may be mounted on the wiring board 5. The connector terminals 4A of the connector 4 are electrically connected to the second pads 16B in the third conductive layer 16 of the wiring board 5 through the solder bumps 18.

[0048] In the semiconductor device 1, the chips 3 are mounted on the wiring board 5 having the thin film layer 12 with a high wiring density, so that the chips 3 can be easily connected to each other by a wiring pattern with a high wiring density.

[0049] [Method of manufacturing wiring board 5 according to the first embodiment] Next, a method for manufacturing the wiring board 5 of Example 1 will be described. Fig. 5A to Fig. 8 are diagrams illustrating the manufacturing process of the wiring board 5 of Example 1. Note that, although an example of the process for manufacturing one wiring board 5 is shown here, a process for manufacturing a plurality of parts that will become the wiring board 5 may be produced and then diced into individual wiring boards 5.

[0050] FIG. 5A is an explanatory diagram showing an example of a preparation step. In the preparation step shown in FIG. 5A, a support carrier 50 is prepared. The support carrier 50 has a structure in which a prepreg 52 and a copper foil with a carrier 53 are sequentially laminated on a core substrate 51 on which copper foil is formed. The core substrate 51 is, for example, a glass epoxy substrate having a thickness of about 0.7 mm, and the thickness of the copper foil is, for example, about 7 to 50 μm. The prepreg 52 is, for example, a woven or nonwoven fabric such as glass fiber or aramid fiber impregnated with a thermosetting epoxy resin or polyimide resin in advance. The copper foil with a carrier 53 has a structure in which a thin foil made of copper having a thickness of about 1.5 to 5 μm is peelably attached to a thick foil (carrier foil) made of copper having a thickness of about 10 to 50 μm via a release layer (not shown).

[0051] The structure of the support carrier 50 is an example, and is not limited thereto. For example, in the support carrier 50, a laminate in which a plurality of prepregs are laminated may be used instead of the core substrate 51. Also, the support carrier 50 may have a structure in which a carrier-attached copper foil 53 is arranged on both sides of a glass substrate, a metal substrate, or the like, via a release layer.

[0052] FIG. 5B is an explanatory diagram showing an example of a conductor layer forming step. Next, in the step shown in FIG. 5B, a photosensitive resist layer (not shown) is formed on the entire upper surface (upper surface of the thin foil) of the upper copper foil 53 with a carrier, and the resist layer is exposed and developed to form an opening exposing a portion where the first conductive layer 14 is to be formed. For example, a dry film resist can be used as the resist layer. Then, the first conductive layer 14, which is an electrolytic plating layer, is formed on the upper surface of the copper foil 53 with a carrier exposed in the opening by electrolytic plating using the upper copper foil 53 with a carrier as a power supply layer. The material and thickness of the first conductive layer 14 are as described above. Then, the resist layer is peeled off. The first conductive layer 14 includes the pad 14A and the transmission wiring 20.

[0053] 5C is an explanatory view showing an example of an insulating layer forming step. In the step shown in FIG. 5C, an insulating layer 11 is formed on the upper surface of an upper prepreg 52 to cover an upper copper foil with a carrier 53 and a first conductive layer 14.

[0054] Specifically, for example, a semi-cured film-like insulating resin containing a non-photosensitive thermosetting resin as a main component is prepared. Then, this insulating resin is laminated on the upper surface of the upper prepreg 52 so as to cover the copper foil 53 with the carrier and the first conductive layer 14, and is cured while being heated and pressed to form the insulating layer 11. A semi-cured multilayer film is laminated on the upper surface of the upper prepreg 52 so as to cover the copper foil 53 with the carrier and the first conductive layer 14, and is cured while being heated and pressed to form the insulating layer.

[0055] Next, via holes are formed in the insulating layer 11, penetrating the front and back of the insulating layer 11 to expose the upper surface of the first conductive layer 14. The via holes can be formed by laser processing using, for example, a CO2 laser, a YAG laser, an excimer laser, or the like. After the via holes are formed, it is preferable to perform a desmear process to remove resin residues adhering to the surface of the first conductive layer 14 exposed at the bottom of each via hole.

[0056] Next, in the step, the first via 11A is formed in the insulating layer 11. The first via 11A can be formed by, for example, a semi-additive method. Specifically, first, a seed layer is formed by electroless plating or sputtering on the surface of the insulating layer 11 including the inner wall of the via hole and the surface of the first conductive layer 14 exposed in the via hole. For example, a copper layer having a thickness of about 100 to 350 nm can be used as the seed layer. A laminated film in which a titanium layer having a thickness of about 20 to 50 nm and a copper layer having a thickness of about 100 to 300 nm are laminated in this order can be used as the seed layer. By forming a titanium layer under the seed layer, the adhesion between the insulating layer 11 and the first via 11A can be improved. Titanium nitride or the like may be used instead of titanium. Note that titanium and titanium nitride are metals that are more corrosion-resistant than copper.

[0057] Next, a photosensitive resist layer is formed on the entire upper surface of the seed layer, and the resist layer is exposed and developed to form an opening exposing a portion where the first via 11A is to be formed. For example, a dry film resist can be used as the resist layer. Then, an electrolytic plating layer (e.g., a copper layer) is formed on the upper surface of the seed layer exposed in the opening by electrolytic plating using the seed layer as a power supply layer.

[0058] Next, after peeling off the resist layer, the electrolytic plating layer is used as a mask to etch away the seed layer in the portion not covered by the electrolytic plating layer. This forms a first via 11A in which the electrolytic plating layer is laminated on the seed layer. Through the steps up to this point, a layer structure is formed in which the insulating layer 11 and the first conductive layer 14 are arranged around the support carrier 50.

[0059] Next, in the process, the upper surface side of the first via 11A is polished to expose the upper surface of the insulating layer 11 and the upper surface of the first via 11A filling the via hole, thereby forming the first via 11A filling the via hole. For example, a chemical mechanical polishing (CMP) method or the like can be used to polish the first via 11A. For example, the upper surface of the first via 11A can be flush with the upper surface of the insulating layer 11.

[0060] When polishing the first via 11A, a part of the upper surface of the insulating layer 11 may be polished and removed at the same time. By polishing the upper surface of the insulating layer 11 together with the first via 11A and removing a part of the upper surface of the insulating layer 11, the roughness of the upper surface of the insulating layer 11 can be made smaller than that before polishing. That is, the smoothness of the upper surface of the insulating layer 11 can be improved. The roughness of the upper surface of the insulating layer 11 is, for example, about Ra 300 to 400 nm before performing the CMP method (before polishing), and can be made about Ra 15 to 40 nm by performing the CMP method. In this way, by reducing the roughness of the upper surface of the insulating layer 11 and improving the smoothness, it becomes possible to form fine wiring (a wiring layer with a high wiring density) in a later process. The roughness of the lower surface of the insulating layer 11 is, for example, about Ra 180 to 280 nm.

[0061] In the next step, the second conductive layer 15 is formed on the insulating layer 11. A photosensitive resist layer (not shown) is formed on the entire upper surface of the first via 11A, and the resist layer is exposed and developed to form an opening that exposes the portion where the second conductive layer 15 is to be formed. For example, a dry film resist can be used as the resist layer. Then, the second conductive layer 15, which is an electrolytic plating layer, is formed on the upper surface of the first via 11A exposed in the opening by electrolytic plating using the first via 11A as a power supply layer. The material and thickness of the second conductive layer 15 are as described above. Then, the resist layer is peeled off. The second conductive layer 15 includes a pad 15A.

[0062] Fig. 6A is an explanatory diagram showing an example of a thin film layer forming step. In the step shown in Fig. 6A, a thin film layer 12 is formed on an insulating layer 11 and a second conductive layer 15. The thin film layer 12 is formed into a high-density wiring layer by using, for example, a semi-additive method.

[0063] Next, the same process is repeated to form a first insulating layer 61, a first wiring layer 62, a second insulating layer 63, a second wiring layer 64, and a third insulating layer 65 in the thin film layer 12, and a third conductive layer 16 is formed on the uppermost third insulating layer 65 of the thin film layer 12. The above-mentioned surface treatment layer is formed on the surfaces (only the upper surface, or the upper surface and side surfaces) of the pads constituting the third conductive layer 16. The third conductive layer 16 includes a first pad 16A and a second pad 16B.

[0064] Next, in the process, the outer periphery of the structure is cut using a dicing blade or the like. The cutting is performed so as to remove the area where the insulating layer 11 and the upper prepreg 52 are in direct contact with each other. As a result, it becomes possible to easily peel off the area where the thick foil and the thin foil in the carrier-attached copper foil 53 are in contact with each other. In other words, the main part of the support carrier 50 can be easily removed.

[0065] FIG. 6B is an explanatory diagram showing an example of a support carrier peeling step. In the step shown in FIG. 6B, the thin foil is removed from the structure from which the main part of the support carrier 50 has been removed. The thin foil in the copper foil 53 with carrier can be removed by, for example, wet etching. As a result, the lower surface of the first conductive layer 14 is exposed on the lower surface of the insulating layer 11. The lower surfaces of the insulating layer 11 and the first conductive layer 14 can be flush with each other, for example. That is, the transmission wiring 20 in the first conductive layer 14 is exposed on the lower surface of the insulating layer 11.

[0066] FIG. 7 is an explanatory diagram showing an example of a solder forming process. In the process shown in FIG. 7, a solder layer 17 is formed on the lower surface of the first conductive layer 14 by screen printing or the like. The material and thickness of the solder layer 17 are as described above. Then, an adhesive layer 13 is formed on the lower surface of the insulating layer 11 to cover the solder layer 17. The adhesive layer 13 can be formed, for example, by laminating an insulating thermosetting resin film called NCF (Non Conductive Film) on the lower surface of the insulating layer 11 so as to cover the solder layer 17, and then heating and curing the film. Through the above process, the wiring board 5 is completed. Note that the solder layer 17 and the adhesive layer 13 are not essential components of the wiring board 5, and may be formed when necessary (for example, immediately before mounting the wiring board 5 on the build-up board 2).

[0067] As a result, wiring board 5 having first conductive layer 14, insulating layer 11, second conductive layer 15, thin film layer 12, and third conductive layer 16 is completed.

[0068] 8 is an explanatory diagram showing an example of a wiring board mounting process. A plurality of chips 3 and a connector 4 are flip-chip mounted on a wiring board 5. A chip terminal 3A of the chip 3 is electrically connected to a first pad 16A in a third conductive layer 16 of the wiring board 5 via a solder bump 18. A chip terminal 4A of the connector 4 is electrically connected to a second pad 16B in a third conductive layer 16 of the wiring board 5 via a solder bump 18. A pad 14A in a first conductive layer 14 of the wiring board 5 and a pad 2A on a build-up board 2 are electrically connected to each other via a solder layer 17 to form a semiconductor device 1.

[0069] In the wiring board 5 of the first embodiment, the transmission wiring 20 that electrically connects between the via connected to the first pad 16A and the via connected to the second pad 16B is disposed in the insulating layer 11 that is thicker than the insulating layer in the thin film layer 12. Since the insulating layer 11 is thicker than the insulating layer in the thin film layer 12, the transmission wiring 20 can be made thick. As a result, the wiring resistance of the transmission wiring 20 can be reduced, and the insertion loss and reflection loss when a high-speed signal passes through the transmission wiring 20 can be suppressed, thereby improving the transmission characteristics of the high-speed signal.

[0070] In the wiring board 5, the transmission wiring 20 is disposed in the first conductive layer 14 on the surface of the insulating layer 11 opposite to the surface in contact with the thin film layer 12. The transmission wiring 20 is embedded in the insulating layer 11 so as to be in contact with the adhesive layer 13. The dielectric tangent of the insulating layer 11 having the transmission wiring 20 is smaller than the dielectric tangent of the thin film layer 12. As a result, the dielectric tangent can suppress the insertion loss and reflection loss when a high-speed signal passes through the transmission wiring 20, thereby improving the transmission characteristics of the high-speed signal.

[0071] The wiring board 5 transmits serial high-speed signals between the chip 3 and the connector 4 through the transmission wiring 20. As a result, it is possible to suppress the insertion loss and reflection loss that occur when the high-speed signals pass through.

[0072] The transmission wiring 20 is formed in the same process as the pads 14A when forming the first conductive layer 14. As a result, the transmission wiring 20 can be formed easily.

[0073] For ease of explanation, the transmission wiring 20 is illustrated as transmitting signals between the chip 3 mounted on the wiring board 5 and the connector 4, but the transmission wiring 20 may transmit signals, for example, between chips 3 or between connectors 4, and may be modified as appropriate.

[0074] In addition, in the wiring board 5 of Example 1, an example is given of the case where the transmission wiring 20 is arranged on the first conductive layer 14, but this is not limited to this, and for example, the transmission wiring 20 may be arranged on the second conductive layer 15, and this embodiment will be described below as Example 2. EXAMPLES

[0075] Fig. 9 is an explanatory diagram showing an example of a semiconductor device 1A of Example 2, and Fig. 10 is a schematic cross-sectional view showing an example of a wiring board 5A. The same components as those in the semiconductor device 1 of Example 1 are given the same reference numerals, and descriptions of the overlapping components and operations are omitted. The wiring board 5A shown in Fig. 2 differs from the wiring board 5A shown in Fig. 10 in that, instead of arranging the transmission wiring 20 in the first conductive layer 14, the transmission wiring 20A is arranged in the second conductive layer 15.

[0076] The wiring board 5A has an insulating layer 11, a thin film layer 12, and an adhesive layer 13. The insulating layer 11 has a first conductive layer 14, a second conductive layer 15, and a first via 11B. As described above, the thickness of the insulating layer 11 is, for example, about 45 μm to 80 μm. As described above, the thickness of the first insulating layer 61, the second insulating layer 63, and the third insulating layer 64 in the thin film layer 12 is, for example, about 5 μm to 10 μm.

[0077] The first conductive layer 14 has a pad 14A that connects to a pad 2A of the build-up substrate 2. The first conductive layer 14 is the lowest conductive layer, and is covered with an insulating layer 11. The second conductive layer 15 has a transmission wiring 20A in addition to a pad 15A that electrically connects between a first via 11B in the insulating layer 11 and a second via 12A in the thin film layer 12. The second conductive layer 15 has a thickness of, for example, about 10 to 20 μm.

[0078] The first via 11B is a via wiring buried in the insulating layer 11. More specifically, the first via 11B is a via wiring filled in a via hole that penetrates the insulating layer 11 and exposes the upper surface of the first conductive layer 14, and is electrically connected to the first conductive layer 14. The via hole may be a truncated cone-shaped recess in which the diameter of the opening on the thin film layer 12 side is smaller than the diameter of the bottom of the opening formed by the upper surface of the first conductive layer 14. The diameter of the opening of the via hole may be, for example, about 60 to 70 μm.

[0079] The upper surface of the first via 11B is exposed from the upper surface of the insulating layer 11. The upper surface of the first via 11B can be flush with the upper surface of the insulating layer 11, for example. The upper surface of the first via 11B is directly bonded to the lower surface of the thin film layer 12. In addition, the lower surface of the first via 11B is directly bonded to the first conductive layer 14 within the insulating layer 11. The material of the first via 11B is, for example, the same material as the first conductive layer 14.

[0080] The first via 11B is composed only of a via wiring formed in a via hole of the insulating layer 11. In other words, the first via 11B does not have a wiring pattern integrally formed on the upper surface of the insulating layer 11. The first via 11B and the thin film layer 12 are electrically connected but are not integral. Specifically, in a manufacturing method described later, the thin film layer 12 is formed by sequentially laminating a wiring layer and an insulating layer. The wiring layer in the thin film layer 12 is a high-density wiring pattern (for example, a line / space of about 3 μm / 3 μm) formed by a semi-additive method. The thin film layer 12 has a thin film wiring layer, a third conductive layer 16, and a second via 12A.

[0081] The thin-film wiring layer includes a first insulating layer 61, a first wiring layer 62 provided on the first insulating layer 61, a second insulating layer 63 covering the first wiring layer 62 and laminated on the first insulating layer 61, a second wiring layer 64 provided on the second insulating layer 63, and a third insulating layer 65 covering the second wiring layer 64 and laminated on the second insulating layer 63. The thicknesses of the first wiring layer 62 and the second wiring layer 64 in the thin-film wiring layer are, for example, about 1 to 3 μm. The thin-film wiring layer is illustrated as having a five-layer structure including the first insulating layer 61, the first wiring layer 62, the second insulating layer 63, the second wiring layer 64, and the third insulating layer 65, but is not limited to the five-layer structure and can be appropriately changed.

[0082] The transmission wiring 20A in the second conductive layer 15 is disposed in the insulating layer 11 in the boundary portion between the insulating layer 11 and the thin film layer 12. The wiring thickness of the second conductive layer 15 is thicker than the first wiring layer 62 or the second wiring layer 64 in the thin film wiring layer. The transmission wiring 20A electrically connects between the first via 11B electrically connected to the first via 12A1 (12A) connected to the first pad 16A, and the first via 11B electrically connected to the second via 12A2 (12A) connected to the second pad 16B. In other words, the transmission wiring 20A electrically connects between the chip 3 connected to the first pad 16A and the connector 4 connected to the second pad 16B, and is, for example, a serial transmission path that transmits a serial high-speed signal.

[0083] [Method of manufacturing wiring board according to embodiment 2] Next, a method for manufacturing the wiring board 5A of Example 2 will be described. Figures 11A to 15 are diagrams illustrating the manufacturing process of the wiring board 5A of Example 2. Note that, although an example of the process for manufacturing one wiring board 5A is shown here, a process for manufacturing a plurality of parts that will become the wiring board 5A may also be used, in which the parts are manufactured and then diced into individual wiring boards 5A.

[0084] Fig. 11A is an explanatory diagram showing an example of a preparation step. In the preparation step shown in Fig. 11A, a support carrier 50 is prepared. The support carrier 50 has a structure in which a prepreg 52 and a copper foil with a carrier 53 are sequentially laminated on a core substrate 51 on which a copper foil is formed, for example.

[0085] FIG. 11B is an explanatory diagram showing an example of a conductor layer forming step. Next, in the step shown in FIG. 11B, a photosensitive resist layer (not shown) is formed on the entire upper surface (upper surface of the thin foil) of the upper copper foil with carrier 53, and the resist layer is exposed and developed to form an opening exposing a portion where the second conductive layer 15 is to be formed. For example, a dry film resist can be used as the resist layer. Then, the second conductive layer 15, which is an electrolytic plating layer, is formed on the upper surface of the copper foil with carrier 53 exposed in the opening by electrolytic plating using the upper copper foil with carrier 53 as a power supply layer. The material and thickness of the second conductive layer 15 are as described above. Then, the resist layer is peeled off. The second conductive layer 15 includes a pad 15A and a transmission wiring 20A.

[0086] 11C is an explanatory view showing an example of an insulating layer forming step. In the step shown in FIG. 11C, an insulating layer 11 is formed on the upper surface of the upper prepreg 52 to cover the upper copper foil with carrier 53 and the second conductive layer 15.

[0087] Specifically, for example, a semi-cured film-like insulating resin containing a non-photosensitive thermosetting resin as a main component is prepared. Then, this insulating resin is laminated on the upper surface of the upper prepreg 52 so as to cover the copper foil 53 with the carrier and the second conductive layer 15, and is cured while being heated and pressed to form the insulating layer 11. A semi-cured multilayer film is laminated on the upper surface of the upper prepreg 52 so as to cover the copper foil 53 with the carrier and the second conductive layer 15, and is cured while being heated and pressed to form the insulating layer 11.

[0088] Next, via holes are formed in the insulating layer 11, penetrating the insulating layer 11 from the front to the back to expose the underside of the second conductive layer 15. The via holes can be formed by laser processing using, for example, a CO2 laser, a YAG laser, an excimer laser, or the like. After the via holes are formed, it is preferable to perform a desmear process to remove resin residues adhering to the surface of the second conductive layer 15 exposed at the bottom of each via hole.

[0089] Next, in the process, the first via 11B is formed in the insulating layer 11. The first via 11B can be formed by, for example, a semi-additive method. Specifically, first, a seed layer is formed by electroless plating or sputtering on the surface of the insulating layer 11 including the inner wall of the via hole and the surface of the second conductive layer 15 exposed in the via hole. For example, a copper layer having a thickness of about 100 to 350 nm can be used as the seed layer. A laminated film in which a titanium layer having a thickness of about 20 to 50 nm and a copper layer having a thickness of about 100 to 300 nm are laminated in this order can be used as the seed layer. By forming a titanium layer under the seed layer, the adhesion between the insulating layer 11 and the first via 11B can be improved. Titanium nitride or the like may be used instead of titanium. Note that titanium and titanium nitride are metals that are more corrosion-resistant than copper.

[0090] Next, a photosensitive resist layer is formed on the entire upper surface of the seed layer, and the resist layer is exposed and developed to form an opening exposing a portion where the first via 11B is to be formed. For example, a dry film resist can be used as the resist layer. Then, an electrolytic plating layer (e.g., a copper layer) is formed on the upper surface of the seed layer exposed in the opening by electrolytic plating using the seed layer as a power supply layer.

[0091] Next, after peeling off the resist layer, the electrolytic plating layer is used as a mask to remove the seed layer in the portion not covered by the electrolytic plating layer by etching. This forms a first via 11B in which the electrolytic plating layer is laminated on the seed layer. Through the steps up to this point, a layer structure is formed in which the insulating layer 11 and the second conductive layer 15 are arranged around the support carrier 50.

[0092] Next, in the process, the lower surface side of the first via 11B is polished to expose the lower surface of the insulating layer 11 and the lower surface of the first via 11B filling the via hole, thereby forming the first via 11B filled in the via hole.

[0093] In the next step, the first conductive layer 14 is formed under the insulating layer 11. A photosensitive resist layer (not shown) is formed on the entire lower surface of the first via 11B, and the resist layer is exposed and developed to form an opening that exposes the portion where the first conductive layer 14 is to be formed. For example, a dry film resist can be used as the resist layer. Then, the first conductive layer 14, which is an electrolytic plating layer, is formed on the lower surface of the first via 11B exposed in the opening by electrolytic plating using the first via 11B as a power supply layer. The material and thickness of the first conductive layer 14 are as described above. Then, the resist layer is peeled off. The first conductive layer 14 includes the pad 14A.

[0094] FIG. 12A is an explanatory diagram showing an example of the inversion support carrier formation process. In the process shown in FIG. 12A, a double-sided adhesive release sheet 56 is attached to the lower surfaces of the first conductive layer 14 and the insulating layer 11. The release sheet 56 has, for example, a polyimide-based base film layer 56A and adhesive layers 56B and 56C made of an acrylic adhesive laminated on the front and back of the base film layer. The release sheet 56 is, for example, a heat-peeling type or UV-peeling type sheet. Furthermore, in the process, an inversion support carrier 55 is attached to the lower surface of the release sheet 56. The inversion support carrier 55 is, for example, a substrate such as glass or metal.

[0095] FIG. 12B is an explanatory diagram showing an example of the support carrier peeling step. In the step shown in FIG. 12B, the outer periphery of the structure is cut using a dicing blade or the like. The cutting is performed so as to remove the region where the insulating layer 11 and the upper prepreg 52 are in direct contact with each other. As a result, it becomes possible to easily peel off the part where the thick foil and the thin foil in the copper foil with carrier 53 are in contact with each other. That is, the main part of the support carrier 50 can be easily removed. The thin foil is removed from the structure from which the main part of the support carrier 50 has been removed. The thin foil in the copper foil with carrier 53 can be removed by, for example, wet etching. As a result, the upper surface of the second conductive layer 15 is exposed on the upper surface of the insulating layer 11. The upper surface of the insulating layer 11 and the upper surface of the second conductive layer 15 can be made flush with each other, for example. That is, the transmission wiring 20A is exposed on the upper surface of the insulating layer 11.

[0096] Fig. 13A is an explanatory diagram showing an example of a thin film layer forming step. In the step shown in Fig. 13A, a thin film layer 12 is formed on an insulating layer 11 and a second conductive layer 15. The thin film layer 12 is formed into a high-density wiring layer by using, for example, a semi-additive method.

[0097] Next, the same process is repeated to form the first insulating layer 61, the first wiring layer 62, the second insulating layer 63, the second wiring layer 64, and the third insulating layer 65 in the thin film layer 12, and the third conductive layer 16 is formed on the uppermost third insulating layer 65 of the thin film layer 12. The above-mentioned surface treatment layer is formed on the surfaces (only the upper surface, or the upper surface and the side surface) of the pads 16A and 16B that constitute the third conductive layer 16. The third conductive layer 16 includes a first pad 16A and a second pad 16B.

[0098] Fig. 13B is an explanatory diagram showing an example of an inversion support carrier peeling step. In the step shown in Fig. 13B, the release sheet 56 adhered to the first conductive layer 14 and the insulating layer 11 is peeled off to peel off the release sheet 56 and the inversion support carrier 55. As a result, the main part of the inversion support carrier 55 can be easily removed. The lower surface of the first conductive layer 14 is exposed on the lower surface of the insulating layer 11. The lower surface of the insulating layer 11 and the lower surface of the first conductive layer 14 can be flush with each other, for example.

[0099] FIG. 14 is an explanatory diagram showing an example of a solder forming process. In the process shown in FIG. 14, a solder layer 17 is formed on the lower surface of the first conductive layer 14 by screen printing or the like. The material and thickness of the solder layer 17 are as described above. Then, an adhesive layer 13 covering the solder layer 17 is formed on the lower surface of the insulating layer 11. The adhesive layer 13 can be formed, for example, by laminating an insulating thermosetting resin film such as NCF on the lower surface of the insulating layer 11 so as to cover the solder layer 17, and then heating and curing the laminate. Through the above process, the wiring board 5A is completed. Note that the solder layer 17 and the adhesive layer 13 are not essential components of the wiring board 5A, and may be formed when necessary (for example, immediately before mounting the wiring board 5A on the build-up board 2).

[0100] As a result, wiring board 5A having first conductive layer 14, insulating layer 11, second conductive layer 15, thin film layer 12, and third conductive layer 16 is completed.

[0101] 15 is an explanatory diagram showing an example of a wiring board mounting process. A plurality of chips 3 and a connector 4 are flip-chip mounted on a wiring board 5A. A chip terminal 3A of the chip 3 is electrically connected to a first pad 16A in a third conductive layer 16 of the wiring board 5A via a solder bump 18. A chip terminal 4A of the connector 4 is electrically connected to a second pad 16B in a third conductive layer 16 of the wiring board 5 via a solder bump 18. A pad 14A of the first conductive layer 14 of the wiring board 5A and a pad 2A on the build-up board 2 are electrically connected to each other via a solder layer 17 to form a semiconductor device 1A.

[0102] In the wiring board 5A of the second embodiment, the transmission wiring 20A is disposed on the second conductive layer 15 at the boundary between the insulating layer 11 and the thin film layer 12. The transmission wiring 20A is embedded in the insulating layer 11 so as to contact the thin film layer 12. Since the thickness of the insulating layer 11 is thicker than the thickness of the insulating layer in the thin film layer 12, the transmission wiring 20A can be made thick. As a result, the wiring resistance of the transmission wiring 20A can be reduced, thereby suppressing insertion loss and reflection loss when a high-speed signal passes through the transmission wiring 20A, and improving the transmission characteristics of the high-speed signal.

[0103] Furthermore, the dielectric loss tangent of the insulating layer 11 having the transmission wiring 20A is smaller than the dielectric loss tangent of the thin film layer 12. As a result, the dielectric loss tangent can suppress the insertion loss and reflection loss when a high-speed signal passes through the transmission wiring 20A, thereby improving the transmission characteristics of the high-speed signal.

[0104] The transmission wiring 20A is formed in the same process as the pad 15A when forming the second conductive layer 15. As a result, the transmission wiring 20A can be formed easily.

[0105] In this embodiment, the case of application to an interposer substrate is illustrated, but the present invention is not limited to this, and may be, for example, a structure in which an insulating layer and a thin film layer are laminated in order on a core substrate, and a plurality of pads are formed on the thin film layer. As a result, the same effect can be obtained by forming the transmission wiring in a thick wiring layer within the insulating layer.

[0106] In addition, the first via 12A1 and the second via 12A2 having via wiring electrically connected to the transmission wiring 20 may have a larger diameter than the other vias formed in the thin film layer, thereby reducing the insertion loss of high-speed signals passing through the transmission wiring. [Explanation of symbols]

[0107] 1 Semiconductor device 2 Build-up board 3. Chip 4 Connector 5, 5A wiring board 11 Insulating layer 12 thin film layers 14 First conductive layer 15 Second conductive layer 16 Third conductive layer 16A 1st Pad 16B 2nd Pad 20, 20A, 20B Transmission wiring 11A, 11B First via 12A 2nd Via

Claims

1. A first insulating layer; a first wiring layer provided on the first insulating layer; a thin film layer provided on one surface of the first insulating layer, the thin film layer including a second insulating layer different from the first insulating layer and a second wiring layer, The thin film layer is a first pad and a second pad provided on a surface opposite to a surface facing the first insulating layer; a first via electrically connecting to the first pad; a second via electrically connected to the second pad; The first wiring layer includes: The second wiring layer is thicker than the first wiring layer. The first wiring layer includes: A wiring board comprising a transmission wiring electrically connecting the first via and the second via.

2. The dielectric loss tangent of the first insulating layer having the transmission wiring is 2. The wiring board according to claim 1, wherein the second insulating layer is smaller than the second insulating layer in the thin film layer.

3. The wiring thickness of the first wiring layer is Within the range of 10 to 20 μm, The wiring thickness of the second wiring layer is 2. The wiring board according to claim 1, wherein the thickness is within a range of 1 to 3 μm.

4. The transmission wiring is 2. The wiring board according to claim 1, wherein the wiring transmits a serial high-speed signal between the first via and the second via.

5. The first wiring layer includes: a first conductive layer formed on the other surface of the first insulating layer; a second conductive layer formed on the one surface of the first insulating layer; The thin film layer is a third conductive layer formed on a surface opposite to a surface facing the first insulating layer; The first insulating layer comprises: a third via electrically connecting the first conductive layer and the second conductive layer; The thin film layer is 2. The wiring board according to claim 1, further comprising the first via and the second via electrically connecting the second conductive layer and the third conductive layer.

6. The transmission wiring is 6. The wiring board according to claim 5, wherein the wiring board is formed in the first conductive layer.

7. The transmission wiring is 6. The wiring board according to claim 5, wherein the wiring board is formed in the second conductive layer.

8. 3. The wiring board according to claim 2, wherein the dielectric tangent of the first insulating layer is within a range of 0.0004 to 0.

02.

9. a wiring board on which the first electronic component and the second electronic component are mounted; A semiconductor device having a multilayer wiring board on which the wiring board is mounted, The wiring board includes: A first insulating layer; a first wiring layer provided on the first insulating layer; a thin film layer including a second insulating layer different from the first insulating layer and a second wiring layer provided on one surface of the first insulating layer, The thin film layer is a first pad and a second pad provided on a surface opposite to a surface facing the first insulating layer; a first via electrically connected to a first pad connected to the first electronic component; a second via electrically connected to a second pad connected to the second electronic component; The first wiring layer includes: The second wiring layer is thicker than the first wiring layer. The first wiring layer includes: a transmission wiring electrically connecting the first via and the second via,

10. A first insulating layer; a first wiring layer formed on the first insulating layer; a first conductive layer in the first wiring layer formed on one surface of the first insulating layer; a second conductive layer in the first wiring layer formed on the other surface of the first insulating layer; a thin film layer including a second insulating layer different from the first insulating layer and a second wiring layer formed on one surface of the first insulating layer; a third conductive layer formed on a surface opposite to a surface facing the first insulating layer, The step of forming the first insulating layer includes: forming the first insulating layer thicker than the wiring thickness of the second insulating layer; The step of forming the thin film layer includes: a first pad and a second pad provided on a surface opposite to a surface facing the first insulating layer; a first via electrically connecting to the first pad; forming a second via electrically connecting to the second pad; The step of forming the first conductive layer includes: a transmission wiring that electrically connects between the first via and the second via is formed in the first conductive layer.

11. A first insulating layer; a first wiring layer formed on the first insulating layer; a first conductive layer in the first wiring layer formed on one surface of the first insulating layer; a second conductive layer in the first wiring layer formed on the other surface of the first insulating layer; a thin film layer including a second insulating layer different from the first insulating layer and a second wiring layer formed on one surface of the first insulating layer; a third conductive layer formed on a surface opposite to a surface facing the first insulating layer, The step of forming the first insulating layer includes: forming the first insulating layer thicker than the wiring thickness of the second insulating layer; The step of forming the thin film layer includes: a first pad and a second pad provided on a surface opposite to a surface facing the first insulating layer; a first via electrically connecting to the first pad; forming a second via electrically connecting to the second pad; The step of forming the second conductive layer includes: a transmission wiring that electrically connects between the first via and the second via is formed in the second conductive layer.

Images