Element array circuit, electromagnetic wave sensor, temperature sensor, and strain sensor

Abstract

To provide an element array circuit that can obtain a measured value related to a resistance value or the like quickly with high accuracy.SOLUTION: An element array circuit includes one or more first wiring lines, a plurality of second wiring lines, a plurality of impedance elements, one or more operational amplifiers, one or more conversion elements, and one or more switching portions. The plurality of second wiring lines each extends in a direction different from a direction in which one or more first wiring lines extend. The plurality of impedance elements is each coupled to both one of one or more first wiring lines and one of the plurality of second wiring lines. One or more operational amplifiers each include a positive input terminal, a negative input terminal that can be coupled to one of the plurality of second wiring lines, and an output terminal. One or more conversion elements are each coupled to the negative input terminal and the output terminal, and each convert a current flowing through one of the plurality of second wiring lines coupled to the negative input terminal into voltage. One or more switching portions are each coupled to one of the one or more conversion elements in parallel between the negative input terminal and the output terminal, and may come into either a conduction state or a non-conduction state.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to an element array circuit having an element array in which a plurality of impedance elements are arranged, and to an electromagnetic wave sensor, a temperature sensor, and a strain sensor including the element array circuit. [Background technology]

[0002] A resistor element array circuit having a plurality of resistor elements arranged in a matrix has been disclosed. Such a resistor element array circuit is used, for example, as an infrared detection circuit (see, for example, Patent Document 1). In such an infrared detection circuit, a plurality of infrared sensitive resistors, such as thermistors, whose resistance value changes in response to temperature changes, are arranged. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 08-94443 Summary of the Invention [Problem to be solved by the invention]

[0004] In element array circuits such as infrared detection circuits, it is desirable to be able to quickly and accurately obtain measured values ​​related to resistance values ​​and the like. [Means for solving the problem]

[0005] An element array circuit according to an embodiment of the present invention includes one or more first wirings, a plurality of second wirings, a plurality of impedance elements, one or more operational amplifiers, one or more conversion elements, and one or more switching units. The plurality of second wirings each extend in a direction different from the one or more first wirings. The plurality of impedance elements are each connected to both one of the one or more first wirings and one of the plurality of second wirings. Each of the one or more operational amplifiers has a positive input terminal, a negative input terminal connectable to one of the plurality of second wirings, and an output terminal. Each of the one or more conversion elements is connected to the negative input terminal and the output terminal, and converts a current flowing through one of the plurality of second wirings connected to the negative input terminal into a voltage. Each of the one or more switching units is connected in parallel with one of the one or more conversion elements between the negative input terminal and the output terminal, and can be in a conductive state or a non-conductive state.

[0006] In an element array circuit according to an embodiment of the present invention, the parasitic capacitance of the second wiring connected to the negative input terminal is quickly charged by making the switching unit conductive and connecting the second wiring connected to the negative input terminal to the output terminal. After this charging, the switching unit is switched to a non-conductive state, and the output voltage from the output terminal caused by the impedance element can be measured. Effect of the Invention

[0007] According to an embodiment of the element array circuit of the present invention, it is possible to obtain measurement values ​​quickly and with high accuracy. [Brief description of the drawings]

[0008] [Figure 1] 1 is a circuit diagram illustrating a configuration example of an element array circuit according to a first embodiment of the present invention. [Diagram 2] 2 is a flowchart illustrating an example of a measurement operation of the element array circuit shown in FIG. 1. [Diagram 3] 2 is a circuit diagram illustrating a charging operation of a parasitic capacitance in the element array circuit shown in FIG. [Figure 4]2 is an explanatory diagram for explaining a change in output voltage in the element array circuit 1 of FIG. [Diagram 5] FIG. 11 is a circuit diagram illustrating a configuration example of an element array circuit according to a second embodiment of the present invention. [Figure 6] FIG. 13 is a circuit diagram illustrating a configuration example of an element array circuit according to a third embodiment of the present invention. [Figure 7] 7 is a flowchart illustrating an example of a measurement operation of the element array circuit shown in FIG. 6. [Figure 8] 7 is a circuit diagram illustrating a charging operation of a parasitic capacitance in the element array circuit shown in FIG. 6. [Figure 9] FIG. 13 is a circuit diagram illustrating a configuration example of an element array circuit according to a fourth embodiment of the present invention. [Figure 10] FIG. 13 is a schematic diagram illustrating a configuration example of a sensor device according to a fifth embodiment of the present invention. [Figure 11] FIG. 11 is a circuit diagram illustrating an example of the configuration of an element array circuit according to a first modified example of the present invention. [Figure 12] FIG. 13 is a circuit diagram illustrating an example of the configuration of an element array circuit according to a second modified example of the present invention. [Figure 13] FIG. 13 is a circuit diagram illustrating an example of the configuration of an element array circuit according to a third modified example of the present invention. [Figure 14] FIG. 13 is a circuit diagram illustrating an example of the configuration of an element array circuit according to a fourth modified example of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The description will be given in the following order. 1. First embodiment (first example of an element array circuit having a plurality of column lines and a plurality of operational amplifiers) 2. Second embodiment (second example of element array circuit having multiple column lines and multiple operational amplifiers) 3. Third embodiment (first example of element array circuit equipped with column line selection unit) 4. Fourth embodiment (second example of element array circuit having column line selection unit) 5. Fifth embodiment (example of sensor device equipped with element array circuit) 6. Variations

[0010] <1. First embodiment> [Overall configuration example of element array circuit 1] 1 is a circuit diagram showing a schematic configuration example of an element array circuit 1 according to a first embodiment of the present invention. The element array circuit 1 is mounted on, for example, an infrared thermograph, and is configured to output an output voltage according to the intensity of infrared rays irradiated onto the element array circuit 1.

[0011] As shown in FIG. 1, the element array circuit 1 includes, for example, a plurality of row lines A (represented as A1 to Am in FIG. 1), a plurality of column lines B (represented as B1 to Bn in FIG. 1), a plurality of resistive elements R (represented as R(1,1) to R(m,n) in FIG. 1), a row line selection unit SA, a plurality of operational amplifiers OP (represented as OP1 to OPn in FIG. 1), a plurality of capacitive elements CP (represented as CP1 to CPn in FIG. 1), a plurality of switches SW1 (represented as SW1 to SWn in FIG. 1), and a control unit CTRL. Note that, although FIG. 1 illustrates an example in which m row lines A are arranged, the number of the plurality of row lines A can be set arbitrarily. Similarly, FIG. 1 illustrates an example in which n column lines B are arranged, the number of the plurality of column lines B can be set arbitrarily. 1, a resistive element R connected to both the a-th row line Aa of the m row lines A1 to Am and the b-th column line Bb of the n column lines B1 to Bn is represented as R(a, b). The same notation is used in the drawings subsequent to FIG. 1. The row lines A and the column lines B are not in direct contact with each other.

[0012] (Row line A) The row line A is a specific example of a "first wiring" of the invention. Each of the row lines A extends in a first direction, and the row lines A are arranged adjacent to each other in a second direction different from the first direction. In the example of Fig. 1, the row lines A extend, for example, in the Y-axis direction, and are arranged adjacent to each other in the X-axis direction perpendicular to the Y-axis direction.

[0013] A first end of each of the row lines A can be connected to a DC power supply PS1 via a switch SWA1 (represented as SWA1-1 to SWA1-m in FIG. 1) of the row line selection unit SA, and can be connected to a DC power supply PS2 via a switch SWA2 (represented as SWA2-1 to SWA2-m in FIG. 1) of the row line selection unit SA. In addition, first ends of a plurality of resistive elements R are connected to each of the row lines A. In the example of FIG. 1, n resistive elements R are connected in parallel to one row line A. Specifically, the first ends of the resistive elements R(1,1) to R(1,n) arranged in the Y-axis direction are connected to the row line A1 extending in the Y-axis direction. Similarly, the first ends of the resistor elements R(2,1) to R(2,n) aligned in the Y-axis direction are connected to the row line A2 extending in the Y-axis direction, and the first ends of the resistor elements R(m,1) to R(m,n) aligned in the Y-axis direction are connected to the row line Am extending in the Y-axis direction. In the example of Fig. 1, the second ends of each of the multiple row lines A, opposite to the first ends, are connected to the first ends of the resistor elements R(1,n) to R(m,n) aligned in the X-axis direction.

[0014] When measuring a resistance element R (for convenience, referred to as a selected resistance element RS) selected from the multiple resistance elements R, a switch SWA1 corresponding to the selected Row line AS is made conductive so that a first voltage V1 is applied from a DC power supply PS1 to a Row line A (for convenience, referred to as a selected Row line AS) corresponding to the selected resistance element RS. When measuring the selected resistance element RS, a second voltage V2 (≠ V1) is applied from a DC power supply PS2 to all Row lines A other than the selected Row line A (for convenience, referred to as unselected Row lines AU) via a conductive switch SWA2 corresponding to the unselected Row line AU. 1 shows, as an example, a state in which the resistance elements R(1,1) to R(1,n) are selected. That is, FIG. 1 shows a state in which the switch SWA1-1 is in a conductive state, so that the first voltage V1 is applied from the DC power supply PS1 to the selected Row line A1 corresponding to the selected resistance elements R(1,1) to R(1,n), and a state in which the switches SWA2-2 to SWA2-m are in a conductive state, so that the second voltage V2 (≠ V1) is applied from the DC power supply PS2 to all the unselected Row lines A2 to Am other than the selected Row line A1. In this case, all of the switches SWA1-2 to SWA1-m connected to the unselected Row lines A2 to Am are in a non-conductive state, and the switch SWA2-1 connected to the selected Row line A1 is also in a non-conductive state. Either the first voltage V1 or the second voltage V2 may be 0V.

[0015] (Column B) The column line B is a specific example of a "second wiring" of the present invention. Each of the column lines B extends in a direction different from that of the row lines A. For example, each of the column lines B extends in a second direction, and the column lines B are arranged adjacent to each other in a first direction different from the second direction. In the example of Fig. 1, the column lines B extend in the X-axis direction, for example, and are arranged adjacent to each other in the Y-axis direction.

[0016] A first end of each of the multiple column lines B is connected to a corresponding one of the multiple operational amplifiers OP. Specifically, a first end of the column line B1 is connected to the negative input terminal T2 of the operational amplifier OP1, a first end of the column line B2 is connected to the negative input terminal T2 of the operational amplifier OP2, and a first end of the column line Bn is connected to the negative input terminal T2 of the operational amplifier OPn.

[0017] Further, second ends of the multiple resistance elements R are connected to each of the multiple column lines B. The second end of the resistance element R is an end of the resistance element R opposite to the first end connected to the row line A. In the example of FIG. 1, m resistance elements R are connected in parallel to one column line B. Specifically, the second ends of the resistance elements R(1,1) to R(m,1) arranged in the X-axis direction are connected to a column line B1 extending in the X-axis direction. Similarly, the second ends of the resistance elements R(1,2) to R(m,2) arranged in the X-axis direction are connected to a column line B2 extending in the X-axis direction, and the second ends of the resistance elements R(1,n) to R(m,n) arranged in the X-axis direction are connected to a column line Bn extending in the X-axis direction. In the example of FIG. 1, the second ends of the multiple column lines B opposite to the first ends are connected to the second ends of the resistance elements R(m,1) to R(m,n) arranged in the Y-axis direction.

[0018] (Resistance element R) The resistance element R is a specific example corresponding to an "impedance element" of the present invention. Each of the multiple resistance elements R is connected to both one of the multiple row lines A and one of the multiple column lines B. Each of the multiple resistance elements R has a first end connected to the row line A and a second end connected to the column line B. As described above, in the example of FIG. 1, n resistance elements R are connected to each of the multiple row lines A, and m resistance elements R are connected to each of the multiple column lines B. There is one resistance element R connected to both one row line A of the multiple row lines A and one column line B of the multiple column lines B. Therefore, one resistance element R can be identified by selecting one row line A from the multiple row lines A and selecting one column line B from the multiple column lines B.

[0019] The resistance element R is a part of an infrared light receiving element that converts infrared light collected by a lens or the like into an electric signal, and is specifically a resistance change layer that exhibits a resistance change due to a temperature change. The resistance change layer is, for example, a thermistor film. The thermistor film contains, for example, vanadium oxide, amorphous silicon, polycrystalline silicon, oxide with a spinel crystal structure containing manganese, titanium oxide, or yttrium-barium-copper oxide. In addition, an infrared absorbing layer that absorbs infrared light and generates heat is provided adjacent to the thermistor film. The infrared absorbing layer contains, for example, silicon oxide (SiO2), aluminum oxide (Al2O3), silicon nitride (Si3N4), or aluminum nitride (AlN). In the resistance element R, the temperature change of the infrared absorbing layer and the temperature change of the resistance change layer occur depending on the intensity of the infrared light received, and as a result, the resistance value of the resistance change layer changes.

[0020] (Row line selection section SA) The row line selection unit SA has a plurality of switches SWA1 (SWA1-1 to SWA1-m) and a plurality of switches SWA2 (SWA2-1 to SWA2-m). Each of the plurality of switches SWA1 (SWA1-1 to SWA1-m) and the plurality of switches SWA2 (SWA2-1 to SWA2-m) can switch between a conductive state and a non-conductive state. Each of the plurality of switches SWA1 (SWA1-1 to SWA1-m) is provided between a corresponding one of the row lines A (A1 to Am) and a DC power supply PS1. Each of the plurality of switches SWA2 (SWA2-1 to SWA2-m) is provided between a corresponding one of the row lines A (A1 to Am) and a DC power supply PS2.

[0021] The Row line selection unit SA selects one Row line A (for convenience, referred to as a selected Row line AS) from among the plurality of Row lines A, connects the selected Row line AS to a DC power supply PS1 that applies a first voltage V1 to the selected Row line AS, and connects the unselected wirings AU to a DC power supply PS2 that applies a second voltage V2 to the unselected wirings AU other than the selected Row line AS among the plurality of Row lines A. The second voltage V2 is different from the first voltage V1. The operation of the Row line selection unit SA is controlled by the control unit CTRL. That is, the switching operations of the plurality of switches SWA1 (SWA1-1 to SWA1-m) and the plurality of switches SWA2 (SWA2-1 to SWA2-m) in the Row line selection unit SA are performed based on commands from the control unit CTRL.

[0022] (Op Amp OP) Each of the operational amplifiers OP is connected to a corresponding one of the column lines B. Each of the operational amplifiers OP (denoted as OP1 to OPn in FIG. 1) includes a positive input terminal T1, a negative input terminal T2, and an output terminal T3. The positive input terminal T1 is connected to a DC power supply PS2, and a second voltage V2 is applied to the positive input terminal T1. The negative input terminal T2 is connected to a corresponding one of the column lines B. Each of the operational amplifiers OP operates so that the positive input terminal T1 and the negative input terminal T2 have the same potential, so that the potential of the negative input terminal T2 is approximately the second voltage V2. The output terminal T3 is connected to the negative input terminal T2 via a capacitance element CP.

[0023] (Capacitor element CP) The capacitance element CP is a specific example of a "conversion element" of the present invention. Each of the multiple capacitive elements CP is connected to both the negative input terminal T2 and the output terminal T3 of a corresponding one of the operational amplifiers OP, and converts the current flowing through the column line B connected to the negative input terminal T2 into a voltage. Specifically, in the example of FIG. 1, the capacitive element CP1 is connected to both the negative input terminal T2 and the output terminal T3 of the operational amplifier OP1, and converts the current flowing through the column line B1 into a voltage. Similarly, the capacitive element CP2 is connected to both the negative input terminal T2 and the output terminal T3 of the operational amplifier OP2, and converts the current flowing through the column line B2 into a voltage, and the capacitive element CPn is connected to both the negative input terminal T2 and the output terminal T3 of the operational amplifier OPn, and converts the current flowing through the column line Bn into a voltage.

[0024] (Switch) The switch SW is one example of a feature corresponding to a "switching portion" of the invention. Each of the switches SW is connected to a corresponding one of the operational amplifiers OP. Each of the switches SW is connected in parallel with a corresponding one of the capacitive elements CP between the negative input terminal T2 and the output terminal T3 of the corresponding one of the operational amplifiers OP. Each of the switches SW can be in a conductive state or a non-conductive state. Specifically, in the example of FIG. 1, the switch SW1 is connected in parallel with the capacitive element CP1 between the negative input terminal T2 and the output terminal T3 of the operational amplifier OP1, and can be in a conductive state or a non-conductive state. Similarly, the switch SW2 is connected in parallel with the capacitive element CP2 between the negative input terminal T2 and the output terminal T3 of the operational amplifier OP2, and can be in a conductive state or a non-conductive state. The switch SWn is connected in parallel with the capacitive element CPn between the negative input terminal T2 and the output terminal T3 of the operational amplifier OPn, and can be in a conductive state or a non-conductive state.

[0025] (Control CTRL) The control unit CTRL is, for example, a microcomputer, and a CPU (Central Processing Unit) executes a control program to perform a predetermined control process. The control unit CTRL, for example, controls the switching operation of a plurality of switches SW. The control unit CTRL charges the parasitic capacitance of each of the plurality of column lines B, and then controls to switch one switch SW corresponding to each column line B to a non-conductive state. The control unit CTRL charges the parasitic capacitance of each column line B by turning on one switch SW corresponding to each column line B and conducting the column line B connected to the negative input terminal T2 of the corresponding operational amplifier OP and the output terminal T3 of the corresponding operational amplifier OP.

[0026] The control unit CTRL controls the switching operation of the row line selection unit SA. That is, the control unit CTRL sets one switch SWA1 corresponding to the selected row line AS in a conductive state, and sets the other switches SWA1 corresponding to the unselected row lines AU in a non-conductive state. In addition, the control unit CTRL sets one switch SWA2 corresponding to the selected row line AS in a non-conductive state, and sets the other switches SWA2 corresponding to the unselected row lines AU in a conductive state. Here, the selected row line AS is one row line A corresponding to the selection resistance element RS. The unselected row lines AU are all the row lines A other than the selected row line AS.

[0027] After charging the parasitic capacitance of each column line B, the control unit CTRL switches one switch SW corresponding to each column line B to a non-conductive state, and then measures the output voltage from the output terminal T3 of one operational amplifier OP corresponding to each column line B, which is caused by the selection resistance element RS connected to both the selected row line AS and each column line B.

[0028] Moreover, the time during which the switch SW corresponding to each column line B is brought into a conductive state to charge the parasitic capacitance of each column line B should be longer than the time during which the charge of the capacitance element CP corresponding to each column line B is almost completely discharged. Specifically, the time should be longer than five times the product of the capacitance value of the capacitance element CP corresponding to each column line B and the resistance value (resistance value when the switch SW is brought into a conductive state) of the corresponding switch SW. Moreover, the time during which the switch SW corresponding to each column line B is brought into a conductive state to charge the parasitic capacitance of each column line B should be longer than five times the product of the capacitance value of the parasitic capacitance of each column line B and the resistance value of the switch SW corresponding to each column line B. This is because the parasitic capacitance of each column line B is sufficiently charged, and the output voltage caused by each selection resistance element RS can be accurately measured.

[0029] Each of the DC power supplies PS1 and PS2 may be provided inside the element array circuit 1 or may be provided outside the element array circuit 1.

[0030] [Measurement operation in element array circuit 1] In the element array circuit 1, for example, it is possible to measure each of the multiple resistance elements R in the following manner. Note that the following measurement operation is performed in response to a command from the control unit CTRL.

[0031] 2 is a flowchart illustrating an example of a measurement operation of the element array circuit 1. First, all the switches are set to a non-conductive state (step S101). Specifically, the multiple switches SW1 (SW1 to SWn), the multiple switches SWA1 (SWA1-1 to SWA1-m), and the multiple switches SWA2 (SWA2-1 to SWA2-m) shown in FIG. 1 are all set to a non-conductive state (open state).

[0032] Next, a selected Row line AS corresponding to the selected resistance element RS to be measured is selected (step S102). Specifically, the switch SWA1 of the selected Row line AS to which the selected resistance element RS is connected is turned on, and a first voltage V1 is applied to the selected Row line AS. The switch SWA1 corresponding to the unselected Row line AU is maintained in a non-conductive state. Furthermore, the switch SWA2 of the unselected Row line AU is turned on, and a second voltage V2 is applied to the unselected Row line AU. The switch SWA2 corresponding to the selected Row line AS is maintained in a non-conductive state. The example in FIG. 1 shows a state in which the resistance elements R(1,1) to R(1,n) are selected as the selected resistance element RS. That is, the switch SWA1-1 corresponding to the Row line A1 as the selected Row line AS is turned on, and a first voltage V1 is applied to the Row line A1. Meanwhile, the switches SWA1-2 to SWA1-m corresponding to the Row lines A2 to Am as the unselected Row lines AU are maintained in a non-conductive state. Furthermore, the switches SWA2-2 to SWA2-m corresponding to the row lines A2 to Am as the unselected row lines AU are brought into a conductive state, and a second voltage V2 is applied to the row lines A2 to Am, while the switch SWA2-1 corresponding to the row line A1 as the selected row line AS is kept in a non-conductive state.

[0033] Next, one switch SW corresponding to each column line B is turned on (step S103), and the parasitic capacitance of each column line B is charged (step S103). Specifically, one switch SW corresponding to each column line B is turned on, and the column line B connected to the negative input terminal T2 of the corresponding operational amplifier OP is brought into conduction with the output terminal T3 of the corresponding operational amplifier OP. In the example of FIG. 1, the switch SW1 corresponding to the column line B1 to which the resistor element R(1,1) as the selected resistor element RS is connected is turned on, and the negative input terminal T2 and the output terminal T3 of the operational amplifier OP1 are brought into conduction. Similarly, the switch SW2 corresponding to the column line B2 to which the resistor element R(1,2) as the selection resistor element RS is connected is turned on to make the negative input terminal T2 and output terminal T3 of the operational amplifier OP2 conductive, and the switch SWn corresponding to the column line Bn to which the resistor element R(1,n) as the selection resistor element RS is connected is turned on to make the negative input terminal T2 and output terminal T3 of the operational amplifier OPn conductive. FIG. 3 shows a circuit diagram for explaining the charging operation of the parasitic capacitance PC in the element array circuit 1. As shown by the dashed arrow in FIG. 3, by turning the switch SW1 on, a current flows from the operational amplifier OP1 to the column line B1, and the parasitic capacitance PC parasitic to the column line B1 is charged. Similarly, by turning the switch SW2 on, the parasitic capacitance PC parasitic to the column line B2 is charged, and by turning the switch SWn on, the parasitic capacitance PC parasitic to the column line Bn is charged. Here, it is preferable to charge the parasitic capacitance PC of each column line B by keeping one switch SW corresponding to each column line B in a conductive state for a time longer than the time required for the charge of one capacitance element CP corresponding to each column line B to be discharged almost entirely. Specifically, it is preferable to keep the switch SW1 in a conductive state for a time longer than five times the product of the capacitance value of the capacitance element CP1 and the resistance value of the switch SW1, i.e., five times the time constant, to charge the parasitic capacitance PC of the column line B1. If the switch SW1 is kept in a conductive state for a time five times the product of the capacitance value of the capacitance element CP1 and the resistance value of the switch SW1, 99.3% of the charge of the capacitance element CP1 is discharged.Similarly, it is preferable to charge the parasitic capacitance PC of the column line B2 by turning on the switch SW2 for a time longer than five times the product of the capacitance value of the capacitance element CP2 and the resistance value of the switch SW2, and it is preferable to charge the parasitic capacitance PC of the column line Bn by turning on the switch SWn for a time longer than five times the product of the capacitance value of the capacitance element CPn and the resistance value of the switch SWn. It is also preferable to charge the parasitic capacitance PC of each column line B by turning on one switch SW corresponding to each column line B for a time longer than five times the product of the capacitance value of the parasitic capacitance PC of each column line B and the resistance value of one switch SW corresponding to each column line B. This is because the parasitic capacitance PC of each column line B is sufficiently charged, and the output voltage caused by each selection resistance element RS can be accurately measured. It is preferable to charge the parasitic capacitance PC of the column line B1 by keeping the switch SW1 in a conductive state for a time longer than five times the product of the capacitance value of the parasitic capacitance PC of the column line B1 and the resistance value of the switch SW1, i.e., five times the time constant. Similarly, it is preferable to charge the parasitic capacitance PC of the column line B2 by keeping the switch SW2 in a conductive state for a time longer than five times the product of the capacitance value of the parasitic capacitance PC of the column line B2 and the resistance value of the switch SW2, and it is preferable to charge the parasitic capacitance PC of the column line Bn by keeping the switch SWn in a conductive state for a time longer than five times the product of the capacitance value of the parasitic capacitance PC of the column line Bn and the resistance value of the switch SWn.

[0034] Next, one switch SW corresponding to each column line B is turned off (step S104). As a result, one switch SW corresponding to each column line B is turned on, and charging of the parasitic capacitance PC of each column line B is completed. In the example of FIG. 1, the switch SW1 corresponding to the column line B1 is switched to a non-conductive state. Similarly, the switch SW2 corresponding to the column line B2 is switched to a non-conductive state, and the switch SWn corresponding to the column line Bn is switched to a non-conductive state. At this time, since the potential of the negative input terminal T2 of each operational amplifier OP is the second voltage V2, a voltage (V2-V1) that is the difference between the first voltage V1 and the second voltage V2 is applied to the resistance elements R(1,1) to R(1,n), and a current that depends on the resistance value of each of the resistance elements R(1,1) to R(1,n) flows through each of the resistance elements R(1,1) to R(1,n), flows through each of the column lines B1 to Bn, and flows toward each of the capacitance elements CP1 to CPn. In contrast, a second voltage V2 is applied to the row lines A2 to Am other than the row line A1, which is the selected row line AS, and to the column lines B1 to Bn. Therefore, the voltage applied to the resistance elements R other than the resistance elements R(1,1) to R(1,n) serving as the selected resistance element RS is 0, and no current flows through the resistance elements R other than the resistance elements R(1,1) to R(1,n).

[0035] Next, the output voltage corresponding to each selected resistor element RS is measured (step S105). Specifically, the output voltage from the output terminal T3 of one operational amplifier OP corresponding to each column line B, which is caused by the selected resistor element RS connected to both the selected row line AS and each column line B, is measured. In the example of FIG. 1, the output voltage Vout from the output terminal T3 of the operational amplifier OP1 corresponding to the resistor element R(1,1) connected to both the row line A1 and the column line B1 is measured. Similarly, the output voltage Vout from the output terminal T3 of the operational amplifier OP2 corresponding to the resistor element R(1,2) connected to both the row line A1 and the column line B2 is measured, and the output voltage Vout from the output terminal T3 of the operational amplifier OPn corresponding to the resistor element R(1,n) connected to both the row line A1 and the column line Bn is measured. The current flowing through each of the column lines B1 to Bn is converted into a voltage by each of the capacitance elements CP1 to CPn, and is output as an output voltage Vout from the output terminal T3 of the operational amplifiers OP1 to OPn corresponding to the resistor elements R(1,1) to R(1,n). The output voltage Vout can be expressed as the following equation (1).

[0036] Vout[V]={(V2[V]-V1[V]) / (cs[F]×rs[Ω])}×T[sec.]+V2[V] ……(1) Where: V1 [V]: the first voltage applied to the selected row line AS. V2 [V]: A second voltage applied to the positive input terminal T1. cs[F]: the capacitance value of one capacitive element CP corresponding to each column line B. rs [Ω]: the resistance value of one selection resistance element RS corresponding to each column line B. T [sec.]: the elapsed time from when one switch SW corresponding to each column line B is turned off. Vout [V]: the output voltage of one operational amplifier OP corresponding to each column line B after T [sec.] has elapsed.

[0037] FIG. 4 is an explanatory diagram for explaining the change in the output voltage Vout from the output terminal T3 of the operational amplifier OP1 in the element array circuit 1. The horizontal axis of FIG. 4 represents time t, and the vertical axis of FIG. 4 represents the output voltage Vout. In FIG. 4, time t0 is the time when the switch SW1 is switched to the conductive state in step S103 and charging of the parasitic capacitance PC of the column line B1 is started. In FIG. 4, time t1 is the time when the switch SW1 is switched to the non-conductive state in step S104 and charging of the parasitic capacitance PC of the column line B1 is completed. Therefore, the charging time of the parasitic capacitance PC of the column line B1 is from time t0 to time t1. In FIG. 4, time t2 is the time when the output voltage Vout_t2 is measured after the time T has elapsed from time t1. The example shown in FIG. 4 is an example in which the first voltage V1 is greater than the second voltage V2, and the output voltage Vout gradually decreases as time elapses from time t1. Since the capacitance value cs [F] of the capacitance element CP is known, the output voltage Vout depends on the resistance value rs [Ω] of the selective resistance element RS as shown in equation (1). Therefore, based on the above equation (1), the resistance value rs of each selective resistance element RS can be calculated from the output voltage Vout_t2 at time t2.

[0038] This completes the measurement operation in the element array circuit 1. When measuring the output voltage Vout corresponding to a resistive element R other than the resistive elements R(1,1) to R(1,n), the above steps S101 to S105 are repeated. However, for the column line B to which the resistive element R that has already been measured is connected, the operation of recharging the parasitic capacitance may be omitted. In this embodiment, the order of steps S102 and S103 may be interchanged, or step S102 may be placed between steps S104 and S105.

[0039] [Effects of element array circuit 1] As described above, the element array circuit 1 of the present embodiment includes one or more row lines A, a plurality of column lines B, a plurality of resistance elements R, one or more operational amplifiers OP, one or more capacitance elements CP, and one or more switches SW. The plurality of column lines B extend in a direction different from that of the one or more row lines A. The plurality of resistance elements R are each connected to both one of the one or more first row lines A and one of the plurality of column lines B. The one or more operational amplifiers OP have a positive input terminal T1, a negative input terminal T2 connectable to one of the plurality of column lines B, and an output terminal T3. The one or more capacitance elements CP are connected to the negative input terminal T2 and the output terminal T3, and convert a current flowing through the column line B connected to the negative input terminal T2 into a voltage. The one or more switches SW are connected in parallel with the capacitance element CP between the negative input terminal T2 and the output terminal T3, and can be in a conductive state or a non-conductive state. In the element array circuit 1 configured as above, a switch SW corresponding to each column line B is turned on to electrically connect the column line B connected to the negative input terminal T2 of the corresponding operational amplifier OP to the output terminal T3 of the corresponding operational amplifier OP, thereby quickly charging the parasitic capacitance of the column line B connected to the negative input terminal T2 of the corresponding operational amplifier OP. After this charging, the switch SW is turned off to measure the output voltage Vout from the output terminal T3 of the operational amplifier OP corresponding to each selected resistor element RS.

[0040] However, for example, in the infrared detection circuit of Patent Document 1, a resistive element (resistor Rt mn) and the parasitic capacitance of the wiring connected to the resistor element and the negative input terminal of the operational amplifier form a low-pass filter. Due to the effect of such a low-pass filter, it may take a long time for the potential of the negative input terminal of the operational amplifier to which the wiring is connected to reach a steady state due to charging of the parasitic capacitance, and it may take a long time for the output voltage value caused by the resistor element to reach a steady state. Therefore, in order to accurately measure the resistance value of the resistor element, it is necessary to wait a long time until the output voltage value reaches a steady state. Although it is possible to measure the output voltage value before it reaches a steady state, the accuracy of the measurement value will decrease.

[0041] In this regard, the element array circuit 1 of the present embodiment is provided with the switch SW, which makes it possible to quickly charge the parasitic capacitance that is parasitic on each column line B. Therefore, the output voltage Vout resulting from the selection resistance element RS connected to each column line B can be quickly brought to a steady state, and the output voltage Vout related to the resistance value of each selection resistance element RS can be quickly and accurately measured.

[0042] Furthermore, the element array circuit 1 of this embodiment is provided with multiple operational amplifiers OP, with one operational amplifier OP corresponding to each of the multiple column lines B. Therefore, the output voltage Vout can be measured more quickly than when, for example, each of the multiple column lines B is selectively connected to one operational amplifier OP to measure the output voltage Vout.

[0043] <2. Second embodiment> [Overall configuration example of element array circuit 2] Fig. 5 is a circuit diagram showing a schematic example of the overall configuration of an element array circuit 2 according to a second embodiment of the present invention. As shown in Fig. 5, the configuration of the element array circuit 2 is substantially the same as the configuration of the element array circuit 1 according to the first embodiment shown in Fig. 1, except that a plurality of resistive elements RE (represented as RE1 to REn in Fig. 5) are used as a plurality of conversion elements instead of a plurality of capacitive elements CP. Therefore, in the following description, the resistive element RE will be mainly described, and descriptions of other components will be omitted as appropriate.

[0044] (Resistance element RE) The resistive element RE is a specific example corresponding to the "conversion element" and the "first resistive element" of the present invention. The resistive element RE includes, for example, a resistor made of a metal material having a predetermined specific resistance. Each of the resistive elements RE is connected to both the negative input terminal T2 and the output terminal T3 of a corresponding operational amplifier OP, and converts the current flowing through the column line B connected to the negative input terminal T2 into a voltage. Specifically, in the example of FIG. 5, the resistive element RE1 is connected to both the negative input terminal T2 and the output terminal T3 of the operational amplifier OP1, and converts the current flowing through the column line B1 into a voltage. Similarly, the resistive element RE2 is connected to both the negative input terminal T2 and the output terminal T3 of the operational amplifier OP2, and converts the current flowing through the column line B2 into a voltage, and the resistive element REn is connected to both the negative input terminal T2 and the output terminal T3 of the operational amplifier OPn, and converts the current flowing through the column line Bn into a voltage. The resistance value of each of the resistive elements RE is greater than the resistance value of the corresponding switch SW.

[0045] [Measurement operation in element array circuit 2] In the element array circuit 2, it is possible to measure each of the multiple resistance elements R, for example, in the following manner. Note that the following measurement operation is performed in response to a command from the control unit CTRL.

[0046] The measurement operation of the element array circuit 2 is basically the same as that of the element array circuit 1 (see FIG. 2). That is, as shown in the flowchart of FIG. 2, before the measurement of the resistance element R, the parasitic capacitance of each column line B is promptly charged (step S103). Specifically, in the example of FIG. 5, the switch SW1 corresponding to the column line B1 to which the resistance element R(1,1) as the selected resistance element RS is connected is brought into a conductive state, and the negative input terminal T2 and the output terminal T3 of the operational amplifier OP1 are brought into a conductive state. Similarly, the switch SW2 corresponding to the column line B2 to which the resistance element R(1,2) as the selected resistance element RS is connected is brought into a conductive state, and the negative input terminal T2 and the output terminal T3 of the operational amplifier OP2 are brought into a conductive state, and the switch SWn corresponding to the column line Bn to which the resistance element R(1,n) as the selected resistance element RS is connected is brought into a conductive state, and the negative input terminal T2 and the output terminal T3 of the operational amplifier OPn are brought into a conductive state. As a result, the parasitic capacitances of the column lines B1, B2, and Bn are charged. As in the first embodiment, the time during which the switch SW corresponding to each column line B is turned on to charge the parasitic capacitance PC of each column line B is preferably longer than five times the product of the capacitance value of the parasitic capacitance PC of each column line B and the resistance value of the switch SW corresponding to each column line B.

[0047] Next, one switch SW corresponding to each column line B is turned off (step S104). As a result, one switch SW corresponding to each column line B is turned on, and charging of the parasitic capacitance PC of each column line B is completed. In the example of FIG. 5, the switch SW1 corresponding to the column line B1 is switched to a non-conductive state. Similarly, the switch SW2 corresponding to the column line B2 is switched to a non-conductive state, and the switch SWn corresponding to the column line Bn is switched to a non-conductive state. At this time, a voltage (V2-V1) that is a difference between the first voltage V1 and the second voltage V2 is applied to the resistance elements R(1,1) to R(1,n), and a current that depends on the resistance value of each of the resistance elements R(1,1) to R(1,n) flows through each of the resistance elements R(1,1) to R(1,n), flows through each of the column lines B1 to Bn, and flows through each of the resistance elements RE1 to REn. In FIG. 5, the dashed arrow indicates the current flowing through the resistor RE1 depending on the resistance value of the resistor R(1,1). On the other hand, a second voltage V2 is applied to the other row lines A2 to Am other than the row line A1, which is the selected row line AS, and to the column lines B1 to Bn. Therefore, the voltage applied to the other resistor elements R other than the resistor elements R(1,1) to R(1,n) as the selected resistor element RS is 0, so that no current flows through the other resistor elements R other than the resistor elements R(1,1) to R(1,n). Next, the output voltage corresponding to each selected resistor element RS is measured (step S105). Specifically, the output voltage from the output terminal T3 of one operational amplifier OP corresponding to each column line B, which is caused by the selected resistor element RS connected to both the selected row line AS and each column line B, is measured. The currents flowing through the column lines B1 to Bn are converted to voltages by the resistive elements RE1 to REn, respectively, and are output as output voltages Vout from the output terminals T3 of the operational amplifiers OP1 to OPn corresponding to the resistive elements R(1,1) to R(1,n), respectively. The output voltage Vout can be expressed as the following equation (2).

[0048] Vout[V]=(re[Ω] / rs[Ω])×(V2[V]-V1[V])+V2[V] ……(2) Where: V1 [V]: the first voltage applied to the selected row line AS. V2 [V]: A second voltage applied to the positive input terminal T1. re [Ω]: the resistance value of one resistive element RE corresponding to each column line B. rs [Ω]: the resistance value of one selection resistance element RS corresponding to each column line B. Vout [V]: the output voltage of one operational amplifier OP corresponding to each column line B.

[0049] Since the resistance value re [Ω] of the resistor RE1 is known, the output voltage Vout depends on the resistance value rs [Ω] of the selective resistor RS as shown in formula (2). Therefore, based on the above formula (2), the resistance value rs of each selective resistor RS can be calculated from the output voltage Vout.

[0050] [Effects of element array circuit 2] The element array circuit 2 of this embodiment is also expected to have the same effects as the element array circuit 1 of the first embodiment. That is, since the element array circuit 2 of this embodiment is provided with the switches SW, it is possible to quickly charge the parasitic capacitances parasitic on each column line B. Therefore, it is possible to quickly bring the output voltage Vout caused by the selection resistance elements RS connected to each column line B to a steady state, and it is possible to quickly and accurately measure the output voltage Vout related to the resistance value of each selection resistance element RS.

[0051] Furthermore, the element array circuit 2 of the present embodiment is provided with multiple operational amplifiers, with one operational amplifier OP corresponding to each of the multiple column lines B. Therefore, the output voltage Vout can be measured more quickly than when, for example, each of the multiple column lines B is selectively connected to one operational amplifier OP to measure the output voltage Vout.

[0052] <3. Third embodiment> [Overall configuration example of element array circuit 3] FIG. 6 is a circuit diagram showing a schematic configuration example of an element array circuit 3 according to a third embodiment of the present invention. As shown in FIG. 6, the configuration of the element array circuit 3 is different from that of the element array circuit 1 in FIG. 1 in that a column line selection unit SB is further provided, and the number of each of the switches SW, the capacitance elements CP, and the operational amplifiers OP is set to one. Therefore, in the following description, the column line selection unit SB is mainly described, and the description of the other components is omitted as appropriate. Note that FIG. 6 shows an example in which m row lines A are arranged, but the number of the row lines A can be set arbitrarily. Similarly, FIG. 6 shows an example in which n column lines B are arranged, but the number of the column lines B can be set arbitrarily. In addition, in the example shown in FIG. 6, one set of the switch SW, the capacitance element CP, and the operational amplifier OP is provided for n column lines B, but two or more sets of the switch SW, the capacitance element CP, and the operational amplifier OP may be provided for n column lines B.

[0053] (Column line selection section SB) The column line selection unit SB has a plurality of switches SWB1 (SWB1-1 to SWB1-n) and a plurality of switches SWB2 (SWB2-1 to SWB2-n). Each of the plurality of switches SWB1 (SWB1-1 to SWB1-n) and the plurality of switches SWB2 (SWB2-1 to SWB2-n) can be switched between a conductive state and a non-conductive state. Each of the plurality of switches SWB1 (SWB1-1 to SWB1-n) is provided between a corresponding one of the column lines B (B1 to Bn) and the negative input terminal T2 of the operational amplifier OP. Each of the plurality of switches SWB2 (SWB2-1 to SWB2-n) is provided between a corresponding one of the column lines B (B1 to Bn) and a DC power supply PS2.

[0054] The column line selection unit SB selects one column line B (for convenience, referred to as a selected column line BS) from among the multiple column lines B, and connects the selected column line BS to the negative input terminal T2 of the operational amplifier OP. The column line selection unit SB also connects the other column lines B (for convenience, referred to as unselected column lines BU) other than the selected column line BS to a DC power supply PS2 via multiple switches SWB2 (SWB2-1 to SWB2-n). The operation of the column line selection unit SB is controlled by the control unit CTRL. That is, the switching operations of the multiple switches SWB1 (SWB1-1 to SWB1-n) and the multiple switches SWB2 (SWB2-1 to SWB2-n) in the column line selection unit SB are performed based on commands from the control unit CTRL.

[0055] [Measurement operation in element array circuit 3] In the element array circuit 3, it is possible to measure each of the multiple resistance elements R, for example, in the following manner. Note that the following measurement operation is performed in response to a command from the control unit CTRL.

[0056] Fig. 7 is a flow chart explaining the measurement operation of the element array circuit 3. First, all the switches are set to a non-conductive state (step S301). Specifically, the single switch SW, the multiple switches SWA1 (SWA1-1 to SWA1-m), the multiple switches SWA2 (SWA2-1 to SWA2-m), the multiple switches SWB1 (SWB1-1 to SWB1-n), and the multiple switches SWB2 (SWB2-1 to SWB2-n) shown in Fig. 6 are all set to a non-conductive state (open state).

[0057] Next, a selected row line AS corresponding to the selected resistor element RS to be measured is selected (step S302). This step S302 is performed in the same manner as step 102 in FIG. 2 described in the first embodiment.

[0058] Next, a selected column line BS corresponding to the selected resistive element RS to be measured is selected (step S303). Specifically, the switch SWB1 connected to the selected column line BS to which the selected resistive element RS is connected is turned on, and the selected column line BS is connected to the operational amplifier OP. The switch SWB1 corresponding to the unselected column line BU is maintained in a non-conductive state. Furthermore, the switch SWB2 of the unselected column line BU is turned on, and a second voltage V2 is applied to the unselected column line BU. The switch SWB2 corresponding to the selected column line BS is maintained in a non-conductive state. The example of FIG. 6 shows a state in which the resistive element R(1,1) is selected as the selected resistive element RS. That is, the switch SWB1-1 corresponding to the column line B1 as the selected column line BS is turned on, and the column line B1 is connected to the operational amplifier OP. Meanwhile, the switches SWB1-2 to SWB1-n corresponding to the column lines B2 to Bn as the unselected column lines BU are maintained in a non-conductive state. Furthermore, the switches SWB2-2 to SWB2-n corresponding to the column lines B2 to Bn as the unselected column lines BU are brought into a conductive state, and a second voltage V2 is applied to the column lines B2 to Bn. On the other hand, the switch SWB2-1 corresponding to the column line B1 as the selected column line BS is maintained in a non-conductive state.

[0059] Next, the switch SW is turned on (step S304) to charge the parasitic capacitance of the selected column line BS corresponding to the selected resistive element RS to be measured. Specifically, the switch SWB1-1 corresponding to the column line B1 as the selected column line BS is turned on, and the switch SW is turned on to connect the column line B1 to the output terminal T3 of the operational amplifier OP. FIG. 8 shows a circuit diagram for explaining the charging operation of the parasitic capacitance PC in the element array circuit 3. As shown by the dashed arrow in FIG. 8, by turning on the switch SW, a current flows from the operational amplifier OP1 to the column line B1, and the parasitic capacitance PC of the column line B1 is charged. Here, it is desirable to charge the parasitic capacitance PC of the selected column line BS with the switch SW turned on for a time longer than the time required for the charge of the capacitance element CP to be almost completely discharged. Specifically, it is desirable to charge the parasitic capacitance PC of the selected column line BS by turning on the switch SW for a time longer than five times the product of the capacitance value of the capacitance element CP and the resistance value of the switch SW, i.e., five times the time constant. When the switch SW is turned on for a time longer than five times the product of the capacitance value of the capacitance element CP and the resistance value of the switch SW, 99.3% of the charge of the capacitance element CP is discharged. It is also desirable to charge the parasitic capacitance PC of the selected column line BS by turning on the switch SW for a time longer than five times the product of the capacitance value of the parasitic capacitance PC of the selected column line BS and the sum of the resistance value of the switch SW and the resistance value of the switch SWB corresponding to the selected column line BS (resistance value when the switch SWB is turned on). This is because the parasitic capacitance PC of the selected column line BS is sufficiently charged, and the output voltage Vout caused by the selected resistive element RS can be accurately measured.

[0060] Next, the switch SW is turned off (step S305). This ends the charging of the parasitic capacitance PC of the selected column line BS with the switch SW turned on. At this time, a voltage (V2-V1) that is the difference between the first voltage V1 and the second voltage V2 is applied to the resistance element R(1,1), and a current that depends on the resistance value of the resistance element R(1,1) flows through the resistance element R(1,1), through the column line B1 as the selected column line BS, and toward the capacitance element CP. In contrast, a second voltage V2 is applied to the row lines A2 to Am other than the row line A1 that is the selected row line AS, and to the column line B1. Therefore, of the resistance elements R(1,1) to R(1,m) connected to the column line B1 as the selected column line BS, the voltage applied to the other resistance elements R other than the resistance element R(1,1) as the selected resistance element RS is 0, so that no current flows through the resistance elements R(1,2) to R(1,m). Moreover, the resistive elements R connected to the column lines B2 to Bn as the unselected column lines BU are not connected to the capacitive element CP, and therefore do not affect the capacitive element CP.

[0061] Next, the output voltage corresponding to the selection resistor element RS is measured (step S306). This step S306 is performed in the same manner as step 105 in FIG. 2 described in the first embodiment. In step S306, the output voltage Vout from the output terminal T3 of the operational amplifier OP is measured. As described in the first embodiment, the resistance value rs of the selection resistor element RS can be calculated from the output voltage Vout from the output terminal T3 of the operational amplifier OP based on the formula (1). However, in this embodiment, in the formula (1), cs [F] is read as the capacitance value of the capacitance element CP, rs [Ω] is read as the resistance value of one selection resistor element RS corresponding to the selected column line BS, T [sec.] is read as the elapsed time after the switch SW is turned off, and Vout [V] is read as the output voltage of the operational amplifier OP after T [sec.] has elapsed.

[0062] With the above, the measurement operation in the element array circuit 3 is completed. When measuring the output voltage Vout corresponding to a resistive element R other than the resistive element R(1,1), the above steps S301 to S306 are repeated. However, for the column line B to which the resistive element R already measured is connected, the operation of recharging the parasitic capacitance may be omitted. In addition, in the example of FIG. 6, the first end of the unselected column line BU is connected to the DC power supply PS2 via the switch SWB2, so that the parasitic capacitance of the unselected column line BU can be charged to some extent by the current from the DC power supply PS2. However, a slight error (offset voltage) may occur between the second voltage V2 applied from the DC power supply PS2 and the potential of the negative input terminal T2, and due to this error, the charging of the parasitic capacitance of the unselected column line BU by the current from the DC power supply PS2 may be insufficient. For this reason, in order to perform a measurement with higher accuracy, the switch SW may be turned on and the parasitic capacitance of the selected column line BS may be charged every time the selected column line BS is selected. In this embodiment, the order of steps S302 to S305 may be arbitrarily changed under the conditions that "step S303 precedes step S305" and "step S304 precedes step S305." Specifically, the order of steps S302 to S305 may be S302→S304→S303→S305, S303→S302→S304→S305, S303→S304→S302→S305, S303→S304→S305→S302, S304→S302→S303→S305, S304→S303→S302→S305, or S304→S303→S305→S302. If step S304 precedes step S303, the switch SW is turned on and the switch SWB1 corresponding to the column line B selected as the selected column line BS is turned on, at which point charging of the parasitic capacitance PC of the column line B selected as the selected column line BS begins.Also, in the example of Figure 6, the first ends of the unselected column lines BU are connected to a DC power supply PS2 via a switch SWB2, but as long as the unselected column lines BU are not connected to a capacitive element CP and no current flows between the unselected column lines BU and the capacitive element CP, it does not matter where the first ends of the unselected column lines BU are connected.

[0063] [Effects of element array circuit 3] The element array circuit 3 of this embodiment is also expected to have the same effect as the element array circuit 1 of the first embodiment. That is, since the element array circuit 3 of this embodiment is provided with the switch SW, it is possible to quickly charge the parasitic capacitance of the selected column line BS. Therefore, the output voltage Vout caused by the selected resistor element RS connected to the selected column line BS can be quickly brought to a steady state, and the output voltage Vout related to the resistance value of the selected resistor element RS can be quickly and accurately measured.

[0064] Furthermore, in the element array circuit 3 of this embodiment, a column line selection unit SB is used to selectively connect each of the multiple column lines B to one operational amplifier OP, making it possible to make the circuit more compact than the element array circuit 1 of the above-described embodiment which has multiple operational amplifiers OP.

[0065] <4. Fourth embodiment> [Overall configuration example of element array circuit 4] FIG. 9 is a circuit diagram showing a schematic configuration example of an element array circuit 4 according to a fourth embodiment of the present invention. As shown in FIG. 9, the configuration of the element array circuit 4 is substantially the same as the configuration of the element array circuit 3 according to the third embodiment shown in FIG. 6, except that one resistive element RE is used instead of one capacitive element CP as one conversion element. Note that FIG. 9 shows an example in which m row lines A are arranged, but the number of the row lines A can be set arbitrarily. Similarly, FIG. 9 shows an example in which n column lines B are arranged, but the number of the column lines B can be set arbitrarily. In addition, in the example shown in FIG. 9, one set of a switch SW, a capacitive element CP, and an operational amplifier OP is provided for n column lines B, but two or more sets of a switch SW, a capacitive element CP, and an operational amplifier OP may be provided for n column lines B.

[0066] The measurement operation of the element array circuit 4 of this embodiment can also be performed according to the procedure (steps S301 to S306) described in the third embodiment with reference to FIG. 7. As in the third embodiment, the time during which the switch SW is turned on and the parasitic capacitance PC of the selected column line BS is charged should be longer than five times the product of the capacitance value of the parasitic capacitance PC and the sum of the resistance value of the switch SW and the resistance value of the switch SWB corresponding to the selected column line BS. In addition, in step S306, the output voltage Vout from the output terminal T3 of the operational amplifier OP is measured. As described in the second embodiment, the resistance value rs of the selected resistor element RS can be calculated from the output voltage Vout from the output terminal T3 of the operational amplifier OP based on the formula (2). However, in this embodiment, in the formula (2), re [Ω] is replaced with the resistance value of the resistor element RE, rs [Ω] is replaced with the resistance value of one selected resistor element RS corresponding to the selected column line BS, and Vout [V] is replaced with the output voltage of the operational amplifier OP.

[0067] [Effects of element array circuit 4] The element array circuit 4 of this embodiment is also expected to have the same effect as the element array circuit 3 of the third embodiment. That is, since the element array circuit 4 of this embodiment is provided with the switch SW, it is possible to quickly charge the parasitic capacitance of the selected column line BS. Therefore, the output voltage Vout caused by the selected resistor element RS connected to the selected column line BS can be quickly brought to a steady state, and the output voltage Vout related to the resistance value of the selected resistor element RS can be quickly and accurately measured.

[0068] Furthermore, in the element array circuit 4 of this embodiment, the column line selection unit SB is used to selectively connect each of the multiple column lines B to one operational amplifier OP, making it possible to make the circuit more compact than the element array circuit 2 of the above-described embodiment which has multiple operational amplifiers OP.

[0069] <5. Fifth embodiment> Fig. 10 is a schematic diagram showing a configuration example of a sensor device 101 including an element array circuit of the present invention. As shown in Fig. 10, the sensor device 101 includes a detection unit 10, a calculation unit 20, a storage unit 30, and an output unit 40. The sensor device 101 is, for example, an electromagnetic wave sensor that detects the intensity of a received electromagnetic wave. Note that the configuration of the sensor device 101 shown in Fig. 10 is one example and is not limited thereto.

[0070] The detection unit 10 has at least one of the element array circuits 1 to 4 described in the first to fourth embodiments. The detection unit 10 is, for example, an infrared detection unit that receives infrared rays and outputs a voltage that changes according to the intensity of the received infrared rays. However, the detection unit 10 may also receive electromagnetic waves other than infrared rays (for example, terahertz waves) and output a voltage that changes according to the intensity of the received electromagnetic waves.

[0071] The calculation unit 20 receives the output voltage from the detection unit 10 and performs calculation processing such as converting it into data of desired parameters. The memory unit 30 stores the data generated by the calculation unit 20. The output unit 40 outputs the data generated by the calculation unit 20 to an external device as an electrical signal.

[0072] According to the sensor device 101 of the present embodiment, since the sensor device 101 is provided with the detection section 10 having at least one of the element array circuits 1 to 4, it is possible to quickly and accurately measure the intensity of the received electromagnetic wave.

[0073] In this embodiment, the resistive element R in the detection unit 10 is a light receiving element that converts electromagnetic waves such as infrared rays into an electric signal, but the sensor device 101 of this embodiment is not limited to this case.

[0074] For example, a temperature-sensitive resistor using a thermistor material or a temperature-sensitive conductive ink material may be used as the resistance element R of the element array circuits 1 to 4 in the detection unit 10. Such a temperature-sensitive resistor changes its electrical resistance value depending on whether the temperature is high or low. In this case, the sensor device 101 becomes a temperature sensor capable of detecting the temperature distribution within a surface.

[0075] Alternatively, a pressure-sensitive element using a pressure-sensitive conductive ink material or the like may be used as the resistance element R of the element array circuits 1-4 in the detection unit 10. Such a pressure-sensitive element is configured so that the electrical resistance value changes according to the strength of the pressure applied. A sensor device 101 including a detection unit 10 using a pressure-sensitive element as the resistance element R serves as a pressure sensor capable of detecting pressure distribution within a surface.

[0076] Furthermore, a strain gauge may be used as the resistance element R of the element array circuits 1-4 in the detection unit 10. Such a strain gauge is configured so that its electrical resistance value changes according to the strength of the applied stress. A sensor device 101 including a detection unit 10 using a strain gauge as the resistance element R serves as a strain sensor capable of detecting stress distribution within a plane.

[0077] <6. Variations> Although the present disclosure has been described above by giving several embodiments, the present disclosure is not limited to these embodiments and various modifications are possible.

[0078] For example, in the drawings illustrating the element array circuits 1 to 4 of the first to fourth embodiments, the extending directions of the row lines are parallel to each other, but the present invention is not limited to this, and the row lines may be non-parallel to each other. Furthermore, the row lines are not limited to extending in a straight line, and may extend in a curved line as a whole, or may have a shape including a curved portion or a bent portion. Similarly, in the drawings illustrating the element array circuits 1 to 4, the extending directions of the column lines are parallel to each other, but the present invention is not limited to this, and the column lines may be non-parallel to each other. Furthermore, the present invention is not limited to extending in a direction perpendicular to each other. Furthermore, the column lines are not limited to extending in a straight line, and may extend in a curved line as a whole, or may have a shape including a curved portion or a bent portion.

[0079] Although the element array circuits 1 to 4 in the first to fourth embodiments have a plurality of row lines and a plurality of column lines, the present invention is not limited to this. For example, the element array circuit 3A shown in FIG. 11 has only one row line A. The configuration of the element array circuit 3A is substantially the same as the configuration of the element array circuit 3 (FIG. 8) except that it has only one row line A instead of the plurality of row lines A1 to Am and does not have a row line selection unit SA. Moreover, the element array circuit 1A shown in FIG. 12 has only one column line B. The configuration of the element array circuit 1A is substantially the same as the configuration of the element array circuit 1 except that it has only one column line B instead of the plurality of columns B1 to Bn.

[0080] In addition, the element array circuits 1 to 4 in the first to fourth embodiments have a plurality of resistive elements R as a plurality of impedance elements, but the present invention is not limited to this. For example, the element array circuit 1B shown in FIG. 13 has a plurality of semiconductor elements SC. The configuration of the element array circuit 1B is substantially the same as that of the element array circuit 1, except that the element array circuit 1B has a plurality of semiconductor elements SC instead of the plurality of resistive elements R. The semiconductor element SC is, for example, an element whose electrical characteristics change with temperature, such as a diode. For example, instead of the thermistor film given as an example of the resistive element R in the first embodiment, a diode whose impedance value changes with temperature may be used, and the temperature of the diode may be detected as an output voltage due to the impedance value of the diode, and the present invention may be applied to an electromagnetic wave sensor that detects the intensity of electromagnetic waves such as infrared rays, or a temperature sensor that can detect temperature distribution within a surface.

[0081] In addition, the element array circuits 1 to 4 in the first to fourth embodiments have one or more capacitive elements CP or one or more resistive elements RE as one or more conversion elements, but the present invention is not limited to this, and may employ, for example, one or more semiconductor elements. For example, as in the element array circuit 1C shown in FIG. 14, a plurality of diodes D may be used as a plurality of conversion elements. In the example shown in FIG. 14, a current depending on the resistance value of each of the resistive elements R(1,1) to R(1,n) flows through each of the resistive elements R(1,1) to R(1,n), flows through each of the column lines B1 to Bn, and flows through each of the diodes D1 to Dn. The current flowing through each of the column lines B1 to Bn is converted into a voltage by each of the diodes D1 to Dn according to the current-voltage characteristics of each of the diodes D1 to Dn, and is output as an output voltage Vout from the output terminal T3 of the operational amplifiers OP1 to OPn corresponding to each of the resistive elements R(1,1) to R(1,n).

[0082] It should be noted that the effects described in this specification are merely examples and are not limiting, and other effects may also be obtained. [Explanation of symbols]

[0083] 1...element array circuit, A (A1 to Am)...row lines, B (B1 to Bn)...column lines, CTRL...control section, CP (CP1 to CPn)...capacitive elements, OP (OP1 to OPn)...operational amplifiers, PS1, PS2...DC power supplies, R (R(1,1) to R(m,n))...resistive elements, SA...row line selection section, SW (SW1 to SWn)...switches.

Claims

1. one or more first wirings, a plurality of second wirings each extending in a direction different from each of the one or more first wirings, a plurality of impedance elements each connected to both one of the one or more first wirings and one of the plurality of second wirings, one or more operational amplifiers each having a positive input terminal, a negative input terminal connectable to one of the plurality of second wirings, and an output terminal, one or more conversion elements each connected to the negative input terminal and the output terminal of a corresponding one of the one or more operational amplifiers, and converting a current flowing through one of the plurality of second wirings connected to the negative input terminal into a voltage, one or more switching portions each connected in parallel to one of the one or more conversion elements between the negative input terminal and the output terminal of a corresponding one of the one or more operational amplifiers and capable of taking a conductive state and a non-conductive state, comprising an element array circuit.

2. The element array circuit according to claim 1, further comprising a control unit that performs control to switch one of the one or more switching portions corresponding to the negative input terminal to a non-conductive state after charging a parasitic capacitance parasitic on one of the plurality of second wirings connected to the negative input terminal of a corresponding one of the one or more operational amplifiers. The control unit performs the charging of the parasitic capacitance in the control by bringing one of the one or more switching portions corresponding to the negative input terminal into a conductive state and conducting one of the plurality of second wirings connected to the negative input terminal and the output terminal. The element array circuit according to claim 1.

3. After charging the parasitic capacitance, the control unit switches the one switching unit corresponding to the negative input terminal among the one or more switching units to the non-conducting state, and then measures the output voltage from the output terminal caused by one of the plurality of impedance elements connected to both one of the one or more first wirings and one of the plurality of second wirings connected to the negative input terminal. The element array circuit according to claim 2.

4. The element array circuit further includes a second wiring selection unit that selects one of the plurality of second wirings and connects it to the negative input terminal. The element array circuit according to claim 1.

5. After charging the parasitic capacitance parasitic on one of the plurality of second wirings connected to the negative input terminal of the corresponding one of the one or more operational amplifiers, the control unit performs control to switch the one switching unit corresponding to the negative input terminal among the one or more switching units to the non-conducting state. The control unit performs the charging of the parasitic capacitance in the control by making the one switching unit corresponding to the negative input terminal among the one or more switching units in the conducting state and making one of the plurality of second wirings connected to the negative input terminal and the output terminal in the conducting state. The time for charging the parasitic capacitance with the one switching unit in the conducting state is longer than five times the product of the capacitance value of the parasitic capacitance and the sum of the resistance value of the one switching unit and the resistance value of the second wiring selection unit. The element array circuit according to claim 4.

6. The one or more operational amplifiers are a plurality of operational amplifiers. The one or more switching units are a plurality of switching units. The one or more conversion elements are a plurality of conversion elements. Each of the plurality of operational amplifiers is connected to a corresponding one of the plurality of second wirings. 2 of the wirings. Each of the plurality of switching units is connected to a corresponding one of the plurality of operational amplifiers, Each of the plurality of conversion elements is connected to a corresponding one of the plurality of operational amplifiers The element array circuit according to claim 1.

7. After charging a parasitic capacitance parasitic on one of the plurality of second wirings connected to the negative input terminal of a corresponding one of the plurality of operational amplifiers, control is performed to switch one of the plurality of switching units corresponding to the negative input terminal to a non-conductive state, A control unit, further comprising: The control unit performs the charging of the parasitic capacitance in the control by making one of the plurality of switching units corresponding to the negative input terminal conductive and making one of the plurality of second wirings connected to the negative input terminal conductive to the output terminal. By making it,[[]] The time for charging the parasitic capacitance with one of the plurality of switching units corresponding to the negative input terminal in a conductive state is longer than five times the product of the capacitance value of the parasitic capacitance and the resistance value of the one switching unit The element array circuit according to claim 6.

8. The one or more first wirings are a plurality of first wirings, Each of the plurality of impedance elements is connected to both one of the plurality of first wirings and one of the plurality of second wirings The element array circuit according to claim 1.

9. A plurality of first wirings, One or more second wirings each extending in a direction different from each of the plurality of first wirings, A plurality of impedance elements each connected to both one of the plurality of first wirings and one of the one or more second wirings, One or more operational amplifiers having a positive input terminal, a negative input terminal connectable to one of the one or more second wirings, and an output terminal, Each is connected to the negative input terminal and the output terminal of a corresponding one of the one or more operational amplifiers, and converts a current flowing through one of the one or more second wirings connected to the negative input terminal into a voltage; Each is connected in parallel with one of the one or more conversion elements between the negative input terminal and the output terminal of a corresponding one of the one or more operational amplifiers, and can take a conductive state and a non-conductive state; comprising an element array circuit.

10. A control unit that performs control to switch, after charging a parasitic capacitance parasitic on one of the one or more second wirings connected to the negative input terminal of a corresponding one of the one or more operational amplifiers, one of the one or more switching units corresponding to the negative input terminal to a non-conductive state; The control unit performs charging of the parasitic capacitance in the control by bringing one of the one or more switching units corresponding to the negative input terminal into a conductive state and conducting one of the one or more second wirings connected to the negative input terminal and the output terminal. The element array circuit according to claim 9.

11. After performing charging of the parasitic capacitance, the control unit switches one of the one or more switching units corresponding to the negative input terminal to the non-conductive state, and then measures an output voltage from the output terminal due to one of the plurality of impedance elements connected to both one of the plurality of first wirings and one of the one or more second wirings connected to the negative input terminal. The element array circuit according to claim 10.

12. The time for charging the parasitic capacitance with one of the one or more switching units corresponding to the negative input terminal in a conductive state is longer than five times the product of the capacitance value of the parasitic capacitance and the resistance value of one of the one or more switching units corresponding to the negative input terminal. The element array circuit according to claim 10.

13. The one or more conversion elements are one or more capacitive elements, The time for charging the parasitic capacitance with the one switching part corresponding to the negative input terminal among the one or more switching parts in a conductive state is longer than five times the product of the capacitance value of one of the one or more capacitive elements corresponding to the negative input terminal and the resistance value of the one switching part corresponding to the negative input terminal among the one or more switching parts The element array circuit according to claim 2 or claim 10.

14. Each of the one or more conversion elements is a capacitive element, a first resistive element, or a first semiconductor element The element array circuit according to claim 1 or claim 9.

15. Each of the plurality of impedance elements is a second resistive element or a second semiconductor element The element array circuit according to claim 1 or claim 9.

16. A first wiring, A second wiring extending in a direction different from that of the first wiring, An impedance element connected to both the first wiring and the second wiring, An operational amplifier having a positive input terminal, a negative input terminal connectable to the second wiring, and an output terminal, A control unit that measures the output voltage from the output terminal due to the impedance element after charging the parasitic capacitance parasitic on the second wiring connected to the negative input terminal Comprising Element array circuit.

17. An electromagnetic wave sensor having the element array circuit according to claim 1, claim 9, or claim 16.

18. A temperature sensor having the element array circuit according to claim 1, claim 9, or claim 16.

19. A strain sensor having the element array circuit according to claim 1, claim 9, or claim 16.

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