Frame synchronization detection using rate adaptation

Abstract

To provide a method and wireless device for performing frame synchronization detection with a non-integer sample rate.SOLUTION: A communication interface of a wireless device comprises an RF circuit, which receives a packet over a channel at a first frequency and generates a sampled stream of data at a first sample rate corresponding to the first frequency. A data resampler comprises a re-timer engine to determine, using a fractional ratio between the first sample rate and a crystal oscillator (XO)-divided sample rate, re-timer values including differences between pulses of a pseudo-clock corresponding to the XO-integer-divided sample rate and closest corresponding pulses of a clock corresponding to the first sample rate. A correlation (circuit) uses re-sampled data values, the pseudo-clock and the re-timer values to match an expected data pattern to a corresponding data pattern detected in a frame delimiter of the packet.SELECTED DRAWING: Figure 1B

Description

[Technical field]

[0001] This disclosure relates to wireless networks, and more particularly, to frame synchronization detection with rate adaptation between wireless devices. [Background technology]

[0002] Personal Area Networks (PANs), such as Bluetooth® (BT), Bluetooth® Low Energy (BLE), ZigBee®, Infrared, etc., provide wireless connectivity for a variety of personal, industrial, scientific and medical applications. PANs generally use packet-based protocols and have an architecture that includes a Central Device (CD) and Peripheral Devices (PDs). A CD can communicate with multiple PDs.

[0003] For example, some PANs based on BLE technology have a similar communication range to BT networks, but with significantly lower power consumption and cost. Furthermore, BLE devices often remain in sleep mode and transition to active mode when data communication is to occur. The BLE protocol also supports mesh networks, in which data can flow through multiple paths and does not rely on a fixed hierarchy of devices, and often the same device can act as a CD or a PD, depending on the particular network situation and topology.

[0004] In addition, some PANs are used in wireless devices (e.g., CDs) contained within or associated with locking mechanisms of enclosures (e.g., homes, vehicles, garages, sheds, etc.) to provide secure keyless access, also referred to as keyless entry, to a person possessing a locked PD. The locked PD (which may be, for example, a mobile device such as a smartphone) may transmit a specific data pattern within the frame delimiter of a packet. The wireless CD device associated with an enclosure may then perform frame synchronization detection and verify that the specific data pattern matches an expected data pattern that is used in part to provide a level of security for keyless entry. [Brief description of the drawings]

[0005] [Figure 1A] FIG. 1 is a block diagram of a system that can be used for frame synchronization detection with rate adaptation between a wireless device acting as a CD and a wireless device acting as a PD in accordance with an example embodiment. [Figure 1B] 1B is a simplified block diagram of a communication interface of the CD-based wireless device of FIG. 1A according to at least one embodiment. [Diagram 2] 1 is a flow diagram of a method for frame synchronization detection with rate adaptation in accordance with at least one embodiment. [Figure 3A] FIG. 2 is a block diagram of a data resampler circuit of a CD in accordance with at least one embodiment. [Figure 3B] 1 is a block diagram of a retimer engine of a data resampler circuit in accordance with at least one embodiment. [Figure 4] 1 is a graph illustrating retiming between a crystal oscillator (XO) divided sample rate and a local oscillator (LO) based sample rate in at least one embodiment. [Diagram 5] 1 is a flow diagram of a method for frame synchronization detection with rate adaptation in accordance with various embodiments. [Figure 6] 1 is a flow diagram of a method for frame synchronization detection with rate adaptation in accordance with at least one embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0006] The following description sets forth numerous specific details, such as examples of specific systems, devices, components, methods, etc., to provide a good understanding of various embodiments of frame synchronization detection between wireless devices associated with a PAN. The disclosed principles may be generally applied to non-Gaussian Frequency Shift Keying (GFSK) modulation, even to such modulations without frequency. Frame synchronization detection may be understood as detecting a frame delimiter, also referred to as a start frame delimiter (SFD), which identifies or signals in a network packet that data continues within a frame of the packet. In this case, some packets may include a frame delimiter (or SFD) without a payload, and in particular, the frame delimiter itself is used primarily for security purposes, for example, to perform verification of the PD wireless device. Thus, the data of a packet referenced herein may simply refer to a preamble and frame delimiter or may refer to a frame or payload of data within the packet.

[0007] In certain PAN devices, frame sync detection may be used essentially to estimate round trip time (RTT), which may be used in BLE to position. One example of using data positioning is BLE's High Accuracy Distance Measurement (HADM) used for keyless entry, where a BLE device (such as a mobile phone) acts as a digital car key. For example, the frame sync pattern defined in BLE may be used to estimate the RTT of a packet and estimate the distance from the housing. Thus, HADM (and related methods) may be understood as a phase-based ranging technique, which may be enhanced by physical layer (PHY) security features to perform secure distance measurements between two BT-enabled devices. BLE is an example of a protocol that uses frame sync detection, which may be applicable to other contexts or protocols where distance estimation may be required to perform ranging or localization.

[0008] Frame sync detection is best performed at a sample rate that is a simple multiple of the data symbol rate, e.g., 4, 6, 12, etc., typically 1 or 2 Megabits per second (Mbps), which are typically crystal oscillator (XO) frequency division (or sampling) rates, e.g., 24 Megahertz (MHz), 32 MHz, or 48 MHz. Subsequent processing of the data symbols may be straightforward when performed at the well-known XO integer division sample rate, and the sync data patterns (e.g., of digital "0s" and "1s") can be more easily correlated using bit decisions according to Boolean logic. Alternatively, signed soft symbols may be used to obtain more accurate results, in which case correlation can be described as a large number of additions and subtractions. Thus, in practice, the time of arrival (ToA) estimate of the sync frame is only as accurate as the nearest edge of the receiver clock (coarse timing) or as accurate as a fraction of the period of the receiver clock (fractional timing). Some disadvantages of this method include that receivers operating at XO integer fractional sample rates experience significant radio interference problems, for example in the form of clock spurs, which can cause receiver non-detection and affect, for example, receiver sensitization.

[0009] Therefore, to avoid these radio interference problems, the receiver of the wireless device can instead use a sample rate that is divided down from the local oscillator (LO) frequency. The LO frequency is most often (but not always) a non-multiple of the modulation bit rate, e.g., the XO integer division sample rate. While this method avoids some receiver non-detection problems, this solution also requires rate adaptation between the sample rate derived from the LO frequency and the XO integer division sample rate. This type of adaptation typically uses a first-in-first-out (FIFO) buffer to transfer data between the domains. This solution is not entirely satisfactory because ToA measurements require accurate and controllable latency through the FIFO buffer.

[0010] To eliminate the drawbacks experienced by rate adaptation when resampling packets received at the LO-based (or original) sample rate to the XO integer-divided sample rate, the FIFO buffer may be omitted. In this scenario, the data resampler circuit may use pulse removal (e.g., swallowing) or pulse insertion to form a clock that, on average, approximates a rate that is a multiple of the data symbol rate. The approximation of the desired multiple of the data symbol rate may be, for example, 8, 6, or 4 times the data symbol rate and the divided XO rate. For example, the symbol rate may be 1 MHz and the XO frequency used may be 24 MHz, while the average rate approximates 6 MHz or approximates the XO sample rate divided by 4. Thus, the XO integer-divided sample rate may average a fraction of the frequency of the integer-divided XO sample rate. These values ​​are provided by way of example only for illustration.

[0011] According to some embodiments, a receiver wirelessly receives packets over a channel at a first frequency and generates a sampled data stream from the packets at a first sample rate corresponding to the first frequency. In at least some embodiments, the data resampler circuit includes a retimer engine that uses a fractional conversion ratio between the first sample rate and a crystal oscillator (XO) integer-divided sample rate to determine a plurality of retimer values ​​comprising a difference between a pulse of a pseudo-clock corresponding to the XO integer-divided sample rate and a nearest corresponding pulse of a clock corresponding to the first sample rate. The resampler circuit may further include a time shift circuit that resamples resampled data values ​​of the sampled data stream associated with positions of the plurality of retimer values. In these embodiments, a correlation circuit coupled to the resampler circuit may be configured to use the resampled data values, the pseudo-clock, and the plurality of retimer values ​​to match expected data patterns to corresponding data patterns detected in a frame delimiter of the packet. Additional implementation details are described with reference to the current drawings.

[0012] The present disclosure includes many advantages because the correlation circuitry may be enhanced to still perform correlations associated with frame sync detection, despite the fact that the data is not actually resampled at the XO integer divided sample rate. Instead, as described in more detail below, a pseudo clock from the resampled data may be used to correlate the resampled data values ​​to the timing of the LO sample rate. In some embodiments, the pseudo clock is generated by removing (e.g., swallowing) occasional pulses from the faster LO divided sample rate that correspond closely to pulses of the XO divided clock. By retaining these precise retimer values, the correlation circuitry may more accurately correlate peaks of the incoming data (not fully resampled at the XO integer divided sample rate) to peaks of the expected data pattern. For example, the correlation circuitry 148 may detect a peak in the incoming data pattern, locate the clock edge or retimer value associated with the peak, and use this retimer value (associated with the peak) to align with the expected data pattern. In this way, the precise timing associated with the LO divided sample rate is preserved, while subsequent correlations for detection of the peaks are performed using the XO divided pseudo data signal rate. Furthermore, the receiver can operate at non-integer sample rates (eg, non-XO integer divided sample rates) to avoid the radio interference problems mentioned above.

[0013] 1A is a block diagram of a system 100 that can be used for frame synchronization detection with rate adaptation between a wireless device 101 acting as a CD and a wireless device 150 acting as a PD, according to an example embodiment. The system 100 may include, for example, a secure enclosure 50 secured with a locking mechanism 60, and the wireless device is configured to gain access to the secure enclosure via the locking mechanism 60. The secure enclosure 50 may be, for example, a vehicle, a building, a house, a garage, a shed, a vault, etc. The secure enclosure 50 may be, for example, a computer system, industrial equipment, or other item requiring secure access via the locking mechanism 60, which may be a digital locking mechanism. In some embodiments, the locking mechanism 60 is integrated with the wireless device 101.

[0014] In various embodiments, wireless device 150 may be any one of a number of peripheral wireless devices PD1(150A)...PDN(150N), and wireless device 101 may be configured to communicate with some or all of the peripheral wireless devices PD1(150A)...PDN(150N). In different embodiments, wireless device 150 may be a mobile device, such as a cell phone, smartphone, pager, electronic walkie-talkie, tablet, etc. In these embodiments, wireless device 150 may be configured to gain access to secure enclosure 50 by transmitting data that includes a frame delimiter and an enclosed frame.

[0015] In at least some embodiments, the wireless device 101 includes, but is not limited to, a transmitter 102 or TX (e.g., a PAN transmitter), a receiver 104 or RX (e.g., a PAN receiver), a communication interface 106, one or more antennas 110, a memory 114, one or more input / output (I / O) devices 118 (e.g., a display screen, touch screen, keypad, etc.), and a processor 120. All of these components may be coupled to a communication bus 130.

[0016] In some embodiments, a separate antenna is used for each of the transmitter 102 and receiver 104, and therefore the antenna 110 is shown for ease of explanation. In at least some embodiments, the memory 114 may include storage for storing instructions executable by the processor 120 and / or data generated by the communication interface 106. In various embodiments, one or more antennas described herein (e.g., antenna 110) may be used in various devices for PAN-based frequency bands, e.g., Bluetooth® (BT), BLE, Wi-Fi®, ZigBee®, Z-wave®, etc.

[0017] In some embodiments, the communication interface 106 is integrated with the transmitter 102 and receiver 104, e.g., as a front end of the wireless device 101. The communication interface 106 may coordinate to request / receive packets from the peripheral wireless device 150 when instructed by the processor 120. The communication interface 106 may further process data symbols received by the receiver 104 so that the processor 120 can perform further processing, including verifying correlations between phase-based samples of data values ​​obtained from a frame of packets and expected data patterns as part of a security protocol, as described herein.

[0018] 1B is a simplified block diagram of the communication interface 106 of the wireless device 101 of FIG. 1A according to at least one embodiment. In at least some embodiments, the communication interface 106 includes a baseband channel estimator 134, which is used to estimate, and thus detect, the channel, enabling the receiver 104 to receive packets over the channel. Estimating the channel may mean, for example, estimating channel state information (CSI) and a received signal strength indication (RSSI) for each channel. The CSI may include a detailed channel impulse response (e.g., including channel characteristics) with amplitude and phase information. The receiver 104 may adjust the rate of sampling channel characteristics by the baseband channel estimator 134. Thus, the receiver 104 or the baseband channel estimator 134 may include a local oscillator (LO), which samples at a specific sampling rate for a particular channel, which is often a non-integer multiple of the sample rate.

[0019] In various embodiments, the communication interface 106 includes RF circuitry 140, although the RF circuitry 140 described herein may also be coupled to the communication interface 106 and thus located elsewhere within the front end of the wireless device 101. In at least some embodiments, the RF circuitry 140 includes (or is coupled to) a crystal oscillator (XO) 142 and includes a data resampler circuit 144 and a correlation circuit 148. The data resampler circuit 144 may include a retimer engine 154 and generate (or cause to be generated) a retimer value used by the correlation circuit 148 to perform frame synchronization detection. The correlation circuit 148 may also include a fractional time estimator 149.

[0020] While the XO 142 may provide the clock and manage sampling and processing in an XO-based design, the direct conversion of data to and from the frequency domain by XO has the drawbacks discussed above. In some embodiments, the RF circuitry is implemented as a programmable processor, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a processing unit (e.g., a CPU or GPU), or other microprocessor device that may include a combination of circuit-based hardware, logic, firmware, and / or software.

[0021] In various embodiments, the data resampler circuit 144 is configured to resample the input data, which has already been sampled by the receiver 104 at a sample rate derived from the LO frequency, to a pseudo sample rate derived from the XO frequency. This pseudo sample rate derived from the XO frequency may be governed by a pseudo clock, which is generated to correspond, on average, to the XO integer division frequency, e.g., 4 MHz, 6 MHz, 12 MHz, 24 MHz, etc. The correlation circuit 148 may use the pseudo clock to match expected data patterns to corresponding data patterns detected in the frame delimiters of the packets, for example, by frame sync detection.

[0022] 2 is a flow diagram of a method 200 of frame synchronization detection with rate adaptation in accordance with at least one embodiment. Method 200 may be performed by processing logic that may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions operating or executed on a processing device), or a combination thereof. In some embodiments, method 200 is performed by communication interface 106, and potentially by a combination of communication interface 106 and processor 120.

[0023] In operation 210, the data of the packet is sampled at a local oscillator (LO) sample rate specific to the channel to be estimated, as described with reference to Figures 1A-1B. This LO sample rate is not specific to any XO integer division frequency. As an illustrative example only, assume that the LO sample rate is 6.42 MHz.

[0024] In operation 220, the data resampler circuit 144 resamples the data in a manner that increases (interpolates) or decreases (decimates) the data sample rate. The sample rate of the data output from the data resampler circuit 144 can then be, on average, the XO integer division sample rate and thus correspond to a "pseudo" clock at the XO integer division frequency. As an example for illustrative purposes only, assume that the XO integer division sample rate is 6.0 MHz and thus slightly slower than the LO division sample rate. Figure 4, described in detail below, shows both the non-integer clock corresponding to the LO division sample rate and the XO integer division clock corresponding to the XO integer division sample rate.

[0025] In operation 220, the data resampler circuit 144 (e.g., the retimer engine 154) may determine a retimer value using a fractional rate between the LO divided sample rate and the XO integer divided sample rate, e.g., as the difference between a pulse of the pseudo clock corresponding to the XO integer divided sample rate and the nearest corresponding pulse of the clock corresponding to the LO divided sample rate. These retimer values ​​may be provided to the correlation circuit 148.

[0026] Also, in operation 220, the data resampler circuit 144 may resample the data values ​​of the sampled data stream associated with the position of the retimer value and may provide these resampled data values ​​to the correlation circuit 148. The functions of the data resampler circuit 144, including the generation of a pseudo clock, are described in further detail below.

[0027] In operation 230 , data (eg, resampled data values) at the XO integer-divided sample rate is provided to correlation circuit 148 .

[0028] In operation 240, a correlation between the data pattern in the frame delimiter of the packet and the expected data pattern from the trusted peripheral device (PD) is performed by the correlation circuit 148. More specifically, the correlation circuit 148 may use the resampled data values, the pseudo clock and the retimer value to match the expected data pattern to the corresponding data pattern detected in the frame delimiter. Furthermore, in at least some embodiments, the fractional time estimator 149 further establishes the time of arrival (ToA) of the frame delimiter. The resolution of the fractional time is typically much better than the period of the clock, which in this case is the average period of the pseudo clock.

[0029] FIG. 3A is a block diagram of a data resampler circuit 344 of a CD according to at least one embodiment. FIG. 4 is a graph showing retiming between a crystal oscillator (XO) divided sample rate and a local oscillator (LO) based sample rate in at least one embodiment, which is also referred to. The timing and data generated by the data resampler circuit 344 may be provided to the correlation circuit 148 (FIG. 2B). In at least one embodiment, the data resampler circuit 344 is the data resampler circuit 144 of FIG. 2B.

[0030] In at least some embodiments, the data resampler circuit 344 includes the LO clock 302, the buffer 305, the phase locked loop (PLL) 317, the pseudo clock generator 320, the time shift circuit 325, and the retimer engine 354. In some embodiments, the PLL 317 is located in another portion of the communication interface 106 or at the front end of the wireless device 101 and need not be incorporated within the data resampler circuit 344, for example. In at least one embodiment, the retimer engine 354 is the retimer engine 154 of FIG. 2B.

[0031] In various embodiments, the buffer 305 includes a delay line and samples the input data (e.g., the sampled data stream from the receiver 104) using a local oscillator (LO) integer division clock 302 that matches the frequency of the LO used by the receiver 104. In these embodiments, the buffer 305 outputs data of the delayed sampled data stream corresponding to a first frequency derived from the LO by a simple integer divider, which may be specific to the channel over which the packet is estimated to be received, as described above. This delay and further sampling allows other components to generate different timing and data values ​​corresponding to the next sampled stream, as described below. FIG. 4 shows the curves associated with the non-integer clock corresponding to the LO integer division sample rate, with the plus signs (+) marking the original samples saved from the sampling performed by the receiver 104.

[0032] In at least some embodiments, the retimer engine 354 tracks the data timing relationship between the input sampling rate (of the input data) and the XO integer division sample rate. Using the example from before, the fractional ratio is the fractional difference between 6.42 Msps and 6.00 Msps, which is -0.0660, e.g., the distance between the first two samples of the graph in FIG. 4. The retimer engine 354 may then use this fractional ratio to determine multiple retimer values ​​that are the difference between a pulse of the pseudo clock corresponding to the XO integer division sample rate and the closest corresponding pulse of the clock corresponding to the next sample rate, e.g., the LO clock 302. For purposes of illustration following the example of FIG. 4, the retimer value is the abscissa number (along the x-axis of the graph) that corresponds to the sample position in the next sampled stream. In some embodiments, the retimer value can be understood to be the clock edge that is adapted from the LO clock 302 without the pulse being removed (or swallowed). Thus, the retimer value may estimate the time shift or time interpolation required for sampled data at the first sample rate to output data at the XO integer division sample rate. In the graph of Figure 4, the retimer value is rounded off for simplicity, but in practice may be held to many decimal places (e.g., up to 12). In these embodiments, the retimer engine 354 provides the retimer value to the time shift circuit 325, and the retimer value is described below as equal to a fractional interpolation command to the time shift circuit 325.

[0033] In some embodiments, the pseudo clock generator 320 is configured to generate the pseudo clock described above. The PLL 317 may generate a PLL clock that is derived based on, for example, the LO clock 302. The PLL 317 may be configured to use the LO clock 302 as an input reference, where the PLL 317 locks the frequency and phase of the LO clock 302 to provide a PLL-based clock that is as accurate as possible at the non-integer sample rate.

[0034] In these embodiments, the pseudo clock generator 320 receives the LO integer-divided clock and removes (e.g., swallows) a pulse from the LO integer-divided clock in response to each removal command from the retimer engine 354, as described below. In these embodiments, the pseudo clock generator 320 uses the removed pulse (or the swallowed pulse, as described in the art) to further generate a pseudo clock as the PLL clock, where the pseudo clock corresponds, on average, to the XO integer-divided sample rate.

[0035] In at least some embodiments, the retimer engine 354 also detects one retimer value of the multiple retimer values ​​that meets (e.g., at least satisfies or exceeds) a threshold value, e.g., that indicates that there is a crossover between retimer values ​​over time that are approximately integer values ​​(e.g., unity value ("1")) minus fractional ratio values. In response to such detection, the retimer engine 354 can trigger a removal command (e.g., a pulse swallow command) to the pseudo clock generator 320. As shown in FIG. 4, the retimer value crossover exists between -0.490 and +0.440, indicating a jump of approximately +1.

[0036] More specifically, FIG. 3B is a block diagram of a retimer engine 354 of the data resampler circuit 344 according to at least one embodiment. In at least one embodiment, the retimer engine 354 includes a register 360 that stores one retimer value of a plurality of retimer values. In some embodiments, the register 360 can buffer the plurality of retimer values. The retimer engine 354 may further include an adder 352 to add a fractional conversion ratio to the retimer value to determine a fractional retimer value. The retimer engine 354 may further include a comparator 364 that compares the fractional retimer value to a predetermined negative decimal value, the predetermined negative decimal value being, for example, −0.5, although other values ​​such as −0.4 or −0.6 are also contemplated. When using −0.5 as the predetermined negative decimal value, the retimer value may swing between −0.5 and +0.5 (see FIG. 4). The retimer engine 354 may further include a switch 366 configured to add a value of one ("1") to the fractional retimer value to generate a positive retimer value in response to the fractional retimer value being less than or equal to a predetermined negative decimal value. A voltage source 370, such as a charge pump, may also be included to perform the addition of the one value. In these embodiments, the comparator 364 is also configured to trigger a removal command to the pseudo clock generator 320 in response to the one value being added, e.g., in response to the fractional retimer value being less than or equal to a predetermined negative decimal value.

[0037] With further reference to FIG. 3A, in various embodiments, the time shift circuit 325 is configured to resample (e.g., via interpolation or decimation) data values ​​of the incoming sampled data stream based on a retimer command, e.g., a retimer value that functions as a fractional interpolation command. To perform this function, the time shift circuit 325 may receive a retiming value from the retimer engine 354 and a pseudo clock from the pseudo clock generator 320. As shown in FIG. 4, the dashed lines correspond to sample positions (e.g., pulses) of the pseudo clock provided by the pseudo clock generator 320, on average at the XO integer division sample rate. The "X" positions can be understood as the resampled data values ​​that the time shift circuit 325 has determined at one of the pulses (or clock edges) of the sampled data stream (having a first sample rate) from the nearest corresponding position (or pulse) of the pseudo clock (see the horizontal interpolation lines for the X positions). In some embodiments, the time shift circuit 325 includes a plurality of digital fractional delay filters that resample (or interpolate) data values ​​based on corresponding ones of the plurality of retimer values ​​using a pseudo clock. Each fractional delay filter may use, for example, one or more Farrow structures.

[0038] 5 is a flow diagram of a method 500 of frame synchronization detection with rate adaptation in accordance with various embodiments. Method 500 may be performed by processing logic that may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions operating or executed on a processing device), or a combination thereof. In some embodiments, method 500 is performed by RF circuitry 140 and potentially by a combination of communications interface 106 and processor 120 (FIG. 1B).

[0039] In operation 510, the processing logic performs a data signal rate conversion and determines a retimer value. More specifically, the data resampler 144 may determine a fractional conversion ratio between the first sample rate of the sampled data stream (e.g., corresponding to the LO clock 302) and the XO integer division sample rate. In the example of FIG. 4, this was illustrated as being −0.0660 (rounded to −0.07) by way of example only. The processing logic (e.g., the retimer engine 354) may further determine a number of retimer values ​​(e.g., as shown in FIG. 4) including the difference between a pulse of the pseudo clock corresponding to the XO integer division sample rate and the nearest corresponding pulse of the clock corresponding to the first sample rate.

[0040] In operation 520, the processing logic obtains soft frequency samples based on the in-phase quadrature (IQ) values ​​of the resampled data values. The soft frequency samples may capture the frequency deviations in the sampled data values, e.g., symbols that are still to be resolved as 1 or 0 bits. More specifically, the time shift circuit 325 (or similar logic) may resample the data values ​​of the sampled data stream associated with the positions of the multiple retimer values. In some embodiments, the delay line of the buffer 305 may convert the set of unrotated in-phase quadrature (IQ) inputs of the sampled data stream to phase to generate a set of phase samples and determine phase differences between adjacent phase samples of the multiple phase samples of the first data symbol. The processing logic may further subtract each phase difference of the first data symbol from a corresponding phase difference of a second data symbol adjacent to the first data symbol to generate multiple inter-symbol differences. The processing logic may further accumulate the multiple inter-symbol differences across the multiple sequentially sampled symbols for the first data symbol as soft frequency samples.

[0041] At operation 530, processing logic may estimate oversampled frequency samples of the soft frequency samples at a multiple of the symbol rate of the pseudo clock, e.g., convert the soft samples to the domain of the pseudo clock. In some embodiments, the symbol rate multiple may be 2x, 4x, 6x, 8x, etc., the symbol rate of the pseudo clock.

[0042] At operation 540, processing logic may buffer the oversampling frequency samples to a constant number of symbols equal to the symbols of the frame sync pattern of the frame delimiter. In some embodiments, the frame sync pattern is 32 symbols, so all 32 x 6 equidistant samples may be buffered and used to correlate against the expected data pattern of the frame delimiter when operating at a multiple of 6 of the pseudo clock. 32 symbols are suggested as an example, but other numbers of symbols are contemplated.

[0043] In operation 550, processing logic (e.g., correlation circuit 148 of FIGS. 1B and 3A) may correlate the buffered oversampled frequency samples to expected frequency symbols of the expected data pattern to detect correlation peaks. For example, in some embodiments, the processing logic detects peaks in the resampled data values ​​and within a threshold of a corresponding peak of the expected data pattern according to mathematical operations including multiplication and addition. The processing logic may further determine one retimer value of the multiple retimer values ​​that most closely corresponds in time to the detected peak. In some embodiments, the processing logic further modifies the position of the peak using at least the retimer value and correlates (including aligns) the peak at the modified position to the corresponding peak.

[0044] In some embodiments, to modify the position of the peak, processing logic determines a numerical fractional value associated with a period of the pseudo clock. Processing logic may further determine a retimer fractional value that corresponds to an edge of the detected peak using the clock and based on the retimer value. Processing logic may further combine the numerical fractional value and the retimer fractional value with the position to generate a modified position of the peak. In this context, position refers to a timing event defined by an edge of the pseudo clock.

[0045] In various embodiments, if the peak at the corrected position meets a second threshold (e.g., closer compared to the first threshold) or if the sampled data fits to a peak of the curve of the expected data pattern within a predetermined fractional resolution, the processing logic may create a sync found event and store a retimer value corresponding to the corrected peak position for the sync found event. The fractional part of the correlation may be obtained by fitting a function to the value of the corrected peak and to two adjacent sample values ​​of the sampled data stream. Additionally or alternatively, other logic, circuits and / or algorithms may be used to refine the exact position determined for the peak.

[0046] 6 is a flow diagram of a method of frame synchronization detection with rate adaptation according to at least one embodiment. Method 600 may be performed by processing logic that may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions operating or executed on a processing device), or a combination thereof. In some embodiments, method 600 is performed by RF circuitry 140 and potentially by a combination of communications interface 106 and processor 120 (FIG. 1B).

[0047] At operation 610, the receiver 104 wirelessly receives a packet over a channel at a first frequency.

[0048] In operation 620, the receiver 104 generates a sampled data stream from the packet at a first sample rate corresponding to the first frequency.

[0049] In operation 630, the processing logic (e.g., the data resampler circuit 344) uses a fractional ratio between a first sample rate and a crystal oscillator (XO) integer-divided sample rate to determine a number of retimer values ​​comprising a difference between a pulse of a pseudo clock corresponding to the XO integer-divided sample rate and the nearest corresponding pulse of a clock corresponding to the first sample rate.

[0050] In operation 640, processing logic (eg, the data resampler circuit 344) resamples data values ​​of the sampled data stream associated with the positions of the multiple retimer values.

[0051] At operation 650, processing logic (e.g., correlation circuit 148) uses the resampled data values, the pseudo clock and multiple retimer values ​​to match expected data patterns to corresponding data patterns detected in the frame delimiter of the packet.

[0052] It will be apparent to those skilled in the art that at least some embodiments may be practiced without these specific details. In other instances, well-known components, elements, or methods are not described in detail or are presented in simple block diagram form to avoid unnecessarily obscuring the subject matter described herein. Thus, the specific details described below are merely illustrative. Particular implementations may vary from these illustrative details and still be considered to be within the spirit and scope of the present embodiments.

[0053] In the description, references to "an embodiment," "one embodiment," "an exemplary embodiment," "some embodiments," and "various embodiments" mean that the particular features, structures, steps, acts, or characteristics described in connection with the embodiment(s) are included in at least one embodiment. Moreover, the appearances of the phrases "an embodiment," "one embodiment," "an exemplary embodiment," "some embodiments," and "various embodiments" in various places in the description are not necessarily all referring to the same embodiments.

[0054] The description includes references to the accompanying drawings, which form a part of the detailed description. The drawings show illustrative examples in accordance with exemplary embodiments. These embodiments, which may be referred to herein as "examples," are described in sufficient detail to enable one of ordinary skill in the art to practice the embodiments of the claimed subject matter described herein. The embodiments may be combined, other embodiments may be utilized, or structural, logical, and electrical changes may be made without departing from the spirit and scope of the claimed subject matter. It is to be understood that the embodiments described herein are not intended to limit the scope of the subject matter, but rather to enable one of ordinary skill in the art to practice, make, and / or use the subject matter.

[0055] The description includes references to the accompanying drawings, which form a part of the detailed description. The drawings show illustrative examples in accordance with exemplary embodiments. These embodiments, which may be referred to herein as "examples," are described in sufficient detail to enable one of ordinary skill in the art to practice the embodiments of the claimed subject matter described herein. The embodiments may be combined, other embodiments may be utilized, or structural, logical, and electrical changes may be made without departing from the spirit and scope of the claimed subject matter. It is to be understood that the embodiments described herein are not intended to limit the scope of the subject matter, but rather to enable one of ordinary skill in the art to practice, make, and / or use the subject matter.

[0056] Certain embodiments may be implemented by firmware instructions stored on a non-transitory computer-readable medium, such as, for example, a volatile memory and / or a non-volatile memory. These instructions may be used to program and / or configure one or more devices including a processor (e.g., a CPU) or equivalent thereof (e.g., a processing core, a processing engine, a microcontroller, etc.), such that when executed by the processor or equivalent thereof, the instructions cause the device to perform the described operations for the USB-C / PD mode transition architecture described herein. Non-transitory computer-readable storage media may include, but are not limited to, electromagnetic storage media, read-only memory (ROM), random access memory (RAM), erasable programmable memory (e.g., EPROM and EEPROM), flash memory, or other media of a non-transitory type now known or later developed suitable for storing information.

[0057] Although the operations of the circuits and blocks herein are illustrated and described in a particular order, in some embodiments, the order of operations of each circuit / block may be changed such that certain operations may be performed in reverse order or such that certain operations may be performed at least in part simultaneously and / or in parallel with other operations. In other embodiments, instructions or sub-operations of different operations may be performed in an intermittent and / or alternating manner.

[0058] In the foregoing specification, the disclosure has been described with reference to certain exemplary embodiments. It will be apparent, however, that various modifications and changes may be made thereto without departing from the broader spirit and scope of the disclosure as set forth in the appended claims. The specification and drawings are therefore to be regarded in an illustrative rather than a restrictive sense.

Claims

1. 1. A wireless device, comprising: a receiver for wirelessly receiving packets over a channel at a first frequency and generating a sampled data stream from the packets at a first sample rate corresponding to the first frequency; a data resampler circuit coupled to the receiver; a correlation circuit coupled to the data resampler circuit; Equipped with the data resampler circuit comprises a retimer engine and a time shift circuit; the retimer engine uses a fractional conversion ratio between the first sample rate and a crystal oscillator (XO) integer-divided sample rate to determine a plurality of retimer values ​​comprising a difference between a pulse of a pseudo-clock corresponding to the XO integer-divided sample rate and a nearest corresponding pulse of a clock corresponding to the first sample rate; the time shift circuit resamples data values ​​of the sampled data stream associated with positions of the plurality of retimer values; the correlation circuit uses the resampled data values, the pseudo clock, and the plurality of retimer values ​​to match expected data patterns to corresponding data patterns detected in the frame delimiters of the packets. Wireless devices.

2. the XO integer-divided sample rate averages a fraction of a frequency of the integer-divided XO sample rate, and the first sample rate is a non-integer sample rate specific to the channel; The wireless device of claim 1 .

3. the time shift circuit includes a plurality of digital fractional delay filters, the plurality of digital fractional delay filters using the pseudo clock to resample the data values ​​based on corresponding retimer values ​​of the plurality of retimer values; The wireless device of claim 1 .

4. The data resampler circuit further includes a pseudo clock generator that generates the pseudo clock, and the pseudo clock generator receiving a phase-locked loop (PLL) clock derived based on the clock corresponding to the first sample rate; removing a pulse from the PLL clock in response to each removal command from the retimer engine; generating the pseudo clock comprising the PLL clock using the removed pulses; the pseudo clock corresponds, on average, to the XO integer division sample rate; The wireless device of claim 1 .

5. The retimer engine further comprises: Detecting a retimer value among the plurality of retimer values ​​that satisfies a threshold; triggering a removal command to the pseudo clock generator in response to said detecting; The wireless device of claim 4.

6. The retimer engine a register for storing one retimer value among the plurality of retimer values; an adder that adds the fractional conversion ratio to the retimer value to determine a fractional retimer value; a comparator for comparing the fractional retimer value with a predetermined negative decimal value; Switch and Equipped with causing said switch to add a value of one to said fractional retimer value to produce a positive retimer value in response to said fractional retimer value being less than or equal to said predetermined negative decimal value; In response to the one value being added, the comparator triggers a removal command to the pseudo clock generator. The wireless device of claim 4.

7. The correlation circuit further comprises: detecting peaks in the resampled data values ​​that are within a threshold of corresponding peaks in the expected data pattern; determining a retimer value of the plurality of retimer values ​​that corresponds most closely in time to the detected peak; modifying the position of the peak using at least the retimer value; correlating the peak at the corrected position with the corresponding peak; The wireless device of claim 1 .

8. To correct the position of the peak, the correlation circuit determining a numerical fractional value associated with a period of said pseudo-clock; determining a retimer fraction value corresponding to the detected edge of the peak using the clock and based on the retimer value; combining the numerical fractional value and the retimer fractional value with the position to generate the corrected position of the peak. The wireless device of claim 7.

9. The data resampler circuit further comprises: obtaining soft frequency samples based on in-phase and quadrature values ​​of the resampled data values; estimating oversampling frequency samples of the soft frequency samples at a multiple of a symbol rate of the pseudo clock; buffering the oversampling frequency samples into a constant number of symbols equal to the symbols of a frame synchronization pattern of the frame delimiter; the correlation circuit further correlates the buffered oversampled frequency samples with expected frequency symbols of the expected data pattern to detect correlation peaks. The wireless device of claim 1 .

10. 1. A method of operating a wireless device, comprising: the wireless device comprises a receiver; a data resampler circuit coupled to the receiver; and a correlation circuit coupled to the data resampler circuit; The method of operating the wireless device comprises: wirelessly receiving, by the receiver, a packet over a channel at a first frequency; generating, by the receiver, a sampled data stream from the packet at a first sample rate corresponding to the first frequency; determining, by the data resampler circuit, a plurality of retimer values ​​comprising a difference between a pulse of a pseudo clock corresponding to the XO integer-divided sample rate and a nearest corresponding pulse of a clock corresponding to the first sample rate using a fractional conversion ratio between the first sample rate and a crystal oscillator (XO) integer-divided sample rate; resampling, by the data resampler circuit, data values ​​of the sampled data stream associated with positions of the plurality of retimer values; using the resampled data values, the pseudo clock, and the plurality of retimer values ​​to match expected data patterns to corresponding data patterns detected in a frame delimiter of the packet; A method comprising:

11. the XO integer-divided sample rate averages a fraction of a frequency of the integer-divided XO sample rate, and the first sample rate is a non-integer sample rate specific to the channel; The method of claim 10.

12. The method of operating the wireless device further includes using a plurality of fractional delay filters to resample the data values ​​based on corresponding retimer values ​​of the plurality of retimer values ​​using the pseudo clock. The method of claim 10.

13. The method of operating the wireless device comprises: receiving, by the data resampler circuit, a phase-locked loop (PLL) clock derived based on the clock corresponding to the first sample rate; removing a pulse from said PLL clock in response to each removal command received from a retimer engine; generating, by the data resampler circuit, the pseudo clock comprising the PLL clock using the removed pulses; further comprising the pseudo clock corresponds, on average, to the XO integer division sample rate; The method of claim 10.

14. The method of operating the wireless device comprises: detecting a retimer value of the plurality of retimer values ​​that satisfies a threshold; triggering a removal command by the retimer engine in response to the detection; further comprising: The method of claim 13.

15. The method of operating the wireless device comprises: storing a retimer value of the plurality of retimer values ​​in a register; adding, by an adder, the fractional conversion ratio to the retimer value to determine a fractional retimer value; comparing, by a comparator, the fractional retimer value with a predetermined negative decimal value; in response to the fractional retimer value being less than or equal to the predetermined negative decimal value, adding a value of one to the fractional retimer value using a switch to generate a positive retimer value; triggering a remove command by the comparator in response to the one value being added; further comprising: The method of claim 13.

16. The method of operating the wireless device comprises: detecting, by said correlation circuit, peaks in said resampled data values ​​that are within a threshold of corresponding peaks in said expected data pattern; determining a retimer value of the plurality of retimer values ​​that corresponds most closely in time to the detected peak; modifying the position of the peak using at least the retimer value; correlating the peak at the corrected position with the corresponding peak by the correlation circuit; further comprising: The method of claim 10.

17. The step of modifying the position of the peak comprises: determining a numerical fractional value associated with a period of said pseudo-clock; determining, using the clock and based on the retimer value, a retimer fraction value corresponding to the detected edge of the peak; combining the numerical fractional value and the retimer fractional value with the position to generate the corrected position of the peak; Including, 17. The method of claim 16.

18. The method of operating the wireless device comprises: obtaining soft frequency samples based on in-phase and quadrature values ​​of the resampled data values; estimating oversampling frequency samples of the soft frequency samples at a multiple of a symbol rate of the pseudo clock; buffering the oversampling frequency samples into a constant number of symbols equal to the symbols of a frame synchronization pattern of the frame delimiter; correlating the buffered oversampled frequency samples with expected frequency symbols of the expected data pattern to detect correlation peaks; further comprising: The method of claim 10.

19. a first wireless device configured to gain access to the secure enclosure by transmitting data including a frame delimiter; a second wireless device located within the secure enclosure; and A system comprising: The second wireless device a receiver for wirelessly receiving packets over a channel at a first frequency and generating a sampled data stream from the packets at a first sample rate corresponding to the first frequency; a data resampler circuit coupled to the receiver; a correlation circuit coupled to the data resampler circuit; Equipped with the data resampler circuit comprises a retimer engine and a time shift circuit; the retimer engine uses a fractional ratio between the first sample rate and a crystal oscillator (XO) integer-divided sample rate to determine a plurality of retimer values ​​comprising a difference between a pulse of a pseudo-clock corresponding to the XO integer-divided sample rate and a nearest corresponding pulse of a clock corresponding to the first sample rate; the time shift circuit resamples data values ​​of the sampled data stream associated with positions of the plurality of retimer values; the correlation circuit uses the resampled data values, the pseudo clock, and the plurality of retimer values ​​to match expected data patterns to corresponding data patterns detected in the frame delimiters of the packets. system.

20. the XO integer-divided sample rate averages a fraction of a frequency of the integer-divided XO sample rate, and the first sample rate is a non-integer sample rate specific to the channel; 20. The system of claim 19.

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