Semiconductor element

Abstract

To provide a semiconductor element using CNT in which hysteresis is small and a change in threshold voltage caused by a magnitude of a drain voltage is suppressed.SOLUTION: A semiconductor element includes a gate electrode 2, a source electrode 3, a drain electrode 4, a semiconductor layer 5 in contact with the source electrode 3 and the drain electrode 4, and a gate insulation layer 6 insulating the semiconductor layer 5 from the gate electrode 2. The semiconductor layer 5 includes a carbon nano-tube network structure, and the semiconductor layer 5 is encapsulated by an encapsulation layer of which the dielectric constant is 5.0 or smaller. In the source electrode 3 and the drain electrode 4, portions in contact with the semiconductor layer 5 are formed from group VI elements in the periodic table.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device, a method for manufacturing the semiconductor device, and the like. [Background technology]

[0002] In recent years, as the Internet of Things (IoT) has become more widespread in society, various things are now connected to the Internet, and a wide variety of semiconductor elements are beginning to be required. Various substrates are used for these various semiconductor elements, and for example, flexible semiconductor elements made using flexible substrates and semiconductor elements that can be manufactured using materials that can be applied to simple processes such as printing are being actively studied.

[0003] Carbon nanotubes (CNTs) have high field-effect mobility and high chemical stability. In addition, CNTs can be dispersed in solutions, making them a material that can be applied to simple processes, and they can be applied or formed into films on various substrates. For this reason, CNTs are considered as a candidate material for forming semiconductor layers, and semiconductor elements using CNTs are being actively investigated. Specifically, research on CNT field-effect transistors (CNT-FETs), which use CNTs as the channel, is being actively conducted.

[0004] Patent Document 1 discloses a method for manufacturing a semiconductor device, which comprises a step of using a nanocarbon ink containing nanocarbon, a solvent, and polyoxyethylene alkyl ether to deposit the nanocarbon ink in a channel layer formation region between a source electrode and a drain electrode to form a channel layer, and shows that when forming a channel layer made of nanocarbon by a printing method in the production of TFTs, a channel layer having a nanocarbon density in an appropriate range can be formed.

[0005] Patent Document 2 discloses a molecular transistor with reduced current hysteresis, which includes an insulating substrate made of an oxide, a semiconductor channel made of a nanostructure formed on the insulating substrate, a source electrode and a drain electrode arranged so as to sandwich the semiconductor channel between them, and a gate electrode for applying a gate voltage to the semiconductor channel to control the conduction of the semiconductor channel, wherein a hydrophobic film is formed on the insulating substrate so as to be chemically bonded to the surface of the insulating substrate, an organic ferroelectric layer is formed on the semiconductor channel, and the semiconductor channel is sandwiched between the hydrophobic film and the organic ferroelectric layer.

[0006] Non-Patent Document 1 discloses that a semiconductor layer made of a high-density, non-uniform random network of CNTs is covered with a fluorine-based resin in order to reduce hysteresis. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] WO2019 / 066074 publication [Patent Document 2] JP 2007-96129 A [Non-patent literature]

[0008] [Non-Patent Document 1] T.-J. Ha et.al., Appl. Master. Interface, 2014, 6, 8441-8446. Summary of the Invention [Problem to be solved by the invention]

[0009] For a semiconductor device to be put to practical use, its electrical characteristics must be stable under various conditions of use, such as having small hysteresis and a constant threshold voltage regardless of the magnitude of the drain voltage.

[0010] The semiconductor element disclosed in Patent Document 1 has a problem of large hysteresis because it operates with the channel layer or semiconductor layer exposed to the atmosphere. The molecular transistor disclosed in Patent Document 2 is configured on the premise of use as a non-volatile memory, in which an organic ferroelectric layer is formed in the semiconductor channel, and the memory effect is realized by changing the threshold voltage depending on the voltage applied to the organic ferroelectric layer. However, since the threshold voltage changes depending on the applied voltage, it is not suitable for use as a normal transistor such as an amplifier. The semiconductor element disclosed in Non-Patent Document 1 succeeds in reducing hysteresis by sealing the semiconductor layer with a fluorine-based resin, but has the problem that the threshold voltage changes depending on the magnitude of the drain voltage. For example, there is a problem that the threshold voltage in the linear region where the drain voltage (drain-source voltage) is not very high is smaller than the threshold voltage in the saturation region where the drain voltage is high.

[0011] In one aspect, the present disclosure provides a semiconductor element using CNTs, in which hysteresis is small and change in threshold voltage due to the magnitude of the drain voltage is suppressed, and a method for manufacturing the same. [Means for solving the problem]

[0012] In one aspect, the present disclosure provides a semiconductor device including a gate electrode, a source electrode, a drain electrode, a semiconductor layer in contact with the source electrode and the drain electrode, and a gate insulating layer insulating the semiconductor layer from the gate electrode, the semiconductor layer including a carbon nanotube network structure, and the semiconductor layer having a relative dielectric constant of 5.0The present invention relates to a semiconductor element that is encapsulated with the following encapsulation layer, and the portions of the source electrode and the drain electrode that are in contact with the semiconductor layer are formed of an element of Group 6 of the periodic table.

[0013] The present disclosure provides, in one aspect, a method for manufacturing a semiconductor device including a gate electrode, a source electrode, a drain electrode, a semiconductor layer in contact with the source electrode and the drain electrode, and a gate insulating layer insulating the semiconductor layer from the gate electrode, forming a semiconductor layer including a carbon nanotube network structure using the carbon nanotube dispersion; forming a source electrode and a drain electrode on the semiconductor layer, the source electrode and the drain electrode being in contact with the semiconductor layer and including a layer of a Group 6 element of the periodic table; The present invention relates to a method for manufacturing a semiconductor element, comprising: encapsulating the semiconductor layer to form an encapsulation layer having a relative dielectric constant of 5.0 or less. Effect of the Invention

[0014] According to the present disclosure, it is possible to provide a semiconductor element using CNTs, which has small hysteresis and in which changes in threshold voltage due to the magnitude of the drain voltage are suppressed. [Brief description of the drawings]

[0015] [Figure 1] FIG. 1 is a schematic perspective view of a semiconductor device according to one embodiment of the present disclosure. [Diagram 2] FIG. 2 is a schematic cross-sectional view of the semiconductor element shown in FIG. [Diagram 3] FIG. 3 is a schematic diagram illustrating a network structure of carbon nanotubes constituting a semiconductor device according to one embodiment of the present disclosure. [Figure 4] FIG. 4 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present disclosure. [Diagram 5] 5A to 5C are diagrams showing the steps of a method for manufacturing a semiconductor device according to one embodiment of the present disclosure. [Figure 6] 6A to 6C are diagrams showing the steps of a method for manufacturing a semiconductor device according to one embodiment of the present disclosure. [Figure 7] FIG. 7 is an atomic force microscope (AFM) image of a semiconductor layer constituting the semiconductor element of Example 1. As shown in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] It is often thought that the change in threshold voltage depending on the magnitude of the drain voltage is due to the semiconductor layer. However, the inventors of the present invention believe that the contact parts between the semiconductor layer made of CNT and the source electrode (S electrode) and drain electrode (D electrode) (hereinafter, these may be collectively referred to as "SD electrodes") are also the cause, and as a result of extensive investigation, they found that hysteresis can be effectively reduced and the change in threshold voltage can be reduced by forming the part of the SD electrode that contacts the CNT with an element of Group 6 of the periodic table and sealing the semiconductor layer with an electrically inactive material.

[0017] The reason why the source electrode and drain electrode each include a layer of a Group 6 element of the periodic table (hereinafter sometimes referred to as the "Group 6 element layer") and the Group 6 element layer is in contact with the semiconductor layer to reduce the above-mentioned threshold voltage change is not clear, but it is speculated as follows. The following document reports that Group 6 elements form a 6-coordinate bond structure with CNTs due to their electronic structure, improving electrical conductivity. It is speculated that by forming the parts of the source electrode and drain electrode that are in contact with the CNTs from a Group 6 element, the electrical connection between the CNTs and these electrodes is improved, and the threshold voltage change due to the magnitude of the drain voltage is suppressed. Literature: I. Kalinina et. al., Macromol. Chem. Phys. 2012, 213 1001-1019

[0018] In addition, in order to limit the exposure of the semiconductor layer to the atmosphere, covering the semiconductor layer with a sealing layer is considered to be effective from the viewpoint of reducing hysteresis. In order not to affect the electrical properties of the semiconductor layer, the sealing layer is preferably made of an electrically inactive material, specifically, a material that does not dope electrons or holes into the semiconductor layer and has a small dielectric constant and does not have ferroelectricity. When the sealing layer is made of a material that can dope electrons or holes into the semiconductor layer, the charge state of the semiconductor layer changes depending on the level of the drain voltage, and the threshold voltage is likely to change. When the sealing layer is made of a material that has a large dielectric constant or a material that exhibits ferroelectricity, particularly when the drain voltage is high, charges are induced at the interface between the sealing layer and the semiconductor layer, making it easy for the threshold voltage to change and the hysteresis to become large. Usually, a material with a dielectric constant of 5.0 or less does not exhibit ferroelectricity. It has been found that when the sealing layer is made of a material with a dielectric constant of 5.0 or less, not only is hysteresis reduced, but also the change in the threshold voltage is unexpectedly suppressed.

[0019] As described above, in the semiconductor element of the present disclosure, the portion of the SD electrode that contacts the CNT is made of a Group 6 element, and the semiconductor layer is sealed with a material with a dielectric constant of 5.0 or less, thereby effectively reducing hysteresis and effectively suppressing changes in threshold voltage due to changes in the drain voltage.

[0020] Hereinafter, a semiconductor device according to one embodiment of the present disclosure will be described with reference to the drawings.

[0021] As shown in FIG. 1 and FIG. 2, the semiconductor element of the present disclosure is, in one embodiment, a CNT-field effect transistor (CNT-FET), and preferably a p-type CNT field effect transistor. The semiconductor element 1 includes a gate electrode 2, a source electrode 3, a drain electrode 4, and a semiconductor layer 5. A gate insulating layer 6 is disposed between the semiconductor layer 5 and the gate electrode 2, and the gate insulating layer 6 insulates the semiconductor layer 5 from the gate electrode 2. In the embodiment shown in FIG. 1 and FIG. 2, the source electrode 3 and the drain electrode 4 are formed on the surface of the semiconductor layer 5 opposite to the surface on the gate insulating layer 6 side with a predetermined interval (channel length) therebetween, but in another embodiment, the source electrode and the drain electrode may be formed on the surface on the gate insulating layer 6 side of the semiconductor layer as long as they are insulated from the gate electrode. The portion (channel region) of the semiconductor layer 5 disposed between the source electrode 3 and the drain electrode 4 is covered with a sealing layer 8 to prevent the semiconductor layer 5 from contacting the atmosphere. For the same reason, in an embodiment in which the source electrode and the drain electrode are formed on the surface of the semiconductor layer on the gate insulating film side, it is preferable that the surface of the semiconductor layer exposed to the atmosphere, for example, the surface (entire surface) opposite to the surface on the insulating layer side of the semiconductor layer, is covered with an encapsulating layer, and in addition, it is preferable that the end surfaces are also covered with an encapsulating layer. In the semiconductor element 1, the semiconductor layer 5 preferably includes a CNT network structure, which is easy to manufacture and can pass a large amount of current.

[0022] [Source electrode, drain electrode] The source electrode 3 and the drain electrode 4 are electrically connected by the CNT network structure of the semiconductor layer 5 functioning as a channel. As can be clearly seen from FIG. 2, the source electrode 3 and the drain electrode 4 each include a group 6 element layer 31, 41 formed of a group 6 element, and the group 6 element layer 31, 41 is in contact with the semiconductor layer 5. Examples of the group 6 element include chromium (Cr), molybdenum (Mo), and tungsten (W), and among these, chromium (Cr) is preferable. From the viewpoint of preventing oxidation deterioration of the group 6 element layer and ensuring the conductivity of the electrode, the source electrode 3 and the drain electrode 4 further have a multilayer structure including one or more upper layers 32, 43 formed of a conductive material other than the group 6 element on the surface opposite to the surface of the group 6 element layer on the semiconductor layer 5 side. In another embodiment, the source electrode and the drain electrode may have a single layer structure made of a group 6 element layer. The conductive material is not particularly limited, and examples thereof include metals such as titanium, copper, gold, platinum, chromium, aluminum, palladium, and molybdenum, semiconductors such as polysilicon, and conductive metal oxides such as indium tin oxide (ITO), among which gold is preferred because of its chemical stability. Methods for forming the Group 6 element layer and the upper layer include conventionally known methods such as vacuum deposition, electron beam, sputtering, plating, CVD, ion plating coating, inkjet, and printing, depending on the material.

[0023] The average thickness of the Group 6 element layers 31, 41 is preferably 1 nm or more, more preferably 5 nm or more, and even more preferably 20 nm or more, from the viewpoint of reducing hysteresis and suppressing a change in threshold voltage. Also, from the viewpoint of processability of the CNT-FET, it is preferably 1000 nm or less, more preferably 500 nm or less. In the present disclosure, the average thickness of the Group 6 element layers can be measured, for example, by cutting the CNT-FET in its thickness direction to prepare a measurement sample so that the cross section is as shown in FIG. 2, and observing the cross section of the CNT-FET with a scanning electron microscope.

[0024] The average thickness of the upper layers 32, 42 (the total thickness of each layer when the upper layer has a multilayer structure) is preferably 5 nm or more, more preferably 10 nm or more, and even more preferably 20 nm or more from the viewpoint of preventing oxidative deterioration of the Group 6 element layers 31, 41 and ensuring the conductivity of the electrodes, and is preferably 1000 nm or less, more preferably 500 nm or less from the viewpoint of processability of the CNT-FET. In the present disclosure, the average thickness of the upper layer can be measured, for example, by preparing a measurement sample by cutting the CNT-FET in its thickness direction so that the cross section is as shown in FIG. 2, and observing the cross section of the CNT-FET with a scanning electron microscope.

[0025] The channel length (L) and channel width (W) may be dimensions known in the art, with the channel length (L) being, for example, 10 μm or more and 1000 μm or less, and the channel width (W) being, for example, 10 μm or more and 10,000 μm or less, although the present disclosure is not limited thereto.

[0026] [Sealing layer] In the semiconductor element 1 of the present disclosure, the semiconductor layer 5 is sealed by a sealing layer 8 that prevents the semiconductor layer 5 from coming into contact with the outside air in order to make the semiconductor layer 5 waterproof and dustproof. The sealing layer 8 may be composed of a single layer, or may be composed of a plurality of laminated layers. The material forming the sealing layer 8 has a relative dielectric constant of preferably 5.0 or less, more preferably 4.0 or less, and even more preferably 3.0 or less, from the viewpoint of reducing hysteresis and suppressing changes in threshold voltage. There is no particular limit on the lower limit of the relative dielectric constant, but it is usually 1.5 or more. The relative dielectric constant of the material forming the sealing layer 8 is a value measured by the method described in the examples.

[0027] The material for forming the sealing layer 8 is preferably an electrically inactive compound that does not dope electrons or holes into the semiconductor layer, is preferably a hydrophobic polymer, and is preferably a material that does not cause a side reaction with the CNTs during sealing. From the viewpoint of reducing hysteresis and suppressing changes in the threshold voltage, at least one polymer selected from styrene-based resins, fluororesins, and acrylic-based resins is preferably used.

[0028] Examples of styrene-based resins include polystyrene (P-St) (dielectric constant: 2.5), acrylonitrile-styrene copolymer (AS) (dielectric constant: 2.9), and acrylonitrile-butadiene-styrene copolymer (ABS) (dielectric constant: 3.2), while examples of fluorine-based resins include commercially available products such as CYTOP (registered trademark) CTL-809A (manufactured by AGC) (dielectric constant: 2.1), and examples of acrylic-based resins include polymethyl methacrylate (PMMA) (dielectric constant: 2.8), polybutyl methacrylate (dielectric constant: 2.7), etc. The material of the sealing layer 8 may be one of these resin materials or a combination of two or more of them. Furthermore, from the viewpoint of reducing hysteresis and suppressing changes in threshold voltage, the material of the sealing layer 8 is preferably one or more polymers selected from CYTOP (registered trademark) CTL-809A (dielectric constant 2.1), polystyrene (dielectric constant 2.5) and PMMA (dielectric constant 2.8), with CYTOP (registered trademark) CTL-809A (dielectric constant 2.1) being more preferable.

[0029] The average thickness of the sealing layer 8 in the region (channel region) between the source electrode 3 and the drain electrode 4 (the sum of the average thicknesses of the layers when the sealing layer is formed by laminating multiple layers) is preferably 200 nm or more, more preferably 500 nm or more, and even more preferably 1000 nm or more, from the viewpoint of ensuring sufficient barrier properties against moisture, oxygen, etc. and reducing hysteresis. There is no particular upper limit on the average thickness of the sealing layer, but it is preferably 1 mm or less. In the present disclosure, the average thickness of the sealing layer 8 can be measured by an atomic force microscope (AFM) or a stylus-type surface profiler.

[0030] [Gate electrode, gate insulating film] The semiconductor element 1 according to one embodiment of the present disclosure is a so-called bottom-gate type semiconductor element, in which a silicon substrate functions as a gate electrode 2, and a thermal oxide film SiO2 formed on one main surface of the silicon substrate functions as a gate insulating film 6. In the example shown in Fig. 1 and Fig. 2, the entire surface of one main surface of the silicon substrate is covered with the gate insulating film 6, but it is sufficient that the semiconductor layer 5 and the silicon substrate are insulated from each other, and it is sufficient that at least the region in which the source electrode 3, the drain electrode 4, and the semiconductor layer 5 are arranged is covered with the gate insulating layer 6.

[0031] The gate insulating layer 6 may have a single-layer structure, a multi-layer structure, or a partially multi-layer structure. The total thickness of the gate insulating layer 6 is preferably 10 nm or more, more preferably 20 nm or more, from the viewpoint of sufficiently reducing the leakage current of the gate. Also, from the viewpoint of reducing the operating voltage, it is preferably 500 nm or less, more preferably 200 nm or less. Examples of materials for the gate insulating layer include inorganic compounds such as silicon oxide, silicon nitride, and hafnium oxide, and organic compounds such as vinylphenol resin, paraxylene resin, vinylidene fluoride resin, and polyimide resin.

[0032] The semiconductor element of the present disclosure is not limited to a form in which a silicon substrate functions as the gate electrode 2, and may be a form in which a substrate is provided with an insulating surface on which at least an electrode is disposed, and a gate electrode is disposed on the substrate. The substrate may be, for example, an inorganic material such as glass, sapphire, alumina sintered body, silicon wafer, or a substrate having a surface covered with an oxide film, or may be a sheet made of polyimide (PI) resin, polyester resin, polyamide resin, epoxy resin, polysulfone resin, polyamide resin, or the like, or may be a film-like flexible material made of these.

[0033] The material of the gate electrode is not particularly limited as long as it has conductivity, and examples thereof include metals such as gold, platinum, chromium, titanium, and aluminum, and semiconductors such as silicon that have been made conductive by doping with impurities. The gate electrode is formed, for example, by depositing these metals at an arbitrary position. A separately prepared metal thin film may be disposed at an arbitrary position on the substrate as the gate electrode. Methods for forming these electrodes include conventionally known methods such as vacuum deposition, electron beam, sputtering, plating, CVD, ion plating coating, inkjet, and printing, depending on the material.

[0034] The semiconductor element of the present disclosure can be of various types, such as a back gate type, a side gate type, and a top gate type, depending on the position of the gate electrode.

[0035] [Semiconductor layer] The CNTs constituting the semiconductor layer are thin cylindrical ones formed by rolling up a graphene sheet into a cylindrical shape. The semiconductor layer 5 is constituted by a network structure of CNTs. In the present disclosure, the network structure of CNTs is a structure in which adjacent CNTs are entangled with each other and connected in a wide range in a mesh-like manner. In the present disclosure, the network structure refers to a structure in which the CNTs in the semiconductor layer are not oriented in a specific direction, and one CNT preferably intersects with five or more other CNTs. The CNTs are scattered in all directions without being aligned in one direction by being randomly oriented in a two-dimensional direction. By using such a network structure, the CNTs can pass a large current through the semiconductor layer, and since they are not oriented in a specific direction, anisotropy does not appear in the conductivity. Furthermore, in the network structure, one CNT does not connect the source electrode and the drain electrode, but multiple CNTs form a conductive path between the source electrode and the drain electrode, so that even if a small amount of metallic CNT is mixed in, a good on / off ratio can be obtained without short-circuiting the source electrode and the drain electrode.

[0036] In the present disclosure, the CNT network structure may be a multi-layer structure in which the CNT density in the thickness direction is high, for example, in which there are many parts in the network structure where one or more CNTs are stacked above or below the intersection point where two CNTs intersect and in the vicinity of the intersection point. However, from the viewpoint of improving the on / off ratio, the CNT network structure is preferably a substantially single-layer CNT film. If the semiconductor layer is a substantially single-layer CNT film, a sufficient gate voltage is applied to the CNTs located relatively far from the gate electrode, thereby obtaining a good on / off ratio. It is possible to confirm that the CNT network structure is a substantially single-layer CNT film by the average film thickness of the semiconductor layer being 5 nm or less.

[0037] As shown in Fig. 3, the CNT network structure is preferably a CNT network structure in which two CNTs 50 cross each other and are connected in a mesh-like pattern in the planar direction by the repetition of the cross-sectional structure. In the substantially single-layer CNT film, preferably, there is substantially no portion in which three or more CNTs are stacked in the thickness direction (the direction perpendicular to the surface of the semiconductor layer 5), more preferably, there is almost no portion, and even more preferably, there is no portion. The fact that the semiconductor layer is a substantially single-layer CNT film can be confirmed by cross-sectional observation using an atomic force microscope (AFM).

[0038] From the viewpoint of improving the on / off ratio, the average thickness of the semiconductor layer 5 is preferably 5 nm or less, more preferably 4 nm or less, and further preferably 3 nm or less. From the viewpoint of ensuring a sufficient amount of current, the average thickness of the semiconductor layer 5 is preferably 0.1 nm or more, and more preferably 0.3 nm or more. In the present disclosure, the average thickness of the semiconductor layer 5 can be measured by an atomic force microscope (AFM).

[0039] In addition, in order to obtain the effect of a substantially single-layer CNT film, it is preferable that the CNTs are in a non-aggregated and non-bundled state. A bundled state is a state in which multiple CNTs are attached to each other and bundled together. If such a CNT is used in the semiconductor layer, it becomes difficult to apply a gate voltage and the on / off ratio deteriorates, as in the case of using multi-layered CNTs. If 10% or more of the length of each CNT overlaps with other CNTs, it can be said to be in a bundled state. Since the diameter of a CNT is about 1 to 2 nm, if the average film thickness of the semiconductor layer is 5 nm or less, the semiconductor layer will be substantially free of bundles (i.e., in a non-bundled state).

[0040] The density of the CNT network is set to 100 / μm in order to obtain a sufficient drain current. 2 It is preferable that the density is 8000 fibers / μm or more. Moreover, if the density is too high, a conductive path is formed between the source and drain electrodes by a small amount of metallic CNT mixed in, causing a short circuit between them, resulting in a decrease in the on / off ratio. In the present disclosure, from the viewpoint of suppressing the decrease in the on / off ratio, the density is set to 8000 fibers / μm 2 It is preferable that:

[0041] The CNTs constituting the semiconductor layer 5 may be only single-walled carbon nanotubes (SWCNTs) in which a graphene sheet is wound in one layer, or a mixture of SWCNTs and double-walled carbon nanotubes (DWCNTs) in which a graphene sheet is wound in two layers, or multi-walled carbon nanotubes (MWCNTs) in which a graphene sheet is wound in three or more layers, but among these, from the viewpoint of reducing leakage current and ensuring a sufficient on / off ratio, it is preferable to be substantially composed of SWCNTs only, and more preferable to be composed of SWCNTs only. Note that these CNTs can be distinguished by known means, such as Raman spectroscopy.

[0042] CNTs include metallic CNTs that exhibit metallic properties and semiconducting CNTs that exhibit semiconducting properties, and semiconducting CNTs are preferred as CNTs constituting the semiconductor layer 5. CNTs may be synthesized by conventionally known synthesis methods such as the high pressure carbon monoxide disproportionation method (HiPco method), the improved direct injection pyrolysis synthesis method (e-DIPS method), the arc discharge method, and the laser ablation method. However, SWCNTs synthesized by these general synthesis methods are mixtures containing about 1 / 3 metallic SWCNTs and about 2 / 3 semiconducting SWCNTs, so it is preferred to form the semiconductor layer 5 using a CNT dispersion obtained by applying a technique to the mixture to increase the content of semiconducting SWCNTs. The content of semiconducting CNTs in the CNTs constituting the semiconductor layer 5 is preferably 70% by mass or more, more preferably 80% by mass or more, even more preferably 90% by mass or more, and even more preferably 95% by mass or more.

[0043] In the present disclosure, the content of semiconducting CNTs in the semiconductor layer 5 can be considered as the ratio of semiconducting CNTs to the total amount of CNTs (the sum of semiconducting CNTs and metallic CNTs) in the CNT dispersion used to form the semiconductor layer 5. In the present disclosure, the ratios of semiconducting CNTs in the CNT dispersion and in the semiconductor layer 5 can be calculated, for example, from the results of Raman spectrum measurement using a Raman spectrometer described in the Examples.

[0044] The average diameter of SWCNTs is preferably 0.5 nm or more, more preferably 0.8 nm or more, from the viewpoint of ensuring sufficient field effect mobility, and is preferably 3 nm or less, more preferably 2 nm or less, from the viewpoint of suppressing leakage current by providing an appropriate band gap as a semiconductor and ensuring a sufficient on / off ratio. The average diameter of SWCNTs can be calculated by measuring the diameters of 10 or more CNTs from an image obtained using a transmission electron microscope and averaging them.

[0045] The average length of SWCNT is preferably 0.1 μm or more, more preferably 0.3 μm or more, and even more preferably 0.5 μm or more from the viewpoint of reducing the intersections of CNTs and ensuring sufficient mobility, and is preferably shorter than the distance (channel length) between the source electrode and the drain electrode of the semiconductor element from the viewpoint of reducing the leakage current caused by the mixed metallic CNTs and ensuring a sufficient on / off ratio, more preferably 2 / 3 or less of the channel length, and even more preferably half or less of the channel length. For example, it is preferably 100 μm or less, more preferably 50 μm or less, even more preferably 20 μm or less, and even more preferably 10 μm or less. The average length of SWCNT can be calculated, for example, by measuring the lengths of 10 or more CNTs from an image obtained using a transmission electron microscope and averaging them.

[0046] 4, in order to enhance the adsorptivity of CNTs, the semiconductor element of the present disclosure preferably has a structure in which the surface of the gate insulating layer 6 is treated with a surface treatment agent to form the adsorption layer 9, and the adsorption layer 9 is disposed between the semiconductor layer 5 and the gate insulating layer 6 and in contact with them. Since the presence of a compound having an anionic group on the gate insulating layer 6 can cause charge trapping and can be a cause of increased hysteresis or a cause of a decrease in the on / off ratio, it is preferable that the adsorption layer 9 is formed of a compound having no anionic group.

[0047] The adsorption layer 9 is preferably formed of a silane coupling agent having no anion group, such as 3-aminopropyltriethoxysilane (APTES), methyltriethoxysilane (MTES), methyltrimethoxysilane (MTMS), N-2-(aminoethyl)-3-aminopropyltrimethoxysilane, octadecyltrichlorosilane (OTS), fluorine-substituted octatrichlorosilane (PFOTS), tetracyanoquinodimethane, etc. The adsorption layer 9 may be formed by dissolving these materials in an organic solvent, and applying the resulting solution to the gate insulating layer 6 by a coating method such as a dip coating method, or by a gas phase method.

[0048] [Method of manufacturing semiconductor devices] Next, a method for manufacturing the semiconductor element 1 shown in Figures 1 and 2 will be described. Figures 5A to C and Figures 6A to C are cross-sectional views showing the manufacturing method of the semiconductor element 1 in the order of steps.

[0049] 5A, a gate electrode 2 is prepared, one of whose main surfaces is covered with a gate insulating film 6. Specifically, a silicon substrate (gate electrode 2) is prepared, the one of whose main surfaces is thermally oxidized to have a silicon oxide (SiO2) layer (gate insulating film 6).

[0050] Next, as shown in FIG. 5B, the CNT dispersion is applied to the entire surface of the gate insulating film 6 opposite the surface on the gate electrode 2 side to form a coating film 15. The CNTs are then allowed to stand for a while to fully adsorb onto the surface of the gate insulating film 6. Thereafter, before drying, excess CNTs are removed from the coating film 15 to reduce the thickness of the coating film. Next, the remaining coating film is dried to form a substantially single-layer CNT film as the semiconductor layer 5' as shown in FIG. 5C. The CNT dispersion can be applied by a method of dropping the CNT dispersion using a dispenser, a printing method such as inkjet printing, screen printing, or offset printing, a spin coating method, or a dip coating method. Among these, from the viewpoint of forming a CNT network structure with good homogeneity, the method of dropping the CNT dispersion using a dispenser and the spin coating method are preferred. The adsorption of the CNTs onto the surface to which the CNT dispersion is applied (the surface of the gate insulating film 6, or the surface of the adsorption layer 9 when the CNT dispersion is applied to the adsorption layer 9 (see FIG. 4)) is performed by hydrophobic interaction between the CNTs and the surface to which the CNT dispersion is applied. Excess CNTs are preferably removed from the coating film 15 by a washing process described below before drying. A substantially single-layer CNT film can be formed by appropriately adjusting the thickness of the coating film 15 before the washing process, the CNT concentration in the CNT dispersion, the time from application of the CNT dispersion to washing, and the like.

[0051] (CNT dispersion) The CNT dispersion contains CNT and a dispersion medium, and if necessary, a dispersant for CNT. The concentration of CNT in the CNT dispersion is preferably 0.1 μg / mL or more, more preferably 0.5 μg / mL or more, and even more preferably 1.0 μg / mL or more from the viewpoint of ensuring a sufficient amount of current, and is preferably 7.0 μg / mL or less, more preferably 5.0 μg / mL or less, and even more preferably 3.0 μg / mL or less from the viewpoint of forming a substantially single-layered homogeneous CNT network structure.

[0052] The dispersion medium is preferably an aqueous medium, and the aqueous medium is preferably pure water, ion-exchanged water, purified water, or distilled water, and more preferably pure water. The aqueous medium may contain, in addition to water, a lower alcohol such as methanol, ethanol, or isopropyl alcohol, or a water-soluble organic solvent such as acetone, tetrahydrofuran, or dimethylformamide.

[0053] In one embodiment of the present disclosure, for example, it is preferable to form the semiconductor layer 5 using a CNT dispersion obtained by applying a technique for increasing the content of semiconducting CNT to a mixture of metallic CNT and semiconducting CNT. In one embodiment of the present disclosure, it is preferable to form the semiconductor layer 5 using a semiconducting SWCNT dispersion obtained by a method described in, for example, JP 2021-080121 A, JP 2021-080120 A, JP 2021-080119 A, or JP 2019-202912 A. These semiconducting SWCNT dispersions contain, for example, an acrylic acid-based resin as a dispersant for CNT. Examples of the acrylic acid-based resins disclosed in these publications include polyacrylic acid, copolymers of acrylic acid and phenoxydioxyethylene acrylate (PDEA), copolymers of acrylic acid and methoxydioxypropylene acrylate (MDPA), copolymers of acrylic acid and polyethylene glycol monoacrylate (average number of moles of ethyleneoxy groups added is 2 to 10), and homopolymers of polyethylene glycol monomethacrylate (average number of moles of ethyleneoxy groups added is 2 to 45).

[0054] The content of semiconducting CNTs in the CNTs contained in the semiconducting SWCNT dispersion is preferably 70 mass % or more, more preferably 80 mass % or more, even more preferably 90 mass % or more, and even more preferably 95 mass % or more.

[0055] The time period from immediately after the formation of the coating film 15 until the start of the cleaning process to remove excess CNTs is preferably 1 minute or more, more preferably 5 minutes or more, even more preferably 10 minutes or more, and even more preferably 30 minutes or more, from the viewpoint of proper adsorption of the CNTs to the underlying layer, i.e., the gate insulating layer 6 or the adsorption layer 9, and is preferably 180 minutes or less, more preferably 120 minutes or less, and even more preferably 90 minutes or less, from the viewpoint of productivity.

[0056] [Cleaning process] In one embodiment of the method for producing a semiconductor element according to the present disclosure, in forming the semiconductor layer 5, a CNT dispersion is applied to a surface to be coated to form a coating film, the CNTs are adsorbed on the surface to be coated, and excess CNTs are removed from the coating film while the coating film is wet, and then a drying process is performed to form the semiconductor layer. Here, "wet" refers to a state before the dispersion medium, which is a component of the CNT dispersion, has completely evaporated, for example, referring to a state before the drying process described below is started. The removal of excess CNT from the coating film 15 is carried out, for example, by a washing process. The washing process can be carried out, for example, by pouring a washing liquid onto the coating film 15 after the CNTs have been appropriately adsorbed to the lower layer through the above-mentioned standing time, or by immersing a laminate including the coating film 15, the gate insulating layer 6, and the gate electrode 2 in a washing liquid in a bath. From the viewpoint of forming a substantially single-layer CNT film and a homogeneous CNT network structure, a method of washing the laminate including the coating film 15 by immersing it in a washing liquid in a bath is preferred. As the washing liquid, in order not to remove the CNTs that are adsorbed to the lower layer and that constitute a substantially single-layer CNT film, for example, ultrapure water, alcohol such as ethanol or methanol, or polar solvents such as acetone or tetrahydrofuran (THF) are preferred. The immersion time is preferably 1 minute or more, more preferably 3 minutes or more, even more preferably 5 minutes or more, even more preferably 10 minutes or more, even more preferably 30 minutes or more, and preferably 180 minutes or less, more preferably 120 minutes or less, even more preferably 90 minutes or less, and even more preferably 80 minutes or less.

[0057] The coating film 15 washed as described above is subjected to a drying treatment to volatilize the dispersion medium, thereby forming a semiconductor layer 5'. The drying treatment is performed, for example, by placing the coating film 15 in an atmosphere set at a predetermined temperature. The temperature of the atmosphere is preferably 50°C or higher, more preferably 80°C or higher, and even more preferably 100°C or higher, and preferably 250°C or lower, more preferably 220°C or lower, and even more preferably 200°C or lower. The drying time is preferably 5 minutes or longer, more preferably 10 minutes or longer, more preferably 20 minutes or longer, and even more preferably 30 minutes or longer, and preferably 240 minutes or lower, more preferably 180 minutes or lower, more preferably 120 minutes or lower, and even more preferably 90 minutes or lower.

[0058] Next, as shown in FIG. 6A, on the semiconductor layer 5', a Group 6 element layer 31, 41 and an upper layer 32, 42 of the source electrode 3 and the drain electrode 4 are formed in this order. The formation method of these layers may be a conventionally known method. For example, a metal mask is disposed on the surface of the semiconductor layer 5' opposite to the surface on the gate insulating film 6 side, and a metal material to be the source electrode 3 and the drain electrode 4 is vacuum-deposited on the opening of the metal mask, respectively.

[0059] Next, as shown in FIG. 6B, after removing the extra portion of the semiconductor layer 5' by etching, the silicon substrate 2 on which the source electrode 3 and the drain electrode 4 are formed is heated at 100°C or higher and 200°C or lower for 30 minutes or more and 60 minutes or less to remove trace moisture adsorbed on the gate insulating layer 6 and the semiconductor layer 5 and to perform annealing.

[0060] Next, as shown in FIG. 6C, a sealing layer 8 is formed on the portion (channel region) disposed between the source electrode 3 and the drain electrode 4 of the semiconductor layer 5. Specifically, for example, a solution of the resin for forming the sealing layer 8 is applied by a coating method such as spin coating, and then the sealing layer 8 is formed by drying as necessary.

Example

[0061] Hereinafter, the present disclosure will be described in more detail by way of examples, which are illustrative only and the present disclosure is not limited to these examples.

[0062] 1. Measurement method of various parameters [Measurement of weight average molecular weight of polymer] The weight average molecular weight of the polymer used for preparing the SWCNT dispersion was measured under the following conditions using gel permeation chromatography (hereinafter also referred to as "GPC"). <GPC conditions> Measuring device: HLC―8320GPC (manufactured by Tosoh Corporation) Column: α―M + α―M (manufactured by Tosoh Corporation) Eluent: 60mmol / L H3PO4 and 50mmol / L LiBr in N,N-dimethylformamide (DMF) Flow rate: 1.0mL / min Column temperature: 40℃ Detection: RI Sample size: 0.5mg / mL Standard material: Monodisperse polystyrene (manufactured by Tosoh Corporation)

[0063] [Semiconducting SWCNT content] The Raman spectrum of the SWCNT before dispersion and the SWCNT dispersion (dispersed SWCNT) dried on the slide glass was measured with a laser Raman microscope (Nanophoton Corporation "RAMAN touch") at an excitation wavelength of 633 nm. The RBM (radial breathing mode) peak (100-350 cm) of the Raman spectrum excited at 633 nm was -1 ), there are peaks specific to semiconducting SWCNTs and peaks specific to metallic SWCNTs. m The area A of the peak specific to semiconducting SWCNTs s Ratio of (A s / m ) and the peak area A specific to metallic SWCNTs in the SWCNT dispersion. m The area A of the peak specific to semiconducting SWCNTs s Ratio of (A s / m The semiconducting SWCNT content in the SWCNTs after dispersion can be calculated by calculating (a) of the semiconducting SWCNTs before dispersion (67 mass%). The semiconducting SWCNT content in the SWCNT dispersion can be calculated from the following formula:

[0064] Semiconducting SWCNT content = [(0.67 / A s / m )×A s / m '×100] / [0.33+(0.67 / A s / m )×A s / m ']

[0065] [Measurement of average diameter and length of SWCNTs] The average diameter and average length of SWCNTs were calculated by measuring the diameter and length of 10 or more CNTs from images obtained using a transmission electron microscope and averaging them.

[0066] [Measurement of average thickness of semiconductor layer] Using an atomic force microscope (AFM), the height from the surface of the thermal oxide film (SiO2) to the surface of the semiconductor layer was measured at five random locations, and the average thickness of the semiconductor layer was determined by averaging the measurements.

[0067] [Measurement of carbon nanotube density in carbon nanotube networks] An atomic force microscope was used to obtain an image of the region (channel region) between the source and drain electrodes in the semiconductor layer, and the carbon nanotube density (tubes / μm) was calculated by squaring the number of CNTs present on one side of a 1 μm square. 2 ) was measured.

[0068] [Measurement of average thickness of sealing layer] Using a stylus-type surface profiler, the height from the surface of the semiconductor layer to the surface of the sealing layer between the source electrode and the drain electrode was measured at five random locations, and the average of these measurements was used to measure the average thickness of the sealing layer.

[0069] [Dielectric constant of sealing layer] The relative dielectric constant of the sealing layer was measured at 25° C. and 1 MHz by molding the resin used for the sealing layer into a film and using a capacitance method with an impedance analyzer.

[0070] [Measurement of the average thickness of SD electrodes (group 6 element layer and upper layer)] To measure the average thickness of the group 6 element layer and the upper layer, after measuring the electrical characteristics of the semiconductor element, a measurement sample was prepared by cutting the CNT-FET so that its cross section would be as shown in Figure 2. Next, the cut surface of the CNT-FET was observed with a scanning electron microscope to measure the average thickness of the group 6 element layer and the upper layer, and the results are shown in Table 1.

[0071] [Hysteresis measurement] The transfer characteristics of the semiconductor element were measured in air. The drain current (Ids) was measured when the gate voltage (Vgs) was changed using a semiconductor characteristic evaluation device (manufactured by KEITHLEY Corporation). The drain voltage (Vds) was set to -1V, and the gate voltage (Vgs) was swept back and forth between 20V and -20V. The hysteresis was calculated from the absolute value |Vgs1-Vgs2| of the gate voltage difference between the outbound (scan from 20V to -20V) and return (scan from -20V to 20V) when the drain current (Ids) was -100nA. The results are shown in Table 1 below.

[0072] [Measurement of threshold voltage difference] After calculating the hysteresis using the above method, the drain voltage was set to -20V, and the gate voltage was swept from 20V to -20V in the same manner. It is difficult to accurately calculate the threshold voltage, which is the voltage when a large current begins to flow. Therefore, the gate voltage (Vgs) when the forward drain current (Ids) becomes -100nA was set as the threshold voltage for convenience in order to evaluate the degree of change in threshold voltage due to the magnitude of the drain voltage, and the difference ΔVg (=Vgs4-Vgs3) between the threshold voltage (Vgs3) when the drain voltage (Vds) is set to -1V (linear region) and the threshold voltage (Vgs4) when the drain voltage (Vds) is set to -20V (saturation region) was calculated. The results are shown in Table 1 below.

[0073] [Preparation of CNT dispersion] A polymer (weight average molecular weight: 100,000) synthesized using polyethylene glycol (9) monomethacrylate (PEG (9) MA, Shin-Nakamura Chemical Co., Ltd., "MG-90G, the average number of moles of polyoxyethylene added is 9) as a raw material monomer by the method described in JP 2021-80120 A was dissolved in ultrapure water to obtain a 0.5 wt% PEG (9) MA aqueous solution. 30 mg of single-walled CNT (NanoIntegris' "HiPco-Raw", average diameter 1.0 nm, average length 0.5 μm) was added to 30 g of the 0.5 wt% PEG (9) MA aqueous solution to obtain a mixed solution. Next, while stirring with a stirrer, the mixture was dispersed for 10 minutes using an ultrasonic homogenizer (Branson's "450D") at 30% output and a liquid temperature of 10°C. The dispersed solution was then centrifuged for 60 minutes using an ultracentrifuge (Hitachi Koki's "CX100GXII", rotor S50) at a rotation speed of 50,000 rpm and a liquid temperature of 20°C. 80% of the supernatant was collected from the liquid surface on a volume basis, and the ratio of semiconducting CNTs to the total amount of CNTs (total of semiconducting CNTs and metallic CNTs) (content of semiconducting CNTs) was 98% by mass, thereby obtaining CNT dispersions to be used in the following Examples 1 to 5 and Comparative Examples 1 to 3. The SWCNTs used were 100 to 220 cm -1 There is a peak specific to metallic SWCNTs in the vicinity of 220–350 cm -1 There is a peak specific to semiconducting SWCNTs in the vicinity.

[0074] [Example 1] A 1 cm thick thermal oxide film (SiO2) with a thickness of 200 nm is deposited. 2 An adsorption layer of 3-aminopropyltriethoxysilane (APTES) was formed on a silicon substrate of (area of ​​the main surface) by a gas phase method. Next, the CNT dispersion obtained by the above method was diluted with pure water to adjust the concentration to 1.45 μg / mL in terms of CNT mass. This was applied to the entire surface of the adsorption layer to form a coating film, which was then left to stand at room temperature for 1 hour. Then, before performing a drying process, the silicon substrate on which the coating film had been formed was immersed in ultrapure water for 60 minutes to remove excess CNTs, and then it was pulled out of the ultrapure water and dried in an atmosphere at 180°C for 60 minutes to obtain a semiconductor layer with an average film thickness of 2 nm. From the AFM image, the network density of the carbon nanotubes in the semiconductor layer was 625 tubes / μm 2In addition, an atomic force microscope was used to observe an image of a 1 μm square in the region (channel region) between the source electrode and the drain electrode in the semiconductor layer, and it was found that the CNTs were randomly oriented in the two-dimensional direction along their longitudinal direction, and each CNT intersected with five or more other CNTs. In addition, for all the CNTs observed in the 1 μm square, the total length of the parts that overlapped with other CNTs (intersecting parts) in the longitudinal direction of the CNTs was 3%.

[0075] Next, Cr was vacuum-deposited through a metal mask to an average thickness of 30 nm, and then Au was vacuum-deposited on the Cr layer to an average thickness of 30 nm, so that the channel length (L) and channel width (W) were 100 μm and 1000 μm, respectively, to form a source electrode and a drain electrode with a two-layer structure (Cr layer / Au layer). The substrate on which the source electrode and the drain electrode were formed was heated at 180° C. for 1 hour. Next, the excess semiconductor layer was removed by etching, and then a fluororesin (CYTOP (registered trademark), CTL-809A, manufactured by AGC) was spin-coated (first step: 500 rpm for 5 s, second step: 3000 rpm for 20 s). After that, the substrate was heated at 180° C. for 60 minutes to form a sealing layer with an average thickness of 600 nm. In this manner, the semiconductor element shown in FIG. 1 and FIG. 2 was fabricated.

[0076] [Example 2] A semiconductor element was produced in the same manner as in Example 1, except that a sealing layer with an average thickness of 1200 nm was formed by spin-coating (first step: 500 rpm for 5 s, second step: 2000 rpm for 20 s) and then heating at 180°C for 60 minutes.

[0077] [Example 3] A semiconductor element was formed in the same manner as in Example 1, except that a 1 wt % chloroform solution of polystyrene (weight average molecular weight: 35000) was spin-coated (1800 rpm, 30 s) instead of a fluororesin (CYTOP (registered trademark), CTL-809A, manufactured by AGC Corporation) to form a sealing layer with an average thickness of 600 nm.

[0078] [Example 4] A semiconductor element was formed in the same manner as in Example 3, except that a sealing layer was formed using a 1 wt % chloroform solution of PMMA (weight average molecular weight: 15000) in place of the 1 wt % chloroform solution of polystyrene.

[0079] [Example 5] A semiconductor device was formed in the same manner as in Example 1, except that the thickness of the Cr layer was 5 nm.

[0080] [Comparative Example 1] A semiconductor device was produced in the same manner as in Example 1, except that Ti was used instead of Cr in the source and drain electrodes.

[0081] [Comparative Example 2] A semiconductor element was produced in the same manner as in Example 1, except that the sealing layer was not formed.

[0082] [Comparative Example 3] A semiconductor element was formed in the same manner as in Example 3, except that a sealing layer was formed using a 1 wt % acetone solution of polyvinylidene fluoride (KF polymer #7200, manufactured by Kureha) instead of a 1 wt % chloroform solution of polystyrene.

[0083] [Table 1]

[0084] Fig. 7 shows an atomic force microscope photograph of the semiconductor layer constituting the semiconductor element of Example 1. As shown in Fig. 7, it can be confirmed that the semiconductor layer has a CNT network structure.

[0085] As shown in Table 1, in Examples 1 to 5, the portions of the source electrode and drain electrode that contact the semiconductor layer are made of Cr, an element of Group 6 of the periodic table, and the semiconductor layer is made of a material with a dielectric constant of 5.0 or less, so that the hysteresis is smaller than in the comparative examples, and the change in threshold voltage due to the magnitude of the drain voltage is suppressed. In Comparative Example 3, even though the portions of the source electrode and drain electrode that contact the semiconductor layer are made of Cr, an element of Group 6 of the periodic table, the semiconductor layer is not made of a material with a dielectric constant of 5.0 or less, so that the hysteresis is larger than in the examples, and the change in threshold voltage is also larger. [Industrial Applicability]

[0086] As described above, according to the present disclosure, it is possible to provide a semiconductor element having small hysteresis and in which change in threshold voltage due to the magnitude of the drain voltage is suppressed, thereby contributing to improving the performance of devices using this semiconductor element. [Explanation of symbols]

[0087] 1. Semiconductor element 2. Semiconductor substrate (gate electrode) 3. Source Electrode 4 Drain electrode 31,41 Group 6 element layer 32,42 upper layer 5 Semiconductor layer 6 Gate insulation layer 8 Sealing layer 9 Adsorption layer 15 Coating 50 Carbon Nanotubes

Claims

1. A semiconductor device including a gate electrode, a source electrode, a drain electrode, a semiconductor layer in contact with the source electrode and the drain electrode, and a gate insulating layer insulating the semiconductor layer from the gate electrode, wherein the semiconductor layer includes a network structure of carbon nanotubes, wherein the semiconductor layer is encapsulated with a sealing layer having a relative permittivity of 5.0 or less, and a portion of the source electrode and the drain electrode in contact with the semiconductor layer is formed of a Group 6 element of the periodic table.

2. The semiconductor device according to claim 1, wherein an average thickness of each of the layers formed of the Group 6 element in the source electrode and the drain electrode is 25 nm or more.

3. The semiconductor device according to claim 1 or 2, wherein the Group 6 element is chromium.

4. The semiconductor device according to claim 1 or 2, wherein an average thickness of the sealing layer is 200 nm or more.

5. The semiconductor device according to claim 1 or 2, wherein the sealing layer contains one or more resins selected from the group consisting of fluororesins, acrylic resins, styrene resins, vinyl resins, and olefin resins.

6. The semiconductor device according to claim 1 or 2, wherein the carbon nanotube is a single-walled carbon nanotube.

7. The semiconductor device according to claim 1 or 2, wherein a content ratio of semiconductor carbon nanotubes among the carbon nanotubes contained in the semiconductor layer is 70% by mass or more.

8. A method for manufacturing a semiconductor device including a gate electrode, a source electrode, a drain electrode, a semiconductor layer in contact with the source electrode and the drain electrode, and a gate insulating layer insulating the semiconductor layer from the gate electrode, comprising forming a semiconductor layer including a network structure of carbon nanotubes using a carbon nanotube dispersion. Forming a source electrode and a drain electrode including a Group 6 element layer of the periodic table in contact with the semiconductor layer on the semiconductor layer. A method of manufacturing a semiconductor device, including sealing the semiconductor layer and forming a sealing layer having a relative permittivity of 5.0 or less.

9. The method of manufacturing a semiconductor device according to claim 8, wherein the carbon nanotube concentration of the carbon nanotube dispersion is 0.1 μg / mL or more and 7.0 μg / mL or less.

10. In the formation of the semiconductor layer, The method of manufacturing a semiconductor device according to claim 8 or 9, wherein the carbon nanotube dispersion is applied to form a coating film, the carbon nanotubes are adsorbed on the surface to be coated, excess carbon nanotubes are removed from the coating film while the coating film is not dried, and then a drying process is performed to form the semiconductor layer.

11. The method of manufacturing a semiconductor device according to claim 10, wherein the removal of the excess carbon nanotubes is performed by washing with a cleaning liquid.

12. The method of manufacturing a semiconductor device according to claim 10, wherein the removal of the excess carbon nanotubes is performed by immersing the coating film in a cleaning liquid.

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