Manufacturing method for semiconductor device, and semiconductor device
Patent Information
- Application Number
- JP2022157633
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2022-09-30
- Publication Date
- 2025-07-09
- Estimated Expiration
- 2042-09-30
AI Technical Summary
Existing semiconductor capacitor technologies face challenges in achieving both high capacitance and low leakage current, particularly as capacitor sizes decrease with advancements in integrated circuit integration.
A manufacturing method involving the formation of a mixed layer by reacting a high dielectric constant film containing tetravalent metal cations with an oxide film containing pentavalent metal cations, such as ZrO2 and Nb2O5, to create a conductive interface that reduces Capacitance Equivalent Thickness (CET) and minimizes leakage current.
The method effectively increases capacitance and reduces leakage current by forming a conductive mixed layer that maintains charge neutrality and prevents film damage, achieving improved capacitor performance.
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Abstract
Description
[Technical field]
[0001] The present disclosure relates to a method for manufacturing a semiconductor device and a semiconductor device. [Background technology]
[0002] Capacitors used in DRAMs and the like have a lower electrode, a high dielectric constant film, and an upper electrode formed in that order on a substrate, and Patent Document 1 describes a capacitor that uses zirconium oxide as the high dielectric constant film.
[0003] Patent Document 2 describes a semiconductor device having a first dielectric film containing tantalum oxide or niobium oxide, a second dielectric film provided between a lower electrode and the first dielectric film, and a third dielectric film between the first dielectric film and an upper electrode, and also describes the use of zirconium oxide or the like for the second and third dielectric films. [Prior art documents] [Patent documents]
[0004] [Patent Document 1] JP 2001-152339 A [Patent Document 2] JP 2004-266009 A Summary of the Invention [Problem to be solved by the invention]
[0005] The present disclosure provides a semiconductor device and a manufacturing method thereof that can achieve both high capacitance and low leakage current of a capacitor. [Means for solving the problem]
[0006] A method for manufacturing a semiconductor device according to one embodiment of the present disclosure includes the steps of forming a lower electrode on a substrate, forming a high dielectric constant film made of an oxide containing tetravalent metal cations on the lower electrode, forming an oxide film made of an oxide containing pentavalent metal cations on the high dielectric constant film, reacting the high dielectric constant film with the oxide film to form a conductive mixed layer in which the oxide containing the tetravalent metal cations and the oxide containing the pentavalent metal cations are mixed, and forming an upper electrode. Effect of the Invention
[0007] According to the present disclosure, a semiconductor device and a manufacturing method thereof are provided that can achieve both high capacitance and low leakage current of a capacitor. [Brief description of the drawings]
[0008] [Figure 1] 4 is a flowchart showing a method for manufacturing the semiconductor device according to the first embodiment. [Diagram 2] 2A to 2C are cross-sectional views showing process steps in a manufacturing method for the semiconductor device according to the first embodiment. [Diagram 3] FIG. 1 is a graph showing the relationship between CET and leakage current in a conventional ZrO2 single-film capacitor. [Figure 4] FIG. 1 is a cross-sectional view showing a part of a structure of a conventional capacitor. [Diagram 5] FIG. 1 shows the calculated distribution of density of states (DOS) when 5 of 16 Ti sites in TiO2 are substituted with Zr. [Figure 6] FIG. 1 is a diagram showing the relationship between the number of Zr atoms substituting Ti sites of TiO2 and the band gap. [Figure 7] FIG. 1 shows the distribution of density of states (DOS) calculated when the number of Zr substitutions at 24 Nb sites in Nb2O5 is 0 and 8. [Figure 8] FIG. 1 is a diagram showing the relationship between the number of Zr atoms substituting the Nb sites of Nb2O5 and the band gap. [Figure 9]FIG. 4 is a diagram showing the results of actually manufacturing a semiconductor device (capacitor) according to the first embodiment and understanding its characteristics. [Figure 10] 10 is a flowchart showing a method for manufacturing a semiconductor device according to a second embodiment. [Figure 11] 10A to 10C are cross-sectional views showing some of the steps of a method for manufacturing a semiconductor device according to a second embodiment. [Figure 12] FIG. 1 shows the distribution of density of states (DOS) calculated when the number of Zr substitutions at 28 Nb sites in Nb12O29, which has oxygen deficiency compared to Nb2O5, is 4. [Figure 13] FIG. 1 is a diagram showing the relationship between the number of Zr atoms substituting Nb sites in Nb12O29 and the band gap, in comparison with the case where Nb sites in Nb2O5 are substituted with Zr atoms. [Figure 14] FIG. 1 is a diagram showing the relationship between the number of Zr atoms substituting Ti sites in Ti9O17 and the band gap, in comparison with the case where Ti sites in TiO2 are substituted with Zr atoms. [Figure 15] FIG. 11 is a diagram showing the results of actually manufacturing a semiconductor device (capacitor) according to the second embodiment and grasping its characteristics. [Figure 16] 10 is a flowchart showing a method for manufacturing a semiconductor device according to a third embodiment. [Figure 17] 10A to 10C are cross-sectional views showing some of the steps of a method for manufacturing a semiconductor device according to a third embodiment. [Figure 18] FIG. 11 is a diagram showing the results of actually manufacturing a semiconductor device (capacitor) according to the third embodiment and understanding its characteristics. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0009] Hereinafter, an embodiment will be described with reference to the accompanying drawings.
[0010] <First embodiment> First, the first embodiment will be described. FIG. 1 is a flow chart showing a method for manufacturing a semiconductor device according to the first embodiment, and FIG. 2 is a cross-sectional view showing the steps.
[0011] In this embodiment, first, a lower electrode 102 is formed on a substrate 101 (step ST1, FIG. 2(a)). The substrate 101 is not particularly limited, but may be a semiconductor substrate, for example, a Si substrate. The lower electrode 102 may be a TiN film. In addition to a TiN film, the lower electrode 102 may be a TiSiN film, a TiAlN film, a TiMeN (Me: transition metal) film, a W film, a Mo film, or a Ru film. The lower electrode 102 may be formed by CVD, ALD, or PVD (sputtering).
[0012] Next, a high dielectric constant film (High-k film) 103 made of an oxide containing tetravalent metal cations is formed as a capacitive film on the lower electrode 102 (step ST2, FIG. 2(b)). The High-k film 103 made of an oxide containing tetravalent metal cations may be a ZrO2 film or a HfO2 film. The High-k film 103 may be formed by CVD, ALD, or PVD (sputtering). The thickness of the High-k film 103 may be in the range of 2 to 10 nm.
[0013] Next, an oxide film 104 made of an oxide containing a pentavalent metal cation is formed on the high-k film 103 (step ST3, FIG. 2(c)). The oxide film 104 made of an oxide containing a pentavalent metal cation may be a Nb2O5 film, a Ta2O5 film, or a V2O5 film. The oxide film 104 can be formed by CVD, ALD, or PVD (sputtering). The thickness of the oxide film 104 may be 1 nm or less.
[0014] Next, the high-k film 103 and the oxide film 104 are reacted at the interface to form a conductive mixed layer 105, which is a mixture of an oxide containing tetravalent metal cations and an oxide containing pentavalent metal cations (step ST4, FIG. 2(d)). The mixed layer 105 can be formed as a reaction layer during annealing for crystallizing the high-k film 103. For example, when the high-k film 103 is a ZrO2 film and the oxide film 104 is a Nb2O5 film, diffusion of Zr and Nb occurs by annealing, and the conductive mixed layer 105 is formed as NbZrO x The annealing temperature may be within a range of 250 to 600° C. The annealing time may be 120 minutes or less. The composition of the mixed layer 105 can be adjusted by the annealing temperature and time, and the mixed layer 105 can be made conductive by increasing the amount of Zr.
[0015] Next, the upper electrode 106 is formed on the mixed layer 105 or the oxide film 104 (step ST5, FIG. 2(e)). The upper electrode 106 may be a TiN film. As the upper electrode 106, a TiSiN film, a TiAlN film, a TiMeN (Me: transition metal) film, a W film, a Mo film, or a Ru film may be used in addition to the TiN film. The upper electrode 106 can be formed by CVD, ALD, or PVD (sputtering).
[0016] After the upper electrode 106 is formed, annealing is performed for the purpose of removing damage, etc., and the process is completed. Note that even with this annealing, a mixed layer due to atomic diffusion is unlikely to occur between the upper electrode 106 and the mixed layer 105.
[0017] In this embodiment, the mixed layer 105 may be formed in step ST4 after the upper electrode 106 is formed in step ST5.
[0018] The semiconductor device manufactured in the above manner is used as a capacitor, typically a capacitor for a DRAM.
[0019] As shown in FIG. 2(e), the semiconductor device manufactured by the method of this embodiment has a lower electrode 102 formed on a substrate 101, a High-k film 103 made of an oxide containing tetravalent metal cations formed on the lower electrode 102, a mixed layer 105 formed on the High-k film 103, and an upper electrode 106 formed on the mixed layer 105.
[0020] In this embodiment, the mixed layer 105 is composed of a combination of tetravalent metal cations and pentavalent metal cations, and therefore, as described below, defects are generated to satisfy the charge neutrality condition, and the mixed layer 105 may become conductive. By forming the conductive mixed layer 105, the thickness of the dielectric portion is accordingly reduced, and the capacitance equivalent thickness (CET) can be reduced to increase the capacitance. Furthermore, the presence of the mixed layer 105 can reduce the leakage current.
[0021] The details will be explained below. Recently, the integration and speed of LSIs have progressed further, and the design rules of semiconductor elements constituting LSIs have become finer and finer. As a result, the capacitance of capacitors used in DRAMs, for example, has been on a downward trend, and an increase in the capacitance of the capacitor is required. In a capacitor having a single layer of a high-k ZrO2 film between TiN electrodes as a dielectric film as shown in Patent Document 1, the CET can be reduced by thinning the ZrO2 film, thereby increasing the capacitance of the capacitor. However, thinning the ZrO2 film causes an increase in leakage current, and it is difficult to achieve both high capacitance and low leakage current by reducing the CET. That is, as shown in FIG. 3, the relationship between CET and leakage current is almost linear up to about 3.5 nm of the ZrO2 film, whereas when the film thickness of the ZrO2 film becomes thinner than 3 nm, for example, 2.5 nm, the leakage current increases more than the straight line (trend line). Patent Document 2 also describes a capacitor having multiple dielectric films, but does not intend to achieve both high capacitance and low leakage current.
[0022] Therefore, in this embodiment, an oxide film 104 made of an oxide containing a pentavalent metal cation, for example, Nb2O5, is formed on a high-k film 103 made of an oxide containing a tetravalent metal cation, for example, a ZrO2 film. Then, the high-k film 103 and the oxide film 104 are reacted (atomic diffusion) at the interface by annealing to form a mixed layer 105 in which they are mixed. For example, when the high-k film 103 is a ZrO2 film and the oxide film 104 is a Nb2O5 film, NbZrO x A mixed layer 105 containing the above is formed.
[0023] In the case of a conventional capacitor having a configuration in which a ZrO2 film 103' is provided as a dielectric film between a lower electrode 102' and an upper electrode 106' made of TiN as shown in FIG. 4, a reaction (atomic diffusion) occurs between the upper electrode 106' and the ZrO2 film 103' by annealing after the formation of the upper electrode 106', and the TiZrO x A mixed layer (interface layer) 105' consisting of these is formed.
[0024] In this case, the mixed layer 105' can be considered as a layer in which some of the Ti sites are replaced with Zr, and the defect structural formula in this case is as shown in the following formula (1).
number
[0025] Fig. 6 is a diagram showing the relationship between the number of Zr atoms substituting for Ti sites in TiO2 and the band gap. As shown in this figure, regardless of the number of Zr atoms substituted in TiO2, the band gap does not close and it behaves as an insulator. Therefore, by forming the mixed layer 105', the dielectric layer is increased accordingly.
[0026] That is, the CET of the ZrO2 film is ZrO2 The CET of the TiZrO2 mixed layer 105' is TiZrO2 Then, the CET of the entire capacitor is CET TZT is as follows: ZrO2 and CET TiZrO2 Thus, the mixed layer 105' acts in a direction that increases the CET. CET TZT =CET TiZrO2 +CET ZrO2
[0027] In contrast, the mixed layer 105 of the present embodiment is a mixture of an oxide containing a pentavalent metal cation, such as Nb2O5, and an oxide containing a tetravalent metal cation, such as ZrO2, for example, NbZrO x When ZrO2, an oxide containing tetravalent metal cations, is added to Nb2O5, an oxide containing pentavalent metal cations, that is, when some of the Nb sites are replaced with Zr, the defect structural formula is as shown in formula (2) below.
number
[0028] Figure 7 shows the distribution of density of states (DOS) calculated when the number of Zr substitutions at 24 Nb sites in Nb2O5 is 0 and 8. As shown in Figure 7, the calculation also confirms that when Zr is 8, energy levels originating from the electron orbitals of oxygen and Zr are generated in the gaps in the DOS distribution, resulting in electrical conductivity.
[0029] Figure 8 shows the relationship between the number of Zr atoms substituting for the Nb sites of Nb2O5 and the band gap. As shown in this figure, the band gap narrows as the number of Zr atoms substituted in Nb2O5 increases, and when the number of Zr atoms substituted reaches 8 or more, the band gap closes and the material changes into a conductor.
[0030] That is, in this embodiment, the mixed layer 105 can be made conductive by increasing the substitution number of tetravalent metal cations (Zr in this example) in the mixed layer 105. In this embodiment, the conductive mixed layer 105 is formed by adjusting the heat treatment conditions during annealing.
[0031] The high-k film 103 is a ZrO2 film, and the mixed layer 105 is a NbZrO x If CET of the ZrO2 film is CET ZrO2 , NbZrO x CET to CET NbZrOx Then, the CET of the entire capacitor is CET TNZT is as follows: ZrO2 and CET NbZrOx It becomes the sum of with. CET TNZT =CET NbZrOx +CET ZrO2 Here, NbZrO x is conductive, so CET NbZrOx is almost 0. Therefore, the thickness of the dielectric film is thinner than that of the conventional capacitor using only ZrO2 film, and CET can be reduced. xThe presence of the mixed layer 105 can prevent damage to the high-k film 103 during the formation of the upper electrode 106, etc. In other words, without the mixed layer 105, the high-k film 103 would be chemically damaged by Cl, NH3, etc. when the upper electrode 106 is formed by ALD, or physically damaged by plasma when the upper electrode 106 is formed by PVD, but the presence of the mixed layer 105 prevents such damage. Therefore, even though the CET is small, an increase in leakage current can be suppressed. This makes it possible to achieve both high capacitance and low leakage current for the capacitor.
[0032] The semiconductor device (capacitor) of this embodiment was actually manufactured and its characteristics were ascertained. Here, a ZrO2 film with a thickness of 4 nm and a Nb2O5 film with a thickness of 0.6 nm were formed on a lower electrode made of a TiN film formed on a Si substrate, and then annealing was performed to obtain NbZrO x A capacitor was manufactured by forming a film on the film and then forming an upper electrode made of a TiN film on top of the film (Sample 1). The CET and leakage current of the Sample 1 capacitor were determined. As a result, as shown in Figure 9, it was confirmed that the CET could be reduced by about 15% while suppressing the increase in leakage current compared to a capacitor (Ref) with a conventional structure using a single ZrO2 film, and that the characteristics were improved compared to the trend line of the single ZrO2 film.
[0033] <Second embodiment> Next, a second embodiment will be described. FIG. 10 is a flow chart showing a method for manufacturing a semiconductor device according to the second embodiment, and FIGS. 11A to 11C are cross-sectional views showing some of the steps.
[0034] In this embodiment, steps ST11 to ST13 similar to steps ST1 to ST3 in the first embodiment are performed. That is, a lower electrode 102 is formed on a substrate 101 (step ST11), a high dielectric constant film (High-k film) 103 made of an oxide containing tetravalent metal cations is formed as a capacitance film (step ST12), and an oxide film 104 made of an oxide containing pentavalent metal cations is formed on the High-k film 103 (step ST13).
[0035] Next, similarly to step ST4 in the first embodiment, for example, during annealing for crystallizing the High-k film 103, the High-k film 103 and the oxide film 104 are reacted at the interface to form a conductive mixed layer 105 in which an oxide containing a tetravalent metal cation and an oxide containing a pentavalent metal cation are mixed (step ST14, FIG. 11(a)).
[0036] Next, an oxygen-withdrawing layer 108 for extracting oxygen is formed on the mixed layer 105 (step ST15, FIG. 11(b)). At this time, as shown in FIG. 11(b), the oxygen-withdrawing layer 108 is formed via a barrier film 107 made of, for example, a TiN film. The oxygen-withdrawing layer 108 may be a metal film made of an active metal such as TiAl. The oxygen-withdrawing layer 108 may be made of TiAl, Ti, Al, or the like.
[0037] Next, the upper electrode 106 made of, for example, a TiN film is formed on the oxygen-withdrawing layer 108 in the same manner as in step ST5 of the first embodiment (step ST16, FIG. 11(c)).
[0038] Next, a heat treatment is performed in a reducing atmosphere (step ST17, FIG. 11(d)). As a result, oxygen is extracted from the lower mixed layer 105 to the oxygen-extracting layer 108, forming a mixed layer 105a in which oxygen deficiency occurs. The heat treatment can be performed under the conditions of an H2-containing atmosphere (hydrogen concentration: 1 to 100%, for example, 4%), a temperature of 350 to 600°C, for example, 400°C, and a time of 120 minutes or less, for example, 10 minutes.
[0039] The formation of the oxygen-withdrawing layer 108 in step ST15 and the heat treatment in a reducing atmosphere in step ST17 constitute a reduction treatment step.
[0040] After step ST17, annealing is further performed as necessary, and the process is terminated.
[0041] In this embodiment, the formation of the mixed layer 105 in step ST14 may be performed during step ST17, or during annealing after step ST17. When step ST14 is performed during annealing after step ST17, the extraction of oxygen (reduction treatment) in ST17 is performed on the oxide film 104.
[0042] In this embodiment as well, the semiconductor device manufactured as described above is used as a capacitor, typically a capacitor of a DRAM.
[0043] In this embodiment, the mixed layer 105 is formed by a combination of tetravalent metal cations and pentavalent metal cations, and oxygen vacancies are generated in the mixed layer 105 to satisfy the charge neutrality condition. The mixed layer 105a is formed by performing a reduction process to extract oxygen, which generates oxygen vacancies. Therefore, the mixed layer 105a is more likely to be conductive than the mixed layer 105 due to the presence of oxygen vacancies, and the conductivity can be increased. Therefore, the effect of reducing CET can be increased more than in the first embodiment. In addition, the presence of the mixed layer 105a can prevent not only damage to the High-k film 103 during the formation of the upper electrode 106 as described above, but also damage to the High-k film 103 during the reduction process, and can suppress an increase in leakage current.
[0044] The details will be explained below. As described above, the mixed layer 105, which is a mixture of an oxide containing a pentavalent metal cation, such as Nb2O5, and an oxide containing a tetravalent metal cation, such as ZrO2, may become conductive due to oxygen vacancies and defects derived from negatively charged Zr. The mixed layer 105a, in which oxygen is extracted from the mixed layer 105 and oxygen vacancies are increased, tends to become more conductive.
[0045] Figure 12 shows the structure of Nb2O5 with oxygen deficiency. 12 O 29 12 is a diagram showing the distribution of the density of states (DOS) calculated when the number of Zr substitutions for 28 Nb sites in Nb2O5 is 4. 12 O 29 In the case of (a), even if the number of Zr substitutions is as small as four, it is confirmed that energy levels originating from the oxygen and Zr electron orbitals are generated within the gaps in the DOS distribution, resulting in electrical conductivity.
[0046] Figure 13 shows the Nb 12 O 29 This figure shows the relationship between the number of Zr atoms substituting the Nb sites of Nb2O5 and the band gap, in comparison with the case where the Nb sites of Nb2O5 are substituted with Zr atoms. As shown in this figure, 12 O 29 In the case of Nb2O5, the band gap narrows more rapidly due to the substitution of Zr atoms than in the case of Nb2O5, and when the number of Zr atoms substituted is 4 or more, the band gap closes and the material changes into a conductor.
[0047] That is, in this embodiment, the mixed layer 105a in which oxygen vacancies are increased by performing an oxygen extraction process, which is a reduction process, on the mixed layer 105, is more likely to be conductive than the mixed layer 105. Therefore, the CET can be further reduced compared to the first embodiment.
[0048] In the case of a conventional capacitor in which the oxide film 104 made of an oxide containing a pentavalent metal cation is not formed as described above, even if oxygen vacancies are caused by a reduction treatment after the mixed layer (interface layer) 105' is formed, the band gap changes as shown in FIG. 14, and the capacitor remains an insulator. 17 This figure shows the relationship between the number of Zr atoms substituting for the Ti sites of Ti9O and the band gap, in comparison with the case where the Ti sites of TiO2 are substituted with Zr atoms. 17 Like TiO2, the band gap does not close and the material behaves as an insulator regardless of the number of Zr atoms substituted.
[0049] The semiconductor device (capacitor) of this embodiment was actually manufactured to understand its characteristics. Here, a 4 nm thick ZrO2 film and a 0.6 nm thick Nb2O5 film were formed on a lower electrode made of a TiN film formed on a Si substrate, and then annealing was performed to form an NbZrOx film. Then, a 3 nm thick TiN film and a 3 nm thick TiAl film were formed thereon, and an upper electrode made of a TiN film was further formed, and a capacitor was manufactured by performing a heat treatment at 400°C in a reducing atmosphere (Sample 2). The CET and leakage current were obtained for the capacitor of Sample 2. As a result, as shown in FIG. 15, it was confirmed that the CET could be reduced by about 35% while suppressing the increase in leakage current to two orders of magnitude or less compared to a conventional capacitor (Ref) using a single ZrO2 film, and the characteristics were improved compared to the trend line of the single ZrO2 film. In addition, FIG. 15 also shows the results of Sample 1 of the first embodiment, and it can be seen that Sample 2 has a higher CET reduction effect than Sample 1.
[0050] <Third embodiment> Next, a third embodiment will be described. FIG. 16 is a flow chart showing a method for manufacturing a semiconductor device according to the third embodiment, and FIGS. 17A to 17C are cross-sectional views showing some of the steps.
[0051] In this embodiment, steps ST21 to ST23 are performed similarly to steps ST1 to ST3 in the first embodiment. That is, a lower electrode 102 is formed on a substrate 101 (step ST21), a high dielectric constant film (High-k film) 103 made of an oxide containing tetravalent metal cations is formed as a capacitance film (step ST22), and an oxide film 104 made of an oxide containing pentavalent metal cations is formed on the High-k film 103 (step ST23).
[0052] Next, similarly to step ST4 in the first embodiment, for example, during annealing for crystallizing the High-k film 103, the High-k film 103 and the oxide film 104 are reacted at the interface to form a conductive mixed layer 105 in which an oxide containing a tetravalent metal cation and an oxide containing a pentavalent metal cation are mixed (step ST24, FIG. 17(a)).
[0053] Next, a reduction treatment is performed (step ST25, FIG. 17(b)). As a result, the mixed layer 105 is reduced to form a mixed layer 105b in which oxygen deficiencies occur. The reduction treatment can be performed by heat treatment in a hydrogen gas (H2 gas) atmosphere or a deuterium gas (D2 gas) atmosphere as a reducing atmosphere, and can be performed under conditions of, for example, a temperature of 250 to 600°C and a time of 60 minutes or less. The reduction treatment may also be performed using H2 plasma.
[0054] Next, the upper electrode 106 made of, for example, a TiN film is formed on the mixed layer 105b in the same manner as in step ST5 of the first embodiment (step ST26, FIG. 17(c)).
[0055] After step ST26, annealing is further performed as necessary, and the process is terminated.
[0056] In this embodiment, the mixed layer 105 in step ST24 may be formed during step ST26, or during annealing after step ST26. If step ST24 is performed during annealing after step ST26, oxygen vacancies are generated in the oxide film 104 during the reduction treatment in step ST25.
[0057] In this embodiment as well, the semiconductor device manufactured as described above is used as a capacitor, typically a capacitor of a DRAM.
[0058] In this embodiment, similarly to the second embodiment, the mixed layer 105 is formed by a combination of tetravalent metal cations and pentavalent metal cations, and a reduction process is performed on the mixed layer 105 in which defects are generated to satisfy the charge neutrality condition, to form a mixed layer 105b in which oxygen deficiencies are generated in the mixed layer 105. Therefore, the mixed layer 105b is more likely to be conductive than the mixed layer 105 due to the presence of oxygen deficiencies, and the conductivity can be increased. Therefore, the effect of reducing CET can be increased more than in the first embodiment. In addition, similarly to the mixed layer 105a in the second embodiment, the mixed layer 105b can prevent damage to the High-k film 103 not only during the formation of the upper electrode 106 but also during the reduction process, and can suppress an increase in leakage current.
[0059] The semiconductor device (capacitor) of this embodiment was actually manufactured to understand the characteristics. Here, a 4 nm thick ZrO2 film and a 0.6 nm thick Nb2O5 film were formed on a lower electrode made of a TiN film formed on a Si substrate, and then annealed to form an NbZrOx film. Then, a reduction process was performed at 541°C in an H2 gas atmosphere, and an upper electrode made of a TiN film was formed thereon to manufacture a capacitor (Sample 3). A capacitor was manufactured under the same conditions as Sample 3, except that the reduction process was performed in a D2 gas atmosphere (Sample 4). The CET and leakage current of this capacitor were obtained. As a result, as shown in FIG. 18, it was possible to reduce the CET by about 30% while suppressing the increase in leakage current to two orders of magnitude or less compared to a conventional capacitor (Ref) using a single ZrO2 film, and it was confirmed that the characteristics were improved compared to the trend line of the single ZrO2 film.
[0060] <Other applications> Although the embodiments have been described above, the embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The above-described embodiments may be omitted, substituted, or modified in various forms without departing from the scope and spirit of the appended claims. [Explanation of symbols]
[0061] 101; Substrate 102; Lower electrode 103;High-k films made of oxides containing tetravalent metal cations 104;Oxide film consisting of oxides containing pentavalent metal cations 105,105a,105b;Mixed layer 106;Top electrode 107;TiN film 108: Oxygen extraction layer
Claims
1. forming a lower electrode on a substrate; forming a high dielectric constant film made of an oxide containing a tetravalent metal cation on the lower electrode; forming an oxide film made of an oxide containing a pentavalent metal cation on the high dielectric constant film; forming a mixed layer having electrical conductivity in which the oxide containing the tetravalent metal cation and the oxide containing the pentavalent metal cation are mixed by reacting the high dielectric constant film with the oxide film; forming a top electrode; The method for manufacturing a semiconductor device comprising the steps of:
2. The high dielectric constant film made of an oxide containing a tetravalent metal cation is ZrO ２ Film and HfO ２ 2. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor substrate.
3. The oxide film made of an oxide containing a pentavalent metal cation is Nb ２ O ５ membrane, V ２ O ５ Membrane, and Ta ２ O ５ 2. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor substrate.
4. The high dielectric constant film made of an oxide containing a tetravalent metal cation is ZrO ２ The oxide film is made of an oxide containing a pentavalent metal cation, and the .... ２ O ５ The method for manufacturing a semiconductor device according to claim 1 , wherein the semiconductor device is a film.
5. 2. The method for manufacturing a semiconductor device according to claim 1, wherein said upper electrode and said lower electrode are made of a TiN film.
6. The method for manufacturing a semiconductor device according to claim 1 , further comprising the step of performing a reduction treatment at least after the step of forming the oxide film.
7. 7. The method for manufacturing a semiconductor device according to claim 6, wherein the step of performing the reduction treatment comprises forming an oxygen-pulling layer on the mixed film or the oxide film, and extracting oxygen from the mixed film or the oxide film to the oxygen-pulling layer by heat treatment in a reducing atmosphere.
8. 8. The method for manufacturing a semiconductor device according to claim 7, wherein the heat treatment in a reducing atmosphere is performed after the step of forming the upper electrode.
9. 8. The method for manufacturing a semiconductor device according to claim 7, wherein oxygen vacancies are generated in said mixed layer by extracting oxygen into said oxygen-extracting layer.
10. 7. The method for manufacturing a semiconductor device according to claim 6, wherein the step of performing the reduction treatment is performed by heat treatment in a hydrogen gas atmosphere or a deuterium gas atmosphere.
11. The method for manufacturing a semiconductor device according to claim 10, wherein oxygen deficiencies are generated in the mixed layer by the heat treatment in the hydrogen gas atmosphere or the deuterium gas atmosphere.
12. The method for manufacturing a semiconductor device according to claim 10 , wherein the step of performing the reduction treatment is performed before the step of forming the upper electrode.
13. 6. The method for manufacturing a semiconductor device according to claim 1, wherein the oxide film has a thickness of 1 nm or less.
14. 6. The method of claim 1, wherein the semiconductor device is a capacitor of a DRAM.
15. A substrate; a lower electrode formed on the substrate; a high dielectric constant film formed on the lower electrode and made of an oxide containing a tetravalent metal cation; a mixed layer having electrical conductivity, the mixed layer being formed on the high dielectric constant film and being a mixture of the oxide containing the tetravalent metal cation and the oxide containing the pentavalent metal cation; an upper electrode formed on the mixed layer; The semiconductor device has
16. The semiconductor device according to claim 15 , wherein the mixed layer has oxygen vacancies.
17. 17. The semiconductor device according to claim 15, which is used as a capacitor of a DRAM.